JP2009229151A - Digital filter for pulse measurement - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital filter for pulse measurement for calculating appropriate parameters from an input signal before measuring the pulse of the input signal and improving filter characteristics by using the parameters. <P>SOLUTION: The digital filter for measuring pulses has a parameter calculation means that has a circuit for holding a signal sampled from an input signal approximated by an exponential function, a circuit for detecting the peak value of the held signal, a circuit for calculating the mantissa part of the input signal from a pulse value including the peak value and the position of the pulse value, and a circuit for averaging the mantissa values calculated from each of a plurality of input signals, where the average value is set to the mantissa part of the input signal. The parameter calculation means has: a circuit for calculating the rise time of the input signal; a circuit for averaging the rise time calculated from each of a plurality of input signals; and a circuit for setting the average value to the amount of delay and calculating a digital filter coefficient from the mantissa part and the amount of delay. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a digital filter for pulse measurement used in general analyzers, and more particularly to a digital filter comprising a parameter calculation means having a mantissa calculation function, a delay amount calculation function, and a filter coefficient calculation function.

In the digital filter for pulse measurement that obtains the height (crest value) of the input signal approximated by the exponential function y = a ^x (0 <a <1), the n-fold difference configuration is effective. The digital filter that performs the n-th difference processing has the characteristics that the output is a bipolar waveform with positive and negative symmetry, the adjacent pulses can be separated neatly, the baseline correction is not required, and the circuit scale can be reduced. ing.

  As a digital filter that performs such n-time difference processing, there is a digital filter described in Patent Document 1 (for example, see Patent Document 1). The digital filter described in Patent Document 1 includes a first register composed of a plurality of memory cells in which input signals are stored serially, and a first coefficient that multiplies the input signal from the first register by a predetermined coefficient. A first difference processing means comprising a multiplication means, a first subtraction means for receiving the input signal and an output of the first multiplication means and performing a subtraction process, and an output of the first difference processing means In response, a second register comprising a plurality of memory cells stored in serial order, a second multiplying means for multiplying an output from the second register by a predetermined coefficient, and an output of the first subtracting means And a second subtracting unit including a second subtracting unit that receives the output of the second multiplying unit and performs a subtraction process.

  For such a digital filter, a transfer function (z function) as described below is often used in practice.

^{h (z) = (1-} z -L) (1-k M z -M)
{L: Delay time 1, M: Delay time 2, k _M : Filter coefficient (0 <k _M ≦ 1)}
Generally, L, M is the rise time of the signal, k _M is Together in a ^M, clean bipolar waveform is obtained. FIG. 6 shows an input waveform and an output waveform in that case, and FIG. 7 shows a configuration example of the difference filter when the difference process is performed twice.
JP 2008-2920 A

  However, in such a digital filter, it is necessary to appropriately set the filter coefficient and the delay time calculated from the mantissa part of the input signal (corresponding to the exponent function a). For this reason, there arises a problem that the filter characteristics are greatly deteriorated when the time constant of the input signal is changed due to some influence such as switching of the detector or change of the state. For this reason, conventionally, it has been necessary to have a plurality of parameters in advance and reset the parameters in accordance with the state of the detector model, input signal, and the like.

  The present invention has been made paying attention to the above problems, and calculates an appropriate parameter from an input signal before measuring the pulse of the input signal, and uses the parameter to improve the filter characteristics. The purpose is to provide a filter.

  In order to solve the above-mentioned problems, a digital filter for pulse measurement according to claim 1 of the present invention is a circuit for measuring a pulse of an input signal approximated to an exponential function, and holding a signal sampled from the input signal A circuit for detecting a peak value of the held sampling signal, a circuit for calculating a mantissa part of the input pulse signal from a pulse value including the peak value of the sampled signal and a position of the pulse value, and a plurality of input pulses And a circuit for taking an average value of the mantissa part calculated from each of the signals, and comprising parameter calculation means for using the average value as the mantissa part of the input signal.

  The digital filter for pulse measurement according to claim 2, wherein the parameter calculating means calculates the rise time of the input pulse signal, and the circuit takes an average value of the rise times calculated from each of the plurality of input pulse signals. The average value is used as a delay amount.

  The digital filter for pulse measurement according to claim 3 is characterized in that the parameter calculating means includes a circuit for calculating a digital filter coefficient from the mantissa part and the delay amount.

  In the digital filter of the present invention, a signal is input immediately before pulse measurement, a mantissa part and a delay amount are obtained from the input signal, and a filter coefficient is obtained from the mantissa part and the delay amount. An accurate pulse height can be obtained from the filter output by performing pulse measurement of the input signal after setting the obtained delay amount and filter coefficient in the digital filter.

  According to the present invention, since the optimum parameter is automatically set before measurement, it is not necessary to set the parameter in the digital filter before measuring the pulse of the input signal. In addition, the digital filter can always be operated with appropriate parameters regardless of the characteristics of the input signal, that is, the switching of the detector and the analog characteristics of the previous stage, so that a highly accurate measurement result can be obtained.

  Hereinafter, the present invention will be described in more detail with reference to embodiments.

  FIG. 1 is a block diagram of a configuration example for calculating the mantissa part and the delay amount in the parameter calculation means of the digital filter for pulse measurement according to the embodiment, FIG. 2 shows an example of four pulses of the input signal, and FIG. FIGS. 3 and 4 are diagrams for explaining specific examples of the input signal and delay amount calculation, mantissa calculation, and filter coefficient calculation of the B part, C part, and D part).

The block diagram of FIG. 1 is as follows. First, when a pulse signal (A part, B part, C part, D part,...) Approximated by an exponential function {y = a ^x (0 <a <1)} is input, the data string is shifted. The data are sequentially stored in the register 1 (in this example, a 32-stage shift register). If the peak determination circuit 2 determines that the value of the center position of the shift register 1 (the 16th stage shift register) is equal to or greater than a certain threshold and is a peak compared to the previous and subsequent values, the shift register 1 Stop shift operation.

  Next, a value that is delayed to some extent from the peak value (in the example of FIGS. 3 and 4, data after 8 sample times from the peak position) is changed to a fixed value 3 (four points in the examples of FIGS. 3 and 4). 24th to 27th shift register positions (center shift register positions +8 to +11)) and the data selection circuit 4 are used for selection. The four points of data are normalized by dividing each of the four points by a peak value by a normalizing circuit (÷ peak value) 5 to obtain an output y, and the time difference between the four points of the data position and the peak position is normalized (-shift register). Normalize by 6) to get the output x.

  The reason for using a value delayed somewhat from the peak position here is that the input signal is not a true exponential function, but has a value with a time constant via a low-pass filter. This is because it deviates from the true function value.

Thereafter, the logarithm calculation circuit 7 receives the output y and obtains the logarithm logarithm for the output y. The reciprocal calculation circuit 8 receives the output x and obtains the reciprocal 1 / x from the output x. The inverse number 1 / x is multiplied by the multiplier 9 to obtain (log) / x. Next, the inverse logarithm calculation circuit 10 obtains the inverse logarithm 10 ⁽ log ^{) / x,} and an output a is obtained as a calculation result. Such inverse logarithm calculation is performed for each of the outputs x and y obtained by normalization. Since a obtained by inverse logarithm calculation is 10 ⁽ log ^{) / x} rather than y ^{1 / x} when realized by hardware, the configuration is easier.

  Thereafter, the obtained inverse logarithm calculation results a are stored in the storage circuit 11. In the example of FIGS. 3 and 4, four antilogarithm calculation results corresponding to “mantissa calculation 1 to 4” are stored. With respect to the stored four values, the largest and smallest values are excluded, the average value of the second and third values is taken, and this average value is held by the averaging “1” circuit 12. Specifically, in the example of FIGS. 3 and 4, for example, in the A part data, the maximum value 0.93004 and the minimum value 0.92039 are excluded from the calculated values of the inverse logarithm of 4 points (mantissa calculation 1 to 4). , 0.92535 and 0.92193, take an average value of 0.92364. Similarly, the average value of the B part data is 0.92457, the average value of the C part data is 0.94127, and the average value of the D part data is 0.93372.

The above processing up to the averaging “1” circuit 12 is performed for a certain number of peaks (in this example, 4 peaks in the A part to D part data), and the averaging “2” circuit 13 makes a total of 4 peaks. The average value of the calculation is taken, and this average value is stored in the flip-flop 14 and output as the mantissa part a of the desired exponential function. Specifically, in the examples of FIGS. 3 and 4, the added value of each average value of the A part to D part data is
0.92364 + 0.92457 + 0.94127 + 0.93372 = 3.7232
Therefore, the average of the added values is
3.7232 / 4 = 0.9308 (238 expressed in 8-bit precision)
The average value 0.9308 is the mantissa part.

  The calculation of the delay amount (delay time) in the parameter calculation means is as follows.

  In the shift register 1, the rising start position is detected in order to measure the rising edge of the input signal in a state where the shift operation is stopped after the peak detection. In this detection, the output of the shift register 1 is compared with the previous and subsequent values by the start position determination circuit 15, and when the increase amount exceeds a certain value, it is determined as the rising start position. In the example of FIGS. 3 and 4, the rising start position is “0 from the start position”.

  Next, the difference between the rising start position and the peak position is calculated by the adder 16 and the difference is added to obtain an average value by the averaging circuit 18. In the averaging circuit 18, the average value is calculated for a certain number of peaks (in this example, four peaks), the average value for all four peaks is obtained, and this average value is stored in the flip-flop 19. The desired delay amount (delay time) DLY2 is output. In this example, since the peak position is always the position of the shift register at the center of the 16th stage, the adder 16 uses the difference between the rising start position and the position of the fixed value 17 (center shift register position) at the 16th stage. Will take.

  Specifically, in the example of FIGS. 3 and 4, the difference between the rising start position and the peak position of the input signal is 10 clocks for the A part data, 10 clocks for the B part data, 11 clocks for the C part data, and D part data. In this case, since it is 10 clocks, the total is 41 clocks. When this total value is divided by 4 to obtain an average value, 10 clocks are obtained. These 10 clocks are a delay amount.

  However, since the digital filter is a two-step filter, two delay settings (DLY1, DLY2) are required. The two delay amounts may be approximately the same value, but it is known that the noise component increases specifically at the same value. Therefore, the delay amount on the DLY1 side is slightly (for example, −1 to 1). +1) Adjust. Specifically, if DLY2 is 10 clocks, DLY1 becomes 9 clocks or 11 clocks, and this DLY1 is stored and output by the flip-flop 21.

Next, the filter coefficient calculation in the parameter calculation means is as follows. A block diagram of a configuration example for calculating the filter coefficient is shown in FIG. The mantissa part a and the output of the prohibition gate circuit 31 are input to the multiplier 30 and multiplied, and the product is stored in the flip-flop 32. Initially, “1” is stored in the flip-flop 32, and since the signal “0” is input from the zero-value decoder 34 to the prohibition input terminal of the prohibition gate circuit 31, the prohibition gate circuit 31 is prohibited. The output is “1”, and the multiplier 30 multiplies the mantissa a by “1” to output “a”, and the flip-flop 32 stores “a”. Thereafter, the multiplier 30 multiplies the mantissa part a and the stored contents of the flip-flop 32 by DLY times, and finally a ^DLY (a: mantissa part, DLY: delay time) is stored in the flip-flop 32. The

On the other hand, the zero value decoder 34 outputs “0” until the delay amount DLY is counted by the DLY counter 33, but when the delay amount DLY is counted by the DLY counter 33, the DLY value decoder 35 This is decoded, and the flip-flop 36 is activated by the output. The flip-flop 36 stores the output a ^DLY of the multiplier 30 and outputs it as a filter coefficient k.

Specifically, in the examples of FIGS. 3 and 4, from the calculation result of the delay time DLY (10) and the mantissa part a (0.9308),
a ^DLY = 0.9308 ¹⁰ = 0.488 (125 in 8-bit precision)
Thus, 0.488 is a filter coefficient.

  As described above, since the filter characteristics are improved by setting the obtained delay amount and filter coefficient as parameters in the digital filter, an accurate pulse height can be obtained from the filter output by performing pulse measurement of the input signal after setting.

  In addition, since optimum parameters (delay amount, filter coefficient) are automatically set before measurement, it is not necessary to set parameters in the digital filter before measuring the pulse of the input signal. In addition, the digital filter can always be operated with appropriate parameters regardless of the characteristics of the input signal, that is, the switching of the detector and the analog characteristics of the previous stage, so that a highly accurate measurement result can be obtained.

It is a block diagram of the example of a structure which calculates the mantissa part and delay amount in the parameter calculation means of the digital filter for pulse measurement which concerns on embodiment. In the block diagram of FIG. 1, it is a wave form diagram which shows the example of 4 pulses of an input signal. In the block diagram of FIG. 1, it is a diagram for explaining an example of input signals of 4 pulses (A part, B part, C part, D part), delay amount calculation, mantissa part calculation, and filter coefficient calculation; It is a figure which shows the data for 2 pulses (A part, B part). In the block diagram of FIG. 1, it is a diagram for explaining an example of input signals of 4 pulses (A part, B part, C part, D part), delay amount calculation, mantissa part calculation, and filter coefficient calculation; It is a figure which shows the data for 2 pulses (C part, D part). It is a block diagram of the structural example which calculates the filter coefficient in the parameter calculation means of the digital filter for pulse measurement which concerns on embodiment. It is a waveform diagram of an example of an input signal for a digital filter according to a conventional example, and a waveform diagram of an example of an output signal obtained by the digital filter. It is a block diagram which shows the structural example of the 2nd time difference digital filter which concerns on a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Shift register 2 Peak determination circuit 3,17 Fixed value 5,6 Normalization circuit 9,30 Multiplier 10 Anti-logarithm calculation circuit 12 Average "1" circuit 13 Average "2" circuit 15 Start position determination circuit 16 Adder 18 Averaging circuit 20 Delay amount adjusting circuit 31 Prohibited gate circuit 33 DLY counter 34 0 value decoder 35 DLY value decoder

Claims (3)

In the digital filter that measures the pulse of the input signal approximated to the exponential function,
A circuit for holding a signal sampled from the input signal, a circuit for detecting a peak value of the held sampling signal, a pulse value including the peak value of the sampled signal, and a mantissa of the input pulse signal from the position of the pulse value A circuit for calculating a part and a circuit for taking an average value of the mantissa part calculated from each of a plurality of input pulse signals, and comprising parameter calculation means for using the average value as a mantissa part of the input signal. A digital filter for pulse measurement.   The parameter calculation means includes a circuit that calculates a rise time of the input pulse signal and a circuit that takes an average value of the rise times calculated from each of the plurality of input pulse signals, and the average value is used as a delay amount. The digital filter for pulse measurement according to claim 1.   3. The digital filter for pulse measurement according to claim 2, wherein the parameter calculating means includes a circuit for calculating a digital filter coefficient from the mantissa part and the delay amount.