JP2009225851A - Processor device of endoscope - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to be returned into a state that an image processing is normally performed so as to perform a stable image display. <P>SOLUTION: An electric endoscope system 2 includes an electronic endoscope 10, a processor device 11, and a light source device 12. The processor device 11 includes: an image forming circuit 36 which takes in an imaging signal captured by a CCD 20 of the electronic endoscope 10 and forms image data of the imaging signal; a detected data addition circuit 39 which adds detected data to the image data; an image processing circuit 40 which executes image processing of the image data; a determination circuit 41 which compares the image-processed image data with determination data and determines whether the image data is abnormal or not; and an initialization circuit 43 which initializes an FPGA 49 constituting the image processing circuit 40 when determined to be abnormal by the determination circuit 41. In the FPGA 49 initialized by the initialization circuit 43, a logic circuit program is read again from a ROM 50 to reconstruct a logic circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an endoscope processor device that forms an image and processes an image from an imaging signal obtained by an imaging means of an endoscope.

  The processor device of the endoscope takes in an imaging signal obtained by imaging the inside of the subject with an imaging means (solid-state imaging device such as a CCD) of the endoscope, forms image data from the imaging signal, and further converts the image data into the formed image data Image processing such as noise reduction, blur correction, color correction, and white balance correction, or special image processing such as contour enhancement and color enhancement is performed for output, and an image is displayed on the monitor.

In the processor device, a programmable integrated circuit such as an FPGA (Field Programmable Gate Array) is used as described in Patent Document 1, for example, in order to execute the above-described image data formation and image processing. The programmable integrated circuit does not need to design a unique circuit for executing image data formation or image processing, and the logic circuit can be freely rewritten by reading a logic circuit program stored in advance. This process can be executed on a single chip. Also, the logic circuit can be easily changed in accordance with the specifications of the processor device.
JP 2005-152368 A

  However, in the programmable integrated circuit, the logic circuit may be destroyed due to the influence of external noise. In particular, during an operation using an endoscope, an instrument driven by a high voltage such as an electric knife may be used, and therefore, it is easily affected by noise. When the logic circuit data is destroyed, the image is disturbed or the image is not output, making it difficult to observe the inside of the subject. In this case, once the power is turned off and turned on again, the logic circuit is reconstructed in the programmable integrated circuit and the image can be observed. However, the power is turned off and turned on again until the image is displayed. Takes a long time. During this time, the patient's internal visual field cannot be secured, so that even if an unexpected situation occurs, it cannot be dealt with, and the patient is exposed to a dangerous state.

  In addition, when forming image data, it is formed with horizontal synchronization and vertical synchronization, but if the part that manages the vertical synchronization of the circuit that forms the image data malfunctions due to noise, it will shift to frame switching. Occurs, image data cannot be formed accurately, and the same problem as described above occurs.

  As a method of coping with this problem, it is conceivable to perform a software reset process on the image forming circuit at the timing of vertical synchronization in order to make sure that the frame is switched. However, this idea presupposes a processing system that handles only moving images and periodically receives vertical synchronization signals, and the endoscope system handles not only moving images but also still images. There is no function to perform a soft reset process.

  For this reason, if a malfunction occurs in the image forming circuit, there is no choice but to perform a hardware reset process. It is unrealistic to perform each timing of vertical synchronization.

  The present invention has been made in consideration of the above circumstances, and can easily return to a state in which image processing is normally executed, and can perform stable image display without being affected by noise. An object of the present invention is to provide an endoscopic processor device capable of performing the above-described operation.

  In order to achieve the above object, an endoscope processor device according to the present invention includes an image processing unit that forms image data from an imaging signal obtained by an imaging unit of an endoscope and performs image processing on the formed image data. And a detection data adding means for adding detection data to the imaging signal or the image data before performing at least one of the formation of the image data or the image processing. Determination of whether or not the image processing means is abnormal by comparing at least one of the image data formation or the image processing with the predetermined determination data And an initialization unit that initializes the image processing unit when the determination unit determines that there is an abnormality.

  The image processing unit is configured to be capable of executing a plurality of types of image processing, and includes a determination data storage unit that stores the determination data corresponding to each of the plurality of types of image processing. Preferably, the determination is performed by reading out the determination data corresponding to the content of the image processing from the determination data storage means.

  The detection data is for determining a vertical synchronization shift when the image data is formed, and the initialization unit preferably performs the initialization at the timing of the vertical synchronization.

  Note that the image processing unit preferably includes a non-programmable integrated circuit in which a logic circuit cannot be rewritten, and the initialization unit performs a reset process on the non-programmable integrated circuit.

  Further, the image processing means has a programmable integrated circuit that can rewrite the logic circuit by reading the logic circuit program, and the initialization means can cause the programmable integrated circuit to reread the logic circuit program. preferable. Furthermore, the detection data adding means includes the programmable integrated circuit, and the initialization means adds the logic to the programmable integrated circuit of the detection data adding means in addition to the programmable integrated circuit of the image processing means. It is preferable to reload the circuit program.

  The programmable integrated circuit is preferably an FPGA (Field Programmable Gate Array). The detection data adding means preferably adds the detection data to an invalid display area of an image represented by the image data.

  Further, the image processing means includes an image forming unit that forms the image data and an image processing unit that performs the image processing, and these are preferably provided on separate substrates.

  According to the processor device of the endoscope of the present invention, the detection data is added to the imaging signal or the image data, and at least one of the image data formation and the image processing is performed, and then the image data is predetermined. The image processing means is initialized by checking whether the image processing means is abnormal or not, and when it is determined that there is an abnormality, the apparatus itself is turned on again, It is possible to return to a state in which image processing is normally executed more easily than when performing a general reset process, and stable image display can be performed without being affected by noise.

  In FIG. 1, the electronic endoscope system 2 includes an electronic endoscope 10, a processor device 11, and a light source device 12. A power switch 13 for turning on / off the entire electronic endoscope system 2 is provided on the front surface of the processor device 11, and a light source 52 (see FIG. 2) is turned on / off on the front surface of the light source device 12. A lighting switch 14 is provided. The electronic endoscope 10 includes a flexible insertion portion 15 that is inserted into a body cavity, an operation portion 16 that is connected to a proximal end portion of the insertion portion 15, and a communication connector 17 that is connected to the processor device 11. And a light source connector 18 connected to the light source device 12 and a universal cord 19 connecting the operation section 16 and the connectors 17 and 18. The processor device 11 is electrically connected to the electronic endoscope 10 and the light source device 12, and comprehensively controls the operation of the entire electronic endoscope system 2.

  At the distal end of the insertion portion 15, a distal end portion 15 a in which a CCD 20 (see FIG. 2) for intra-body cavity photographing is incorporated is continuously provided. A bending portion 15b connecting a plurality of bending pieces is provided behind the tip portion 15a. The bending portion 15b is bent in the vertical and horizontal directions when the angle knob 21 provided in the operation portion 16 is operated and the wire inserted in the insertion portion 15 is pushed and pulled. Thereby, the front-end | tip part 15a is orient | assigned to the desired direction in a body cavity.

  In FIG. 2, an observation window 22 and an illumination window 23 are provided at the distal end portion 15a. An optical system 24 for capturing image light in the subject is attached to the back of the observation window 22, and a CCD 20 is attached to the back of the optical system 24. The CCD 20 has an interline transfer type structure, for example, and has a pixel arrangement in a honeycomb arrangement. The imaging device is not limited to the honeycomb array CCD 20 but may be a Bayer array CCD, and is not limited to the CCD, and may be a CMOS.

  In FIG. 3, the honeycomb-arranged CCD 20 is arranged in a checkered lattice (honeycomb) pattern in which the light receiving portions 25 constituting the pixels are shifted by a half pitch for each column. The light receiving unit 25 is provided with a color filter. Reference numerals R, G, and B are colors transmitted by the color filters respectively disposed in the light receiving unit 25, and R represents red, G represents green, and B represents blue. In the CCD 20, a row in which G color filters are arranged in a horizontal direction and a row in which every other R and B color filters are arranged in a horizontal direction are alternately arranged. When subject light is incident on the CCD 20, R, G, B subject light is incident on the light receiving unit 25 through the color filter, and signal charges generated by photoelectric conversion of the light receiving unit 25 are accumulated. Then, the signal charge is vertically transferred in accordance with a read pulse of a timing / driver circuit 37 described later, and further, the image charge is output by horizontal transfer.

  Returning to FIG. 2, signal lines 26 and 27 that pass through the insertion unit 15, the operation unit 16, and the universal cord 19 are connected to the CCD 20. The signal line 26 is connected to the processor device 11 via the universal cord 19 and the communication connector 17.

  Inside the communication connector 17 are an amplifier (hereinafter abbreviated as AMP) 28 connected to the signal line 27, a correlated double sampling / programmable gain amplifier (hereinafter abbreviated as CDS / PGA) 29, and an A / D. A converter (hereinafter abbreviated as A / D) 30 is provided. The AMP 28 amplifies the imaging signal output from the CCD 20 with a predetermined gain, and outputs this to the CDS / PGA 29.

  The CDS / PGA 29 performs correlated double sampling on the imaging signal amplified by the AMP 28 to reduce noise, and outputs it to the A / D 30. The A / D 30 converts the analog imaging signal output from the CDS / PGA 29 into a digital imaging signal and outputs the digital imaging signal. The digital imaging signal output from the A / D 30 is sent to the processor device 11 via the signal line 31.

  An irradiation lens 32 is provided in the back of the illumination window 23. The irradiation end of the light guide 33 faces the irradiation lens 32. The light guide 33 passes through the insertion portion 15, the operation portion 16, the universal cord 19, and the light source connector 18, and the incident end 33 a is exposed from the rear of the light source connector 18. The light guide 33 is formed by bundling a large number of optical fibers (for example, made of quartz).

  The processor device 11 is provided with a patient board 34 and a main board 35. The patient board 34 controls an image forming circuit 36, a timing / driver circuit 37, and the image forming circuit 36 and the timing / driver circuit 37. A sub-controller 38 is provided. The main board 35 includes a detection data adding circuit 39, an image processing circuit 40, a determination circuit 41, a ROM 42 (determination data storage means), an initialization circuit 43, a display circuit 44, and a system controller that comprehensively controls the processor device 11. 45 is provided. When the communication connector 17 of the electronic endoscope 10 is connected to the processor device 11, the CCD 20 is connected to the timing / driver circuit 37 via the signal line 26, and the A / D 30 is connected to the image forming circuit via the signal line 31. 36, respectively.

  The image forming circuit 36 performs various types of signal processing for forming image data from digital imaging signals. The image forming circuit 36 includes a DSP (Digital Signal Processor) 46 formed of a non-programmable integrated circuit. The DSP 46 is composed of a large number of arithmetic units, and a logic circuit for performing the above various signal processings is housed in one chip. The signal processing performed by the image forming circuit 36 includes color separation processing for separating an RGB signal (imaging signal) into a luminance signal and a color difference signal, a false color removal processing for the separated color difference signal, and a separated luminance signal and color difference signal. Matrix operation processing for forming image data composed of RGB signals by performing matrix operation, pixel interpolation processing for interpolating the defective pixels of the above-described honeycomb array CCD 20, gain correction, white balance adjustment, gamma correction, and the like are performed.

  The image forming circuit 36 performs the signal processing in synchronization with the horizontal synchronizing signal and the vertical synchronizing signal output from the timing / driver circuit 37. For example, when performing color separation processing, the RGB signal is separated into a luminance signal and a color difference signal and output in synchronization with the horizontal synchronization signal and the vertical synchronization signal.

  The signal processing performed by the image forming circuit 36 is not limited to those described above. For example, level adjustment processing for adjusting the black level, size conversion for conversion into the number of horizontal and vertical pixels suitable for display or storage, and the like. Processing etc. may be included.

  The image data formed by the image forming circuit 36 is output to the detection data adding circuit 39. The detection data adding circuit 39 adds detection data to the image data. As detection data to be added to image data in the present embodiment, as shown in FIG. 4, predetermined pixels located in an invalid display area 47 b masked by a display circuit 44 described later in the effective pixel area 47 of the image data. Is set so as to have a predetermined color and gradation value. For example, detection of pixels 48a to 48d adjacent to the four corners of the image data as the predetermined color is R color and the gradation value is the maximum value. Append data to image data. The image data to which the detection data is added by the detection data addition circuit 39 is output to the image processing circuit 40.

  The image processing circuit 40 includes an FPGA 49 and a ROM 50. The FPGA 49 is a kind of programmable integrated circuit in which the logic circuit can be rewritten by reading the logic circuit program from the ROM 50. When the FPGA 49 is initialized by the initialization circuit 43 described later, the logic circuit program for image processing is read from the ROM 50. The logic circuit is rewritten by reading. As a result, the logic circuit constructed in the image processing circuit 40 executes a plurality of types of image processing on the image data to which the detection data is added. The image processing circuit 40 is not limited to the FPGA, and other programmable integrated circuits such as CPLD (Complex Programmable Logic Device) may be used.

  The image processing performed on the image data by the image processing circuit 40 includes, for example, contour enhancement processing, enhancement processing of a specific color or region, brightness adjustment processing, or the like. The patient board 34 and the main board 35 are connected via an isolation device (not shown) such as a photocoupler. Thereby, the electronic endoscope 10 and the processor device 11 are insulated and separated.

  The image data that has been subjected to image processing by the image processing circuit 40 is output to the determination circuit 41. The ROM 42 stores determination data corresponding to each of a plurality of types of image processing performed by the image processing circuit 40. The determination circuit 41 reads predetermined determination data from the ROM 42 and compares the determination data with image data that has been subjected to image processing to determine whether or not the image processing circuit 40 has an abnormality. When there is no abnormality, the determination circuit 41 outputs the image data to the display circuit 44, and when there is an abnormality, the determination circuit 41 outputs an initialization instruction signal to the initialization circuit 43.

  As the determination data used for the collation in the determination circuit 41, image data in a state where the above-described detection data 48a to 48d is subjected to image processing according to the contents of the image processing executed in the image processing circuit 40. It is remembered. The determination data is compared with the image data that has been subjected to image processing. When the position, color, and gradation match, it is determined that there is no abnormality, and when it does not match, it is determined that there is an abnormality.

  The initialization circuit 43 initializes the image processing circuit 40 when receiving the initialization instruction signal. In the case of the present embodiment, since the image processing circuit 40 is configured by the FPGA 49, as an initialization process, the logic circuit program written in the FPGA 49 is erased, and the logic circuit program is read again from the ROM 50. The FPGA 49 is made to construct a logic circuit. The initialization circuit 43 initializes the image processing circuit 40 when the determination circuit 41 determines that there is an abnormality as described above, and when an initialization instruction signal is input from the system controller 45 when the power is turned on. To do.

  The display circuit 44 masks the image data output from the determination circuit 41, encodes and outputs the video signal, and displays the endoscopic image on a monitor 51 (see also FIG. 1) connected to the processor device 11 by cable. Display as. As shown in FIG. 4, the display circuit 44 masks the outside of the circular observation region 47a suitable for observation out of the effective pixel region 47 of the image data as an invalid display region 47b.

  The timing / driver circuit 37 is a driving pulse (vertical / horizontal scanning pulse or the like) for controlling the charge readout timing of the CCD 20, the shutter speed of the electronic shutter of the CCD 20, and the image forming circuit 36 and the image processing circuit 40. A horizontal synchronization signal and a vertical synchronization signal for performing various signal processes are generated.

  The light source device 12 includes a light source 52 that emits illumination light, a condenser lens 53, a light source control circuit 54, and a CPU 55 that controls the light source device 12 in an integrated manner. The illumination light emitted from the light source 52 is condensed by the condenser lens 53 and guided to the incident end 33 a of the light guide 33. The light source 52 is a discharge lamp such as a xenon lamp, but is not limited thereto, and a halogen lamp, LED (light emitting diode), fluorescent light emitting element lamp, or LD (laser diode) may be used.

  The light source control circuit 54 transforms the power supply voltage supplied when the power switch 13 is operated, and supplies the lighting power according to the lighting instruction signal input from the CPU 55 when the lighting switch 14 is operated to supply the light source 52. Lights up.

  The operation of the above configuration will be described with reference to the flowchart of FIG. When performing inspection with the electronic endoscope system 2, the connectors 17 and 18 of the electronic endoscope 10 are inserted into the processor device 11 and the light source device 12, and the processor device 11 and the light source device 12 are connected. 11 power switch 13 is turned on. When the power switch 13 is turned on, the processor device 11 and the light source device 12 are turned on, and power is supplied from the processor device 11 to the electronic endoscope 10.

  The electronic endoscope 10 is turned on by the supply of power from the processor device 11, and the CCD 20 is activated to start imaging. The imaging signal output from the CCD 20 is amplified, reduced in noise, and digitally converted by the AMP 28, CDS / PGA 29, and A / D 30, and output to the image forming circuit 36. The image forming circuit 36 forms image data from the digital imaging signal and outputs it to the detection data adding circuit 39. In the detection data adding circuit 39, the detection data 48a to 48d are added to the invalid display area 47b of the image data. The image data to which the detection data is added is subjected to image processing by the image processing circuit 40 and output to the determination circuit 41.

  Then, the determination circuit 41 collates the image data sent from the image processing circuit 40 with the determination data read from the ROM 42. If they match, the determination circuit 41 determines that there is no abnormality and sends it to the display circuit 44. Output image data. The image data masked by the display circuit 44 is displayed on the monitor, and the user can observe the inside of the subject with the image displayed on the monitor.

  On the other hand, if the image data and the determination data do not match, the determination circuit 41 determines that there is an abnormality and transmits an initialization instruction signal to the initialization circuit 43. The initialization circuit 43 to which the initialization instruction signal is input causes the FPGA 49 to read the logic circuit program in the ROM 50, initializes the image processing circuit 40, and reconstructs the logic circuit. As a result, due to the image processing circuit 40, the state where the image data is abnormal is instantaneously restored to the normal state.

  As described above, when there is an abnormality in the image data, the image processing circuit 40 is initialized, so that it is surely normal in a shorter time than when the processor device 11 is turned off and then turned on again as in the prior art. It is possible to easily return to a new state. As a result, even when a device having a high driving voltage such as a high-frequency knife is used nearby, the image can be stably displayed on the monitor without being affected by noise.

  In the above embodiment, the detection data 48a to 48d are added to the invalid display area 47b masked by the display circuit 44. However, the present invention is not limited to this. For example, as shown in FIG. The dummy area 56 may be added as detection data outside the effective pixel area 47 of the acquired image data. For example, if the number of pixels in the vertical direction of the effective pixel region 47 is 480 lines, the dummy region 56 is provided on the 481st line. The dummy area 56 of the 481st line is set to a predetermined color and luminance value. Then, the determination circuit 41 determines whether or not the dummy area 56 is normally processed. The dummy area 56 is deleted when masked by the display circuit 44 so that it is not output as image data for display.

  In the above embodiment, the image processing circuit 40 is composed of the FPGA 49 and the ROM 50. However, as shown in FIG. 7, the detection data adding circuit 39 may be composed of the FPGA 57 and the ROM 58. The FPGA 57 constructs a logic circuit by reading a logic circuit program from the ROM 58. In this configuration, when the determination circuit 41 determines that there is an abnormality in the image data, the initialization circuit 43 initializes the FPGA 57 together with the FPGA 49 and rereads the logic circuit program from the ROM 50 and ROM 58 to the FPGA 49 and FPGA 57, respectively. If the logic circuit data of the FPGA 57 has been destroyed, even if it is determined to be abnormal by the determination circuit 41, it will not return to a normal state if only the FPGA 49 is initialized, but the FPGA 57 is also initialized in the same way as the FPGA 49. It is possible to return to a normal state.

  In the above embodiment, when it is determined that there is an abnormality in the image data, the image processing circuit is initialized and returned to a normal state. However, the present invention is not limited to this, and the abnormality is detected. If it is determined that there is, the image forming circuit 36 may be initialized to return to a normal state. In the second embodiment of the present invention described below, the image forming circuit 36 is initialized when the image data output from the image forming circuit 36 is abnormal. In this case, as shown in FIG. 8, the detection data adding circuit 59 disposed on the output side of the A / D 30 and the input side of the DSP 46 constituting the image forming circuit 36, and the output side of the DSP 46 and the detection data adding circuit 39 A determination circuit 60 disposed on the input side and an initialization circuit 61 for initializing the DSP 46 are provided. In the detection data adding circuit 59, for example, with respect to a digital image pickup signal output from the A / D 30, an image pickup signal having a gradation value R <G is detected with respect to R and G pixels at predetermined positions. Respectively. The predetermined position to which the detection data is added is a pixel in the invalid display area 47b as in the above embodiment.

  The DSP 46 constituting the image forming circuit 36 operates alone to execute various signal processes after the power is turned on. Therefore, when the vertical synchronization signal and horizontal synchronization signal from the timing / driver circuit 37 and the operation of the DSP 46 are deviated, particularly when the operation of the DSP 46 is deviated with respect to the vertical synchronizing signal of the timing / driver circuit 37. Anomalies may occur in the image data. 9 shows a case where the DSP 46 operates normally in synchronization with the vertical synchronization signal from the timing / driver circuit 37 (FIG. 9A), and the operation of the DSP 46 with respect to the vertical synchronization signal from the timing / driver circuit 37. It is a conceptual diagram which shows (FIG.9 (B)) when deviation arises in.

  In the normal state shown in FIG. 9A, the columns 62a, 62c, 62e... Where the G image signals are arranged, and the columns 62b, 62d, 62f. The image pickup signal output alternately in synchronization with the horizontal synchronization signal H and further output in synchronization with the horizontal synchronization signal H is sequentially subjected to various signal processing in synchronization with the vertical synchronization signal V and output.

  On the other hand, as shown in FIG. 9B, in an example in which the operation of the DSP 46 is shifted with respect to the vertical synchronization signal from the timing / driver circuit 37, the row 62a in which the first G color image pickup signals are arranged. Is skipped, the column 62b in which the next R and B color image signals are arranged is erroneously recognized as the column 62a, and the image signals in the column 62a are not subjected to signal processing. The DSP 46 performs signal processing on the columns 62c, 62e,... In which the G color image signals are arranged, and outputs them as the columns 62b, 62d, 62f in which the R, B color image signals are arranged. As described above, the image data is formed based on the pixels of different positions and colors due to the deviation. Therefore, the monitor 51 displays an image whose position and color are different from the normal state. End up.

  The determination circuit 60 is in the same state as when the detection data is added to the image data, that is, whether or not the R and G pixels at predetermined positions added as the detection data have a gradation value R <G. Determine whether. When the image forming circuit 36 is in a normal state, the R and G pixels at the predetermined positions are output as normal image data with the gradation value R <G, but as described above, the image forming circuit 36 When the operation of the DSP 46 constituting the circuit 36 deviates from the vertical synchronization signal from the timing / driver circuit 37, the signal processing is performed with the row in which the G color image signals are arranged as the row in which the R and B color image signals are arranged. Therefore, the detection data added to the R and G pixels at the predetermined position will have oppositely sized gradation values, that is, R> G. Therefore, the determination circuit 60 determines that there is no abnormality when the gradation value of the pixel at the predetermined position is R <G, and determines that there is an abnormality when the gradation value is R> G. When there is no abnormality, the determination circuit 60 outputs image data. When there is an abnormality, the determination circuit 60 outputs an initialization instruction signal to the initialization circuit 61.

  The initialization circuit 61 initializes the image forming circuit 36 when receiving the initialization instruction signal. In the case of the present embodiment, since the image forming circuit 36 is configured by the DSP 46, the DSP 46 is reset at a timing synchronized with the vertical synchronizing signal of the timing / driver circuit 37 as an initialization process. The initialization circuit 61 configures the image forming circuit 36 when an initialization instruction signal is input from the system controller 45 when the power is turned on, as well as when the determination circuit 60 determines that there is an abnormality as described above. The DSP 46 is initialized. In this manner, when there is an abnormality in the image data, the DSP 46 constituting the image forming circuit 36 is initialized, so that, as in the above embodiment, the processor device 11 is turned off once and turned on again. It is possible to easily return to the normal state easily in time.

  The substance and the added position of the detection data exemplified in the above embodiment do not limit the present invention. For example, a specific mark may be added as detection data, or may be added to the observation region 47a. Furthermore, in the above-described embodiment, the determination circuits 41 and 60 determine that there is an abnormality once, and the initialization circuits 43 and 60 initialize immediately. However, the present invention is not limited to this, and the predetermined number of frames is continuously abnormal. It is good also as a structure initialized when it determines with.

  In the above-described embodiment, the image forming circuit 36 is configured from a non-programmable integrated circuit, and the image processing circuit 40 is configured from a programmable integrated circuit. However, the present invention is not limited thereto, and the image forming circuit 36 is configured from a programmable integrated circuit. The processing circuit 40 may be composed of a non-programmable integrated circuit.

  Moreover, in the said embodiment, although the structure which separated the processor apparatus and the light source device was mentioned as an example, this invention is not restricted to this, It is good also as a structure which integrated the processor apparatus and the light source device. . Furthermore, in the said embodiment, although the electronic endoscope is illustrated, it is not restricted to this, It can apply also to the ultrasonic endoscope with which the ultrasonic transducer was integrated in the front-end | tip part.

It is an external view of an electronic endoscope system. It is a block diagram which shows the outline of the electrical constitution of an electronic endoscope system. It is a top view which shows the outline of a structure of CCD of a honeycomb arrangement | sequence. It is a top view which shows an example of the detection data added to image data. It is a flowchart which shows the flow of a subject test | inspection. It is a top view which shows the example of the detection data different from FIG. It is a block diagram which shows the Example which comprises a detection data addition circuit by FPGA. FIG. 10 is a block diagram illustrating an embodiment of a configuration for initializing an image forming circuit when there is an abnormality in image data formed by the image forming circuit. 2 is a conceptual diagram illustrating a state in which an image forming circuit operates normally and a case where an abnormality has occurred. FIG.

Explanation of symbols

2 Electronic Endoscope System 10 Electronic Endoscope 11 Processor Device 12 Light Source Device 20 CCD
36 Image forming circuit 40 Detection data addition circuit 40 Image processing circuit 41 Judgment circuit 43 Initialization circuit 46 DSP
49,57 FPGA

Claims (9)

In an endoscope processor device including image processing means for forming image data from an imaging signal obtained by an imaging means of an endoscope and performing image processing on the formed image data,
Detection data adding means for adding detection data to the imaging signal or the image data before performing at least one of the formation of the image data or the image processing;
Determination means for determining whether or not there is an abnormality in the image processing means by comparing the image data with predetermined determination data after performing at least one of the formation of the image data or the image processing When,
An endoscope processor apparatus, comprising: an initialization unit that initializes the image processing unit when the determination unit determines that there is an abnormality. The image processing means is configured to be capable of executing a plurality of types of image processing,
Determination data storage means for storing the determination data corresponding to each of the plurality of types of the image processing;
The endoscope processor apparatus according to claim 1, wherein the determination unit reads the determination data corresponding to the content of the image processing from the determination data storage unit and performs the determination. The detection data is for determining a vertical synchronization shift when forming the image data,
The endoscope processor device according to claim 1, wherein the initialization unit performs the initialization at the timing of the vertical synchronization. The image processing means has a non-programmable integrated circuit in which the logic circuit cannot be rewritten,
4. The endoscope processor device according to claim 1, wherein the initialization unit performs a reset process on the non-programmable integrated circuit. The image processing means has a programmable integrated circuit capable of rewriting a logic circuit by reading a logic circuit program,
5. The endoscope processor device according to claim 1, wherein the initialization unit causes the programmable integrated circuit to re-read the logic circuit program. The detection data adding means has the programmable integrated circuit,
6. The endoscope according to claim 5, wherein the initialization unit causes the programmable integrated circuit of the detection data adding unit to reread the logic circuit program in addition to the programmable integrated circuit of the image processing unit. Mirror processor device.   7. The endoscope processor apparatus according to claim 5, wherein the programmable integrated circuit is an FPGA (Field Programmable Gate Array).   The endoscope processor device according to any one of claims 1 to 7, wherein the detection data adding means adds the detection data to an invalid display area of an image represented by the image data.   2. The image processing unit includes an image forming unit that forms the image data and an image processing unit that performs the image processing, which are provided on different substrates. 8. The processor unit for an endoscope according to any one of claims 8 to 10.

Images