JP2009212618A - Image detector - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a feedthrough that is superimposed on a signal charge to be transmitted through a data wiring with high accuracy regardless of a variations in parasitic capacity. <P>SOLUTION: A substrate 24 where pixel parts 30 provided with a storage capacity 26 for storing charges generated on a photoelectric conversion layer in accordance with irradiated radiation and a TFT 28 to be turned on by an on signal from gate wiring 34 are arrayed in the shape of a matrix includes a dummy pixel group 77 provided with a dummy wiring 82 intersecting each data wiring 36 and a TFT 78 corresponding to each data wiring 36, wherein a correcting capacity 116 is connected to each data wiring 36. When the TFT 28 of the pixel part 30 is turned on, the feeding of the on signal to the dummy wiring 82 is stopped and the application of voltage to the correcting capacity 116 is stopped, and when the TFT 28 is turned off, the feeding of the on signal to the dummy wiring 82 is resumed and the application of the voltage to the correcting capacity 116 is resumed to thereby cancel a feedthrough generated by the parasitic capacity 38 and the correcting capacity 116 on the data wiring 36 by a feedthrough generated by the parasitic capacity 84 and the correcting capacity 116. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image detection apparatus, and in particular, a plurality of pixel units each including a switching unit that is turned on and off according to a signal voltage supplied via a gate wiring, a holding unit that holds a signal charge, a gate wiring, The present invention relates to an image detection apparatus including a plurality of data lines connected to different pixel portions so as to transmit signal charges held in a holding portion of a pixel portion while they are crossed and a switching unit is turned on.

  In radiography for medical diagnosis, the radiation that has passed through the subject is irradiated to a radiation detector that includes a photoelectric conversion layer that is sensitive to radiation, and the radiation detector is applied according to the radiation dose to the radiation detector. A system that obtains a digital radiographic image by sequentially reading the accumulated charges as a current for each readout unit region and converting the read current into digital data is known. In addition, as a radiation detector, radiation detection with a configuration in which a photoelectric conversion layer is formed on a TFT active matrix substrate in which a large number of TFTs (Thin Film Transistors) arranged in a matrix and signal wiring are formed on a glass substrate. Panels are also known.

  By the way, when a large number of switching elements such as TFTs are arranged in a matrix like a TFT active matrix substrate, a plurality of gate wirings for turning on and off the switching elements and signal charges from the pixels on which the switching elements are turned on are obtained. Since a plurality of data lines for transmission are arranged in an intersecting manner, the voltage applied to the parasitic capacitance existing at the intersection of the gate line and the data line connected to the switching element when the switching element is turned on and off As a result, the noise component (hereinafter referred to as “feedthrough”) is superimposed on the signal charge transmitted through the data wiring. In particular, since the radiation detection panel has a small amount of charge held and accumulated in each pixel, the feedthrough level is larger than the signal charge level transmitted through the data wiring, and the output signal is influenced by the feedthrough. The S / N ratio and the dynamic range of signal components in the output signal are significantly reduced.

  The feedthrough generated when the switching element is turned on and off due to the parasitic capacitance described above has the same level and the opposite polarity, so that the integration period of the signal charge in the charge amplifier at the subsequent stage connected to each data line is If a period from when the switching element is turned on to when a predetermined time elapses after the switching element is turned off (a period until the signal charge including the feedthrough transmitted through the data wiring becomes 0) is set, the switching element is turned on. In principle, it is possible to eliminate the influence of feedthrough from the output signal of the charge amplifier (signal charge integration result) by canceling off the feedthrough and the off-time feedthrough (for example, see Patent Document 1). reference). In reality, however, the feedthrough level is higher than the signal charge level, so that the integrated charge saturation occurs during the integration period of the charge amplifier, so that the effects of feedthrough can be accurately eliminated. However, the S / N ratio of the output signal of the charge amplifier and the dynamic range of the signal component in the output signal are not sufficiently improved.

In relation to the above, in Patent Documents 2 and 3, dummy pixels that do not hold and accumulate signal charges are provided on the radiation detection panel, and the adjustment TFTs of the dummy pixels are turned on and off at the timing opposite to that of the normal pixel TFTs. Thus, a technique for canceling the feedthrough caused by the parasitic capacitance in the normal pixel on the data wiring by the feedthrough caused by the parasitic capacitance in the dummy pixel is disclosed.
JP 2006-101396 A JP 2001-56382 A JP 2004-37382 A

  However, the capacitance of each parasitic capacitance that exists at the intersection of the gate wiring and the data wiring varies due to manufacturing errors, and accordingly, the feedthrough level generated by each parasitic capacitance also varies. Variation occurs. In the techniques described in Patent Documents 2 and 3 described above, the capacitance of the parasitic capacitance in the dummy pixel coincides with the capacitance of the parasitic capacitance in the normal pixel connected to the same data wiring as the dummy pixel. If this is the case, the feedthrough caused by the parasitic capacitance of the normal pixel can be accurately canceled on the data wiring, but in reality, the capacitance of the parasitic capacitance of the dummy pixel is connected to the same data wiring. Most of them are different from the capacitance of the parasitic capacitance of the normal pixel, and the feedthrough of the feedthrough superimposed on the individual data wiring caused by the variation in the capacitance of the parasitic capacitance in each normal pixel is different. There is a problem in that feedthrough caused by parasitic capacitance cannot be accurately suppressed on each data wiring due to the influence of level variation.

  The present invention has been made in consideration of the above facts, and can provide an image detection device capable of accurately suppressing feedthrough superimposed on a signal charge and transmitted through a data wiring regardless of variations in parasitic capacitance. Is the purpose.

  In order to achieve the above object, an image detection apparatus according to a first aspect of the present invention includes a switching unit that is turned on / off according to a signal voltage supplied via a gate wiring, and a holding unit that holds a signal charge. A signal group that is provided so as to intersect with the gate wiring and a pixel group that includes a plurality of pixel portions, and that is held in the holding portion of the pixel portion while the switching unit is on is transmitted. As described above, a plurality of data lines connected to different pixel portions of the pixel group, a plurality of correction capacitors respectively connected to different data lines of the plurality of data lines, and the plurality of corrections Each of the storage capacitors has a correction voltage applying means capable of applying a first correction voltage of an arbitrary magnitude independent of each other for an arbitrary period.

  According to the first aspect of the present invention, there is provided a pixel group composed of a plurality of pixel portions each including a switching means that is turned on / off in response to a signal voltage supplied via a gate wiring and a holding portion that holds a signal charge. ing. A plurality of data lines are provided so as to cross the gate lines, and the plurality of data lines transmit the signal charges held in the holding portion of the pixel portion during the period when the switching unit is turned on. In this way, the pixel groups are connected to different pixel portions. According to a tenth aspect of the present invention, there is further provided a conversion unit that converts irradiated radiation or electromagnetic waves into electric charges, and the holding units of the individual pixel units hold the electric charges converted by the conversion units as signal charges. It may be a configuration. In this case, each of the holding portions of the pixel portions holds charges having a charge amount corresponding to the radiation or electromagnetic wave irradiation amount at the position of each pixel portion.

  As described above, in the first aspect of the present invention, since the plurality of data lines intersect with the gate lines, there are parasitic capacitances at the intersections between the gate lines and the individual data lines. When the switching means of each pixel unit is turned on and off, the magnitude of the signal voltage supplied through the gate wiring changes, and accordingly, the potential difference between the gate wiring and the individual data wiring (that is, the individual parasitics). When the magnitude of the voltage applied to the capacitor changes, feedthrough occurs due to the individual parasitic capacitance, and the generated feedthrough is transmitted through the individual data wiring. Further, the level of feedthrough generated by each parasitic capacitance corresponds to the amount of charge held in each parasitic capacitance, and the amount of charge Q = capacitance C × voltage V. Since the capacitance C varies due to an error or the like, the amount of charge Q held in each parasitic capacitance, that is, the level of feedthrough transmitted through each data wiring also varies.

On the other hand, according to the first aspect of the present invention, even if the parasitic capacitance and the capacitance C are different capacitances, the charge amount Q, that is, the generated feedthrough is generated by adjusting the voltage V based on Q = CV. (C ₁ V ₁ = C ₂ V ₂ : where C ₁ is the capacitance of the parasitic capacitance, V ₁ is the voltage of the parasitic capacitance, C ₂ is the capacitance of another capacitance, and V ₂ is A plurality of correction capacitors connected to different data wirings among the plurality of data wirings, and each of the plurality of correction capacitors has an arbitrary size independent from each other. A correction voltage applying means capable of applying the first correction voltage for an arbitrary period is provided.

  As a result, even if the feedthrough level generated by the parasitic capacitance and transmitted through the individual data wiring varies due to variations in the capacitance of the parasitic capacitance, the feedthrough (hereinafter referred to as the feedthrough generated by the individual correction capacitance) The feedthrough generated by the correction capacitor is referred to as a “correction signal component” for convenience), but the first correction voltages applied to the individual correction capacitors are mutually connected so that the feedthrough generated by the parasitic capacitance is at the same level. In addition to being able to adjust independently, by adjusting the period during which the first correction voltage is applied to each correction capacitor, at the same timing as the occurrence of feedthrough due to each parasitic capacitance, It is possible to generate correction signal components in the opposite direction to the generated feedthrough by the individual correction capacitors. The feedthrough generated by the individual parasitic capacitors and transmitted through the individual data lines, and the correction signal generated by the individual correction capacitors regardless of the variation in the level of the feedthrough transmitted through the individual data lines. By the component, it becomes possible to cancel with high accuracy on each data wiring. Therefore, according to the first aspect of the present invention, it is possible to accurately suppress the feedthrough that is superimposed on the signal charge and transmitted through the data wiring, regardless of variations in parasitic capacitance.

  In the first aspect of the present invention, the plurality of pixel portions, the gate lines, and the plurality of data lines constituting the pixel group may be formed in a single panel. In this case, as the correction capacitor, For example, as described in claim 2, the first dummy wiring intersecting with the data wiring is formed in the panel, so that the parasitic capacitance generated between the data wiring and the first dummy wiring or disposed outside the panel In addition, an external capacitor connected to the data wiring can be used. For example, the parasitic capacitance generated by the first dummy wiring formed in the panel can be generated by the same process as the parasitic capacitance in each pixel unit, and the parasitic capacitance and characteristics in each pixel unit (for example, electrostatic capacitance against temperature change). Therefore, when the above-described parasitic capacitance is used as the correction capacitor, it is possible to more accurately suppress feedthrough transmitted through the data wiring. Further, when the above-described external capacitor is used as the correction capacitor, it is not necessary to provide the first dummy wiring in the panel, so that an increase in the area of the panel can be suppressed and a complicated configuration of the panel can be avoided. .

  In the first aspect of the present invention, for example, as described in the third aspect, a first storage unit that stores the magnitude of the first correction voltage applied to each of the plurality of correction capacitors, and a plurality of correction capacitors The correction voltage application unit is controlled so that the application of the first correction voltage having the magnitude stored in the first storage unit is started when the switching unit is turned off and stopped when the switching unit is turned on. It is preferable to further provide first correction means. Thus, the correction signal component having the same level and the opposite direction as the feedthrough generated by the individual parasitic capacitance can be generated at the same timing as the occurrence of the feedthrough due to the individual parasitic capacitance. Therefore, the feedthrough generated by the individual parasitic capacitance and transmitted through the individual data wiring is corrected by the correction capacitor generated regardless of the variation in the level of the feedthrough transmitted through the individual data wiring. Signal components can be canceled with high accuracy on individual data wirings, and feedthroughs that are superimposed on signal charges and transmitted through the data wirings can be accurately suppressed regardless of variations in parasitic capacitance.

  According to a third aspect of the present invention, the correction voltage applying means includes a plurality of first D / A converters for converting the input correction data into a first correction voltage having a magnitude corresponding to the value of the correction data. And for correcting the first correction voltage output from the first D / A converter by being respectively turned on and off between each first D / A converter and each correction capacitor. A plurality of switching elements capable of switching between application start and application stop of the capacitor. In this case, for example, as described in claim 4, the first storage unit includes a plurality of corrections. A plurality of correction data representing the magnitude of the first correction voltage to be applied to each of the capacitors is stored, and the first correction unit stores the correction data stored in the first storage unit into each first D / D. Each input to A conversion, and on / off of multiple switching elements By controlling, for each of the plurality of correction capacity, the switching means a first correction voltage of a magnitude representing the correction data can be configured to time applied are turned off.

  According to a third aspect of the present invention, a plurality of pixel groups are provided, and the switching means of each pixel group selects a single or a plurality of pixel groups according to signal voltages supplied through different gate wirings. The unit may be turned on in different periods. In this case, for example, as described in claim 5, the first storage unit stores the first correction voltage applied to each of the plurality of correction capacitors. The size is stored in units of a group of pixels that are turned on while the switching means is synchronized, and the first correction means starts applying when the switching means is turned off, and stops applying when the switching means is turned on. So that the first correction voltage to each of the correction capacitors matches the magnitude of the first correction voltage stored in the first storage unit corresponding to the pixel group to which the switching means to be turned on / off belongs. It may be controlled correction voltage applying means.

  As described above, when a plurality of pixel groups are provided, the feed-through that is transmitted through the individual data lines when the switching means is turned on and off is generated depending on the number of pixel groups that the switching means is turned on during the same period. Since the number of parasitic capacitances to be different is different, the level of feedthrough transmitted through the data wiring is also different. On the other hand, according to the fifth aspect of the present invention, the magnitude of the first correction voltage applied to each of the plurality of correction capacitors is set in the first storage unit in units of the pixel group in which the switching means is turned on during the synchronization. The first correction voltage to each of the plurality of correction capacitors that are stored and started when the switching means is turned off and stopped when the switching means is turned on corresponds to the pixel group to which the switching means that is turned on and off belongs. Since the correction voltage application means is controlled so as to coincide with the magnitude of the first correction voltage stored in the first storage unit, the number of pixel groups in which the switching means is turned on during the synchronization (individual data wiring Regardless of the number of parasitic capacitances that are the source of the feedthrough that is transmitted), the feedthrough that is transmitted through the data wiring can be accurately suppressed.

  In the invention according to claim 5, the number of pixel groups in which the switching means is turned on during the synchronization may be switchable. In this case, the switching means is turned on in the first storage section during the synchronization. A plurality of data groups representing the magnitude of the first correction voltage applied to each of the plurality of correction capacitors in units of pixel groups are stored for each number of pixel groups in which the switching means is turned on during synchronization. What is necessary is just to comprise so that a correction | amendment voltage application means may be controlled using the data group corresponding to the number of the pixel groups to which a switching means is turned on between synchronization among the several data groups memorize | stored in 1 memory | storage part.

  The magnitude of the first correction voltage stored in the first storage unit is determined based on, for example, the result of measuring the feedthrough level and stored in advance in the first storage unit. The first correction voltage may be fixedly applied to each of the plurality of correction capacitors without updating the magnitude of the first correction voltage stored in advance in the storage unit. In the invention described in claim 5, the first correction means may be applied to a single or a plurality of gate wirings in a state where the signal charges are not held in the holding portions of the individual pixel portions as described in claim 6, for example. A first compensation to be applied to each of the plurality of correction capacitors when the on / off switching means is turned on / off based on the magnitude of the voltage fluctuation in the individual data wiring, which is generated when the connected switching means is turned on / off. It may be configured to be stored in the first storage unit to determine the magnitude of the voltage.

  There is a possibility that the capacitance of each parasitic capacitance varies with a change in ambient temperature, and in this case, the feedthrough level generated by the parasitic capacitance and transmitted through the data wiring also varies. On the other hand, in the invention according to claim 6, the switching means connected to the single or plural gate wirings is turned on / off in a state where the signal charges are not held in the holding portions of the individual pixel portions. The magnitude of the first correction voltage to be applied to each of the plurality of correction capacitors when the on / off switching means is turned on / off is determined based on the magnitude of the voltage fluctuation (feedthrough level) generated in each data wiring. Therefore, even when the feedthrough level fluctuates due to a change in the ambient temperature or the like, the level of the correction signal component generated by the correction capacitor is changed after the fluctuation. Can be matched. Accordingly, processing such as determination of the magnitude of the first correction voltage and storage in the first storage unit is periodically performed (for example, when the signal charge is supplied to the holding unit of each pixel unit at a certain time or when the ambient temperature changes). By performing this at a timing just before the signal is held, feedthrough transmitted through the data wiring can be accurately suppressed regardless of changes in the ambient temperature.

  Further, in the invention according to any one of claims 1 to 6, a plurality of pixel groups are provided, and the switching means of each pixel group is in accordance with signal voltages supplied via different gate wirings. In the case of a configuration in which a single pixel group or a plurality of pixel groups are turned on in different periods, for example, as described in claim 7, connected to a second dummy wiring provided so as to intersect with a plurality of data wirings A dummy pixel group including a plurality of dummy pixel portions each provided with a correction switching means that is turned on / off in response to a second correction voltage supplied via the second dummy wiring, and a second applied to the second dummy wiring. A second storage unit that stores the magnitude of the correction voltage in units of a pixel group that is turned on while the switching unit is synchronous, and a plurality of dummy pixel unit correction scans when the switching unit is turned off. The second correction voltage to be applied to the second dummy wiring during the period when the correction switching means is turned on while turning on the switching means and turning off the correction switching means of the plurality of dummy pixel portions when the switching means is turned on. There may be further provided second correction means for matching the magnitude of the second correction voltage stored in the second storage unit corresponding to the pixel group to which the switching means to be turned on / off belongs.

  According to the seventh aspect of the present invention, since the second dummy wiring is provided so as to intersect with the plurality of data wirings, a parasitic capacitance (hereinafter referred to as this parasitic capacitance) is provided at the intersection between the second dummy wiring and each data wiring. Each capacitance is referred to as a “correction parasitic capacitance” for convenience. The correction switching means of each dummy pixel portion is configured to be turned on / off according to the second correction voltage supplied via the second dummy wiring, and the magnitude of the second correction voltage applied to the second dummy wiring is large. Are stored in the second storage unit in units of pixel groups in which the switching means is turned on during the synchronization. The second correction means turns on the correction switching means for the plurality of dummy pixel portions when the switching means is turned off, and turns off the correction switching means for the plurality of dummy pixel portions when the switching means is turned on. The second correction voltage to be applied to the second dummy wiring during the period when the switching unit is on is the magnitude of the second correction voltage stored in the second storage unit corresponding to the pixel group to which the switching unit to be turned on / off belongs. To match. Thus, correction signal components in the opposite direction to the feedthrough generated by the individual parasitic capacitances are generated by the individual correction parasitic capacitances at the same timing as the occurrence of the feedthrough due to the individual parasitic capacitances.

  Thus, in the invention according to claim 7, since the same voltage (second correction voltage) is applied to each correction parasitic capacitance via the second dummy wiring, each data wiring is transmitted. It is impossible to adjust the levels of the correction signal components generated by the individual correction parasitic capacitors independently of each other in accordance with the variation in the feedthrough level. However, the magnitude of the second correction voltage applied to the second dummy wiring can be switched in units of the pixel group in which the switching means is turned on during the synchronization, so that it is generated by the parasitic capacitance and transmitted through the data wiring. It is possible to roughly suppress (correct) the feedthrough in units of a pixel group in which the switching means is turned on during the synchronization, and the first independent of each of the plurality of correction capacitors connected to the data wiring. By using together with suppression (correction) of feedthrough by applying a correction voltage, it is possible to obtain an effect such as improvement in accuracy of suppressing feedthrough transmitted through the data wiring.

  That is, for example, when the number of pixel groups in which the switching means is turned on in the same period is switched, the number of parasitic capacitances that are the source of feedthrough that is transmitted through the individual data wirings changes, so that the individual data wirings The level of feedthrough that is transmitted will also vary significantly. For this reason, regardless of the number of pixel groups in which the switching means is turned on during the same period, feedthrough is suppressed by applying the first correction voltages independent of each other to each of the plurality of correction capacitors connected to the data lines. (Correction) When the difference between the maximum value and the minimum value of the first correction voltage is increased, the unit change width of the first correction voltage is also increased, and accordingly, accuracy in suppression (correction) of feedthrough is increased. For example, as the first D / A converter according to claim 3, a D / A converter capable of inputting a larger number of bits is required, and the configuration becomes complicated. .

  On the other hand, as in the seventh aspect of the present invention, the first correction voltage independent from each other is applied to each of the plurality of correction capacitors connected to the data wiring, and each of the plurality of correction capacitors is individually connected via the second dummy wiring. When the feedthrough is suppressed (corrected) in combination with the application of the second correction voltage to the correction parasitic capacitance, for example, the second correction voltage is switched according to the number of pixel groups that are switched on during the synchronization. Etc., the difference between the maximum value and the minimum value of the first correction voltage can be reduced (the unit change width of the first correction voltage can be reduced), thereby improving the accuracy in suppressing (correcting) feedthrough. This can be realized without incurring complexity.

  In the invention according to claim 7, the second correction means converts the input correction data into a second correction voltage having a magnitude corresponding to the value of the correction data, and a second D / A converter. A dummy wiring drive unit that turns on and off the correction switching means of each of the plurality of dummy pixel units by switching the start and stop of application of the second correction voltage output from the second D / A converter to the second dummy wiring. In this case, for example, as described in claim 8, correction data representing the magnitude of the second correction voltage applied to the second dummy wiring is stored in the second storage unit. , Each pixel group in which the switching means is turned on during synchronization is stored as a unit, and the second correction means is stored in the second storage unit corresponding to the pixel group to which the switching means to be turned on / off belongs. Second data Application of the second correction voltage to the second dummy wiring is started when the switching means is turned off, and the second correction voltage is applied to the second dummy wiring when the switching means is turned on. The dummy wiring driving unit can be configured to be stopped.

  The magnitude of the second correction voltage stored in the second storage unit is also determined based on, for example, the result of measuring the feedthrough level, and stored in advance in the second storage unit. 8. The invention according to claim 7, wherein the second correction voltage stored in advance in the storage unit may be fixedly used for applying the second correction voltage to the second dummy wiring without being updated. In the second correction means, for example, as described in claim 9, the switching means connected to the single or plural gate wirings in a state where the signal charges are not held in the holding portions of the individual pixel portions. The magnitude of the second correction voltage to be applied to the second dummy wiring when the on / off switching means is turned on / off is determined on the basis of the magnitude of the voltage fluctuation in the individual data wiring generated by each turning on / off. It may be configured to be stored in the second storage unit.

  As described above, the level of the feedthrough generated by the parasitic capacitance and transmitted through the data wiring may vary with a change in ambient temperature or the like. On the other hand, according to the ninth aspect of the present invention, the switching means connected to the single or plural gate lines is turned on / off in a state where the signal charges are not held in the holding portions of the individual pixel portions. The magnitude of the second correction voltage to be applied to the second dummy wiring when the on / off switching means is turned on / off is determined based on the magnitude of the voltage fluctuation (feedthrough level) generated in each data wiring. Since it is stored in the second storage unit, the level of the correction signal component generated by the correction parasitic capacitance can be adjusted according to the change in the feedthrough level even when the feedthrough level fluctuates due to a change in ambient temperature or the like. Can be changed. Therefore, processing such as determination of the magnitude of the second correction voltage and storage in the second storage unit is periodically performed (for example, when the signal charge is applied to the holding unit of each pixel unit at a certain time or when the ambient temperature changes). By performing this at a timing just before the signal is held, feedthrough transmitted through the data wiring can be accurately suppressed regardless of changes in the ambient temperature.

  As described above, according to the present invention, a plurality of data lines connected to different pixel portions are gated so as to transmit the signal charges held in the holding portion of the pixel portion during the period when the switching unit is turned on. Each of the plurality of correction capacitors is connected to different data wirings among the plurality of data wirings, and each of the plurality of correction capacitors has an arbitrary size independent from each other. Since the correction voltage applying means that can apply the first correction voltage for an arbitrary period is provided, the feedthrough that is superimposed on the signal charge and transmitted through the data wiring can be accurately performed regardless of variations in parasitic capacitance. It has an excellent effect that it can be suppressed.

  Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a radiographic image capturing system 10 according to the present embodiment. The radiographic imaging system 10 includes a radiation generation unit 12 that generates radiation (for example, X-rays (X-rays) and the like), a radiation detection panel 14 that is spaced apart from the radiation generation unit 12, a microcomputer, and various electric devices. A control device 16 configured to include a circuit and acquire image information from the radiation detection panel 14 and perform various processes is provided. Between the radiation generation unit 12 and the radiation detection panel 14 is an imaging position where the subject 18 is positioned at the time of imaging, and carries image information by passing through the subject 18 emitted from the radiation generation unit 12 and positioned at the imaging position. The irradiated radiation is applied to the radiation detection panel 14. In the radiographic image capturing system 10, the radiation detection panel 14 and the control device 16 correspond to the image detection device according to the present invention.

  As shown in FIG. 2, the radiation detection panel 14 has a configuration in which a bias electrode 20 connected to a high-voltage power supply (not shown), a photoelectric conversion layer 22 that absorbs radiation and changes to a charge, and a TFT active matrix substrate 24 are sequentially stacked. Has been. The photoelectric conversion layer 22 is made of amorphous a-Se (amorphous selenium) containing, for example, selenium as a main component (for example, a content rate of 50% or more), and when irradiated with radiation, a charge corresponding to the amount of irradiated radiation. By generating a certain amount of charge (electron-hole pairs) internally, the irradiated radiation is converted into a charge. Thereby, the image information carried by the irradiated radiation is converted into charge information. The photoelectric conversion layer 22 corresponds to the conversion unit described in claim 10.

  As shown in FIG. 3, the TFT active matrix substrate 24 is provided with a storage capacitor 26 for storing the charge generated in the photoelectric conversion layer 22 and a TFT 28 for reading out the charge stored in the storage capacitor 26. A large number of pixel units 30 (in FIG. 3, the bias electrodes 20 and the photoelectric conversion layers 22 corresponding to the individual pixel units 30 are schematically shown as photoelectric conversion units 32) are arranged in a matrix. 3, a plurality of gate wirings 34 extending along the arrow A direction in FIG. 3 for turning on and off the TFTs 28 of the individual pixel portions 30, and extending along the arrow B direction orthogonal to the arrow A direction in FIG. A plurality of data wirings 36 are also provided for reading out stored charges from the storage capacitor 26 via the turned-on TFT 28.

  Note that the gate wiring 34 is a row of a pixel portion composed of a plurality of pixel portions 30 arranged in a matrix on the TFT active matrix substrate 24 along the direction of arrow A in FIG. The same number of rows of pixel portions as each other is provided, and each gate wiring 34 is connected to a row of different pixel portions (each individual pixel portion 30 constituting each). In addition, the data wiring 36 is a pixel unit array including a plurality of pixel units 30 arranged in a matrix on the TFT active matrix substrate 24 and arranged in the direction of arrow B in FIG. The same number of pixel unit columns as the number of pixel unit columns are provided, and the plurality of data wirings 36 are connected to different pixel unit columns (individual pixel units 30 constituting each).

  Of the large number of pixel units 30 provided on the TFT active matrix substrate 24, a plurality of pixel units 30 connected to the same gate wiring 34 (each pixel unit 30 constituting a single row of the pixel units). ) Corresponds to the pixel group according to the present invention, the storage capacitor 26 is the holding unit according to the present invention, the TFT 28 is the switching means according to the present invention, the gate wiring 34 is the signal voltage wiring according to the present invention, the data Each wiring 36 corresponds to each data wiring according to the present invention. In addition, parasitic capacitances 38 exist at the intersections between the gate lines 34 and the data lines on the TFT active matrix substrate 24.

  As shown in FIG. 3, each pixel portion 30 of the TFT active matrix substrate 24 is formed on a glass substrate 50 as a support substrate. As the glass substrate 50, for example, an alkali-free glass substrate (for example, # 1737 manufactured by Corning) can be used. In each pixel unit 30, a gate electrode 52, a storage capacitor lower electrode 54, a gate insulating film 56, a semiconductor layer 58, a source electrode 60, a drain electrode 62, a storage capacitor upper electrode 64, an insulating protective film are formed on a glass substrate 50. 66, an insulating protective film 68, and a charge collecting electrode 70 are formed. Of these, the gate electrode 52, the gate insulating film 56, the source electrode 60, the drain electrode 62, and the semiconductor layer 58 constitute the TFT 28 described above, and a storage capacitor. The lower electrode 54, the gate insulating film 56, and the storage capacitor upper electrode 64 constitute the storage capacitor 26 described above. Although illustration is omitted, a gate wiring 34 is also formed on the metal layer on which the gate electrode 52 of the TFT 28 is formed. The gate electrode 52 of the TFT 28 is connected to the gate wiring 34, the source electrode 60 of the TFT 28 is connected to the data wiring 36, and The drain electrode 62 of the TFT 28 is connected to the storage capacitor upper electrode 64.

The gate insulating film 56 is made of SiN _X , SiO _X, or the like, and is provided so as to cover the gate electrode 52, the gate wiring 34, the storage capacitor lower electrode 54, and the storage capacitor wiring 56. In the region covering the storage capacitor lower electrode 54, it functions as a dielectric layer in the storage capacitor 26. Accordingly, a region sandwiched between the storage capacitor lower electrode 54 and the storage capacitor upper electrode 64 functions as the storage capacitor 26. The semiconductor layer 58 functions as a channel portion of the TFT 28, and the source electrode 60 and the drain electrode 62 are electrically connected via the semiconductor layer 58. Further, the insulating protective film 66 is formed over almost the entire surface (substantially the entire region) corresponding to the single pixel portion 30 on the glass substrate 50, and protects and electrically protects the drain electrode 62 and the source electrode 60. Insulation separation is realized. A contact hole 72 is formed in a portion of the insulating protective film 66 that faces the storage capacitor lower electrode 54.

  The charge collection electrode 70 is made of an amorphous transparent conductive oxide film, is formed so as to fill the contact hole 72, and is formed above the source electrode 60, the drain electrode 62, and the storage capacitor upper electrode 64. The charge collection electrode 70 and the photoelectric conversion layer 22 are electrically connected, and the charge generated in the photoelectric conversion layer 22 is collected by the charge collection electrode 70. The insulating protective film 68 is made of a photosensitive acrylic resin, and realizes electrical isolation between the TFT 28 and other portions. A contact hole 72 passes through the insulating protective film 68, and the charge collection electrode 70 is connected to the storage capacitor upper electrode 64 via the contact hole 72.

  Further, on the TFT active matrix substrate 24 of the radiation detection panel 14 according to the present embodiment, a dummy pixel group 77 including a plurality of dummy pixel portions 76 arranged in a line along the arrow A direction in FIG. A single dummy wiring 82 extending along the arrow A direction is provided. Each dummy pixel section 76 includes a storage capacitor 80 and a TFT 78 as in the normal pixel section 30, and the gate of the TFT 78 is connected to a dummy wiring 82. The dummy pixel group 77 is provided in a region of the TFT active matrix substrate 24 where charge generation according to the radiation dose by the photoelectric conversion layer 22 is not performed, and radiation irradiation to the radiation detection panel 14 is performed. Regardless, no charge is stored in the storage capacitor 80 of the dummy pixel section 76.

  In addition, formation of the area | region where electric charge generation | occurrence | production according to irradiation radiation dose is not performed removes the photoelectric converting layer 22 of the said area | region, or provides the member which interrupts | emits the radiation to the photoelectric converting layer 22 in the said area | region. Can be realized. In addition, as shown in FIG. 3, the parasitic capacitance 84 is also present at the intersection of the dummy wiring 82 and the data wiring, but the individual dummy pixel portion 76 and the dummy wiring 82 are connected to the normal pixel portion 30 and the dummy wiring 82. Since it is formed on the glass substrate 50 by the same process as the gate wiring 34 and the like, the parasitic capacitance 84 is a parasitic capacitance whose characteristics such as a change in capacitance with respect to a change in capacitance and ambient temperature approximate the parasitic capacitance 38. Is obtained. Further, as described above, since no charge is accumulated in the storage capacitor 80 of the dummy pixel section 76 regardless of the irradiation of radiation to the radiation detection panel 14, the storage capacitor 80 of each dummy pixel section 76 can be omitted. It is.

  The dummy pixel group 77 corresponds to the dummy pixel group described in claim 7. The dummy wiring 82 is the second dummy wiring described in claim 7. The TFT 78 is the correction switching means described in claim 7. Corresponds to each.

  On the other hand, the control device of the radiographic imaging system 10 includes a radiation generation control unit 88 that is connected to the radiation generation unit 12 and controls the generation of radiation by the radiation generation unit 12, and a gate line drive that drives the gate wiring 34 and the dummy wiring 82. Unit 90, a signal output from the storage capacitor 26 of each pixel unit 30 of the radiation detection panel 14 via the data wiring 36 and connected to the individual data wiring 36 and the individual storage capacitance wiring 56 of the radiation detection panel 14. A signal detection unit 92 that performs predetermined signal processing such as amplification and A / D conversion on the signal, a correction data storage unit 94A, and is connected to the gate line driving unit 90 and the signal detection unit 92, and also to the radiation detection panel 14 A readout control unit 94 that controls the operation of the gate line driving unit 90 and the signal detection unit 92 at the time of reading out charges from the signal and a signal detection unit 92 connected to An image processing unit 96 that performs predetermined image processing (for example, various corrections such as offset correction and shading correction) on the image represented by the image signal output from the signal detection unit 92 through processing, and image processing by the image processing unit 96 The display 98 for displaying the image signal which passed through as an image is provided.

  The read control unit 94 corresponds to the first correction means described in claims 3 to 6. Further, the read control unit 94 corresponds to second correction means according to claims 7 to 9 together with a dummy line driver 102 and a D / A converter 104 which will be described later. The correction data storage unit 94A corresponds to the first storage unit according to claims 3 to 5 and the second storage unit according to claims 7 and 8, respectively.

  As shown in FIG. 3, the gate line driving unit 90 includes a gate line driver 100 connected to each gate wiring 34 of the radiation detection panel 14 and a dummy line driver connected to a dummy wiring 82 of the radiation detection panel 14. 102. At the time of charge reading from the radiation detection panel 14, the read control unit 94 instructs the gate line driver 100 to drive the gate line 34 and represents the number of gate lines 34 that are driven simultaneously by driving the gate line 34. The number k of simultaneous driving that is a parameter is also notified. The gate line driver 100 normally maintains the voltage level of all the gate lines 34 at a low level (for example, 0 V), and when the drive of the gate line 34 is instructed, a high level voltage signal (ON Signal), the TFT 28 of each pixel portion 30 connected to the gate wiring 34 to which the ON signal is supplied is changed from OFF to ON, and after a predetermined time, the ON signal is supplied to the gate wiring 34. By stopping, the gate line driving process for changing the TFT 28 of each pixel unit 30 connected to the gate wiring 34 that has supplied the ON signal from ON to OFF is the same number of gates as the notified simultaneous driving number k. The wiring 34 is performed in order.

  The dummy line driver 102 is connected to the read control unit 94 via the D / A converter 104. Digital correction data (dummy pixel group drive data described later) is input from the read control unit 94 to the D / A converter 104, and the D / A converter 104 has a magnitude corresponding to the value of the input correction data. Output voltage. When the read control unit 94 instructs the gate line driver 100 to drive the gate line 34, the read control unit 94 also instructs the dummy line driver 102 to drive the dummy line 82. When the drive is instructed, the output voltage (dummy pixel group drive voltage) from the D / A converter 104 is supplied to the dummy wiring 82 to turn on the TFTs 78 of the individual dummy pixel portions 76 and the gate line driver. 100, the supply of the dummy pixel group drive voltage to the dummy wiring 82 is stopped at the timing when the supply of the ON signal to any of the gate wirings 34 is started, and the gate line driver 100 turns on the one of the gate wirings 34. By restarting the supply of the dummy pixel group drive voltage to the dummy wiring 82 at the timing when the supply of the signal is stopped, each dummy To again turn on the TFT78 of Motobu 76.

  The dummy line driver 102 and the D / A converter 104 correspond to the second correction means described in claim 7 and the like together with the read control unit 94. More specifically, the D / A converter 104 corresponds to claim 8. In the second D / A converter described above, the dummy line driver 102 corresponds to the dummy wiring drive unit described in claim 8.

  The signal detection unit 92 includes the same number of operational amplifiers 106 as the number of data wirings 36 provided on the TFT active matrix substrate 24, and the individual data wirings 36 of the radiation detection panel 14 are inverted input terminals of different operational amplifiers 106. Is connected to each. Each operational amplifier 106 has a non-inverting input terminal connected to a GND wiring (ground wiring), and an output terminal connected to an input terminal of a multiplexer (MPX) 112 via a sample hold circuit (not shown). In each operational amplifier 106, one end of a capacitor 108 and a switch 110 is connected to an inverting input terminal, and the other end of the capacitor 108 and the switch 110 is connected to an output terminal. Note that the switch 110 can be formed of a semiconductor switching element such as a MOSFET. With the above configuration, each operational amplifier 106, capacitor 108, and switch 110 outputs a signal having a level corresponding to the integral value of the current flowing through the data line 36 connected to the inverting input terminal while the switch 110 is off. Functions as a charge amplifier.

  The output end of the MPX 112 is connected to the input end of the A / D converter 114, and the output end of the A / D converter 114 is connected to the image processing unit 96. Instead of the configuration in which one MPX 112 and one A / D converter 114 are provided as described above, the MPX 112 is omitted, and the same number of A / D converters 114 as the operational amplifiers 106 (charge amplifiers) are different from each other. A configuration in which each is connected to the output terminal of the charge amplifier) may be employed.

  The signal detection unit 92 includes correction capacitors (capacitors) 116 that are provided in the same number as the data wirings 36 and are connected to different data wirings 36 on the input side of the operational amplifier 106. The other ends of the individual correction capacitors 116 are connected to first terminals of different switching elements 118, and the second terminals of the individual switching elements 118 are connected to output terminals of different D / A converters 120. Yes. The input terminal of each D / A converter 120 is connected to the read control unit 94, and each D / A converter 120 receives digital correction data (correction capacity drive described later) input from the read control unit 94. Outputs a voltage with a magnitude corresponding to the value of (data). The third terminals of the individual switching elements 118 are each connected to a gate line 124 having one end connected to the on / off control unit 122.

  Note that the switching element 118 only needs to have a configuration in which conduction / non-conduction between the first terminal and the second terminal is switched according to the voltage supplied to the third terminal, and for example, a MOSFET or the like can be applied. When a MOSFET or the like is applied as the switching element 118, the source of the MOSFET is connected to the other end of the correction capacitor 116, the drain of the MOSFET is connected to the output end of the D / A converter 120, and the gate of the MOSFET is connected to the gate line 124. That's fine.

  The on / off control unit 122 supplies a high level voltage signal (on signal) to the gate line 124 to turn on the individual MOSFETs 118, thereby outputting the output voltage (correction capacity driving voltage) from the D / A converter 120. Is applied to each correction capacitor 116, and the supply of an ON signal to each gate line 124 is started at the timing when the gate line driver 100 starts supplying an ON signal to any one of the gate wirings 34 (individual correction capacitors). Application of the correction capacitor drive voltage to the gate line 116 is stopped, and the supply of the ON signal to the gate line 124 is resumed at the timing when the gate line driver 100 stops the supply of the ON signal to any one of the gate wirings 34. Thus, the application of the correction capacitor driving voltage to the individual correction capacitors 116 is resumed.

  The switching element 118, the D / A converter 120, and the on / off control unit 122 correspond to the correction voltage applying unit according to the present invention. In particular, the switching element 118 is a switching element according to claim 4. The D / A converter 120 corresponds to each of the first D / A converters described in claim 4. The correction capacitor 116 corresponds to the correction capacitor according to the present invention (specifically, the external capacitor described in claim 2).

  Next, as an operation of the present embodiment, first, correction data acquisition processing performed by the read control unit 94 prior to radiation imaging of the subject 18 will be described with reference to FIG. The correction data acquisition process described below is performed in a state where charges are not accumulated in the accumulation capacitors 26 of the individual pixel units 30 of the radiation detection panel 14. Further, the execution timing of the correction data acquisition process can be determined according to the required level for the image quality of the radiographic image and the required level for the productivity (the number of radiographic images that can be captured per unit time). It may be performed every time when it is read, or may be performed once a day, such as at the start of every day, or may be performed only once at the beginning of installation of the radiographic imaging system 10. .

  In the correction data acquisition process, first, in step 150, 1 is assigned to the simultaneous driving number k of the gate wiring 34, and in the next step 152, the pixel group counter p representing the pixel group to be driven and the pixel group to be driven are set. 1 is assigned to each of the leading gate wiring positions i representing the position of the corresponding gate wiring 34 corresponding to the leading gate wiring 34. In step 154, the gate line driver 100 supplies an ON signal to the gate lines i to i + k−1 (the number of gate lines 34 equal to the number of simultaneous driving k starting from the position i) corresponding to the pixel group p to be driven. To start. Thereby, in the pixel group to be driven corresponding to the gate wirings i to i + k−1, the TFTs 28 of the respective pixel units 30 are turned on. In step 156, it is determined whether or not a predetermined time t1 has elapsed since the start of the supply of the ON signal to the gate wirings i to i + k-1, and step 156 is repeated until the determination is affirmed. Note that the predetermined time t1 is equal to the time during which an ON signal is supplied to each gate wiring 34 when the stored charge is read from the storage capacitor 26 of each pixel unit 30 of the radiation detection panel 14.

  If the determination in step 156 is affirmed, the process proceeds to step 158, and the output data of each charge amplifier is sent to the data data (p corresponding to the pixel group p to be driven via the MPX 112 and the A / D converter 114. , 1) to data (p, jmax). Jmax is the total number of data wirings 36 provided in the radiation detection panel 14. The above-described driving of the gate wirings i to i + k−1 (supply of the ON signal) is performed in a state where no charges are accumulated in the storage capacitors 26 of the individual pixel units 30 of the radiation detection panel 14. No signal charge caused by the accumulated charge in the storage capacitor 26 of each pixel unit 30 flows through 36.

  On the other hand, in normal image reading from the radiation detection panel 14, details will be described later. As shown in FIG. 5C, “normal data acquisition timing”, the gate lines i to i + k−1 are indicated. The supply of the ON signal is stopped, and the output signal of the charge amplifier is acquired as data after a certain period of time has passed. During this time, when the supply of the ON signal is started, feedthrough is performed in accordance with the voltage application to the parasitic capacitance 38 (see FIG. 5 (B), a pulse-shaped fluctuation component convex to the + side) occurs, and even when the supply of the ON signal is stopped, the feedthrough (in FIG. −), The level of the output signal of the charge amplifier at the time of acquisition as data depends on the feedthrough and on signal generated at the start of the on signal supply. Feedthrough occurring during outage becomes equal level to the approximately offset (cancel).

  On the other hand, in the correction data acquisition process, as shown in FIG. 5C, the output signals of the individual charge amplifiers are acquired as data before the supply of the ON signal to the gate wirings i to i + k−1 is stopped. In each charge amplifier, only the feedthrough generated as a result of voltage application to the parasitic capacitance 38 at the start of supply of the ON signal is stored as electric charges, so that it corresponds to the pixel group p to be driven. As data data (p, 1) to data (p, jmax), data that accurately represents the level of feedthrough caused by the voltage application to the parasitic capacitance 38 at the start of supply of the ON signal can be acquired. The feedthrough level generated when the voltage applied to the parasitic capacitor 38 is stopped is equal to the feedthrough level generated when the application of the same voltage to the parasitic capacitor 38 is started. The obtained data data (p, 1) to data (p, jmax) accurately represent the level of feedthrough that occurs when the voltage application to the parasitic capacitor 38 is stopped when the supply of the ON signal is stopped.

  In the next step 160, the switches 110 connected to the individual operational amplifiers 106 are once turned on to reset the accumulated charges of the individual charge amplifiers, and then the individual charge amplifier switches 110 are turned off. In step 162, the supply of the ON signal to the gate lines i to i + k−1 by the gate line driver 100 is stopped. Thereby, in the pixel group to be driven corresponding to the gate wirings i to i + k−1, the TFTs 28 of the pixel units 30 are turned off.

  In the next step 166 to step 172, a process of calculating correction data corresponding to the pixel group p to be driven from data data (p, 1) to data (p, jmax) corresponding to the pixel group p to be driven is performed. . That is, the electrostatic capacitance of each parasitic capacitance 38 existing at the intersection position of the gate wiring 34 and the data wiring 36 has variations due to manufacturing errors of the radiation detection panel 14, and accordingly, the individual parasitic capacitances. Since there is also a variation in the level of the feedthrough generated by 38, the data data (p, 1) to data (p, jmax) corresponding to the pixel group p to be driven also varies in value. Therefore, in step 166, the minimum value data_min is extracted from the data data (p, 1) to data (p, jmax) corresponding to the pixel group p to be driven.

In the next step 168, the minimum value data_min extracted in step 166 is converted into an applied voltage value Vdum to the dummy wiring 82 of the dummy pixel group 77. Conversion from the minimum value data_min to the applied voltage value Vdum can be performed using, for example, the following equation (1).
Vdum = data_min / Cdum (1)
Here, Cdum is the electrostatic capacitance (design value) of the parasitic capacitance 84 in each dummy pixel portion 76 of the dummy pixel group 77. The applied voltage value Vdum obtained by the above calculation is stored in the correction data storage unit 94A as dummy pixel group drive data for the pixel group p to be driven at the simultaneous drive number k.

In step 170, the minimum value data_min extracted in step 166 is subtracted from the data data (p, 1) to data (p, jmax) corresponding to the pixel group p to be driven. In step 172, first, the subtracted data data (p, 1) to data (p, jmax) are applied to the applied voltage values Vcor (p, 1) to Vcor (p, jmax) to the jmax correction capacitors 116. Convert. The conversion from the data data (p, x) to the applied voltage value Vcor (p, x) can be performed using, for example, the same expression (2) as the previous expression (1).
Vcor (p, x) = data (p, x) / Ccor (x) (2)
Here, Ccor (x) is the electrostatic capacity (design value) of the correction capacitor 116 connected to the data wiring x. Then, the jmax applied voltage values Vcor (p, 1) to Vcor (p, jmax) obtained by the above calculation are corrected as jmax correction capacity drive data for the pixel group p at the simultaneous drive number k. The data is stored in the data storage unit 94A.

  Through the above processing, the feedthrough generated by the parasitic capacitance 84 when the voltage is applied to or stopped from the parasitic capacitance 84 existing on the specific data wiring 36, and the correction capacitance connected to the specific data wiring 36. The combined feedthrough obtained by superimposing the feedthrough generated by the correction capacitor 116 when voltage is applied to or stopped from 116 is specified in the pixel group p to be driven when the gate wirings i to i + k−1 are driven. Dummy pixel group drive data defining the magnitude of the voltage applied to the parasitic capacitance 84 existing on the specific data wiring 36 so as to coincide with the feedthrough generated by the parasitic capacitance 38 existing on the data wiring 36 Correction capacitor drive data defining the magnitude of the voltage applied to the correction capacitor 116 connected to the specific data wiring 36 is determined. Rukoto is, so that each is performed for the individual data lines 36.

  When the calculation and storage of the correction data corresponding to the pixel group p to be driven is completed as described above, in the next step 174, the value (i + k) obtained by adding the simultaneous drive number k to the leading gate wiring position i is the radiation. It is determined whether or not the total number imax of the gate wirings 34 provided on the detection panel 14 is larger. If the determination is negative, the routine proceeds to step 176, where the value (i + k) obtained by adding the simultaneous driving number k to the leading gate wiring position i is set as a new leading gate wiring position i, and the pixel group counter p is set to only 1. After incrementing, the process returns to step 154, and steps 154 to 176 are repeated until the determination in step 174 is affirmed. As a result, a pixel group corresponding to the same number of gate lines 34 as the simultaneous drive number k (the initial value of the simultaneous drive number k is 1, and in this case, a pixel group corresponding to a single gate line 34) is used as a unit. The correction data corresponding to each pixel group is calculated and stored in order.

  If the determination at step 174 is affirmative, the routine proceeds to step 178, where it is determined whether or not the simultaneous drive number k has reached the maximum value kmax of the simultaneous drive number. A value equal to the maximum number of the gate wirings 34 that are simultaneously driven when reading out the accumulated charges from the accumulation capacitors 26 of the individual pixel units 30 of the radiation detection panel 14 is set as the maximum value kmax of the simultaneous drive number. For example, if the radiographic imaging system 10 is configured to always drive the gate wiring 34 one by one at the time of reading the accumulated charge from the radiation detection panel 14, the maximum number of simultaneous driving kmax = 1, so in step 178 The judgment is unconditionally affirmed. On the other hand, for example, if the radiographic imaging system 10 is configured to drive two or more gate wirings 34 at the same time when reading the accumulated charge from the radiation detection panel 14, the maximum value kmax of the simultaneous driving number is 2. By setting the above values, the determination in step 178 is denied.

  If the determination in step 178 is negative, the simultaneous drive number k is incremented by 1 in step 180 and then the process returns to step 152 and steps 152 to 180 are repeated until the determination in step 178 is affirmed. As a result, correction data corresponding to all pixel groups is calculated and stored for each case where the number of simultaneous driving k = 1 to kmax.

  Subsequently, the radiography of the subject 18 is performed, and the feed-through correction performed by the readout control unit 94 when reading out the electric charges accumulated in the storage capacitors 26 of the individual pixel units 30 of the radiation detection panel 14 by the radiography. The processing will be described with reference to FIG.

  In this feedthrough correction process, first, in step 200, the simultaneous drive number k of the gate wiring 34 when reading the charge from the radiation detection panel 14 is obtained. Note that if the radiographic imaging system 10 is configured to always drive the gate wiring 34 one by one at the time of reading the accumulated charge from the radiation detection panel 14, the number of simultaneous driving at the time of reading the charge is fixed to “ 1 ”is set. However, if the radiographic imaging system 10 is configured to drive two or more gate wirings 34 at the same time when reading the accumulated charge from the radiation detection panel 14, the charge reading is performed. The simultaneous drive number k is set directly by the user or indirectly by setting the shooting mode and the resolution of the shot image by the user.

  In the next step 202, 1 is assigned to each of the pixel group counter p and the leading gate wiring position i. In step 204, the dummy line driver 102 starts supplying an ON signal to the dummy wiring 82 of the dummy pixel group 77. In step 206, the ON / OFF control unit 122 supplies an ON signal to the jmax switching elements 118 connected to the jmax correction capacitors 116 via the gate line 124. As a result, the jmax number of switching elements 118 are turned on.

  In step 208, the dummy pixel group drive data for the pixel group p at the simultaneous drive number k is read from the correction data storage unit 94A and supplied to the D / A converter 104. As a result, the D / A converter 104 outputs a voltage having a magnitude corresponding to the value (applied voltage value Vdum) of the dummy pixel group driving data for the pixel group p at the simultaneous driving number k. By being supplied to the dummy wiring 82 of the dummy pixel group 77 by the line driver 102, the above voltages are respectively applied to the individual parasitic capacitors 84 of the dummy pixel group 77, and at the same time, the individual dummy pixel portions 76 of the dummy pixel group 77. Each TFT 78 is turned on.

  Further, in the next step 210, jmax correction capacity drive data for the pixel group p at the simultaneous drive number k is read from the correction data storage section 94A, respectively, and jmax D / D corresponding to each correction capacity 116 is read. Each is supplied to the A converter 120. As a result, from each D / A converter 120, the value of the correction capacitor drive data (the applied voltage value Vcor) among the jmax correction capacitor drive data for the pixel group p at the simultaneous drive number k. (p, 1) to Vcor (p, jmax) are output in accordance with the respective voltages, and these voltages are respectively applied to the correction capacitors 116 via the switching elements 118 in the on state.

  In step 212, the gate line driver 100 supplies ON signals to the gate lines i to i + k-1 (the number of gate lines 34 equal to the number of simultaneous driving k starting from the position i) corresponding to the pixel group p to be driven. (See also the change of the gate line potential from OFF to ON in FIG. 7A) and at the same time, the supply of voltage to the dummy wiring 82 of the dummy pixel group 77 by the dummy line driver 102 is stopped (FIG. 7). (See also the change of the dummy wiring potential from ON to OFF in (B)), and the ON signal supply to the gate line 124 by the ON / OFF control unit 122 is also stopped (the application of voltage to the correction capacitor in FIG. 7C). See also change from on to off).

  As a result, the TFTs 28 are turned on in the individual pixel portions 30 of the pixel group p to be driven, and the charges accumulated in the storage capacitors 26 of the individual pixel portions 30 flow through the corresponding data wirings 36 as signal charges. At this time, voltage application of the ON signal is started also to the parasitic capacitances 38 existing in the individual pixel portions 30 of the pixel group p to be driven, so that the feed is performed by the parasitic capacitances 38 of the individual pixel portions 30. Through occurs (refer to the pulse-like fluctuation component convex to the + side in FIG. 7D), and this feed through is superimposed on the signal charge corresponding to the amount of charge stored in the storage capacitor 26, and the data wiring 36 will flow.

  On the other hand, at the same time when the TFTs 28 of the individual pixel units 30 of the pixel group p to be driven are turned on, the supply of voltage to the dummy wiring 82 is stopped, and accordingly, the individual dummy of the dummy pixel group 77 is stopped. When the application of the voltage to the parasitic capacitance 84 of the pixel unit 76 is stopped, the parasitic capacitance 84 of each dummy pixel unit 76 generates a feedthrough having a polarity opposite to that of the feedthrough generated by the parasitic capacitance 38. . Further, at the same time when the TFTs 28 of the individual pixel units 30 of the pixel group p to be driven are turned on, the supply of the on signal to the gate line 124 is also stopped, and accordingly, the individual switching elements 118 are turned on from off. And the application of voltage to the individual correction capacitors 116 is also stopped, so that the feedthrough having a polarity opposite to that of the feedthrough generated by the parasitic capacitance 38 is also generated by the individual correction capacitors 116.

  In FIG. 7E, a composite feed in which the feedthrough generated by the parasitic capacitance 84 existing on the specific data wiring 36 and the feedthrough generated by the correction capacitor 116 connected to the specific data wiring 36 are overlapped. “Through” is shown as “fluctuation component of data line potential by feedthrough correction”. As described above, dummy pixel group drive data that defines the magnitude of the voltage applied to each parasitic capacitor 84 in the dummy pixel section 76 and correction that defines the magnitude of the voltage applied to each correction capacitor 116. The capacitive drive data is determined so that the combined feedthrough in which the feedthrough generated by the parasitic capacitor 84 and the feedthrough generated by the correction capacitor 116 are overlapped with the feedthrough generated by the parasitic capacitor 38. Therefore, the synthetic feedthrough has a polarity opposite to that of the feedthrough generated by the parasitic capacitance 38 and substantially the same amplitude as the pulse-like fluctuation component convex to the minus side shown in FIG. Become.

  As a result, the feedthrough generated by the parasitic capacitance 38 and the combined feedthrough cancel each other on the individual data wiring 36, so that the potential of the individual data wiring 36 is shown as the potential of the data line in FIG. 6 shows a change obtained by adding a slight error of feedthrough correction (deviation of the combined feedthrough with respect to the feedthrough generated by the parasitic capacitance 38) to the signal charge corresponding to the amount of charge stored in the storage capacitor 26, and its amplitude is greatly increased. Becomes smaller.

  In the next step 214, has the predetermined time t1 elapsed since the start of supply of the ON signal to the gate wirings i to i + k−1 (the supply of voltage to the dummy wiring 82 is stopped and the supply of the ON signal to the gate line 124 is stopped)? Step 214 is repeated until the determination is affirmative. When the determination in step 214 is affirmed, the process proceeds to step 216, and the supply of the ON signal to the gate wirings i to i + k−1 by the gate line driver 100 is stopped (from the ON to the OFF of the gate line potential in FIG. 7A). At the same time, the supply of voltage to the dummy wiring 82 of the dummy pixel group 77 is resumed by the dummy line driver 102 (see also the change of the dummy wiring potential from OFF to ON in FIG. 7B). Then, the supply of the ON signal to the gate line 124 by the ON / OFF control unit 122 is also resumed (see also the change from OFF to ON of the voltage application to the correction capacitor in FIG. 7C).

  As a result, the TFTs 28 are turned off in the individual pixel portions 30 of the pixel group p to be driven, and the readout of the stored charges from the storage capacitors 26 of the individual pixel portions 30 is completed. By stopping the voltage application of the ON signal to the parasitic capacitances 38 existing in the individual pixel portions 30 of p, feedthrough is generated by the parasitic capacitances 38 of the individual pixel portions 30 (-in FIG. 7D). This feedthrough flows through the data wiring 36. (Refer to the pulse-like fluctuation component which is convex to the side).

  On the other hand, at the same time when the TFTs 28 of the individual pixel portions 30 of the pixel group p to be driven are turned off, the supply of voltage to the dummy wiring 82 is resumed. When the application of the voltage to the parasitic capacitance 84 of the pixel unit 76 is resumed, the parasitic capacitance 84 of each dummy pixel unit 76 generates a feedthrough having a polarity opposite to that of the feedthrough generated by the parasitic capacitance 38. . Further, simultaneously with the turning off of the TFTs 28 of the individual pixel portions 30 of the pixel group p to be driven, the supply of the on signal to the gate line 124 is resumed, and accordingly the individual switching elements 118 are turned on from off. And the application of the voltage to the individual correction capacitors 116 is resumed, so that the feedthrough having a polarity opposite to that of the feedthrough generated by the parasitic capacitance 38 is generated also by the individual correction capacitors 116.

  The synthetic feedthrough is opposite in polarity and substantially equal in amplitude to the feedthrough generated by the parasitic capacitance 38, like a pulse-like fluctuation component convex to the + side shown in FIG. . As a result, even when the TFTs 28 of the individual pixel portions 30 are turned off, the feedthrough generated by the parasitic capacitance 38 and the combined feedthrough cancel each other on the individual data wirings 36. As shown as the potential of the data line in FIG. 7G, the signal charge corresponding to the amount of charge stored in the storage capacitor 26 has a slight error in feedthrough correction (the combined feed for the feedthrough generated by the parasitic capacitor 38). Through deviation: FIG. 7 (G) shows a change obtained by adding this deviation expressed as “residual component of potential fluctuation due to feedthrough charge”, and its amplitude is greatly reduced.

  In the next step 218, whether a predetermined time t2 has elapsed since the supply of the ON signal to the gate wirings i to i + k−1 is stopped (resumption of supply of the voltage to the dummy wiring 82, resumption of supply of the ON signal to the gate line 124). Step 218 is repeated until the determination is affirmative. If the determination in step 218 is affirmative, the process proceeds to step 220, and the output signal of each charge amplifier is read via the MPX 112 and the A / D converter 114 and read charge amount data corresponding to the pixel group p to be driven. Data (p, 1) to data (p, jmax) are acquired in order. In step 222, as shown in FIG. 7F, the individual switches 110 are once turned on to reset the accumulated charges of the individual charge amplifiers, and then the individual switches 110 are turned off.

  Note that the deviation of the combined feedthrough with respect to the feedthrough generated by the parasitic capacitance 38 is also different between when the TFT 28 is on and when it is off, as shown in FIG. On the other hand, in this embodiment, the individual charge amplifiers start to integrate the potential of the data wiring 36 (charge accumulation) before the TFTs 28 of the individual pixel units 30 are turned on. Each of the signal charges is turned off, and after a predetermined time t2 has elapsed (that is, the supply of the ON signal to the individual gate lines 34 is stopped, and then the signal charge including the feedthrough transmitted through the individual data lines 36 becomes zero. The output signal (accumulated charge) of the charge amplifier is read as read charge amount data data (p, 1) to data (p, jmax). Accordingly, since the deviation when the TFT 28 is on and the deviation when the TFT 28 is off are canceled on the charge accumulated in the charge amplifier, the read capacitance data data (p, 1) to data (p, jmax) are stored in the storage capacitor. Data that accurately represents the accumulated charge amount of 26 is obtained.

  In the next step 224, it is determined whether or not the value (i + k) obtained by adding the simultaneous driving number k to the leading gate wiring position i is larger than the total number imax of the gate wirings 34 provided in the radiation detection panel 14. If the determination is negative, the process proceeds to step 226, and a value (i + k) obtained by adding the simultaneous driving number k to the leading gate wiring position i is set as a new leading gate wiring position i, and the pixel group counter p is set to 1 only. After incrementing, the process returns to Step 208, and Steps 208 to 226 are repeated until the determination at Step 224 becomes affirmative. As a result, readout of stored charges from the storage capacitors 26 of the individual pixel groups (read charge amount data) is performed while performing the above-described feedthrough correction in units of pixels corresponding to the same number of gate lines 34 as the number of simultaneous driving k. data (p, 1) to data (p, jmax) acquisition) are performed in order. When the determination at step 224 is affirmed, the feedthrough correction process is terminated.

  Thus, according to the present embodiment, the feedthrough generated by the parasitic capacitance 38 is combined with the feedthrough generated by the parasitic capacitance 84 of the dummy pixel unit 76 and the feedthrough generated by the correction capacitor 116. Since the cancellation is performed on the individual data wirings 36 by the through, it is possible to accurately suppress the feedthrough generated by the parasitic capacitances 38 on the individual data wirings 36 over the entire period of reading the stored charges from the storage capacitors 26. For example, as shown in FIG. 8A, the amplitude component corresponding to the feedthrough generated by the parasitic capacitance 38 among the amplitude of the potential change of the individual data wirings 36 can be greatly reduced. As a result, the charge accumulated in the charge amplifier is saturated during the period in which the accumulated charge is read from the accumulation capacitor 26, and the broken line shown as “when feedthrough correction is not performed” in FIG. In addition, the saturation of the output signal voltage of the charge amplifier can be prevented, and the accuracy of canceling the feedthrough caused by the parasitic capacitance 38 due to the saturation of the output signal voltage can be prevented from greatly decreasing.

  Further, the amplitude component corresponding to the feedthrough generated by the parasitic capacitance 38 among the amplitude of the potential change of the individual data wiring 36 can be greatly reduced, so that the gain of the charge amplifier is suppressed in order to avoid the saturation of the accumulated charge. There is no need to do so, and there is a margin in the range of the charge amplifier. As a result, the gain of the charge amplifier can be increased as shown in FIG. Here, when the fixed noise is superimposed on the output signal of the charge amplifier as shown in FIG. 8C, a value obtained by converting the superimposed fixed noise level to the input side of the charge amplifier (input converted value). ) Becomes N / A (where N is the level of the superimposed fixed noise, A is the gain of the charge amplifier), and the input conversion value of the fixed noise becomes smaller as the gain A of the charge amplifier becomes larger. Along with this, the S / N ratio of the output signal of the charge amplifier is also improved. Therefore, according to the present embodiment, it is possible to prevent the output signal voltage of the charge amplifier from being saturated and to increase the S / N ratio of the output signal of the charge amplifier by increasing the gain of the charge amplifier. As a result, high-accuracy data that accurately represents the accumulated charge amount of the storage capacitor 26 can be obtained as the read charge amount data data (p, 1) to data (p, jmax).

  In the above description, in the correction data acquisition process (FIG. 4), the gate wiring i corresponding to the pixel group p to be driven is stored in the storage capacitor 26 of each pixel unit 30 of the radiation detection panel 14 while no charge is stored. ˜i + k−1 is driven once (supply of the ON signal is started), and data data (p, 1) to data (p, jmax) corresponding to the pixel group p to be driven are obtained and from the obtained data Although the dummy pixel group drive data and the correction capacitor drive data corresponding to the pixel group p to be driven are determined, the present invention is not limited to this, and the dummy pixel group drive data and After the correction capacitor drive data is once determined, the gate wiring is driven, the voltage application / application stop to the parasitic capacitance 84 of the dummy pixel group 77, and the correction are performed in the same manner as the feedthrough correction process (FIG. 6) described above. Power to the capacitor 116 Applying / stopping application, obtaining data data (p, 1) to data (p, jmax), and correcting the correction capacity driving data according to the obtained data, ) To data (p, jmax) may be repeated until all become 0, thereby determining the correction data. In this case, in addition to the variation in the electrostatic capacitance of the parasitic capacitance 38 in each pixel unit 30, the electrostatic capacitance of the parasitic capacitance 84 in each dummy pixel unit 76 of the dummy pixel group 77 and each correction capacitor 116. Even if there is a variation in the capacitance, the correction data is corrected so that the variation in the parasitic capacitance 84 and the capacitance of the correction capacitor 116 are also corrected in addition to the variation in the parasitic capacitance 38. (Dummy pixel group drive data and correction capacity drive data) can be determined.

Further, in the above, by applying the applied voltage values Vcor (p, 1) to Vcor (p, jmax) to the jmax correction capacitors 116 according to the above equation (2), the jmax correction capacitors 116 are used. Although a mode in which a desired level of feedthrough is generated has been described, the capacitance of each correction capacitor 116 may be adjusted in advance in consideration of the time constant. That is, the time constant τ1 that defines the time change of feedthrough generated in the parasitic capacitor 38 is obtained by the following equation (3).
τ1 = Rgon × Cpr (3)
Here, Rgon is the on-resistance of the switching element inside the gate line driver 100, and Cpr is the capacitance of the parasitic capacitance 38. On the other hand, the time constant τ 2 that defines the time change of the feedthrough generated in the correction capacitor 116 is obtained by the following equation (4).
τ1 = Ron × Ccor (x) (4)
Here, Ron is the on-resistance of the switching element 118, and Ccor (x) is the capacitance of the correction capacitor 116 connected to the data line x. As shown in FIG. 9E, when the time constant τ 2 is smaller than the time constant τ 1, the feedthrough generated in the correction capacitor 116 is attenuated more rapidly than the feedthrough generated in the parasitic capacitor 38. When the time constant τ2 is larger than the time constant τ1, the feedthrough generated in the correction capacitor 116 is attenuated more slowly than the feedthrough generated in the parasitic capacitor 38. As shown in FIG. 4, there is a residual portion that cannot be corrected by feedthrough correction.

  In contrast, the on-resistance Rgon, Ron and the capacitance Cpr are measured or investigated in advance, and the capacitance Ccor (x) of the correction capacitor 116 is adjusted in advance so that the time constant τ2 matches the time constant τ1. If this is done, the above-mentioned residue can be suppressed to be very small. Note that the on-resistance Rgon of the switching element in the gate line driver 100 is approximately constant, but there are the same number of parasitic capacitances 38 corresponding to the single data wiring 36 as the number of the gate wirings 34. Since the capacitance Cpr varies, the derivation of the capacitance Ccor (x) of the correction capacitor 116 is obtained, for example, by obtaining the capacitance Cpr of each of the parasitic capacitances 38 corresponding to the data wiring x, and averaging them. The time constant τ1 calculated using the value may be set so as to match the time constant τ2. In this case, the residual amount can be suppressed to be small on average.

  In the above description, the correction capacitor 116 as the correction capacitor according to the present invention is provided outside the TFT active matrix substrate 24. However, the present invention is not limited to this, and the correction according to the present invention is provided. The capacitor for use may be provided on the TFT active matrix substrate 24 by the same process as the formation of the individual pixel portions 30. In this case, as the correction capacitor according to the present invention, a dummy wiring intersecting with each data wiring (this dummy wiring corresponds to the first dummy wiring according to claim 2) is formed, Parasitic capacitance generated between the dummy wirings (this parasitic capacitance corresponds to the parasitic capacitance described in claim 2) can be used. In this case, the same number of dummy wirings, D / A converters, and dummy line drivers as the data wirings are provided, and different D / A converters and dummy line drivers are connected to the individual dummy wirings. It is possible to apply a correction voltage having an arbitrary magnitude independent of each other to the parasitic capacitance corresponding to the data wiring for an arbitrary period.

  Further, in the above, the dummy pixel group 77 (parasitic capacitance 84) is provided on the TFT active matrix substrate 24 of the radiation detection panel 14, and the correction capacitor 116 is connected to each data wiring 36, and the feed generated by the parasitic capacitance 84 is provided. The mode of canceling (correcting) the feedthrough generated by the parasitic capacitance 38 on the data wiring 36 by the combined feedthrough in which the feedthrough generated by the through and correction capacitor 116 is superimposed has been described. However, the present invention is not limited to this. Instead, the dummy pixel group 77 (parasitic capacitor 84) is omitted, and the feedthrough generated by the parasitic capacitor 38 is canceled (corrected) on the data wiring 36 only by the feedthrough generated by the correction capacitor 116. Also good. The present invention includes the above-described embodiments within the scope of rights.

  Further, in the above, the gates of the TFTs 28 of the plurality of pixel portions 30 (the plurality of pixel portions constituting the pixel group according to the present invention) arranged along the direction of arrow A in FIG. 3 are connected to the same gate wiring 34, Although the embodiment in which the TFTs 28 of the plurality of pixel units 30 are turned on at the same time has been described, the present invention is not limited to this, and the switching means for the individual pixel units constituting the pixel group according to the present invention It is also possible to apply the present invention to a mode in which time-series signals are obtained by sequentially turning on the.

  In the above description, the photoelectric conversion layer 22 that directly converts irradiated radiation into electric charges has been described as the conversion unit according to claim 10, but the present invention is not limited to this, and the conversion unit is irradiated with the photoelectric conversion layer 22. A configuration (indirect conversion method) may be used in which the converted radiation is once converted into electromagnetic waves (for example, visible light) and then converted. In the above description, the photoelectric conversion layer 22 is formed on the TFT active matrix substrate 24. However, the conversion unit includes a substrate on which a plurality of pixel units each including a storage capacitor and a switching unit are arranged. It may be a separate body.

  In the above description, the radiation detection panel 14 having a configuration in which a large number of pixel units 30 (TFTs 28 and storage capacitors 26) are arranged in a matrix (two-dimensionally) has been described as an example. However, the present invention is not limited to this. The electromagnetic wave detection panel may have a configuration in which a plurality of pixel portions are arranged in a line (one-dimensionally).

  In the above description, X-rays have been described as an example of radiation that is converted into electric charges by the photoelectric conversion layer as the conversion unit according to claim 10, but the present invention is not limited to this and is absorbed by the conversion unit. May be other radiation such as an electron beam or α-ray, and any arbitrary light such as visible light, ultraviolet light, or infrared light may be used. It may be an electromagnetic wave in the wavelength range.

It is a schematic block diagram of the radiographic imaging system concerning this embodiment. It is sectional drawing of the area | region in which the single pixel part is formed among radiation detection panels. It is a schematic block diagram of a radiation detection panel and its peripheral circuit. It is a flowchart which shows the content of the correction data acquisition process. It is a timing chart for demonstrating the data acquisition timing in a correction data acquisition process. It is a flowchart which shows the content of the feedthrough correction process. 6 is a timing chart showing an operation at the time of reading charges from a storage capacitor. According to the feedthrough correction, (A) shows the change in the amplitude of the potential change in the data wiring, (B) shows the change in the gain of the charge amplifier, and (C) shows the relationship between the gain of the charge amplifier and the input converted value of the fixed noise. FIG. It is a timing chart for demonstrating adjustment of the electrostatic capacitance of the correction | amendment capacity | capacitance which considered the time constant.

Explanation of symbols

10 Radiation Imaging System 14 Radiation Detection Panel 16 Controller 24 TFT Active Matrix Substrate 26 Storage Capacitor 28 TFT
30 pixel portion 34 gate wiring 36 data wiring 38 parasitic capacitance 76 dummy pixel portion 77 dummy pixel group 78 TFT
82 Dummy wiring 84 Parasitic capacitance 92 Signal detection unit 94 Read control unit 94A Correction data storage unit 102 Dummy line driver 104 D / A converter 116 Correction capacitor 118 Switching element 120 D / A converter 122 On-off control unit 124 Gate line

Claims (10)

A switching unit that is turned on / off in response to a signal voltage supplied via a signal voltage wiring; a pixel group that includes a plurality of pixel units each including a holding unit that holds a signal charge;
Each of the pixel groups is provided so as to intersect with the signal voltage wiring and transmit the signal charges held in the holding unit of the pixel unit during a period in which the switching unit is turned on. A plurality of data lines connected to different pixel portions;
A plurality of correction capacitors respectively connected to different data wirings of the plurality of data wirings;
A correction voltage applying means capable of applying a first correction voltage of any magnitude independent of each other to each of the plurality of correction capacitors for an arbitrary period;
An image detection apparatus.   The plurality of pixel portions, the signal voltage lines, and the plurality of data lines are formed in a single panel, and the correction capacitor is formed with a first dummy line that intersects the data lines in the panel. 2. A parasitic capacitance generated between the data wiring and the first dummy wiring, or an external capacitance arranged outside the panel and connected to the data wiring. Image detection device. A first storage unit that stores a magnitude of a first correction voltage applied to each of the plurality of correction capacitors;
Application of the first correction voltage having a magnitude stored in the first storage unit to each of the plurality of correction capacitors is started when the switching unit is turned off and stopped when the switching unit is turned on. First correction means for controlling the correction voltage application means;
The image detection apparatus according to claim 1, further comprising: The correction voltage applying means includes a plurality of first D / A converters that convert the input correction data into a first correction voltage having a magnitude corresponding to the value of the correction data, and each of the first D / A converters. Start of application of the first correction voltage output from the first D / A converter to the correction capacitor by being provided between the A / A converter and each of the correction capacitors and turned on / off. A plurality of switching elements that can switch application stop, and
The first storage unit stores a plurality of correction data representing the magnitude of a first correction voltage applied to each of the plurality of correction capacitors,
The first correction unit inputs the correction data stored in the first storage unit to each of the first D / A conversions, and controls on / off of the plurality of switching elements, thereby 4. The image detection apparatus according to claim 3, wherein a first correction voltage having a magnitude represented by the correction data is applied to each of a plurality of correction capacitors during a period in which the switching unit is off. A plurality of the pixel groups are provided, and the switching means of the individual pixel groups are turned on in different periods in units of a single or a plurality of pixel groups in accordance with signal voltages supplied via different signal voltage wirings. ,
In the first storage unit, the magnitude of the first correction voltage applied to each of the plurality of correction capacitors is stored in units of pixel groups in which the switching unit is turned on during synchronization,
The first correction means starts application when the switching means is turned off, and stops the application when the switching means is turned on. A first correction voltage to each of the plurality of correction capacitors is turned on and off. 4. The image detection apparatus according to claim 3, wherein the correction voltage application unit is controlled so as to coincide with the magnitude of the first correction voltage stored in the first storage unit corresponding to the pixel group to which the pixel group belongs. .   The first correction unit is generated when each of the switching units connected to a single or a plurality of signal voltage wirings is turned on and off in a state where no signal charges are held in the holding units of the individual pixel units. The first correction voltage to be applied to each of the plurality of correction capacitors when the on / off switching means is turned on / off is determined based on the magnitude of the voltage variation in each of the data lines. 6. The image detection apparatus according to claim 3, wherein the image detection apparatus is stored in a storage unit. A plurality of the pixel groups are provided, and the switching means of the individual pixel groups are turned on in different periods in units of a single or a plurality of pixel groups in accordance with signal voltages supplied via different signal voltage wirings. ,
A plurality of correction switching means each connected to a second dummy wiring provided so as to intersect with the plurality of data wirings, each of which is turned on / off in response to a second correction voltage supplied via the second dummy wiring. A dummy pixel group composed of dummy pixel portions of
A second storage unit that stores the magnitude of the second correction voltage applied to the second dummy wiring in units of pixel groups in which the switching unit is turned on during synchronization;
When the switching means is turned off, the correction switching means of the plurality of dummy pixel portions are respectively turned on, and when the switching means is turned on, the correction switching means of the plurality of dummy pixel portions are respectively turned off, and the correction The second correction voltage stored in the second storage unit corresponding to the pixel group to which the switching unit to be turned on / off belongs, is applied to the second dummy wiring during the period when the switching unit is on. Second correction means for matching the voltage magnitude;
The image detection apparatus according to claim 1, further comprising: In the second storage unit, correction data representing the magnitude of the second correction voltage applied to the second dummy wiring is stored in units of pixel groups in which the switching unit is turned on during synchronization,
The second correction means includes a second D / A converter for converting the input correction data into a second correction voltage having a magnitude corresponding to the value of the correction data, and the second D / A converter. A dummy wiring drive unit that turns on and off each of the correction switching means of the plurality of dummy pixel units by switching between start and stop of application of the second correction voltage output from the second dummy wiring to the second dummy wiring. The correction data stored in the second storage unit corresponding to the pixel group to which the switching means to be turned on / off belongs is input to the second D / A converter, and the switching means is turned off. Sometimes the application of the second correction voltage to the second dummy wiring is started and the application of the second correction voltage to the second dummy wiring is stopped when the switching means is turned on. Image detection apparatus according to claim 7, wherein the controlling the moving unit.   The second correction means is generated when each of the switching means connected to a single or a plurality of gate lines is turned on and off in a state where signal charges are not held in the holding portions of the individual pixel portions. Based on the magnitude of the voltage fluctuation in each of the data lines, the magnitude of the second correction voltage to be applied to the second dummy line when the on / off switching means is turned on / off is determined and stored in the second storage unit. 8. The image detection apparatus according to claim 7, wherein the image detection apparatus is stored. It further includes a conversion unit that converts the irradiated radiation or electromagnetic wave into electric charge,
The image detection apparatus according to claim 1, wherein the holding unit of each pixel unit holds the charge converted by the conversion unit as a signal charge.

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