JP2009206423A - Solid-state imaging element, manufacturing method of solid-state imaging element, and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure stable pixel characteristics and yield by eliminating a step between a region where a pixel array part is formed and a region where a peripheral circuit part is formed. <P>SOLUTION: In a CMOS type image sensor which has the pixel array part formed on a semiconductor substrate 30 and the peripheral circuit part formed at its periphery, the semiconductor substrate 30 has a recess structure, having level differences, such that a second element formation region where the peripheral circuit part is formed is lower than a first element formation region where the pixel array part is formed, and then a step due to a difference in film thickness between the first element formation region and the second element formation region is eliminated to suppress color unevenness (frame-shaped unevenness) due to the step. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an imaging apparatus, and in particular, a solid-state imaging device such as a CMOS (Complementary Metal Oxide Semiconductor) type image sensor, a method for manufacturing the solid-state imaging device, and imaging the solid-state imaging device. The present invention relates to an imaging device used as an element.

  In recent years, research and development of a solid-state imaging device called a CMOS type image sensor that reads a signal photoelectrically converted by a photoelectric conversion device by a MOS transistor instead of a CCD (Charge Coupled Device) which has been the mainstream has been active. It is coming.

  This CMOS image sensor is capable of diverting a CMOS logic LSI process, is easy to on-chip a peripheral circuit part on the same semiconductor substrate (chip) as the pixel array part, and is low in comparison with a CCD image sensor. It is expected from the standpoints that voltage drive is possible and low power consumption.

  When this CMOS image sensor is used in an application field that requires high image quality such as an image sensor of a digital camera, it is necessary to take measures against color unevenness. If there is uneven color, stable pixel characteristics cannot be obtained.

  This uneven color is caused by the difference in film thickness on the semiconductor substrate between the region of the pixel array portion where the wiring pitch of the metal wiring pattern is sparse and the region of the peripheral circuit portion where the wiring pitch of the metal wiring pattern is niche. It is thought to be caused by the step between the two regions. That is, the optical unevenness due to the process in the peripheral portion of the pixel array portion where the film thickness difference occurs, that is, a so-called frame portion is color unevenness, which is also called frame unevenness.

  CMP (Chemical Mechanical Polishing), etc. to eliminate the step between the two regions due to the difference in film thickness on the semiconductor substrate between the region where the pixel array portion is formed and the region where the peripheral circuit portion is formed Although the interlayer film is flattened, the film thickness difference cannot be completely removed even if this flattening process is performed, and color unevenness appears remarkably around the pixel array portion.

  In order to solve such a problem of color unevenness, conventionally, a dummy pixel array unit is disposed as a process dummy between the pixel array unit region and the peripheral circuit unit region, and the pixel array unit region The film thickness change on the semiconductor substrate with respect to the peripheral circuit area is moderated to suppress the occurrence of color unevenness (see, for example, Patent Document 1).

JP 2006-294765 A

  However, when trying to obtain a greater effect in removing color unevenness, it is necessary to increase the pixel area of the process dummy, resulting in an increase in chip size and chip removal from a single wafer. There is concern about a decline in the yield (theoretical yield) representing numbers. On the other hand, if the chip size is to be kept small, the pixel area of the process dummy must be narrowed, so that the color unevenness around the pixel array cannot be removed sufficiently.

  Therefore, the present invention eliminates a step between a region where the pixel array portion is formed and a region where the peripheral circuit portion is formed, and a solid-state imaging device capable of ensuring stable pixel characteristics and yield, and the solid-state imaging An object is to provide an element manufacturing method and an imaging apparatus using the solid-state imaging element as an imaging element.

In order to achieve the above object, the present invention provides:
In a solid-state imaging device in which a pixel array unit and its peripheral circuit unit are integrated on a semiconductor substrate,
In the semiconductor substrate, a first element formation region and a second element formation formed with a step around the first element formation region so as to be lower than the first element formation region. An area and
In the first element forming region, the constituent elements of the pixel array portion are formed, and in the second element forming region, the circuit elements of the peripheral circuit portion are formed.

  In the solid-state imaging device having the above-described configuration, the semiconductor substrate on which the pixel array unit and the peripheral circuit unit thereof are integrated is formed on the second circuit unit in which the peripheral circuit unit is formed with respect to the first element formation region in which the pixel array unit is formed. By adopting a recess structure with a low element formation region, even if there is a difference in the thickness of the interlayer insulating film between the two regions in the wiring layer between the first element formation region and the second element formation region, A step difference between the first element formation region and the second element formation region due to the difference in film thickness can be suppressed.

  According to the present invention, the level difference caused by the film thickness difference between the first element formation region and the second element formation region can be suppressed to be small, thereby suppressing the occurrence of color unevenness due to the level difference. Therefore, stable pixel characteristics and yield can be secured.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[System configuration]
FIG. 1 is a system configuration diagram showing an example of a solid-state imaging device to which the present invention is applied, for example, a CMOS image sensor.

  As shown in FIG. 1, a CMOS image sensor 10 according to this application example is provided with a pixel array unit 11 formed on a semiconductor substrate (chip) (not shown) and the same semiconductor substrate as the pixel array unit 11. And a peripheral circuit provided. As the peripheral circuits of the pixel array unit 11, a vertical drive circuit 12, a column circuit 13, which is a signal processing circuit, a horizontal drive circuit 14, an output circuit 15, a timing generator (TG) 16, and the like are used.

  The pixel array unit 11 includes 2 unit pixels (hereinafter simply referred to as “pixels”) 20 each including a photoelectric conversion element that photoelectrically converts incident visible light into a charge amount corresponding to the amount of light. Dimensionally arranged. A specific configuration of the unit pixel 20 will be described later.

  The pixel array unit 11 further includes pixel drive lines 17 for each pixel row with respect to the matrix arrangement of the unit pixels 20 along the horizontal direction in the drawing (pixel arrangement direction of the pixel row). A vertical signal line 18 is formed along the vertical direction in the figure (pixel arrangement direction of the pixel column). In FIG. 1, one pixel drive line 17 is shown, but the number is not limited to one. One end of the pixel drive line 17 is connected to an output end corresponding to each pixel row of the vertical drive circuit 12.

  The vertical drive circuit 12 is configured by a shift register, an address decoder, and the like. Although a specific configuration is not illustrated, a readout scanning system for sequentially scanning the pixels 20 that read signals in units of rows; Unnecessary charges are swept out (reset) from the photoelectric conversion elements of the pixels 20 in the readout row prior to the readout row by the time of the shutter speed with respect to the readout row in which readout scanning is performed by the readout scanning system. It has a configuration having a sweep scanning system for performing sweep scanning.

  A so-called electronic shutter operation is performed by sweeping (reset) unnecessary charges by the sweep scanning system. Here, the electronic shutter operation refers to an operation in which the photoelectric charge of the photoelectric conversion element is discarded and exposure is newly started (photocharge accumulation is started).

  The signal read by the reading operation by the reading scanning system corresponds to the amount of light incident after the immediately preceding reading operation or electronic shutter operation. The period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the photocharge accumulation time (exposure time) in the unit pixel 20.

  A signal output from each unit pixel 20 in the pixel row selected by scanning by the vertical drive circuit 12 is supplied to the column circuit 13 through each vertical signal line 18. For each pixel column of the pixel array unit 11, the column circuit 13 receives a signal output from each pixel 20 of the selected row for each pixel column, and removes fixed pattern noise specific to the pixel from the signal. Performs signal processing such as CDS (Correlated Double Sampling), signal amplification, and AD conversion.

  Here, the case where a configuration in which the column circuit 13 is arranged with a one-to-one correspondence with the pixel column is shown as an example, but the configuration is not limited to this configuration. It is also possible to employ a configuration in which one column circuit 13 is arranged for each pixel column (vertical signal line 18), and these column circuits 13 are shared in time division among a plurality of pixel columns.

  The horizontal drive circuit 14 includes a shift register, an address decoder, and the like, and sequentially selects the column circuits 13 by sequentially outputting horizontal scanning pulses. Although not shown, a horizontal selection switch is connected to the horizontal signal line 19 at each output stage of the column circuit 13. The horizontal scanning pulses sequentially output from the horizontal driving circuit 14 turn on the horizontal selection switches provided in the output stages of the column circuit 13 in order. These horizontal selection switches are sequentially turned on in response to the horizontal scanning pulse, thereby causing the horizontal signal lines 19 to sequentially output the pixel signals processed by the column circuit 13 for each pixel column.

  The output circuit 15 performs various signal processing on the pixel signals sequentially supplied from the column circuit 13 through the horizontal signal line 19 and outputs the result. As specific signal processing in the output circuit 15, for example, only buffering may be performed, or black level adjustment, correction of variation for each column, signal amplification, color-related processing, and the like are performed before buffering. Sometimes.

  The timing generator 16 generates various timing signals, and controls driving of the vertical drive circuit 12, the column circuit 13, the horizontal drive circuit 14, and the like based on these various timing signals.

(Circuit configuration of unit pixel)
FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the unit pixel 20. As shown in FIG. 2, the unit pixel 20 according to this circuit example includes, in addition to a photoelectric conversion element, for example, a photodiode 21, four transistors, for example, a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25. It is the composition which has.

  Here, as these transistors 22 to 25, for example, N-channel MOS transistors are used. However, the combination of the conductivity types of the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25 here is only an example, and is not limited to these combinations.

  For the unit pixel 20, as the pixel drive line 17, for example, three drive wirings of a transfer line 171, a reset line 172, and a selection line 173 are provided in common for each pixel in the same pixel row. One end of each of the transfer line 171, the reset line 172, and the selection line 173 is connected to an output end corresponding to each pixel row of the vertical drive circuit 12 in units of pixel rows.

  The photodiode 21 has an anode connected to a negative power source, for example, a ground, and photoelectrically converts received light into photocharge (here, photoelectrons) having a charge amount corresponding to the light amount. The cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplification transistor 24 through the transfer transistor 22. The node 26 electrically connected to the gate electrode of the amplification transistor 24 is called an FD (floating diffusion) portion.

  The transfer transistor 22 is connected between the cathode electrode of the photodiode 21 and the FD unit 26, and a transfer pulse φTRF having a high level (for example, Vdd level) is active (hereinafter referred to as “High active”) is transferred to the transfer line. By being applied to the gate electrode via 171, it is turned on, and the photoelectric charge photoelectrically converted by the photodiode 21 is transferred to the FD portion 26.

  The reset transistor 23 is turned on when the drain electrode is connected to the pixel power source Vdd, the source electrode is connected to the FD unit 26, and a high active reset pulse φRST is applied to the gate electrode via the reset line 172. Prior to the transfer of signal charges from the FD unit 26 to the FD unit 26, the FD unit 26 is reset by discarding the charges of the FD unit 26 to the pixel power supply Vdd.

  The amplification transistor 24 has a gate electrode connected to the FD unit 26 and a drain electrode connected to the pixel power source Vdd, and outputs the potential of the FD unit 26 after being reset by the reset transistor 23 as a reset level. The potential of the FD unit 26 after transferring the charge is output as a signal level.

  For example, the selection transistor 25 is turned on by having a drain electrode connected to the source of the amplification transistor 24, a source electrode connected to the vertical signal line 18, and a High active selection pulse φSEL applied to the gate via the selection line 173. Thus, the unit pixel 20 is selected and the signal output from the amplification transistor 24 is relayed to the vertical signal line 18.

  Note that the selection transistor 25 may have a circuit configuration connected between the pixel power supply Vdd and the drain of the amplification transistor 24.

  Further, the unit pixel 20 is not limited to the pixel configuration including the four transistors having the above-described configuration, and may be a pixel configuration including three transistors that serve as the amplification transistor 24 and the selection transistor 25. There is no limitation on the configuration of the pixel circuit.

(Layout configuration on semiconductor substrate)
In the system configuration of the CMOS image sensor 10 according to the application example described above, the unit pixels 20 of the pixel array unit 11 have been described on the assumption that the pixels have the same configuration, but actually, as shown in FIG. The pixel array unit 11 formed on the semiconductor substrate 30 is provided in an effective pixel unit 11A composed of a set of pixels whose pixel signals are used to generate a captured image, and in the peripheral part of the effective pixel unit 11A. The optical black portion (optical black pixel portion) 11B.

  Here, the optical black portion 11B is a pixel portion formed of a set of pixels that are optically shielded. The reason for providing the optical black portion 11B is as follows. That is, in the solid-state imaging device, a noise component called dark current is thermally generated even when no light is incident. Therefore, the optical black portion 11B is provided as a countermeasure against this noise. Specifically, noise components such as dark current can be removed by providing the optical black portion 11B and taking the difference between the pixel signal of the effective pixel portion 11A and the pixel signal of the optical black portion 11B.

  As shown in FIG. 3, on the semiconductor substrate 30, the peripheral portion of the optical black portion 11B called a so-called frame is the vertical drive circuit 12, the column circuit 13, the horizontal drive circuit 14, the output circuit 15, the timing generator 17, etc. The peripheral circuit section 31 is provided with the peripheral circuits.

[Characteristics of this embodiment]
As described above, in the CMOS image sensor 10 having the layout configuration in which the pixel array unit 11 is formed on the semiconductor substrate 30 and the peripheral circuit unit 31 is formed around the pixel array unit 11, in the present embodiment, the semiconductor substrate 30 is a pixel. A structure having a recess structure in which a step is provided so that the second element formation region in which the peripheral circuit portion 31 is formed is lower than the first element formation region in which the array portion 11 is formed. Adopted.

  As described above, the semiconductor substrate 30 on which the pixel array unit 11 and the peripheral circuit unit 31 are integrated is formed on the semiconductor device 30 in which the peripheral circuit unit 31 is formed with respect to the first element formation region in which the pixel array unit 11 is formed. By using a recess structure with a low element formation region, the following operational effects can be obtained.

  In the first element formation region where the pixel array unit 11 is formed, the constituent elements of the unit pixel 20, that is, the photodiode 21 and the transistors 22 to 25 are formed in units of pixels. Further, in the second element formation region in which the peripheral circuit portion 31 is formed, transistors that constitute peripheral circuits such as the vertical drive circuit 12, the column circuit 13, the horizontal drive circuit 14, the output circuit 15, and the timing generator 17 are provided. A circuit element is formed.

  Then, as shown in FIG. 4, for example, in a three-layer structure, metal wirings 41, 42, 43 are wired in the first element formation region, and metal wiring 51 is formed in the second element formation region. , 52, 53 are wired.

  Here, in the first element formation region in which the pixel array unit 11 is formed, it is necessary to secure a region for capturing light for each unit pixel 20, so that the wiring pitch of the patterns of the metal wirings 41, 42, and 43 is Become sparse. On the other hand, in the second element formation region where the peripheral circuit portion 31 is formed, a large number of circuit elements are integrated in a narrow region that is a frame of the semiconductor substrate 30, so that the wiring of the patterns of the metal wirings 51, 52, and 53 is performed. The pitch becomes dense.

  Thus, the 1st element formation area where the wiring pitch of the pattern of metal wiring 41,42,43 is sparse, and the 2nd element formation area where the wiring pitch of the pattern of metal wiring 51,52,53 is dense. Then, when the metal wiring 41, 42, 43 and the metal wiring 51, 52, 53 are formed on the same plane via the interlayer insulating film 60, the first element formation region and the second element formation region It is inevitable that a difference in film thickness of the interlayer insulating film 60 occurs between them.

  On the other hand, as in the present embodiment, the semiconductor substrate 30 on which the pixel array unit 11 and the peripheral circuit unit 31 are integrated is connected to the peripheral circuit with respect to the first element formation region in which the pixel array unit 11 is formed. Since the second element formation region in which the portion 31 is formed has a low recess structure, as shown in FIG. 4, in the wiring layer between the first element formation region and the second element formation region, Even if the film thickness difference of the interlayer insulating film 60 occurs, the step difference between the first element formation region and the second element formation region due to the film thickness difference can be suppressed small.

  Here, taking as an example a case where the wiring structure of the pixel array unit 11 and the peripheral circuit unit 31 is a three-layer structure, for example, by setting the step of the recess structure of the semiconductor substrate 30 to about 400 nm, the first element The step between the element formation regions due to the difference in film thickness of the interlayer insulating film 60 between the formation region and the second element formation region can be almost eliminated. That is, the step of the recess structure is determined based on the wiring structures of the first and second element formation regions, particularly the number of wiring layers.

  Further, since the step due to the film thickness difference between the first element formation region and the second element formation region is eliminated, the optical attribute due to the step in the peripheral portion of the pixel array portion 11, particularly the effective pixel portion 11A. The occurrence of uneven color (frame unevenness), which is a typical unevenness, can be suppressed. That is, as in the case of the prior art, the occurrence of color unevenness can be suppressed without providing a process dummy pixel region, so that stable pixel characteristics and yield can be ensured.

(Method of manufacturing a semiconductor substrate having a recess structure)
Next, a method for manufacturing the semiconductor substrate 30 having a recess structure will be described with reference to the process diagram of FIG.

  First, a silicon oxide film 72 to be a first insulating film is formed on a semiconductor substrate, for example, a silicon substrate 71, and then a silicon nitride film 73 to be a second insulating film is formed on the silicon oxide film 72. (Step 1).

  Next, a photoresist 74 is applied to the first element formation region on the silicon nitride film 73, and the silicon oxide film 72 and the silicon nitride film 73 in the second element formation region are etched using the photoresist 74 as an etching mask. (Step 2). As a result, the silicon oxide film 72 and the silicon nitride film 73 remain only in the first element formation region.

  As described above, the first element formation region is a region where the effective pixel portion 11A of the pixel array unit 11 is formed, and the second element formation region is the optical black portion 11B and the peripheral circuit unit 31 of the pixel array unit 11. Is a region in which is formed (see FIG. 3).

  Next, the silicon substrate 71 is etched using the silicon oxide film 72 and the silicon nitride film 73 in the first element formation region as an etching mask (step 3). For etching the silicon substrate 71, isotropic etching or anisotropic etching is used.

  Finally, the silicon oxide film 72 and the silicon nitride film 73 in the first element formation region are removed by etching (step 4). As a result, a silicon substrate 71 (semiconductor substrate 30) having a recess structure is formed.

  The thicknesses of the silicon oxide film 72 and the silicon nitride film 73 which are insulating films are selected according to the selection ratio between silicon and the insulating film in the etching of the silicon substrate 71.

  In addition, the etching mask for the silicon substrate 71 is not limited to the two-layer structure of the silicon oxide film 72 and the silicon nitride film 73, but may be a one-layer structure of either the silicon oxide film 72 or the silicon nitride film 73. May be.

  As described above, an insulating film is formed on the semiconductor substrate, and then the insulating film in the second element formation region is removed by etching using, for example, a photoresist method, and then the insulation in the first element formation region is performed. A semiconductor substrate having a recess structure can be easily manufactured by etching the semiconductor substrate using the film as an etching mask and then removing the insulating film in the first element formation region.

  The CMOS CCD image sensor 10 to which the present invention is applied may be formed as a single chip, or an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. It may be in a modular form.

  In addition, the CMOS CCD image sensor 10 according to the present embodiment can be used as an imaging element (image input unit) in an imaging apparatus. Here, the imaging apparatus refers to a camera system such as a digital still camera or a video camera, or an electronic device having an imaging function such as a mobile phone. Note that the above-described module form mounted on an electronic device, that is, a camera module may be used as an imaging device.

[Imaging device]
FIG. 6 is a block diagram showing an example of the configuration of the imaging apparatus according to the present invention.

  As shown in FIG. 6, an imaging apparatus 100 according to the present invention includes an optical system including a lens group 101, an imaging element 102, a DSP circuit 103 which is a camera signal processing circuit, a frame memory 104, a display device 105, a recording device 106, An operation system 107, a power supply system 108, and the like are included, and the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109. ing.

  The lens group 101 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 102. The imaging element 102 converts the amount of incident light imaged on the imaging surface by the lens group 101 into an electrical signal in units of pixels and outputs the electrical signal. As the image sensor 102, the CMOS image sensor 10 according to the above-described embodiment is used.

  The display device 105 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image sensor 102. The recording device 106 records a moving image or a still image captured by the image sensor 102 on a recording medium such as a video tape or a DVD (Digital Versatile Disk).

  The operation system 107 issues operation commands for various functions of the imaging apparatus under operation by the user. The power supply system 108 appropriately supplies various power supplies serving as operation power supplies for the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.

  As described above, in the imaging device such as a video camera, a digital still camera, and a camera module for a mobile device such as a mobile phone, by using the CMOS image sensor 10 according to the above-described embodiment as the imaging element 102, In the CMOS image sensor 10, color unevenness caused by a step between the region where the pixel array portion is formed and the region where the peripheral circuit portion is formed can be eliminated, so that the image quality of the captured image can be improved.

1 is a system configuration diagram showing an example of a CMOS image sensor to which the present invention is applied. FIG. It is a circuit diagram which shows an example of the circuit structure of a unit pixel. It is a top view which shows the layout structure on a semiconductor substrate. It is sectional structure drawing with which the effect of this invention is provided. It is process drawing which shows the procedure of the manufacturing method of the semiconductor substrate with a recess structure. It is a block diagram which shows an example of a structure of the imaging device which concerns on this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... CMOS type image sensor, 11 ... Pixel array part, 11A ... Effective pixel part, 11B ... Optical black part, 12 ... Vertical drive circuit, 13 ... Column circuit, 14 ... Horizontal drive circuit, 15 ... Output circuit, 16 ... Timing Generator (TG), 17 ... pixel drive line, 18 ... vertical signal line, 19 ... horizontal signal line, 20 ... unit pixel, 21 ... photodiode, 22 ... transfer transistor, 23 ... reset transistor, 24 ... amplification transistor, 25 ... Select transistor, 30 ... semiconductor substrate, 31 ... peripheral circuit part, 41, 42, 43, 51, 52, 53 ... metal wiring, 60 ... interlayer insulating film, 71 ... silicon substrate, 72 ... silicon oxide film, 73 ... silicon nitride Film, 74 ... Photoresist

Claims (4)

A solid-state imaging device in which a pixel array unit and its peripheral circuit unit are integrated on a semiconductor substrate,
In the semiconductor substrate, a first element formation region and a second element formation formed with a step around the first element formation region so as to be lower than the first element formation region. An area is provided,
The solid-state imaging device, wherein the first element formation region includes a component element of the pixel array portion, and the second element formation region includes a circuit element of the peripheral circuit portion. The solid-state imaging device according to claim 1, wherein the step is determined based on each wiring structure of the first and second element formation regions. A pixel array portion and its peripheral circuit portion are integrated on a semiconductor substrate, and the semiconductor substrate includes a first element formation region and a periphery of the first element formation region, the first element formation region. A method for manufacturing a solid-state imaging device provided with a second element formation region formed with a step so as to be lowered,
In manufacturing the semiconductor substrate having the step,
Forming an insulating film on the semiconductor substrate;
Next, the insulating film in the second element formation region is removed,
Next, the semiconductor substrate is etched using the insulating film in the first element formation region as a mask,
Thereafter, the insulating film in the first element formation region is removed. A method for manufacturing a solid-state imaging element. A solid-state imaging device in which a pixel array unit and its peripheral circuit unit are integrated on a semiconductor substrate;
An imaging device including an optical system that forms an image of incident light on an imaging surface of the solid-state imaging device,
In the semiconductor substrate, a first element formation region and a second element formation formed with a step around the first element formation region so as to be lower than the first element formation region. An area is provided,
The imaging device, wherein a component element of the pixel array portion is formed in the first element formation region, and a circuit element of the peripheral circuit portion is formed in the second element formation region.

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