JP2009205212A - Memory fault processing system, memory fault processing method, and memory fault processing program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To determine whether to continue or stop a process using a memory region according to the use of the process when the correctable defect of the memory occurs. <P>SOLUTION: To an entry registered in a TLB, "a defect frequency" and "a defect threshold " are added. The defect frequency holds the frequency of the correctable defect occurring in a corresponding physical address space. The defect threshold holds the maximum number of correctable defects permitted by the corresponding process. Also, a defect frequency monitoring mechanism connected to the TLB is provided with a function for comparing the defect frequency with the defect threshold, and when the defect frequency exceeds the defect threshold, issuing a signal to stop the process. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory fault processing system, and more particularly to a memory fault processing system for continuing the operation of a process.

  Usually, processes having various purposes operate in the same computer system. Some of these processes must continue to work no matter how many times a correctable failure occurs, or may be stopped immediately to avoid escalating a correctable failure to an uncorrectable failure. There is also a process.

  Here, it is assumed that the memory correctable fault indicates a fault that has been corrected by ECC (Error Correcting Code). Examples of processes that must continue to operate include processes by application software (application software) operating in the kernel and mission critical areas. On the other hand, as an example of a process that may be stopped immediately, a process using application software that simply operates by utilizing the idle time of the processor and that can be re-executed even if it fails can be cited.

  If a correctable failure occurs in the memory space used by a process that can be stopped immediately, if the correctable failure escalates to a non-correctable failure by operating the process as it is, the process stops immediately. However, the system goes down because the good process is continued. As a result, there is a problem that even important processes are stopped.

As a related technique, Japanese Patent Laid-Open No. 04-343148 (Patent Document 1) discloses an exception handling method for an embedded multitask operating system.
In this related technique, when the same task issues unauthorized system calls for a predetermined number of times, the task is terminated.

Japanese Patent Laid-Open No. 11-175409 (Patent Document 2) discloses a memory control system.
In this related technique, when the cumulative number of failures in a physical page exceeds a predetermined value, a substitute process is entered, and the operation is completed after the process is completed.

Japanese Patent Laid-Open No. 04-343148 JP-A-11-175409

  Usually, processes having various purposes operate in the same computer system. Some of them are extremely important processes, while others are less important processes that simply use processor idle time. However, in the existing failure processing method, since the lifetime processing is centrally performed, it is impossible to perform an appropriate processing according to the importance.

  The memory failure processing system according to the present invention starts a process that uses a physical address space, and in a TLB (Translation Look-aside Buffer) entry, the number of failures indicating the number of correctable failures that have occurred in the physical address space, and the process Is registered a failure threshold value indicating the maximum number of correctable failures allowed, and the correctable failure indicates a failure that has been corrected by ECC (Error Correcting Code). When the failure frequency is updated, the failure frequency and the failure threshold value are indicated. In comparison, if the number of failures exceeds the failure threshold, each time a correctable failure occurs with a processor that stops the process and a physical address space, the number of failures is counted and the number of failures is notified to the processor And a memory unit with a fault counter.

  The memory failure processing method of the present invention occurs in the physical address space in the step of starting a process that uses the physical address space of the memory unit with the failure counter and the entry of the TLB (Translation Look-aside Buffer) held by the processor. A step of registering a failure count indicating the number of correctable failures and a failure threshold value indicating the maximum number of correctable failures allowed by the process; and the correctable failure indicates a failure that has been corrected by ECC (Error Collecting Code); Each time a correctable failure occurs on a memory unit with a failure counter, the step of counting the number of failures and providing the number of failures to the TLB, and when the number of failures is updated on the TLB, In comparison, the number of failures exceeds the failure threshold And a step of stopping if the process.

  The memory fault processing program of the present invention is generated in the physical address space in the step of starting the process using the physical address space of the memory unit with the fault counter and the entry of the TLB (Translation Look-aside Buffer) held by the processor. A step of registering a failure count indicating the number of correctable failures and a failure threshold value indicating the maximum number of correctable failures allowed by the process; and the correctable failure indicates a failure that has been corrected by ECC (Error Collecting Code); Each time a correctable failure occurs on a memory unit with a failure counter, the step of counting the number of failures and providing the number of failures to the TLB, and when the number of failures is updated on the TLB, Compared, failure count exceeds failure threshold If there is a program for executing a step of stopping the process to the processor.

  When a correctable failure occurs in the memory, it is possible to decide whether to continue or stop the process according to the use of the process that uses the memory area.

  In the memory failure processing system according to the present invention, “failure count” and “failure threshold” are added to entries registered in a TLB (Translation Look-aside Buffer). The number of failures holds the number of correctable failures that occurred in the corresponding physical address space. The physical address space indicates a memory space that can be accessed by a memory address. The failure threshold holds the maximum number of correctable failures allowed by the corresponding process. The failure frequency monitoring mechanism connected to the TLB has a function of comparing these two and issuing a signal for stopping the process when the failure frequency exceeds the failure threshold.

Hereinafter, a first embodiment of the present invention will be described with reference to the accompanying drawings.
Referring to FIG. 1, the memory fault processing system of the present invention includes a processor 1 and a memory unit 2 with a fault counter.

  The processor 1 includes a TLB 11 with a fault counter, a fault count monitoring unit 12, and an operating system (OS: Operating System) 13.

The TLB 11 with a failure counter has the following three entries in addition to the general TLB function.
(1) The first entry is a process identifier entry for identifying a process using a physical page.
(2) The second entry is a failure count entry that holds the number of failures that occurred in the physical page.
(3) The third entry is a failure threshold entry in which a process using a physical page holds an allowable number of failures.

  The process identifier entry is a unique value set by the operating system (OS) 13. The failure count entry is a value indicating the number of failures indicating how many times the failure has occurred in the physical page when a memory correctable failure occurs. Here, the correctable fault of the memory indicates a fault that has been corrected by ECC (Error Correcting Code). The memory unit 2 with the fault counter corrects the correctable fault of the generated memory with the ECC each time a correctable fault occurs in the memory, and updates the fault count. The failure threshold entry is a value that is specified when a process is started according to the importance of the process. The specified value becomes the failure threshold. Here, these three entries are called TLB entries.

  The failure frequency monitoring unit 12 compares the failure frequency in the TLB entry with the failure threshold value, and if it is detected that “failure frequency> failure threshold value” as a result of the comparison, sends an interrupt signal to the processor 1 and It has a function of transmitting a process identifier indicating a process using a physical page.

  The operating system (OS) 13 operates on the processor 1 and has a function of stopping the process when receiving an interrupt signal and a process identifier from the failure frequency monitoring unit 12. In practice, however, the operating system (OS) 13 can be operated outside the processor 1. For example, the operating system (OS) 13 may operate on another processor that cooperates with the processor 1. Further, the operating system (OS) 13 may be read as firmware (firmware) or application software (application software).

  The memory unit 2 with a fault counter includes a fault notification unit 21 and a memory main body 22.

  The failure notification unit 21 has a function of notifying the processor 1 of the occurrence event together with the failure address and the number of failures each time a correctable failure occurs in the memory main body 22. Here, the failure address indicates an address where a failure has occurred. Whenever a memory correctable failure occurs, the failure notification unit 21 corrects the memory correctable failure that has occurred by ECC and updates the number of failures, and then sends the failure address to the processor 1 together with the failure address and the number of failures. You may make it notify.

  The memory body 22 divides the physical address space into minimum physical page units, and has a counter that counts and holds the number of failures indicating how many correctable failures have occurred for each division unit. Here, the memory main body 22 is divided into MM-0 to MM-N (N is arbitrary). The counter adds the number of failures every time a correctable failure occurs.

  As an example of the processor 1, a processing device such as a CPU (Central Processing Unit) or a microprocessor, or a semiconductor integrated circuit (IC: Integrated Circuit) having a similar function is conceivable. Further, as an example of the memory unit 2 with the fault counter, a semiconductor storage device such as a RAM (Random Access Memory), an EEPROM (Electrically Erasable and Programmable Read Only Memory), a flash memory (Flash Memory), or the like is conceivable. However, actually, it is not limited to these examples.

A configuration example of the processor 1 will be described in detail with reference to FIG.
The TLB 11 with a failure counter stores information in a table format for each of “virtual page number”, “physical page number”, “process identifier”, “number of failures”, and “failure threshold” as a TLB entry.

  The failure frequency monitoring unit 12 includes a comparison unit 121 and an interrupt notification unit 122.

  The comparison unit 121 acquires “process identifier”, “failure count”, and “failure threshold” in the TLB entry of the TLB 11 with fault counter, compares the “failure count” with the “failure threshold”, When it is detected that “number of failures> failure threshold”, the interrupt notification unit 122 is notified of the “process identifier”.

  For example, assume that there is a process A that may be stopped immediately when a correctable failure occurs. This is simply a process that makes effective use of processor idle time. In the case of a process that can be stopped immediately such as process A, the failure threshold value of the TLB entry corresponding to the memory space in which the process operates is set to zero. At this time, when a correctable failure occurs in the corresponding physical page PPN0, the number of failures of the corresponding entry in the TLB is updated. After that, when the failure frequency is compared with the failure threshold value, the failure frequency exceeds the failure threshold value, so that a signal for stopping the corresponding process A is issued. As a result, the memory space in which a correctable failure has occurred is not used, and failure escalation can be avoided. Similarly, in the case of the process B, the number of failures is 4 and the failure threshold is 5, which is below the maximum number of correctable failures that can be tolerated. Therefore, the processing is continued. In process C, the failure threshold is ∞. This indicates that the process must continue to work no matter how many correctable failures occur.

  In response to the notification of the “process identifier” from the comparison unit 121, the interrupt notification unit 122 transmits the “process identifier” and an interrupt signal to the operating system (OS) 13.

Next, the operation of this embodiment will be described in detail.
With reference to the flowchart of FIG. 3, a process when starting a process will be described.
(1) Step S101
In the process activation process, a process activation request is issued. Basically, it is the same as the normal process activation process, but in this embodiment, simultaneously with the process activation, the importance level of the process or the failure threshold value corresponding to the importance level is specified. When the importance level is specified, the specified failure threshold value corresponding to the importance level is used. However, for the sake of simplicity, this time, it is assumed that the failure threshold value itself is used. To proceed. At this time, the operating system (OS) 13 of the processor 1 starts the process with a failure threshold based on the process startup request and the specified failure threshold.
(2) Step S102
A process started with a failure threshold is registered in the TLB 11 with a failure counter by the operating system (OS) 13, and the identifier of the process and the failure threshold specified at startup are also registered in the TLB entry at the same time. Is done. At this time, the operating system (OS) 13 of the processor 1 registers at least the “process identifier” and the “failure threshold” of the process started with the failure threshold in the TLB entry of the TLB 11 with the failure counter. This completes the startup process.

Next, a series of processing when a failure actually occurs will be described.
The processing on the memory unit will be described with reference to the flowchart of FIG.
(1) Step S201
First, when a correctable failure occurs, the memory failure is corrected on the memory unit 2 with the failure counter. At this time, the memory unit with a fault counter 2 corrects the memory fault based on the ECC.
(2) Step S202
Next, the failure counter provided for each minimum physical page unit is updated on the memory unit 2 with the failure counter. Specifically, the memory unit with a fault counter 2 increments the counter corresponding to the smallest physical page including the address where the correctable fault has occurred by one. At this time, the memory unit 2 with the fault counter increments the counter corresponding to each of the MM-0 to MM-N of the memory body 22 by one.
(3) Step S203
When the counter update is completed, the memory unit 2 with the fault counter notifies the processor 1 that a correctable fault has occurred. At this time, the failure notification unit 21 of the memory unit 2 with the failure counter notifies the TLB 11 with the failure counter together with the address where the correctable failure has occurred and the value of the failure counter. Subsequently, the processing moves to the processor 1 side. The processing on the processor 1 is shown in FIG.

Processing on the processor will be described with reference to the flowchart of FIG.
(1) Step S301
The processor 1 receives the failure occurrence notification from the memory unit 2 with the failure counter and accepts the failure address and the number of failures. At this time, the TLB 11 with a failure counter receives the failure address and the number of failures together with the failure occurrence notification from the failure notification unit 21. In this processing on the processor, the processing performed by the TLB 11 with a fault counter may actually be performed by the operating system (OS) 13 on the TLB 11 with a fault counter.
(2) Step S302
Next, the processor 1 searches for an entry including the failure address on the TLB, and updates the number of failures held by the entry. At this time, the TLB 11 with a failure counter searches for an entry including the failure address from the TLB entries, and updates the number of failures held by the found entry.
(3) Step S303
When the failure count is updated, the processor 1 compares the failure count with the failure threshold. At this time, when the failure count is updated in the TLB 11 with the failure counter, the comparison unit 121 of the failure count monitoring unit 12 compares the failure count with the failure threshold. The failure threshold is set in the flow of FIG. 3 and is held on the TLB in the same manner as the number of failures. As a result of comparing the number of failures with the failure threshold, if the number of failures is less than or equal to the failure threshold, the processor 1 ends the process without doing anything thereafter. On the contrary, the processor 1 continues the process when the number of failures exceeds the failure threshold.
(4) Step S304
The processor 1 notifies the operating system (OS) 13 that the number of failures has exceeded the failure threshold. At this time, the comparison unit 121 of the processor 1 notifies the operating system (OS) 13 that the number of failures exceeds the failure threshold via the interrupt notification unit 122. Since the process identifier using the physical page is registered in the TLB entry, the interrupt notification unit 122 notifies the operating system (OS) 13 of the process identifier at the same time when an interrupt signal is transmitted. In a case where a notification from the processor 1 to the operating system (OS) 13 is issued, the processing moves to the operating system (OS) 13 side. The processing on the operating system (OS) 13 is shown in FIG.

Processing on the operating system (OS) will be described with reference to the flowchart of FIG.
(1) Step S401
The operating system (OS) 13 receives the process identifier simultaneously with the notification from the processor 1. Here, the operating system (OS) 13 receives a process identifier and an interrupt signal from the interrupt notification unit 122.
(2) Step S402
The operating system (OS) 13 forcibly terminates the process corresponding to the received process identifier and completes the processing.

  The above is the operation of the present embodiment.

  In this embodiment, by providing a TLB entry with a correctable memory failure counter / threshold, a failure processing function according to the importance of the process can be realized.

The second embodiment of the present invention will be described below.
In the present embodiment, the number of failures is also held on the real memory space side, and memory allocation according to the process is performed at the time of page-in / page-out. That is, when real memory is allocated by page-in, the number of failures in the real memory is compared with the threshold value of the allocated process. In an important process such as the threshold ∞, memory that has failed in the past is not used.

  Note that the memory failure processing system in this embodiment includes a processor 1 and a memory unit 2 with a failure counter. The processor 1 and the memory unit with fault counter 2 are basically the same as those in the first embodiment.

Specifically, the operation of this embodiment will be described.
With reference to the flowchart of FIG. 7, a process of allocating real memory by page-in will be described.
(1) Step S501
When page-in is started, the processor 1 first searches for a physical memory space to be paged-in on the memory unit 2 with a fault counter. At this time, when page-in is started, the operating system (OS) 13 searches the memory main body 22 for a physical memory space to be paged-in.
(2) Step S502
When the detected failure in the physical memory space is equal to or less than the specified value, the processor 1 determines that page-in can be performed. At this time, the operating system (OS) 13 determines that the page-in can be performed on the detected physical memory space when the detected failure of the physical memory space is equal to or less than the specified value. Here, the specified value is a preset value, and is set to “0” in an important process such as a threshold ∞, for example. In this case, the processor 1 uses a memory space that has never failed.
(3) Step S503
If the number of failures is not less than or equal to the specified value, the processor 1 checks the maximum number of searches. If the number of failures is less than or equal to the maximum number of searches, the processor 1 returns to the process of searching for a physical memory space to be paged in. Try to detect physical memory space with a small specified value. At this time, the operating system (OS) 13 investigates the maximum number of searches if the number of failures is not less than the specified value. If the number of failures is not more than the maximum number of searches, the operating system (OS) 13 again sets a physical memory space having a smaller specified value. Search for. However, if there is no page in which a failure has never occurred, the expected page does not exist. Therefore, the maximum number of searches is provided here, and the processor 1 If the number of searches is exceeded, the processing is continued, and page-in is performed even in a physical memory space where a failure has inevitably occurred. At this time, when the maximum number of searches is exceeded, the operating system (OS) 13 determines that page-in can be performed even in a physical memory space where a failure has occurred.
(4) Step S504
The processor 1 determines a physical memory space to be paged in. At this time, the operating system (OS) 13 determines a physical memory space that is determined to be page-in as a physical memory space to be paged-in.

  By repeating the above operations, a safe physical memory space can always be assigned to an important process.

  As described above, the present invention is realized by adding the “failure count” and the “failure threshold” to the entry registered in the TLB. The number of failures holds the number of correctable failures that occurred in the corresponding physical address space. The failure threshold holds the maximum number of correctable failures allowed by the corresponding process. The failure frequency monitoring mechanism connected to the TLB has a function of comparing these two and issuing a signal for stopping the process when the failure frequency exceeds the failure threshold.

  Since the number of failures is also held on the real memory space side, it is possible to perform memory allocation according to the process at the time of page-in / page-out. That is, when allocating real memory during page-in, compare the number of failures in the real memory with the threshold of the allocated process, and do not use memory that has failed in the past in critical processes such as the threshold ∞. can do.

  The present invention can be applied to any computer from a small scale to a large scale, but is particularly effective in a computer that operates in a mission critical area because it has a flexible failure processing method.

FIG. 1 is a diagram showing a configuration example of a memory failure processing system according to the present invention. FIG. 2 is a diagram illustrating a configuration example of a processor. FIG. 3 is a flowchart showing a process when starting a process. FIG. 4 is a flowchart showing processing on the memory unit. FIG. 5 is a flowchart showing processing on the processor. FIG. 6 is a flowchart showing processing on the operating system (OS). FIG. 7 is a flowchart showing a process of allocating real memory by page-in.

Explanation of symbols

1 ... Processor 11 ... TLB with fault counter
DESCRIPTION OF SYMBOLS 12 ... Failure frequency monitoring part 121 ... Comparison part 122 ... Interrupt notification part 13 ... Operating system (OS)
2 ... Memory unit with fault counter 21 ... Fault notification unit 22 ... Memory body

Claims (21)

A process that uses the physical address space is started, and the number of failures indicating the number of correctable failures that occurred in the physical address space is entered in a TLB (Translation Look-aside Buffer) entry, and the maximum correctable failure allowed by the process A failure threshold indicating a number is registered, and the correctable failure indicates a failure that has been corrected by ECC (Error Correcting Code), and when the failure count is updated, the failure count is compared with the failure threshold; A processor that stops the process if the failure count exceeds the failure threshold;
A memory fault processing system comprising the physical address space, and comprising a memory unit with a fault counter that counts the fault count and notifies the processor of the fault count each time the correctable fault occurs. The memory fault handling system according to claim 1,
The processor is
A TLB with a failure counter that has the TLB and stores a process identifier for identifying the process, the number of failures, and the failure threshold in the TLB entry;
The failure frequency is compared with the failure threshold value. When the failure frequency exceeds the failure threshold value, an interrupt signal is transmitted to the operating system (OS) that started the process and the process identifier is transmitted. And a memory failure processing system comprising: a failure frequency monitoring means. The memory fault handling system according to claim 2,
The failure frequency monitoring means includes
When the number of failures is updated on the TLB, the process identifier, the number of failures, and the failure threshold are referred to, the failure times are compared with the failure threshold, and the number of failures exceeds the failure threshold. A comparison means for notifying the process identifier;
A memory failure processing system comprising: interrupt notification means for transmitting the process identifier and the interrupt signal to the operating system (OS) in response to the notification of the process identifier. The memory fault processing system according to any one of claims 1 to 3,
The memory unit with the fault counter is
The physical address space is divided into minimum physical page units, and a memory main body having a counter for counting and holding the number of failures for each division unit;
A memory fault processing system comprising fault notification means for notifying the processor of a fault address and the fault count each time the correctable fault occurs in the memory body. The memory fault handling system according to claim 4,
When the correctable failure occurs, the memory unit with the failure counter performs correction of the correctable failure based on the ECC, and the memory unit with the failure counter corresponds to the minimum physical page including the address where the correctable failure has occurred. Count the number of failures,
The processor acquires the failure address and the failure count from the memory unit with the failure counter, searches an entry corresponding to the failure address on the TLB, and updates the failure count stored in the found entry. When the failure count is updated, the failure count stored in the entry is compared with the failure threshold, and the process is stopped when the failure count exceeds the failure threshold. system. A memory fault processing system according to any one of claims 1 to 5,
When the page-in is started, the processor searches for a physical memory space to be paged in on the memory unit with the fault counter, and when the detected physical memory space fault is equal to or less than a predetermined value, A memory failure processing system that determines that page-in is possible for the detected physical memory space. The memory fault handling system according to claim 6,
The processor investigates the maximum number of searches when the detected failure of the physical memory space is not less than a specified value, and searches for a physical memory space with a smaller specified value if the failure is less than the specified number of searches, A memory failure processing system that, when the number of times is exceeded, determines that page-in is possible even in a physical memory space where a failure has occurred. Starting a process that uses the physical address space of the memory unit with the fault counter;
Registered in the TLB (Translation Look-aside Buffer) entry held by the processor is a failure count indicating the number of correctable failures that occurred in the physical address space, and a failure threshold value indicating the maximum number of correctable failures allowed by the process. And the correctable fault indicates a fault that has been corrected by ECC (Error Correcting Code),
Each time the correctable fault occurs on the memory unit with the fault counter, the fault count is counted, and the fault count is provided to the TLB;
A memory fault processing method comprising: comparing the fault count with the fault threshold when the fault count is updated on the TLB, and stopping the process if the fault count exceeds the fault threshold . The memory failure processing method according to claim 8,
Storing a process identifier for identifying the process, the number of failures, and the failure threshold in the TLB entry;
The failure frequency is compared with the failure threshold value. When the failure frequency exceeds the failure threshold value, an interrupt signal is transmitted to the operating system (OS) that started the process and the process identifier is transmitted. And a memory fault handling method. The memory failure processing method according to claim 9,
When the number of failures is updated on the TLB, the process identifier, the number of failures, and the failure threshold are referred to, the failure times are compared with the failure threshold, and the number of failures exceeds the failure threshold. If not, the step of notifying the process identifier,
A memory failure processing method further comprising: sending the process identifier and the interrupt signal to the operating system (OS) in response to the notification of the process identifier. A memory failure processing method according to any one of claims 8 to 10,
Dividing the physical address space into minimum physical page units, and counting and holding the number of failures for each division unit;
And a step of notifying the failure address and the number of failures each time the correctable failure occurs. The memory failure processing method according to claim 11,
When the correctable failure occurs, the correctable failure is corrected based on the ECC on the memory unit with the failure counter, and the minimum physical page including the address where the correctable failure has occurred is supported. Counting the number of failures;
Obtaining the failure address and the failure count from the memory unit with the failure counter, searching an entry corresponding to the failure address on the TLB, and updating the failure count stored in the found entry;
When the failure count is updated, the failure count stored in the entry is compared with the failure threshold, and if the failure count exceeds the failure threshold, the process is further stopped. Memory failure handling method. A memory failure processing method according to any one of claims 8 to 12,
When page-in is started, searching for a physical memory space to be paged-in on the memory unit with a fault counter; and
And a step of determining that page-in can be performed on the detected physical memory space when the detected failure of the physical memory space is equal to or less than a predetermined value. The memory failure processing method according to claim 13,
If the detected physical memory space failure is not less than or equal to a prescribed value, investigating the maximum number of searches;
If the maximum number of searches is less than or equal to, searching for a physical memory space with a small specified value;
And a step of determining that page-in can be performed even in a physical memory space where a failure has occurred when the maximum number of searches is exceeded. Starting a process that uses the physical address space of the memory unit with the fault counter;
Registered in the TLB (Translation Look-aside Buffer) entry held by the processor is a failure count indicating the number of correctable failures that occurred in the physical address space, and a failure threshold value indicating the maximum number of correctable failures allowed by the process. And the correctable fault indicates a fault that has been corrected by ECC (Error Correcting Code),
Each time the correctable fault occurs on the memory unit with the fault counter, the fault count is counted, and the fault count is provided to the TLB;
When the failure count is updated on the TLB, the failure count is compared with the failure threshold, and if the failure count exceeds the failure threshold, the processor is caused to stop the process. Memory fault handling program. The memory failure processing program according to claim 15,
Storing a process identifier for identifying the process, the number of failures, and the failure threshold in the TLB entry;
The failure frequency is compared with the failure threshold value. When the failure frequency exceeds the failure threshold value, an interrupt signal is transmitted to the operating system (OS) that started the process and the process identifier is transmitted. And a memory failure processing program for causing the processor to further execute the step of performing. The memory failure processing program according to claim 16,
When the number of failures is updated on the TLB, the process identifier, the number of failures, and the failure threshold are referred to, the failure times are compared with the failure threshold, and the number of failures exceeds the failure threshold. If not, the step of notifying the process identifier,
A memory failure processing program for causing a processor to further execute a step of transmitting the process identifier and the interrupt signal to the operating system (OS) in response to the notification of the process identifier. A memory failure processing program according to any one of claims 15 to 17,
Dividing the physical address space into minimum physical page units, and counting and holding the number of failures for each division unit;
A memory failure processing program for causing a processor to further execute a step of notifying a failure address and the number of failures each time the correctable failure occurs. The memory failure processing program according to claim 18,
When the correctable failure occurs, the minimum for performing correction of the correctable failure on the memory unit with the failure counter based on the ECC and causing the processor to execute the address where the correctable failure has occurred Counting the number of failures corresponding to a physical page;
Obtaining the failure address and the failure count from the memory unit with the failure counter, searching an entry corresponding to the failure address on the TLB, and updating the failure count stored in the found entry;
When the failure count is updated, the failure count stored in the entry is compared with the failure threshold, and the process is stopped when the failure count exceeds the failure threshold. Memory failure processing program for execution. A memory failure processing program according to any one of claims 15 to 19,
When page-in is started, searching for a physical memory space to be paged-in on the memory unit with a fault counter; and
A memory failure for causing the processor to further execute a step of determining that page-in can be performed on the detected physical memory space when the detected failure of the physical memory space is equal to or less than a predetermined value; Processing program. The memory failure processing program according to claim 20,
If the detected physical memory space failure is not less than or equal to a prescribed value, investigating the maximum number of searches;
If the maximum number of searches is less than or equal to, searching for a physical memory space with a small specified value;
A memory failure processing program for causing a processor to further execute a step of determining that page-in can be performed even in a physical memory space where a failure has occurred when the maximum number of searches is exceeded.

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