JP2009199420A - Memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller having an effect of suppressing overhead in address conversion. <P>SOLUTION: This memory controller has: a memory 2 having a data storage area 10 partitioned into a plurality of pages, and a table storage area 11 storing a page table recoding association between a logical address and a physical address showing the page, wherein the data storage area 10 is accessed by the physical address; a device 3 making a request to access the memory 2 by the logical address; and a memory control part 4 having a cache 12 for temporarily storing a plurality of records of the page table, and making an access request from the device 3 to the memory 2 by converting the logical access into the physical address according to the association shown by the record stored in the cache 12. The memory control part 4 updates all the records stored in the cache 12 when a miss-hit occurs in the cache 12. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory control device, and more particularly to a memory control device that converts a logical address of a memory requested to be accessed by a device into a physical address using a page table.

Conventionally, a logical address of a memory requested to be accessed by a device is converted into a physical address using a page table, and an address conversion table is provided in addition to a block counter when generating an address when accessing the memory. By converting the continuous value obtained by the block counter to an arbitrary block address set in the address conversion table, the block data stored in discontinuous areas scattered on the memory is processed continuously. There is one that makes it easy to do (see, for example, Patent Document 1).
JP 2002-319233 A

  However, the above-described conventional technique has a problem in that when a miss hit occurs in the cache when address conversion between a logical address and a physical address is performed, overhead is required to read the corresponding record into the cache.

  The present invention has been made in order to solve the conventional problems, and an object of the present invention is to provide a memory control device capable of suppressing the overhead associated with address translation.

  A memory control device according to the present invention includes a data storage area partitioned into a plurality of pages, and a table storage area for storing a page table in which a correspondence between a physical address and a logical address indicating the page is one record. A memory for accessing the data storage area at the physical address; a device for requesting access to the memory at the logical address; and a cache for temporarily storing a plurality of records in the page table. A memory control unit comprising: a memory control unit that requests access from the device to the memory by converting the logical address into the physical address according to a correspondence represented by the record stored in the cache; When the memory control unit misses in the cache Has a configuration for updating all records stored in the cache.

  The present invention can provide a memory control device having an effect that the overhead associated with address translation can be suppressed.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
A memory control apparatus according to a first embodiment of the present invention is shown in FIG.

  As illustrated in FIG. 1, the memory control device 1 includes a memory 2, a device 3 that requests access to the memory 2, and a memory control unit 4 that controls access requests from the device 3.

  The memory 2 is composed of, for example, an SDRAM (Synchronous Dynamic Random Access Memory), a data storage area 10 partitioned into a plurality of pages, and a page table in which the correspondence between a physical address and a logical address indicating a page is one record. And a table storage area 11 for storing.

  In the present embodiment, the data stored in the data storage area 10 is assumed to be continuous data having a large size, such as audio visual data. The size of each page in the data storage area 10 is 4096 bytes.

  Each record in the page table represents the correspondence between the top physical address and the logical address of each page. In the present embodiment, the size of each record is 2 bytes.

  The device 3 is a broadcast input device that receives a broadcast signal from a broadcast receiver, an image input device that receives an image signal from a photographing device, an image compression device that performs image compression such as MPEG or JPEG on the image signal, and a liquid crystal An image output device for outputting an image signal to an output device such as a display, or a memory master such as a CPU (Central Processing Unit). The device 3 makes a request for accessing the data storage area 10 toward the memory 2 with a logical address.

  The memory control unit 4 has a cache 12 for temporarily storing a plurality of records in the page table. In the present embodiment, it is assumed that the cache 12 has a capacity for storing 64 records, that is, a storage capacity of 128 bytes.

  The memory control unit 4 converts the logical address into a physical address according to the correspondence represented by the record stored in the cache 12, thereby requesting the memory 2 from the device 3 to make an access requested by the logical address. It has become.

  In particular, the memory control unit 4 updates all records stored in the cache 12 when a miss hit occurs in the cache 12.

  Here, the memory control unit 4 groups the number of page tables stored in the table storage area 11 of the memory 2 in accordance with the size of the cache 12, that is, in this embodiment, every 64 records. When a miss hit occurs at 12, all records stored in the cache 12 may be updated with a group including a record representing the correspondence to the corresponding logical address.

  In addition, when a memory hit occurs in the cache 12, the memory control unit 4 determines the number corresponding to the size of the cache 12 from the record indicating the correspondence to the corresponding logical address, that is, 64 records in this embodiment. Thus, all the records stored in the cache 12 may be updated.

  The operation of the memory control device 1 configured as described above will be described with reference to FIG.

  First, when an access request is made from the device 3 to the data storage area 10 of the memory 2 with a logical address (S1), whether or not a record indicating the correspondence to the logical address is stored in the cache 12, that is, the cache 12 Whether or not a miss hit occurs is determined by the memory control unit 4 (S2).

  If it is determined that a miss has occurred in the cache 12, a record for the same size as that of the cache 12 is included from the table storage area 11 of the memory 2 by the memory control unit 4. All the records that have been acquired and stored in the cache 12 with the acquired records are updated (S3).

  When it is determined that no miss occurs in the cache 12, or when all the records in the cache 12 are updated, the physical address corresponding to the logical address is stored in the memory based on the record stored in the cache 12. The data is specified by the control unit 4 (S4), and the data storage area 10 of the memory 2 is accessed with the specified physical address (S5).

  The memory control device 1 according to the first embodiment of the present invention has a large continuous size by updating all records stored in the cache 12 when a miss hit occurs in the cache 12. Thus, it is possible to increase the possibility that a record representing the correspondence to the logical address to which access is subsequently requested hits in the cache 12, and to suppress the overhead for address translation.

(Second Embodiment)
FIG. 3 shows a memory control apparatus according to the second embodiment of the present invention. In the present embodiment, the same components as those of the memory control device 1 according to the first embodiment of the present invention are denoted by the same reference numerals and description thereof is omitted.

  As illustrated in FIG. 3, the memory control device 20 includes a memory 2, a plurality of devices 3 a to 3 c that request access to the memory 2, and a memory control unit that controls access requests by the devices 3 a to 3 c. 24. In FIG. 3, three devices 3a to 3c are shown, but the number of devices constituting the memory control device of the present invention is not limited.

  Each of the devices 3a to 3c includes a broadcast input device that receives a broadcast signal from a broadcast receiver, an image input device that receives an image signal from a photographing apparatus, and an image compression that performs image compression such as MPEG or JPEG on the image signal. The image output device is configured to output an image signal to an output device such as a device or a liquid crystal display, or a memory master such as a CPU. Each device 3a to 3c makes a request for access to the data storage area 10 to the memory 2 using a logical address.

  The memory control unit 24 includes caches 12a to 12c corresponding to the devices 3a to 3c, respectively, for temporarily storing a plurality of records in the page table. In the present embodiment, each of the caches 12a to 12c has a capacity for storing 64 records, that is, a storage capacity of 128 bytes.

  The memory control unit 24 converts the logical address into a physical address in accordance with the correspondence represented by the records stored in the caches 12a to 12c, thereby allowing the access requested by the logical address from the devices 3a to 3c to the memory 2 using the physical address. It comes to require.

  In particular, when a miss occurs in any of the caches 12a to 12c, the memory control unit 24 updates all the records stored in the caches 12a to 12c where the miss hit has occurred.

  Here, the memory control unit 24 groups the page tables stored in the table storage area 11 of the memory 2 according to the number corresponding to the sizes of the caches 12a to 12c, that is, 64 records in this embodiment. When a miss occurs in the caches 12a to 12c, all the records stored in the caches 12a to 12c in which the miss occurs are updated in a group including a record indicating the correspondence to the corresponding logical address. Also good.

  In addition, when a miss hit occurs in any of the caches 12a to 12c, the memory control unit 24 determines the number corresponding to the size of the caches 12a to 12c from the record indicating the correspondence to the corresponding logical address, that is, the present embodiment. In the above, all records stored in the caches 12a to 12c in which a miss hit has occurred may be updated with 64 records.

  The operation of the memory control device 20 configured as described above will be described with reference to FIG.

  First, when an access request to the data storage area 10 of the memory 2 is made with a logical address from any of the devices 3a to 3c (S11), the caches 12a to 12c corresponding to the devices 3a to 3c that requested the access control the memory. It is specified by the unit 24 (S12).

  Here, whether or not a record indicating correspondence to the logical address is stored in the specified caches 12a to 12c (hereinafter referred to as “specific cache”), that is, whether or not a miss occurs in the specific cache. Is determined by the memory control unit 24 (S13).

  When it is determined that a miss hit has occurred in the specific cache, the memory control unit 24 stores records for the same size as the caches 12a to 12c, including records indicating the correspondence to the logical addresses. 11 and all the records stored in the specific cache are updated with the acquired records (S14).

  When it is determined that no miss occurs in the specific cache, or when all the records in the specific cache have been updated, the physical address corresponding to the logical address is stored in the memory based on the record stored in the specific cache. The data is specified by the control unit 24 (S15), and the data storage area 10 of the memory 2 is accessed with the specified physical address (S16).

  The memory control device 20 according to the second embodiment of the present invention has the caches 12a to 12c for each of the devices 3a to 3c, and when a miss occurs in each of the caches 12a to 12c, the miss hit occurs. A record representing the correspondence to the logical address that is subsequently requested to be accessed by each device 3a to 3c for continuous data having a large size by updating all the records stored in the caches 12a to 12c. Can increase the possibility of hitting in each of the caches 12a to 12, and the overhead for address translation can be suppressed.

  As described above, the memory control device according to the present invention has an effect that it is possible to suppress the overhead associated with address translation. For example, the logical address of the memory requested to be accessed by the device is used as the page table. This is useful as a memory control device that performs conversion using

1 is a block diagram of a memory control device according to a first embodiment of the present invention. The flowchart for demonstrating operation | movement of the memory control apparatus in the 1st Embodiment of this invention. The block diagram of the memory control apparatus in the 2nd Embodiment of this invention Flow chart for explaining the operation of the memory control device according to the second embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,20 Memory control apparatus 2 Memory 3, 3a, 3b, 3c Device 4, 24 Memory control part 10 Data storage area 11 Table storage area 12, 12a, 12b, 12c Cache

Claims (3)

A data storage area partitioned into a plurality of pages, and a table storage area for storing a page table in which a correspondence between a physical address indicating the page and a logical address is one record, and storing the data at the physical address The memory accessed in the region,
A device that requests access to the memory at the logical address;
An access requested by the device by having a cache for temporarily storing a plurality of records of the page table, and converting the logical address to the physical address according to a correspondence represented by the record stored in the cache; A memory control device including a memory control unit that requests the memory
The memory control unit updates all records stored in the cache when a miss occurs in the cache. At least one device that requests access to the memory at the logical address;
The memory control apparatus according to claim 1, wherein the memory control unit requests the memory to access requested by each of the devices.   The memory control unit has the cache for each device, and when a miss occurs in the cache, updates all records stored in the cache corresponding to the device that requested the access that caused the miss. The memory control device according to claim 2, wherein:

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