JP2009199114A - Information processor and design device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor for making it difficult to analyze the buried place of electronic watermark information, and for making it difficult to alter the watermark information. <P>SOLUTION: This information processor 10 is provided with a storage circuit (random gate circuit 12) for storing a program and an arithmetic circuit (CPU 11) for executing the program. The arithmetic circuit accepts the input of read information for reading the watermark information, and the storage circuit is configured as a random gate circuit as the combination circuit of logic elements, and when readout information is inputted through the arithmetic circuit, information having the watermark information is outputted. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to an information processing apparatus and a design apparatus, and more particularly to a technique for embedding watermark information for specifying the origin of an electronic device.

Traditionally, when a program seller, separate from the program creator, freely adds his / her digital signature to the program to be sold to clarify the source of the program being sold,
It has been proposed to add a dummy module that does not affect the operation to a program and embed an electronic signature as an electronic watermark in the dummy module (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 2005-100347

According to the above-described conventional method, since the digital signature is embedded in the dummy module added to the program, by analyzing the program code and identifying the area that does not affect the actual operation, There is a possibility that the area where the electronic signature is embedded may be easily specified, and the electronic signature may be easily tampered.
SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus and a design apparatus having a program that makes it difficult to analyze the place where electronic watermark information is embedded, and thus makes it difficult to alter the watermark information.

In order to solve the above problem, according to a first aspect of the present invention, there is provided an information processing apparatus having a storage circuit for storing a program and an arithmetic circuit for executing the program, wherein the arithmetic circuit reads watermark information. When the read information is input via the arithmetic circuit, the memory circuit is configured as a random gate circuit as a combination circuit of logic elements. It is characterized by outputting the information it has.
According to the above configuration, the watermark information is held in the random gate circuit as a combinational circuit of logic elements. For this reason, compared with the case where watermark information is held in a normal ROM,
It is possible to prevent the position of the watermark information on the circuit pattern from being specified. As a result, it becomes difficult to analyze the watermark information, and tampering and removal of the watermark information can be suppressed.

According to a second aspect of the present invention, in the first aspect, the instructions constituting the program stored in the storage circuit have watermark information in unused bits, and the arithmetic circuit is
An arithmetic process is executed based on information excluding the watermark information among the instructions.
According to the above configuration, the watermark information is stored in the unused bits of the instructions constituting the program. For this reason, watermark information can be stored without increasing the circuit scale.

According to a third aspect of the present invention, in the first aspect, the instruction includes a conditional branch instruction, and the watermark information is under a predetermined condition that affects a branch of the conditional branch instruction.
It is stored according to the order of the instructions executed by the arithmetic circuit.
According to the above configuration, the watermark information is stored in accordance with the order of instructions read by the arithmetic circuit under a predetermined condition that affects the conditional branch instruction. For this reason, since the watermark information cannot be extracted unless the predetermined condition is known, the analysis of the watermark information becomes more difficult, and the falsification and removal of the watermark information can be suppressed.

According to a fourth aspect of the present invention, in the third aspect, the predetermined condition is that a predetermined input that affects a branch of the conditional branch instruction is given to the arithmetic circuit. It is a feature.
According to the above configuration, the predetermined condition is a predetermined input that affects the branch of the conditional branch instruction. For this reason, by setting the input given to the arithmetic circuit as, for example, a combination of a plurality of inputs, it becomes more difficult to analyze the watermark information, and tampering and removal of the watermark information can be suppressed.

According to a fifth aspect of the present invention, in the second to fourth aspects, the instruction code constituting the instruction is set to have a shorter code length as the frequency of occurrence of the instruction in the program increases. It is characterized by having.
According to the above configuration, the instruction code constituting the instruction is set to have a shorter code length as the appearance frequency in the program increases. For this reason, since the average code length of the instructions held by the random gate circuit is shortened, the circuit scale of the information processing apparatus can be reduced.

According to a sixth aspect of the present invention, in the first to fourth aspects, the storage circuit is subjected to logical compression based on stored bit information.
According to the above configuration, logic compression is performed on the random gate circuit. According to this configuration,
The circuit scale of the random gate circuit can be reduced.

According to a seventh aspect of the present invention, there is provided a design apparatus for designing an information processing apparatus having a storage circuit for storing a program and an arithmetic circuit for executing the program; The storage circuit storing the watermark information input via the input means is configured as a random gate circuit as a combinational circuit of logic elements, and generating means for generating design information of the random gate circuit It is characterized by that.
According to the above configuration, the input means receives the input of watermark information, and the generation means stores the memory circuit storing the watermark information as a random gate circuit as a combination circuit of logic elements,
Design information of the random gate circuit is generated.
Therefore, it is possible to generate circuit information that can prevent the position of the watermark information on the circuit pattern from being specified as compared with the case where the watermark information is held in a normal ROM. As a result, it becomes difficult to analyze the watermark information, and tampering and removal of the watermark information can be suppressed.

Next, preferred embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic configuration block diagram of an information processing apparatus according to an embodiment.
The information processing apparatus 10 is configured, for example, as a one-chip microcomputer, and as shown in FIG. 1, a CPU (Central Processing Unit) 11 (corresponding to “arithmetic circuit” in the claims), a random gate circuit 12 (claims) A register group 13, a peripheral circuit 14, and an I / O (Input Output) circuit 15. here,
The CPU 11 executes various types of information processing based on programs and data stored in the random gate circuit 12 and controls each unit of the apparatus. Random gate circuit 1
Reference numeral 2 denotes a logic circuit that is configured by a combination of logic elements, and an output at that time is determined by an input value. That is, the random gate circuit 12 is connected to a normal ROM (Read
It has a function to memorize the internal state like (Only Memory), and it depends on only the input when a certain input is given, not a sequential circuit where the output is determined by both the input and the internal state. It is a circuit that gives a fixed output. Therefore, the random gate circuit 12 does not have cells as memory elements arranged in a matrix like a normal ROM,
It is composed of a combination of logic elements.

The register group 13 includes a plurality of registers, and functions as a memory that temporarily stores programs and data executed by the CPU 11. The peripheral circuit 14 includes an interrupt circuit, a timer circuit, and a DMA (Direct Memory Access) circuit. The interrupt circuit generates an interrupt caused by an external device connected via, for example, a timer circuit, a DMA circuit, or an I / O circuit 15 and notifies the CPU 11 of the interrupt. The timer circuit is, for example,
Date and time information is generated and supplied to the CPU 11. The DMA circuit is a circuit that transfers information between registers of the register group 13 without passing through the CPU 11, and transfers information between the external device connected to the I / O circuit 15 and the register group 13. is there. The I / O circuit 15 is a circuit that performs control when exchanging information with an external device (not shown). As the peripheral circuit 14,
Other circuits (for example, a co-processor) may be included. Or it is good also as a structure which does not have the peripheral circuit 14 itself. That is, the peripheral circuit 14 is not an essential component.

Here, prior to specific description, the principle of the present invention will be described.
In general, in a processor such as the CPU 11, an instruction (= instruction code + operand) is defined with a fixed bit length in order to simplify processing. For this reason, depending on the type of instruction, bits that do not affect the operation of the instruction, that is, are not given a function or role, are included in the instruction code of the instruction. Since these bits are not used in the execution of each instruction, they will be referred to as unused bits in the following. The number of unused bits varies depending on the instruction and ranges from 1 to multiple bits.

FIG. 2 is a diagram illustrating an example of an instruction set of a processor having an instruction having a 16-bit length.
As described above, each instruction includes an instruction code, and further includes an operand as necessary. For example, the and instruction includes 6th to 15th bits (M
SB) is an instruction code, and the 0th to 5th bits are operands. Jm
In the p instruction, the 10th to 15th bits (MSB) of 16 bits are instruction codes.
The 0th to 9th bits are operands. The nop instruction has no operand and all 16 bits are an instruction code.
As shown in FIG. 2, there are no unused bits for the li instruction (immediate load instruction), the ld instruction (data load instruction), and the st instruction (data store instruction).
On the other hand, the add instruction (add instruction), sub instruction (subtract instruction), and instruction (logical product instruction), or instruction (logical sum instruction) and xor instruction (exclusive logical sum instruction) are hatched in FIG. As shown in the portion, there are 5 unused bits from the 6th bit to the 10th bit.

As for the jmp instruction (jump instruction) and the jz instruction (zero jump instruction (corresponding to “conditional branch instruction” in the claims)), as shown by the hatched portion in FIG. A used bit exists.
As for the nop instruction (no operation instruction), there are 11 unused bits from the 0th bit to the 10th bit as shown by the hatched portion in FIG.
These unused bits have no effect on instruction execution even if the value is rewritten.
Therefore, in the present embodiment, the watermark information is embedded without affecting the size and operation of the original program by writing the bits constituting the watermark information data in at least some of these unused bits. Then, circuit information constituting the random gate circuit 12 is generated based on the instruction code constituting the program in which the watermark information is embedded, and the information processing apparatus 10 is manufactured based on the circuit information. Since the program stored in the random gate circuit 12 of the information processing apparatus 10 manufactured in this way includes watermark information, the information processing apparatus 10 is manufactured by copying by reading the watermark information. It can be determined whether or not it has been done. Further, since the watermark information is embedded in the unused bits of the program, the data amount of the program is not increased. Further, since the watermark information is diffused and embedded in the unused bits, the presence of the watermark information can be noticed by a third party, and the watermark information can be prevented from being deleted or tampered. Further, by storing the watermark information in the random gate circuit 12 having no memory array, even when the circuit pattern is analyzed, the presence of the watermark information is noticed,
Alternatively, it is possible to prevent the watermark information from being deleted or altered.

FIG. 3 is a functional explanatory diagram of the watermark information embedding process.
FIG. 4 is a process flowchart of the watermark information embedding process. Note that the process shown in FIG. 4 is a process executed in the design apparatus 20 (not shown) that generates circuit information of the information processing apparatus 10. The design device 20 includes a CPU (corresponding to “generating means” in the claims), ROM, R
It is constituted by a general personal computer having an AM (Random Access Memory), an HDD (Hard Disk Drive), a keyboard as an input device (corresponding to “input means” in the claims), and the like.
First, the program source is read (step S1) and compiled into a binary code (step S2).
On the other hand, authentication information as watermark information is read (step S3) and converted into watermark information data (step S4). Note that the watermark information is not limited to authentication information, but may be any information obtained by converting desired information into data.
Subsequently, the position of the instruction code included in the binary code of the program and the corresponding unused bit is searched (step S5).
In this case, the following procedures (A1) to (A3) are conceivable as procedures for searching the position of the instruction code and the unused bit.

(A1) The instruction code and the unused bit position in the instruction code are searched according to the storage address of the program.
For example, the instruction code is searched in order from the head of the address to the tail, and the unused bits constituting each instruction code are also searched in order from the head of the address to the tail.

(A2) A predetermined type of instruction code and an unused bit position in the instruction code are searched according to the storage address of the program.
For example, when an add instruction and a sub instruction are searched for as a predetermined type of instruction code, the instruction code of the add instruction and the sub instruction is searched in order from the head to the tail of the address, and each instruction code is configured. Unused bits are also searched in order from the beginning to the end of the address.

(A3) The instruction code and the unused bit position in the instruction code are searched in the processing execution order when it is assumed that processing is performed by inputting predetermined specific data to the program in a predetermined specific order.
For example, when "0" is continuously input as input data, the instruction codes are searched in the order in which the program is executed, and the unused bits that make up each instruction code are searched in order from the beginning to the end of the address. To do.

Subsequently, the design device 20 sequentially embeds a bit string constituting the watermark information data in the searched unused bits (step S6).
In this case, the following (B1) to (B3) can be considered as a procedure for embedding the bit string constituting the watermark information data.

(B1) Among the unused bits constituting each searched instruction code, the watermark information data is constructed in order from the LSB side (0th bit side) to the MSB side or from the MSB side to the LSB side. Embed a bit string.
For example, when each instruction is formed with a fixed bit length of 16 bits, when the 6th to 10th bits are unused bits, and embedded from the LSB side, the 6th bit to the 10th bit The bit strings are embedded sequentially.

(B2) At least when a sufficient number of unused bits are embedded to embed a bit string constituting the watermark information data, the instruction code including the searched unused bits is
A bit string constituting the watermark information data is embedded in order from the lower bit side or the upper bit side in the order in which the instruction codes are searched.
For example, when an add instruction → sub instruction → nop instruction is searched in order, in the case of the above example, there are 5 unused bits from the 6th bit to the 10th bit for the add instruction and the sub instruction, For the nop instruction, there are 11 unused bits from the 0th bit to the 10th bit. Therefore, when the bit string constituting the watermark information data is embedded in order from the lower bit side, the 0th bit of the nop instruction is used. Bit → First bit of nop instruction →
→ 4th bit of nop instruction → 5th bit of nop instruction → 6th bit of add instruction → sub
6th bit of instruction → 6th bit of nop instruction → 7th bit of add instruction → 7th bit of sub instruction → 7th bit of nop instruction → ... → 10th bit of add instruction → 1st bit of sub instruction
The bit string is sequentially embedded in the order of 0 bit to 10th bit of the nop instruction.

(B3) Among the unused bits constituting each searched instruction code, the bit string constituting the watermark information data is embedded in the predetermined number of bits at the predetermined positions in order.
For example, among the unused bits of the retrieved instruction codes, the bits constituting the 1-bit watermark information data are embedded in the most significant bits (the 10th bit in the case of the add instruction described above).
(B4) In the above procedures (B1) to (B3), the remaining unused bits may be configured such that a bit string constituting the watermark information data is repeatedly embedded or arbitrary data is randomly written. Good.

As a result, a binary code program in which watermark information is embedded is generated. The watermarked binary code generated in this way is RTL (Register Transfer Leve).
l) Conversion into information (step S7). Note that RTL is a type of technique for describing a synchronous digital circuit in integrated circuit design. In such a design using RTL, the operation of a circuit is defined as a signal flow (data transfer) between a hardware register (such as a flip-flop) and a Boolean logic circuit that is a combinational circuit. In the process of step S7, R
The TL information is generated as information regarding the random gate circuit 12, as will be described later with reference to FIG.

Subsequently, the design apparatus 20 includes RTL information corresponding to the CPU 11 and other parts,
The RTL information generated in step S7 is synthesized (step S8). The RTL information synthesized in this way is converted into a random gate as a circuit combining logic gates by a logic synthesis software tool (not shown) (step S9). The synthesis result is
An integrated circuit pattern is created by passing to a tool for performing physical layout (not shown). The integrated circuit manufactured based on the pattern of the integrated circuit created in this way is incorporated into an electronic device (step S10). Then, as shown in FIG. 3, when a duplicating device suspected of having been duplicated is found, watermark information is extracted from the random gate circuit 12 and read out in the same procedure as in the case of writing ( In step S21), the written watermark information is compared (step S22). If the same watermark information as the written watermark information or a part of the watermark information that can be identified as the same watermark information is read, the copy is performed. It is possible to easily determine that the error has occurred.
As a result, it is possible to prevent illegal copying, and to deal with illegal copying.

Here, a specific example of a specific watermark information embedding process will be described.
FIG. 5 is an explanatory diagram of an example of the source code of the program.
In the program shown in FIG. 5, a jz instruction that branches to the label LABEL when the operation result is 0 is described as a conditional branch instruction in the middle.
FIG. 6 is a diagram for explaining the bit arrangement of the binary code when the START routine which is the main routine of the program shown in FIG. 5 is compiled.
In FIG. 6, the hatched portion represents the unused bit position in the instruction code.
In the case of FIG. 6, a total of 27 unused bits are included.

FIG. 7 is an explanatory diagram of a bit string of watermark information data.
In FIG. 7, the bit string of the watermark information data is composed of 26 bits, and each bit is represented by alphabets “A” to “Z” for easy understanding. That is,
Each of “A” to “Z” is 1 bit, and its value is “0” or “1”.

FIG. 8 is an explanatory diagram of the embedded state of the bit string of the watermark information data of the first specific example.
In the first specific example, the instruction code and the unused bits are searched by the procedure (A1) described above, and the bit string of the watermark information data is embedded in the unused bits in the instruction code from the LSB side according to the procedure (B1) described above. Is the case.
In this case, the AND instruction stored at the address = “0” is searched first,
For the 6th to 10th bits of the unused bits that constitute the and instruction, 5 bits “A” to “E” of the watermark information data bit string are sequentially applied in the order from the 6th bit to the 10th bit. Will be embedded.
Subsequently, the add instruction stored in the second address = “1” is retrieved, and the ad is searched.
In order from the 6th bit to the 10th bit of the unused bits constituting the d instruction, 5 bits “F” to “J” of the watermark information data bit sequence in order from the 6th bit to the 10th bit are sequentially Will be embedded.

Similarly, the sixth unused bit constituting the xor instruction stored at address = “3”.
From the bit to the 10th bit, 5 of “K” to “O” in the watermark information data bit string
For the 6th to 10th bits of the unused bits that constitute the sub instruction stored in the address = “4” in the order of bits, the watermark information data bit string “
5 bits of “P” to “T” are sequentially embedded, and with respect to the 10th bit of the unused bits constituting the jz instruction stored at the address = “5”, “
1 bit of “U” is embedded, and the 6th to 10th bits of the unused bits constituting the or instruction stored in the address = “8” are included in the watermark information data bit string,
5 bits from “V” to “Z” are sequentially embedded.

The program in which watermark information is embedded in this way is converted into RTL information and CP
After being synthesized with U11 and other RTL information, it is converted into a random gate by a logic synthesis software tool (not shown). FIG. 9 is a diagram showing a description example of the random gate corresponding to the random gate circuit 12 in the hardware description language. In this example, the random gate circuit 12 is described as a random gate that outputs “romout” in response to an input of “romadrs”. More specifically, 0-1 depending on the value of “romadrs”
The value of “ROMOUTS” described in 0 is selected and output. For example, “romad
When the value of “rs” is “0”, “0001_1EDC_B” which is 16-bit information
A00_1000 "is output. A to E correspond to watermark information bits. As described at the end of the case statement, the default value is “0”.
000 — 0000 — 0000 — 0000 ”.

Based on the random gate generated in this way, a tool for performing physical layout creates an integrated circuit pattern. Based on the created pattern of the integrated circuit, the information processing apparatus 10 as an integrated circuit is manufactured and incorporated into a target electronic device.

By the way, when the information processing apparatus 10 manufactured as described above is copied by a third party who does not have a legitimate use right, the I / O of the information processing apparatus 10 that may have been copied.
A personal computer (not shown) is connected to the O circuit 15. Then, the CPU 11 is instructed to read the program stored in the random gate circuit 12 from the personal computer via the I / O circuit 15. As a result, the CPU 11 reads the program stored in the random gate circuit 12 and transfers it to the personal computer via the I / O circuit 15. In the personal computer, watermark information is extracted from the transferred program based on the same procedure as in the case of embedding. As a result, if the extracted watermark information matches the embedded watermark information, it can be determined that the information processing apparatus 10 has been copied.

FIG. 10 is an explanatory diagram of the embedding state of the bit string of the watermark information data of the second specific example.
In the second specific example, the instruction code and the unused bits are searched by the procedure of (A1) described above, and the bit string of the watermark information data is set to the unused bits in the instruction code from the lower bit side according to the procedure of (B2) described above. This is the case when it is embedded.
In this case, the AND instruction stored at the address = “0” is searched first,
The add instruction stored at the address = “1” is searched second, the xor instruction stored at the address = “3” is searched third, and the address = “4” is searched fourth. The stored sub instruction is searched, the jz instruction stored at the address = “5” is searched fifth, and the or instruction stored at the address = “8” is searched sixth. .

Among these retrieved instructions, the least significant bit of the unused bits is located at the sixth bit, so the watermark information data is sequentially from the sixth bit in the order in which the instruction codes are retrieved. Is embedded, and one bit of “A” in the watermark information data bit string is embedded in the sixth bit of the unused bits constituting the “and” instruction stored at the address = “0”. Will be.
Subsequently, one bit of “B” in the watermark information data bit string is embedded in the sixth bit of the unused bits constituting the add instruction stored in the second searched address = “1”. It becomes.

Similarly, the sixth unused bit constituting the xor instruction stored at address = “3”.
One bit of “C” in the watermark information data bit string is embedded in the bit, and the address =
An or instruction stored at address = “8” with one bit of “D” embedded in the watermark information data bit string in the sixth bit of the unused bits constituting the sub instruction stored in “4” Of the watermark information data bit string in the sixth bit of the unused bits constituting
1 bit is embedded. As a result, all the unused bits located in the sixth bit included in the retrieved instruction are embedded with the bits that make up the watermark information data bit string. As a result of searching, one bit of “F” in the watermark information data bit string is embedded in the seventh bit of the unused bits constituting the “and” instruction stored at the address = “0”.
Hereinafter, among the instructions searched in the same manner, the watermark information data bit string is embedded in the seventh bit of the instruction having the unused bit in the seventh bit in the search order,
Bits → 9th → 10th bit
The bits constituting the watermark information data bit string are sequentially embedded, and the process is finally completed in the state shown in FIG.

FIG. 11 is an explanatory diagram of the embedded state of the bit string of the watermark information data of the third specific example.
In the third specific example, the instruction code and the unused bits are searched in the procedure (A3) described above, and the bit string of the watermark information data is embedded in the unused bits in the instruction code from the LSB side according to the procedure (B1) described above. Is the case.
In this case, when a specific data predetermined in the program is input in a predetermined specific order and the process is performed, the instruction having an unused bit and executed first Is an and instruction stored at address = “0”.
“A” in the watermark information data bit string in the order from the 6th bit to the 10th bit with respect to the 6th to 10th bits of the unused bits constituting the AND instruction.
”To“ E ”are sequentially embedded.

Subsequently, since the second instruction to be executed that has an unused bit is the add instruction stored at the address = “1”, it is searched and the instruction that constitutes this add instruction is searched. For the 6th to 10th bits of the used bits, 5 bits “F” to “J” of the watermark information data bit string are sequentially embedded in the order from the 6th bit to the 10th bit.
Similarly, an instruction having an unused bit and the third instruction to be executed is the xor instruction stored at the address = “3”. Therefore, the number of unused bits constituting the xor instruction is From the 6th bit to the 10th bit, “K” to “K” in the watermark information data bit string.
5 bits of “O” are sequentially embedded.

Further, an instruction having a non-use bit and the fourth instruction to be executed has an address =
Since it is a sub instruction stored in “4”, “P” to “T” of the watermark information data bit string with respect to the 6th to 10th bits of the unused bits constituting this sub instruction.
Are sequentially embedded.
At this time, it is assumed that the operation result of the sub instruction is 0 and a zero flag (not shown) is set.
Since the fifth instruction to be executed which has an unused bit is the jz instruction stored at the address = “5”, the tenth unused bit constituting this jz instruction is used. One bit of “U” in the watermark information data bit string is embedded in the bit.

Then, since the zero flag (not shown) is set according to the operation result of the sub instruction stored in the fourth executed address = “4”, the processing is started from the main routine START as a result of the execution of the jz instruction. = Subroutine LABE stored in “10”
Branch to L.
As a result, the sixth instruction to be executed is jmp stored at address = “10”.
Since this is an instruction, one bit of “V” in the watermark information data bit string is embedded in the 10th unused bit constituting the jmp instruction.
According to this example, if it is not known what specific data is input to the CPU 11 in a predetermined specific order, the watermark information cannot be analyzed and falsification becomes very difficult. . On the other hand, when the program is falsified, it is possible to easily detect that the falsification has been performed by detecting the watermark information in a predetermined procedure. Examples of data input to the CPU 11 include data input from the I / O circuit 15.

As described above, according to the present embodiment, the operation of the program is not affected, and
Since watermark information can be embedded without changing the size of the target program for embedding the watermark information, if the third party duplicates the program, the watermark information may be removed or the watermark information may be used to mislead the source of the program. When trying to falsify, the analysis becomes more difficult than in the past, and as a result, the removal or falsification of the watermark information becomes difficult, and the duplication of the program can be suppressed.
Furthermore, even with the same watermark information, various embedding modes are possible. Therefore, the watermark information was embedded by changing the embedding mode of the watermark information for each distribution route such as a program distribution route or a sales route. It becomes possible to specify the distribution route of the program more easily.

In the present embodiment, the random gate circuit 12 holds the program in which the watermark information is embedded. In the random gate circuit 12, like a general ROM,
Since there is no memory array, it is very difficult to determine from the circuit pattern where the program code is stored when the circuit pattern is viewed. For this reason, it is possible to prevent the watermark information from being specified, deleted, or tampered by a third party.
Further, since the random gate circuit 12 is arranged so as to be mixed with other random gates, it is possible to make it more difficult to specify watermark information. Furthermore, the random gate circuit 1
2, logical compression is performed in the process until the pattern of the integrated circuit is generated. For this reason,
Since the logical compression is performed in a state where the watermark information is embedded, it is possible to prevent an increase in circuit scale even when the watermark information is embedded.

It should be noted that the above-described embodiment is merely an aspect of the present invention, and can be arbitrarily modified and applied within the scope of the present invention.
For example, in the above embodiment, the watermark information is embedded in the unused bits of the program. However, the watermark information may be held in a specific area of the random gate circuit 12. For example, watermark information may be embedded in the beginning, center, and end areas of the program.

In the above embodiment, the code length of each instruction code constituting the program is fixed, but the code length of the instruction code is changed according to the appearance frequency of the instruction code appearing in the program. It may be. Specifically, for example, by giving a short code length to an instruction code having a high appearance frequency, the number of gates of the random gate circuit 12 can be reduced, and as a result, the circuit scale of the information processing apparatus 10 can be reduced. it can. As a result, even when watermark information is embedded, the circuit scale can be prevented from increasing.

It is a general | schematic block diagram of the information processing apparatus of embodiment. It is a figure explaining the example of the instruction set of the processor which has a 16-bit length instruction. It is a function explanatory view of watermark information embedding processing. It is a processing flowchart of watermark information embedding processing. It is explanatory drawing of an example of the source code of a program. It is a figure for demonstrating the bit arrangement | sequence of a binary code at the time of compiling the START routine which is the main routine of the program shown in FIG. It is explanatory drawing of the bit sequence of watermark information data. It is explanatory drawing of the embedding state of the bit sequence of the watermark information data of a 1st specific example. It is RTL information of the combinational circuit ROM having the program shown in FIG. It is explanatory drawing of the embedding state of the bit sequence of the watermark information data of the 2nd specific example. It is explanatory drawing of the embedding state of the bit sequence of the watermark information data of a 3rd example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Information processing apparatus, 11 ... CPU, 12 ... Random gate circuit, 13 ... Register group,
14: Peripheral circuit, 15: I / O circuit.

Claims (7)

In an information processing apparatus having a storage circuit for storing a program and an arithmetic circuit for executing the program,
The arithmetic circuit receives read information for reading watermark information,
The storage circuit is configured as a random gate circuit as a combination circuit of logic elements, and outputs the information having the watermark information when the read information is input through the arithmetic circuit.
An information processing apparatus characterized by that. The information processing apparatus according to claim 1,
The instructions constituting the program stored in the storage circuit have watermark information in unused bits,
The arithmetic circuit executes arithmetic processing based on information excluding the watermark information among the instructions.
An information processing apparatus characterized by that. The information processing apparatus according to claim 2,
The instruction includes a conditional branch instruction,
The watermark information is under a predetermined condition that affects the branch of the conditional branch instruction,
Stored according to the order of the instructions executed by the arithmetic circuit,
An information processing apparatus characterized by that. The information processing apparatus according to claim 3,
The information processing apparatus according to claim 1, wherein the predetermined condition is that a predetermined input that affects a branch of the conditional branch instruction is given to the arithmetic circuit. The information processing apparatus according to claim 2, wherein
The information processing apparatus, wherein the instruction code constituting the instruction is set to have a shorter code length as the frequency of appearance of the instruction in the program is higher. The information processing apparatus according to any one of claims 1 to 4,
The information processing apparatus, wherein the storage circuit is subjected to logical compression based on stored bit information. In a design apparatus for designing an information processing apparatus having a storage circuit for storing a program and an arithmetic circuit for executing the program,
Input means for receiving input of watermark information;
The storage circuit that stores the watermark information input through the input unit is configured as a random gate circuit as a combinational circuit of logic elements, and a generation unit that generates design information of the random gate circuit;
The design apparatus characterized by having.

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