JP2009194722A - Communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a communication device capable of obtaining excellent characteristics by correcting device distortion and propagation distortion. <P>SOLUTION: The communication device for reception includes: a high frequency demodulation circuit 2 for converting a received signal into a baseband signal; an analog/digital conversion circuit 3 for converting the baseband signal converted by the high frequency demodulation circuit into a digital signal; and a baseband demodulation circuit 5 which demodulates the baseband signal from the digital signal converted by the analog/digital conversion circuit and outputs the demodulated baseband signal, wherein, between the analog/digital conversion circuit 3 and the baseband demodulation circuit 5, a frequency equalization circuit 4 for reception is provided which corrects device distortion and propagation distortion. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a communication apparatus that performs communication using a telephone line, a wireless line, an optical communication line, and the like, and more particularly, to a communication apparatus having an equalizing function for automatically correcting characteristics in a transmission apparatus and a reception apparatus.

  Conventionally, as a communication device when using a wireless communication line (see, for example, Patent Document 1), baseband modulation is performed on a data to be transmitted, in addition to baseband modulation such as QPSK, 16QAM, and OFDM, and output by performing band limitation using a filter. A modulation circuit, a digital-analog conversion circuit that converts the data output from the baseband modulation circuit into an analog signal, and a high-frequency radio signal having a desired frequency component by modulating the analog signal converted by the digital-analog conversion circuit There is a communication device for transmission provided with a harmonic modulation circuit. The high frequency radio signal is transmitted from the antenna.

  On the other hand, a high-frequency demodulation circuit that converts a signal received by an antenna into a baseband signal, an analog-digital conversion circuit that converts a baseband signal converted by the high-frequency demodulation circuit into a digital signal, and a digital signal that is converted by an analog-digital conversion circuit There is a receiving communication device including a baseband demodulation circuit that demodulates and outputs a baseband signal from a signal.

JP 2004-235803 A

  However, in the above-described communication apparatus, in wideband communication, particularly mobile radio communication, there are characteristic distortions of devices used in the apparatus and fluctuations in power / delay / frequency response in the propagation path, causing deterioration of error rate characteristics.

  The present invention has been made in view of the above-described points, and an object of the present invention is to obtain a communication apparatus capable of correcting device distortion and propagation distortion and obtaining good characteristics.

  The receiving communication device according to the present invention includes a high frequency demodulation circuit that converts a received signal into a baseband signal, an analog-digital conversion circuit that converts a baseband signal converted by the high frequency demodulation circuit into a digital signal, and the analog In a receiving communication device comprising a baseband demodulating circuit that demodulates and outputs a baseband signal from a digital signal converted by a digital converting circuit, a device is provided between the analog-digital converting circuit and the baseband demodulating circuit. A reception frequency equalizing circuit for correcting distortion and propagation distortion is provided.

  The transmission communication apparatus according to the present invention includes a baseband modulation circuit for performing band limitation on data to be transmitted in addition to baseband modulation, and outputting the data output from the baseband modulation circuit as an analog signal. In the transmission communication apparatus, comprising: a digital-analog conversion circuit for conversion; and a harmonic modulation circuit that obtains a signal having a desired frequency component by modulating the analog signal converted by the digital-analog conversion circuit. A transmission frequency equalizing circuit for correcting device distortion and propagation distortion is provided between the circuit and the digital-analog conversion circuit.

  According to the present invention, by incorporating a frequency equalization circuit, it is possible to correct a device distortion used in a transmission / reception apparatus and a propagation distortion in a transmission path, thereby providing a highly reliable communication path.

  The device distortion in the wireless apparatus is a steady distortion although there are individual differences. Therefore, it is necessary to perform fixed equalization that allows fluctuation of individual differences on the transmission side or the reception side. Also, the distortion of the transmission path changes with time due to fading. Therefore, it is necessary to detect and equalize the distortion for each packet on the receiving side.

  In the present invention, by providing a circuit having a frequency equalization function, device distortion and propagation distortion are corrected to obtain good characteristics. Hereinafter, specific embodiments will be described.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a receiving radio apparatus according to Embodiment 1 of the present invention. As shown in FIG. 1, the receiving radio apparatus according to Embodiment 1 includes a high-frequency demodulation circuit 2 that converts a signal received by an antenna 1 into a baseband signal, and a baseband signal that is converted by the high-frequency demodulation circuit 2. An analog-to-digital converter (ADC) 3 for converting to a digital signal, a reception frequency equalizing circuit 4 for correcting device distortion and propagation distortion from the digital signal converted by the analog-to-digital converter 3, and reception And a baseband demodulating circuit 5 for demodulating a baseband signal from the output of the frequency equalizing circuit 4 and outputting it as a data output.

  FIG. 2 is a block diagram showing a detailed internal configuration of the reception frequency equalization circuit 4 shown in FIG. The reception frequency equalization circuit 4 includes a synchronization function block 41 and a frequency equalization function block 42 as shown in FIG. The digital signal oversampled by the analog / digital conversion circuit 3 is input to the synchronization function block 41 via the band limiting filter 6, and the output of the frequency equalization function block 42 is subjected to symbol determination by the symbol determination circuit 7 to restore the data. Is done.

  Here, the synchronous function block 41 is down-sampled by a down-sampling circuit 41a for down-sampling the digital signal converted by the analog-digital conversion circuit 3, a down-sampling timing extraction circuit 41b for determining the timing of down-sampling. A frame timing extraction circuit 41c that determines the timing of serial-parallel conversion of the digital signal for each frame.

  Further, the frequency equalization function block 42 includes a serial / parallel conversion circuit 42a that converts the digital signal down-sampled by the synchronization function block 41 into serial / parallel conversion for each frame based on the timing determined by the frame timing extraction circuit 41c; A guard interval deletion circuit 42b for deleting the guard interval of the digital signal subjected to serial / parallel conversion, a fast Fourier transform (FFT) circuit 42c for performing a fast Fourier transform process on the output of the guard interval deletion circuit 42b, and a fast Fourier transform A frequency domain equalization (FDE) circuit 42d that performs frequency domain equalization on the output of the circuit 42c, and an inverse fast Fourier transform (IF) that performs an inverse fast Fourier transform on the output of the frequency domain equalization circuit 42d. F: has a Inverse FFT) circuit 42e, and a parallel-to-serial conversion circuit 42f to the output of the inverse fast Fourier transform circuit 42e performs parallel-serial conversion, and a weighting estimation circuit 42g for calculating a weighting factor to the frequency domain equalization circuit 42d.

  In the reception frequency equalization circuit 4 having the configuration shown in FIG. 2, the digital signal converted by the analog-digital conversion circuit 3 and oversampled is input to the synchronous function block 41 via the band limiting filter 6 and down-sampled. Down-sampled by the circuit 41a. The timing of downsampling is determined by the downsampling timing extraction circuit 41b.

  The downsampled digital signal is subjected to serial / parallel conversion for each frame by the serial / parallel conversion circuit 42a of the frequency equalization function block 42 based on the timing determined by the frame timing extraction circuit 41c. Thereafter, the guard interval is deleted from the serial-parallel converted digital signal by the guard interval deleting circuit 42b, and the digital signal passes through the fast Fourier transform circuit 42c, the frequency domain equalizing circuit 42d, and the inverse fast Fourier transform circuit 42e. The parallel-to-serial conversion is performed by 42f, symbol determination is performed by the symbol determination circuit 7, and data is restored.

  Here, the weighting coefficient used in the frequency domain equalization circuit 42d is determined by the weight estimation circuit 42g from the pilot signal after deleting the guard interval using the pilot signal frame transmitted at the head of the burst or periodically. .

  FIG. 3 is a block diagram showing a configuration of the weighting estimation circuit 42g shown in FIG. As shown in FIG. 3, the weighting estimation circuit 42g includes a noise power estimation circuit 42g1 for estimating noise power based on the output of the inverse fast Fourier transform circuit 42e, and a guard signal among pilot signals from the inverse fast Fourier transform circuit 42e. A windowing circuit 42g2 that cuts out the time corresponding to the interval, a fast Fourier transform (FFT) circuit 42g3 that converts the output of the windowing circuit 42g2 into frequency domain data by fast Fourier transform, and the estimated noise power A weighting calculation circuit 42g4 for calculating a weighting coefficient to the frequency domain equalization circuit 42d by a division function based on estimation of MMSE (Minimizing Mean Square Error) using a CORDIC (COordinate Rotation Digital Computer) algorithm based on the obtained frequency domain data; Have

  In FIG. 3, a frame including a pilot signal among the received signals passes through the FFT circuit 42c, the FDE circuit 42d, and the IFFT circuit 42e, and then is input to the weighting estimation circuit 42g. The input data is input to the noise power estimation circuit 42g1, and the noise power is estimated. On the other hand, a time corresponding to the guard interval is extracted from the pilot signal by the windowing circuit 42g2, and is converted into frequency domain data by the FFT circuit 42g3. The weight calculation circuit 42g4 determines a weighting coefficient based on the converted frequency domain data and the estimated noise power. In the weight calculation circuit 42g4, the weight calculation is performed by MMSE. At this time, the CORDIC algorithm is used for necessary division. The calculated weighting coefficient is fed back to the FDE circuit 42d and used as a weighting coefficient for frequency domain equalization of the data signal received later.

  FIG. 4 is a block diagram showing a configuration of the frame timing extraction circuit 41c in the synchronous function block 41 shown in FIG. As shown in FIG. 4, the frame timing extraction circuit 41 c includes a correlator 41 c 1 that performs pilot signal correlation detection, an integrator 41 c 2 that integrates the output of the correlator 41 c 2 in a guard interval, and outputs from the integrator 41 c 2. A maximum value searcher 41c3 that performs maximum value detection and determines the detected maximum value as a synchronization detection timing.

  In FIG. 4, the timing detection is performed by the correlator 41c1 with respect to the timing determination code sent from the transmission side. The output of the correlator 41c1 is integrated in the interval of the guard interval by the integrator 41c2, and the maximum value is detected by the maximum value searcher 41c3 to determine the frame timing. This is performed so that the maximum power of the received signal enters within the guard interval, and is particularly effective when the first wave is smaller than the second wave in an NLOS (non line of sight) environment.

  5 and 6 are a signal waveform diagram and a flowchart for explaining the operation of the frame timing extraction circuit 41c shown in FIG. As the output of the correlator 41c1, an output reflecting the impulse response of the propagation path is obtained. By passing this through the integrator 41c2, the output waveform of the integrator 41c2 is obtained, and the maximum value searcher 41c3 determines the maximum value as the timing of synchronous detection.

  That is, as shown in FIG. 6, the maximum value searcher 41c3 compares the output of the integrator 41c2 with a threshold value (steps S61 and S62), and searches for the maximum value among the samples of the guard interval GI from the output above the threshold value. Then, the guard interval GI is determined at the maximum value, and synchronization detection is performed (step S64).

  FIG. 7 is a block diagram showing a configuration of a frame timing extraction circuit 41c different from the configuration shown in FIG. The frame timing extraction circuit 41c shown in FIG. 7 performs a maximum value detection from a correlator 41c1 that performs pilot signal correlation detection, and an output from the correlator 41c1, and determines the detected maximum value as a synchronization detection timing. And a value searcher 41c3.

  According to the frame timing extraction circuit 41c shown in FIG. 7, the maximum value is directly detected by the maximum value searcher 41c3 from the output of the correlator 41c1, and the point is determined as the timing, so that the circuit can be simplified. is there.

  The same effect can be obtained by using the average value correction circuit 43 shown in FIG. 8 instead of the weight estimation circuit 42g having the configuration shown in FIG.

  In FIG. 8, the FFT of the received pilot is input to the adjacent data averaging unit 43a, the average of two adjacent data of the data for determining the weight is obtained, and the data and the average value for determining the weight by the comparison unit 43b And the weighting unit 43c determines a weighting coefficient that eliminates the difference. If the threshold is not exceeded, the weighting unit 43d sets the weighting coefficient to 1.0. A weighting coefficient for the number of points of the FFT is determined, and the data sent behind the pilot is equalized using the weighting coefficient. This process is repeated for all frequency components.

  By using the average value correction circuit 43 shown in FIG. 8, it is possible to easily remove the influence of the DC offset that is often present in the receiving circuit and the like.

  Further, by using the weighting estimation circuit 42g having the configuration shown in FIG. 3 and the average value correction circuit 43 shown in FIG. 8 connected in series, it is possible to simultaneously remove distortions such as fading and DC offset that vary sequentially.

  The above-described first embodiment describes the reception communication device, but can also be applied to a transmission communication device using a similar configuration.

  FIG. 9 is a block diagram showing a configuration of a transmission communication apparatus corresponding to the configuration of the reception communication apparatus shown in FIG. The transmission communication apparatus shown in FIG. 9 includes a baseband modulation circuit 11 that outputs a data to be transmitted by performing band limitation in addition to baseband modulation, and device distortion and propagation of data output from the baseband modulation circuit 11. A transmission frequency equalization circuit 12 that corrects distortion, a digital-to-analog converter (DAC) 13 that converts the output of the transmission frequency equalization circuit 12 into an analog signal, and a digital-analog conversion circuit 13 And a harmonic modulation circuit 14 that modulates the analog signal converted in step (b) to obtain a high-frequency radio signal having a desired frequency component and transmits it from the antenna 15.

  According to the illustrated configuration, a transmission frequency equalization circuit 12 that corrects device distortion and propagation distortion similar to the reception frequency equalization circuit 4 is provided between the baseband modulation circuit 11 and the digital-analog conversion circuit 13. Thus, it is possible to provide a highly reliable communication path by correcting device distortion used in the transmission communication apparatus and propagation distortion in the transmission path.

  The communication device described above is a communication device that includes an antenna and performs communication using a wireless line, but has an optical fiber terminal and an E / O / O / E conversion circuit instead of the antenna. Of course, the present invention can also be applied to a communication device using an optical communication line or a communication device using a telephone line.

It is a block diagram which shows the structure of the radio | wireless apparatus for reception which concerns on Embodiment 1 of this invention. FIG. 2 is a block diagram showing a detailed internal configuration of a reception frequency equalization circuit 4 shown in FIG. 1. It is a block diagram which shows the structure of the weight estimation circuit 42g shown in FIG. FIG. 3 is a block diagram showing a configuration of a frame timing extraction circuit 41c in the synchronous function block 41 shown in FIG. FIG. 5 is a signal waveform diagram for explaining the operation of the frame timing extraction circuit 41c shown in FIG. 5 is a flowchart for explaining the operation of a frame timing extraction circuit 41c shown in FIG. FIG. 5 is a block diagram showing a configuration of a frame timing extraction circuit 41c according to another example different from the configuration shown in FIG. It is a block diagram which shows the structure of the average value correction circuit 43 used instead of the weighting estimation circuit 42g of the structure shown in FIG. It is a block diagram which shows the structure of the communication apparatus for transmission corresponding to the structure of the communication apparatus for reception shown in FIG.

Explanation of symbols

  1 antenna, 2 high frequency demodulation circuit, 3 analog-digital conversion circuit, 4 reception frequency equalization circuit, 5 baseband demodulation circuit, 6 band limiting filter, 7 symbol determination circuit, 41 synchronization function block, 42 frequency equalization function block, 41a downsampling circuit, 41b downsampling timing extraction circuit, 41c frame timing extraction circuit, 42a serial parallel conversion circuit, 42b guard interval deletion circuit, 42c fast Fourier transform circuit, 42d frequency domain equalization circuit, 42e inverse fast Fourier transform Circuit, 42f parallel serial conversion circuit, 42g weighting estimation circuit, 42g1 noise power estimation circuit, 42g2 Windowing circuit, 42g3 FFT circuit, 42g4 weighting calculation circuit, 41c1 correlator, 41c2 Min instrument, 41C3 maximum value search unit, 11 a baseband modulation circuit, 12 a transmission frequency equalization circuit, 13 digital-to-analog conversion circuit, 14 a harmonic modulation circuit, 15 an antenna.

Claims (6)

A high-frequency demodulating circuit that converts a received signal into a baseband signal, an analog-digital converting circuit that converts a baseband signal converted by the high-frequency demodulating circuit into a digital signal, and a digital signal converted by the analog-digital converting circuit In a receiving communication device including a baseband demodulating circuit that demodulates and outputs a baseband signal,
A receiving communication apparatus, wherein a receiving frequency equalizing circuit for correcting device distortion and propagation distortion is provided between the analog-digital conversion circuit and the baseband demodulation circuit. The receiving communication device according to claim 1,
The reception frequency equalization circuit includes:
Downsampling timing extraction circuit for determining the downsampling timing of the digital signal converted by the analog-digital conversion circuit, and frame timing extraction circuit for determining the timing for serial-parallel conversion of the downsampled digital signal for each frame A synchronization functional block having
The digital signal down-sampled by the synchronous functional block is serial-parallel converted for each frame based on the timing determined by the frame timing extraction circuit, and serial-parallel converted by the serial-parallel conversion circuit. A guard interval deletion circuit for deleting a guard interval of a digital signal, a fast Fourier transform circuit for performing a fast Fourier transform on the output of the guard interval deletion circuit, and a frequency domain equalization for processing the output of the fast Fourier transform circuit on a frequency domain Circuit, an inverse fast Fourier transform circuit that performs inverse fast Fourier transform on the output of the frequency domain equalization circuit, and a parallel-serial conversion circuit that performs parallel-serial conversion on the output of the inverse fast Fourier transform circuit Receiving communication apparatus characterized by comprising a function block. The receiving communication device according to claim 2,
The frequency equalization functional block estimates noise power based on the output of the inverse fast Fourier transform circuit, cuts out a time corresponding to the guard interval, converts it to frequency domain data by fast Fourier transform, and estimates the estimated noise. A receiving communication apparatus, further comprising: a weighting estimation circuit that calculates a weighting coefficient for the frequency domain equalization circuit based on power and the converted frequency domain data by a division function using a CORDIC algorithm. The receiving communication device according to claim 2,
The synchronization function block is:
Correlator for detecting the correlation of the pilot signal, integrator for integrating the output of the correlator in the interval of the guard interval, detecting the maximum value from the output of the integrator, and detecting the detected maximum value synchronously And a frame timing extraction circuit comprising a maximum value searcher determined as a receiving communication device. The receiving communication device according to claim 2,
The synchronization function block is:
A frame timing extraction circuit comprising: a correlator for detecting correlation of a pilot signal; and a maximum value searcher for detecting a maximum value from the output of the correlator and determining the detected maximum value as a timing of synchronous detection. A communication apparatus for reception. In addition to baseband modulation for data to be transmitted, a baseband modulation circuit that outputs a band-limited signal, a digital / analog conversion circuit that converts data output from the baseband modulation circuit into an analog signal, and the digital / analog conversion In a communication device for transmission provided with a harmonic modulation circuit that modulates an analog signal converted by a circuit to obtain a signal having a desired frequency component,
A transmission communication apparatus, wherein a transmission frequency equalizing circuit for correcting device distortion and propagation distortion is provided between the baseband modulation circuit and the digital-analog conversion circuit.

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