JP2009194600A - Detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a detection circuit which can reduce variations in thresholds in respective samples due to a process fluctuation or the like, can perform a high-speed operation and performs input detection and/or disconnection detection. <P>SOLUTION: A first detecting receiver 2 is configured with a differential amplifier circuit in which a pair of serial data signals is input to corresponding input ports, a second detecting receiver 3 is configured with a differential amplifier circuit in which a pair of serial data signals is input to corresponding input ports, and a reference receiver 7 is configured with a differential amplifier circuit in which offset is respectively added to respective reference voltage Vrp and Vrm input to corresponding input ports and is output. Each of the differential amplifier circuits of the first detecting receiver 2, the second detecting receiver 3 and the reference receiver 7 has a pair of input transistors configured with MOS transistors in which the respective serial data signals are correspondingly input to gates, voltage differences are provided in substrate gates of the respective input transistors, and offsets are respectively provided. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention detects whether a serial data signal used for a high-speed serial communication system using USB or the like has been input and / or detects whether a transmission medium such as a cable is connected or not. Regarding the circuit.

  In recent years, product interfaces have been speeded up and systems using high-speed serial communication have been developed. For example, such high-speed serial communication uses USB. As a USB standard, there was the USB 1.1 standard, but development of a system using the USB 2.0 standard capable of obtaining a communication speed of 480 Mbps, which is faster than the standard, is in progress. When receiving data with such a system, the presence / absence of connection of the transmission medium and the presence / absence of received data are determined by the value of the amplitude level of the signal.

FIG. 6 is a diagram showing a conventional example of a disconnection detection circuit compliant with the USB 2.0 standard.
The disconnection detection circuit 120 in FIG. 6 receives a pair of serial data signals transmitted from the serial transmission lines DP and DM and having opposite signal levels, and a transmission medium such as a cable is determined depending on the amplitude level of the serial data signals. Disconnection detection receivers 117 and 118 for detecting whether or not they are connected are provided. The cutoff detection receivers 117 and 118 are provided with an offset in the threshold value so as to operate only when the amplitude level of the received differential signal is larger than a predetermined value. Further, the disconnection detection circuit 120 includes an integration circuit 114 that integrates and outputs the output signals OUTa and OUTb of the disconnection detection receivers 117 and 118, and a Schmitt circuit 115 that shapes and outputs the output signal of the integration circuit 114. I have.

FIG. 7 is a timing chart showing an example of signals of the respective units in FIG.
The disconnection detection receivers 117 and 118 are respectively receivers with offsets provided in the threshold values. When serial data signals having an amplitude level larger than the threshold value VHSDISC are received from the serial transmission lines DP and DM, the disconnection detection receivers 117 and 118 are received. Pulse signals corresponding to the serial data signal are generated and output as output signals OUTa and OUTb. On the other hand, even if serial data signals having an amplitude level smaller than the threshold value VHSDISC are received from the serial transmission lines DP and DM, the disconnection detection receivers 117 and 118 do not react, and the output signals OUTa and OUTb are low ( Low) level.

The output signals OUTa and OUTb are integrated by the integration circuit 114, then subjected to waveform shaping by the Schmitt circuit 115 and output as a binary disconnection detection signal HDISCON. That is, the disconnection detection circuit 120 detects whether or not a transmission medium such as a cable is connected based on the difference in the amplitude level of the input serial data signal.
FIG. 8 is a diagram illustrating a circuit example of the disconnection detection receiver 117 of FIG.
In the disconnection detection receiver 117 of FIG. 8, the input transistors 121 and 122 which are P-channel MOS transistors (hereinafter referred to as PMOS transistors) are PMOS transistors of the same size and form a differential pair. A constant current i104 is applied by a PMOS transistor 126 to a connection portion between the input transistor 121 and an N-channel MOS transistor (hereinafter referred to as an NMOS transistor) 123, and an offset is provided in the threshold value. Note that an offset control signal offcnt is input to the gate of the PMOS transistor 126.

  In the disconnection detection receiver 117 of FIG. 8, the gate of the PMOS transistor 121 forms a non-inverting input terminal and is connected to the serial transmission line DP, and the gate of the PMOS transistor 122 forms an inverting input terminal and the serial transmission line DM is connected to the serial transmission line DM. It is connected. An output signal OUTa is output from a connection portion between the PMOS transistor 122 and the NMOS transistor 124. Although not shown, the disconnection detection receiver 118 is different from the disconnection detection receiver 117 in that the serial transmission line DM is connected to the gate of the PMOS transistor 121, and the serial transmission line DP is connected to the gate of the PMOS transistor 122. The circuit configuration is the same as that of the disconnection detection receiver 117.

FIG. 9 is a diagram illustrating a circuit example of the reference receiver 119 of FIG. In FIG. 9, the same or similar parts as those in FIG. 8 are denoted by the same reference numerals.
In the reference receiver 119 of FIG. 9, the output is a pair of output voltages Voa and Vob, and different predetermined offset voltages Vrp and Vrm are respectively input to the gate of the PMOS transistor 121 and the gate of the PMOS transistor 122. Except for this, it has the same circuit configuration as the disconnection detection receiver 117 of FIG.

The offset control signal offcnt is used by using the operational amplifier 113 so that the pair of output voltages Voa and Vob of the reference receiver 119 to which different predetermined offset voltages Vrp and Vrm output from the offset voltage generation circuit 111 are input are the same voltage. The offset control circuit 128 performs offset adjustment on the differential amplifier circuit 127 of the reference receiver 119, and the same offset adjustment as the offset adjustment performed on the reference receiver 119 is performed on the disconnection detection receivers 117 and 118. The offsets of the cutting detection receivers 117 and 118 are made constant.
As described above, conventionally, the offset current amount is fed back and adjusted in accordance with the process, temperature, and the like, thereby reducing the variation in threshold value and obtaining a highly accurate disconnection detection circuit.

Although different from the present invention, a differential circuit composed of first and second transistors to which serial data signals of differential signals are input, and third and fourth transistors to which offset signals are input. And a voltage at a connection point between the drain of the first transistor and the drain of the third transistor, and a voltage at a connection point between the drain of the second transistor and the drain of the fourth transistor, Is provided. When the serial data signal is not applied, the output level is constant. When the serial data signal is applied, an output whose level changes according to the input data is obtained. There was a serial data signal detection circuit (see, for example, Patent Document 1).
JP 2001-102878 A

  However, in the configuration as shown in FIG. 9, when the threshold offset provided in the reference receiver 119 is large, the difference between the gate voltages of the input transistors 121 and 122 becomes large, and the current i108 flowing through the input transistors 121 and 122 becomes large. And i109 become very large. For this reason, the offset current i104 applied by the PMOS transistor 126 increases, and the offset current i104 has a current amount corresponding to the tail current (bias current) i107 flowing through the PMOS transistor 125 of the differential amplifier circuit unit 127.

  Under these circumstances, if the transistor size and threshold voltage vary due to process variations, the offset current i104 differs greatly between the reference receiver 119 and the disconnection detection receivers 117 and 118, and the threshold value There was a problem that offsets varied. Specifically, in the disconnection detection receiver 117 shown in FIG. 8, when the offset current i104 varies and becomes larger than the tail current i107 and becomes larger than the current i106 flowing through the PMOS transistor 122, the serial transmission lines DP and DM are connected. Even when serial data having a large amplitude is input, there is a problem that the output signal OUTa remains constant at a low level and disconnection cannot be detected.

  Actually, in the USB 2.0 standard, since the threshold value offset of the disconnection detection circuit is as large as about five times that of the serial data detection circuit, such a problem may occur. In order to reduce the variation in offset, a method of increasing the gate area of each input transistor is conceivable. However, this causes a problem that the operation speed of the disconnection detection receivers 117 and 118 is lowered and is suppressed. There is also a limit to the range of offset variation that can be performed.

  The present invention has been made to solve such a problem, and by adjusting the threshold offset by the difference in substrate bias of the input transistor in the differential amplifier circuit, it is possible to obtain a sample-by-sample variation due to process variation or the like. Input detection of whether or not a serial data signal used for a high-speed serial communication system conforming to the USB standard or the like that can reduce threshold variation and perform high-speed operation, and / or cable An object of the present invention is to obtain a detection circuit that detects disconnection of whether or not a transmission medium such as the above is connected.

In the detection circuit according to the present invention, an input detection as to whether or not a pair of serial data signals having opposite signal levels has been input and / or a transmission medium such as a cable through which the pair of serial data signals are transmitted is provided. In a detection circuit that detects disconnection of whether or not connected,
A first detection receiver circuit unit configured by a differential amplifier circuit to which the pair of serial data signals are respectively input to corresponding input terminals;
A second detection receiver circuit unit configured by a differential amplifier circuit to which the pair of serial data signals are respectively input to corresponding input terminals;
A detection circuit unit that performs the input detection and / or the disconnection detection by a predetermined method from each output signal of the first detection receiver circuit unit and the second detection receiver circuit unit;
With
Each differential amplifier circuit of the first detection receiver circuit unit and the second detection receiver circuit unit includes a pair of first input transistors each including a MOS transistor to which the serial data signal is input to the gate correspondingly. And an offset is provided by providing a voltage difference between the substrate gates of the first input transistors.

Specifically, each differential amplifier circuit of the first detection receiver circuit unit and the second detection receiver circuit unit is:
A first load circuit section that forms a load on each of the first input transistors;
A first bias current supply circuit for supplying a first bias current to each of the first input transistors;
Each with
Each substrate gate of each of the first input transistors is connected to correspond to an input terminal and an output terminal of the first bias current supply circuit unit.

In addition, a reference receiver circuit unit configured by a differential amplifier circuit that outputs each predetermined voltage input to the corresponding input terminal by adding an offset, and
An offset control signal generation circuit unit that compares each output voltage output from the reference receiver circuit unit, generates an offset control signal according to the comparison result, and outputs the offset control signal;
With
The first bias current supply circuit unit generates the first bias current according to the offset control signal.

  In this case, the differential amplifier circuit of the reference receiver circuit unit has a pair of second input transistors each composed of a MOS transistor to which each predetermined voltage is input to the gate correspondingly, and each second input transistor Each substrate gate is provided with an offset by providing a voltage difference.

Specifically, the differential amplifier circuit of the reference receiver circuit unit is
A second load circuit section that forms a load on each of the second input transistors;
A second bias current supply circuit section for supplying a second bias current to each of the second input transistors;
With
Each substrate gate of each of the second input transistors is connected to correspond to an input terminal and an output terminal of the second bias current supply circuit unit.

  In this case, the second bias current supply circuit unit generates the second bias current according to the offset control signal.

  According to the detection circuit of the present invention, each differential amplifier circuit of the first detection receiver circuit unit and the second detection receiver circuit unit includes a MOS transistor in which each serial data signal is input to a corresponding gate. A pair of first input transistors are provided, and an offset is provided by providing a voltage difference at the substrate gate of each first input transistor. This makes it possible to reduce variations in threshold offset due to variations in transistor size and threshold voltage due to process variations, and to detect whether a transmission medium such as a cable is connected or not. Can be performed accurately and at high speed, and as specified in the USB 2.0 standard, etc., input detection as to whether or not a serial data signal has been input can be accurately performed even in a detection circuit having a large threshold offset. A stable system that can be performed at high speed and conforms to the USB standard or the like can be provided.

  In addition, due to the effects described above, it is not necessary to increase the gate area of the input transistor of the differential amplifier circuit in consideration of process variations, so that the serial data signal is detected when serial data is received and / or the cable is disconnected. It is possible to generate a signal indicating this at high speed.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a circuit example of a detection circuit according to the first embodiment of the present invention.
The detection circuit 1 in FIG. 1 detects whether a serial data signal used in a high-speed serial communication system using USB or the like has been input, and / or disconnects whether a transmission medium such as a cable is connected. The detection is performed.

  The detection circuit 1 includes a first detection receiver 2 configured by a differential amplifier circuit to which a pair of serial data signals are input by connecting serial transmission lines DP and DM to corresponding input terminals, and a first detection signal. A second detection receiver 3 having the same circuit configuration as the receiver 2 is provided. The detection circuit 1 also integrates the output signals OUT1 and OUT2 of the first detection receiver 2 and the second detection receiver 3 and performs waveform shaping of the signal S1 output from the integration circuit 4. And a Schmitt circuit 5 that outputs a binary detection signal HDISCON.

  Further, the detection circuit 1 includes an offset voltage generation circuit 6 that generates and outputs predetermined reference voltages Vrp and Vrm, respectively, and a differential that provides an offset with respect to signals input to the non-inverting input terminal and the inverting input terminal. A reference receiver 7 that forms an amplifier and a pair of output voltages Vo1 and Vo2 output from the reference receiver 7 are compared, an offset control signal offcnt corresponding to the comparison result is generated, and a first detection receiver 2; An operational amplifier 8 that outputs to each of the second detection receiver 3 and the reference receiver 7 is provided. The first detection receiver 2 forms a first detection receiver circuit unit, the second detection receiver 3 forms a second detection receiver circuit unit, and the integration circuit 4 and the Schmitt circuit 5 form a detection circuit unit. The reference receiver 7 forms a reference receiver circuit unit, and the operational amplifier 8 forms an offset control signal generation circuit unit.

  A serial transmission line DP is connected to the non-inverting input terminal of the first detection receiver 2 and the inverting input terminal of the second detection receiver 3, and the inverting input terminal of the first detection receiver 2 and the second detection receiver 3 are connected. A serial transmission line DM is connected to each non-inverted input terminal. In the reference receiver 7, the reference voltage Vrp is input to the non-inverting input terminal, and the reference voltage Vrm is input to the inverting input terminal. The reference receiver 7 sets a predetermined offset value (Vrp−Vrm) to the reference voltages Vrp and Vrm. ) And output to the operational amplifier 8 as output voltages Vo1 and Vo2. The output signal of the operational amplifier 8 is output to the first detection receiver 2, the second detection receiver 3, and the reference receiver 7 as a control signal offcnt for controlling the offset.

Here, FIG. 2 is a circuit diagram showing an example of an internal circuit of the first detection receiver 2 shown in FIG.
In FIG. 2, the first detection receiver 2 includes a differential amplifier circuit unit 11 and an offset control circuit unit 12. The differential amplifier circuit unit 11 includes PMOS transistors M1 and M2 forming a differential pair, and NMOS transistors M3 and M4 forming a current mirror circuit and forming a load of the differential pair. In FIG. 2, the PMOS transistors M1 and M2 form a first input transistor, the NMOS transistors M3 and M4 form a first load circuit unit, and the offset control circuit unit 12 forms a first bias current supply circuit unit.

  The PMOS transistor M1 and the NMOS transistor M3 are connected in series, and the PMOS transistor M2 and the NMOS transistor M4 are connected in series. The gates of the NMOS transistors M3 and M4 are connected, the connection is connected to the drain of the NMOS transistor M3, the sources of the NMOS transistors M3 and M4 are connected, and the connection is connected to the ground voltage VSS. Has been. The gate of the PMOS transistor M1 forms a non-inverting input terminal and is connected to the serial transmission line DP. The gate of the PMOS transistor M2 forms an inverting input terminal and is connected to the serial transmission line DM.

The substrate gate (also referred to as a substrate terminal) of the PMOS transistor M1 is connected to the source, and the substrate gate of the PMOS transistor M2 is connected to the power supply voltage VDD. The substrate gates of the NMOS transistors M3 and M4 are connected to the ground voltage VSS. A connection portion between the PMOS transistor M2 and the NMOS transistor M4 forms an output terminal of the first detection receiver 2, and an output signal OUT1 is output from the output terminal.
The offset control circuit unit 12 generates a tail current, which is a bias current of the differential amplifier circuit unit 11, between the PMOS transistor M5, the drain of the PMOS transistor M5, and the connection between the sources of the PMOS transistors M1 and M2. And a connected resistor R1. In the PMOS transistor M5, an offset control signal offcnt is input to the gate, and the substrate gate is connected to the power supply voltage VDD.

The second detection receiver 3 is different from the first detection receiver 2 in that the serial transmission line DM is connected to the gate of the PMOS transistor M1, and the serial transmission line DP is connected to the gate of the PMOS transistor M2. The circuit configuration is the same as that of the first detection receiver 2.
In such a configuration, the drain current of the PMOS transistor M1 is i1, and the drain current of the PMOS transistor M2 is i2. Furthermore, the drain current of the PMOS transistor M5 flowing from the offset control circuit unit 12 to the PMOS transistors M1 and M2 is i3. The current i3 forms a first bias current. The current i3 is the sum of the currents i1 and i2, and the current i3 is for providing an offset to the threshold value of the first detection receiver 2. A voltage at a connection portion between the sources of the PMOS transistors M1 and M2 is set to V1.

  The current i1 is determined by the voltage value of the input voltage from the serial transmission line DP, and the current i2 is determined by the voltage value of the input voltage from the serial transmission line DM. The offset of the threshold value of the first detection receiver 2 increases in proportion to the current value of the current i3, and the offset value can be adjusted by the voltage of the offset control signal offcnt input from the operational amplifier 8. Specifically, as the voltage of the offset control signal offcnt from the operational amplifier 8 decreases, the current i3 increases and the voltage V1 decreases, and the substrate bias voltage and threshold voltage of the PMOS transistor M2 increase. At this time, since the substrate bias voltage of the PMOS transistor M1 remains 0 and the threshold voltage of the PMOS transistor M1 is constant, the offset of the first detection receiver 2 becomes large.

  On the other hand, as the voltage of the offset control signal offcnt output from the operational amplifier 8 increases, the current i3 decreases and the voltage V1 increases, and the substrate bias voltage and the threshold voltage of the PMOS transistor M2 decrease. Similarly, since the substrate bias voltage of the PMOS transistor M1 remains 0 and the threshold voltage of the PMOS transistor M1 is constant, the offset of the first detection receiver 2 is reduced. Thus, the offset of the first detection receiver 2 can be adjusted according to the offset control signal offcnt that is the output signal of the operational amplifier 8.

FIG. 3 is a diagram showing a circuit example of the reference receiver 7 shown in FIG. In FIG. 3, the same or similar parts as those in FIG.
In the configuration of the reference receiver 7 of FIG. 3, the drain current of the PMOS transistor M1 is i11, and the drain current of the PMOS transistor M2 is i12.
In FIG. 3, the reference receiver 7 includes a differential amplifier circuit unit 11 and an offset control circuit unit 12. In FIG. 3, the PMOS transistors M1 and M2 constitute a second input transistor, the NMOS transistors M3 and M4 constitute a second load circuit unit, and the offset control circuit unit 12 constitutes a second bias current supply circuit unit. i3 forms a second bias current.

  In the differential amplifier circuit 11, the reference voltage Vrp is input to the gate of the PMOS transistor M1, and the reference voltage Vrm is input to the gate of the PMOS transistor M2. The input reference voltages Vrp and Vrm are set to a predetermined offset value (Vrp). -Vrm) is provided and output from the reference receiver 7. An output voltage Vo1 is output from a connection portion between the PMOS transistor M1 and the NMOS transistor M3, and an output voltage Vo2 is output from a connection portion between the PMOS transistor M2 and the NMOS transistor M4.

  In this way, the differential output voltages Vo1 and Vo2 output from the reference receiver 7 are respectively input to the corresponding input terminals of the operational amplifier 8, and the reference receiver 7 feeds back the voltage indicating the comparison result from the operational amplifier 8, and is offset. The offset is adjusted by the control signal offcnt. The operational amplifier 8 adjusts the offset of the reference receiver 7 so that the output voltages Vo1 and Vo2 of the reference receiver 7 have the same value, that is, the currents i11 and i12 are the same. For this reason, the first detection receiver 2, the second detection receiver 3, and the reference receiver 7 have threshold values corresponding to an offset value (Vrp−Vrm) that is a difference between the reference voltages Vrp and Vrm. The threshold values of the first detection receiver 2, the second detection receiver 3, and the reference receiver 7 are constant even if the power supply voltage or the like changes.

Further, the first detection receiver 2 and the second detection receiver 3 are different from the substrate bias difference of the transistors to which the differential signal is input, that is, the threshold voltage, instead of the conventional additional offset current. Since the offset is provided depending on the difference between the threshold values, even when the offset is large, it is possible to reduce the variation of the threshold value for each sample due to the process variation.
The amplitude of the serial data signal defined by the USB 2.0 standard is 400 mV when the serial transmission lines DP and DM are connected, and 800 mV when the serial transmission lines DP and DM are disconnected, and USB 1.1. The value is considerably smaller than 3.3 V defined by the standard.

  As described above, even when the amplitude of the serial data signal becomes small and it is difficult to determine data reception, the detection circuit 1 shown in FIGS. 1 to 3 has a pair of serial transmission lines DP and DM. Can detect the amplitude of the serial data signal accurately, detect whether the pair of serial data signals is input, and / or transmit a cable or the like through which the pair of serial data signals are transmitted. It is possible to accurately detect whether or not a medium is connected. Further, the detection circuit 1 does not need to increase the gate area of the input transistor in order to suppress variation in offset as in the conventional case, and can perform high-speed operation.

Here, FIG. 4 is a diagram showing an example of an internal circuit of the integrating circuit 4 shown in FIG.
In FIG. 4, the integration circuit 4 includes a PMOS transistor M11, NMOS transistors M12 and M13, and a low-pass filter 15. A PMOS transistor M11 and an NMOS transistor M12 are connected in series between the power supply voltage VDD and the ground voltage VSS, and an NMOS transistor M13 is connected in parallel with the NMOS transistor M12. The gate of the PMOS transistor M11 is connected to the ground voltage VSS, the output signal OUT1 from the first detection receiver 2 is input to the gate of the NMOS transistor M12, and the gate of the NMOS transistor M13 is supplied from the second detection receiver 3. An output signal OUT2 is input. A connection part of the PMOS transistor M11 and the NMOS transistors M12 and M13 is connected to an input terminal of the low-pass filter 15. The output signal of the low-pass filter 15 forms the output signal S1 of the integrating circuit 4.

  Here, it is assumed that the current driving capabilities of the NMOS transistors M12 and M13 are larger than those of the PMOS transistor M11, and the on-resistances of the NMOS transistors M12 and M13 are sufficiently smaller than the on-resistance of the PMOS transistor M11. In this way, the signals OUT1 and OUT2 input corresponding to the gates of the NMOS transistors M12 and M13 are inverted in signal level and input to the low-pass filter 15, and are integrated by the low-pass filter 15 to be a Schmitt circuit. 5 is output.

  Further, when the signal OUT1 rises and the signal OUT2 falls, or when the signal OUT1 falls and the signal OUT2 rises, the signals OUT1 and OUT2 may have the same voltage. Thus, there is a possibility that a small pulse is generated in the output signal S1 of the integration circuit 4 during a short period in which the signal levels of the signals OUT1 and OUT2 transition. The Schmitt circuit 5 has different threshold values for the rising and falling edges of the input binary signal S1, thereby waveform shaping and outputting the binary signal having the small pulse. can do.

FIG. 5 is a timing chart showing an example of signals of the respective units in FIG.
The first detection receiver 2 and the second detection receiver 3 form a receiver having an offset in the threshold value, and serial data signals having an amplitude level larger than the threshold value VHDISC from the serial transmission lines DP and DM. Is generated, and a pulse signal corresponding to the data signal is generated and output as output signals OUT1 and OUT2. On the other hand, even if serial data signals having amplitude levels smaller than the threshold value VHSDISC are received from the serial transmission lines DP and DM, the first detection receiver 2 and the second detection receiver 3 do not react, and the output signals OUT1 and OUT2 Each remains at a low level.

  The output signals OUT1 and OUT2 are integrated by the integration circuit 4, and then the waveform is shaped by the Schmitt circuit 5 and output as a binary detection signal HDISCON. That is, the detection circuit 1 detects whether or not a pair of serial data signals having opposite signal levels are input depending on the difference in amplitude level of the input serial data signal, and / or a transmission medium such as a cable. Disconnection detection of whether or not is connected.

  As described above, the detection circuit according to the first embodiment is different from the substrate bias difference of the transistors to which the differential signal is input, that is, the threshold voltage difference, not by the additional offset current as in the conventional case. The offset was provided by. In this way, variations in threshold offset due to variations in transistor size and threshold voltage due to process variations can be reduced, and whether a transmission medium such as a cable is connected or not. Can be detected accurately and at high speed, and the detection of whether or not a serial data signal has been input even in a detection circuit having a large threshold offset as defined in the USB 2.0 standard, etc. Accurate and fast.

It is the figure which showed the circuit example of the detection circuit in the 1st Embodiment of this invention. FIG. 2 is a circuit diagram illustrating an example of an internal circuit of a first detection receiver 2 illustrated in FIG. 1. It is the figure which showed the circuit example of the reference receiver 7 shown in FIG. It is the figure which showed the example of the internal circuit of the integration circuit 4 shown in FIG. FIG. 2 is a timing chart illustrating an example of signals of respective units in FIG. 1. FIG. It is the figure which showed the prior art example of the cutting | disconnection detection circuit based on USB2.0 specification. FIG. 7 is a timing chart showing an example of signals at various parts in FIG. 6. FIG. It is the figure which showed the circuit example of the receiver 117 for a cutting | disconnection detection of FIG. FIG. 7 is a diagram illustrating a circuit example of a reference receiver 119 in FIG. 6.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Detection circuit 2 1st detection receiver 3 2nd detection receiver 4 Integration circuit 5 Schmitt circuit 6 Offset voltage generation circuit 7 Reference receiver 8 Operational amplifier 11 Differential amplification circuit part 12 Offset control circuit part M1, M2, M5 PMOS transistor M3 M4 NMOS transistor R1 resistance

Claims (6)

Input detection as to whether or not a pair of serial data signals having opposite signal levels have been input, and / or disconnection as to whether or not a transmission medium such as a cable for transmitting the pair of serial data signals is connected In the detection circuit that performs detection,
A first detection receiver circuit unit configured by a differential amplifier circuit to which the pair of serial data signals are respectively input to corresponding input terminals;
A second detection receiver circuit unit configured by a differential amplifier circuit to which the pair of serial data signals are respectively input to corresponding input terminals;
A detection circuit unit that performs the input detection and / or the disconnection detection by a predetermined method from each output signal of the first detection receiver circuit unit and the second detection receiver circuit unit;
With
Each differential amplifier circuit of the first detection receiver circuit unit and the second detection receiver circuit unit includes a pair of first input transistors each including a MOS transistor to which the serial data signal is input to the gate correspondingly. And a offset is provided by providing a voltage difference between the substrate gates of the first input transistors. Each differential amplifier circuit of the first detection receiver circuit unit and the second detection receiver circuit unit is:
A first load circuit section that forms a load on each of the first input transistors;
A first bias current supply circuit for supplying a first bias current to each of the first input transistors;
Each with
2. The detection circuit according to claim 1, wherein each substrate gate of each of the first input transistors is connected to correspond to an input terminal and an output terminal of the first bias current supply circuit unit. A reference receiver circuit unit configured by a differential amplifier circuit that outputs an offset to each predetermined voltage input to a corresponding input terminal; and
An offset control signal generation circuit unit that compares each output voltage output from the reference receiver circuit unit, generates an offset control signal according to the comparison result, and outputs the offset control signal;
With
3. The detection circuit according to claim 2, wherein the first bias current supply circuit unit generates the first bias current according to the offset control signal.   The differential amplifier circuit of the reference receiver circuit unit has a pair of second input transistors composed of MOS transistors to which the respective predetermined voltages are input to corresponding gates, and the substrate of each second input transistor 4. The detection circuit according to claim 3, wherein an offset is provided by providing a voltage difference between the gates. The differential amplifier circuit of the reference receiver circuit unit is
A second load circuit section that forms a load on each of the second input transistors;
A second bias current supply circuit section for supplying a second bias current to each of the second input transistors;
With
5. The detection circuit according to claim 4, wherein each substrate gate of each of the second input transistors is connected to correspond to an input terminal and an output terminal of the second bias current supply circuit unit.   The detection circuit according to claim 5, wherein the second bias current supply circuit unit generates the second bias current according to the offset control signal.

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