JP2009194547A - Low-pass filter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-pass filter circuit (loop filter) for making a capacitive element compact, in which a variation in a PLL response characteristic due to voltage dependence when a MOS capacitor is used as a capacitive element and a deterioration in a jitter characteristic by gate leak current when a thin-film gate transistor is used as a MOS capacitor are suppressed. <P>SOLUTION: The loop filter includes a first capacitive element 31, and a resistance element 32 and a second capacitive element 33 which are connected to the capacitive element 31 in series. First current (Ip/10) is given to a first input end IN1 connected to one end of the first capacitive element 31 and second current (Ip/10) is given to a second input end IN2 connected to the other end of the first capacitive element 31 to thereby make the first capacitive element 31 compact. A variable voltage power source 35 connected to the resistance element 32 in series is controlled from a voltage control terminal 36 so as to make applied voltage of both ends of the first capacitive element 31 constant. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a low-pass filter circuit, and more particularly to a technique of a low-pass filter circuit suitable for use as a loop filter in a phase locked loop circuit.

  A phase-locked loop (hereinafter referred to as “PLL”) is now an essential component in a semiconductor integrated circuit system, and is mounted on almost all LSIs. The application range covers various fields such as communication devices, microprocessors, and IC cards.

  FIG. 7 shows a configuration of a general charge pump type PLL. The outline of the PLL will be described with reference to FIG. The phase comparator 10 compares the phase difference between the input clock CKin applied to the PLL and the feedback clock CKdiv, and outputs an up signal UP and a down signal DN corresponding to the phase difference. The charge pump circuit 20 outputs (discharges or sucks) the current Ip based on the up signal UP and the down signal DN. The loop filter 30 smoothes the current Ip and outputs it as a voltage Vout. The voltage controlled oscillator 40 changes the frequency of the output clock CKout of the PLL based on the voltage Vout. The frequency divider 50 divides the output clock CKout by N and feeds it back to the phase comparator 10 as a feedback clock CKdiv. As the above operation is repeated, the output clock CKout gradually converges to a predetermined frequency and is locked.

  Of the PLL components, the loop filter 30 is a particularly important element. It can be said that the response characteristic of the PLL is determined by the filter characteristic of the loop filter 30.

  FIG. 8 shows a typical active loop filter. Of these, FIG. 4A shows a passive filter, and FIG. 4B shows an active filter. Both can be equivalently converted and have the same transfer characteristics. As can be seen from the figure, the loop filter 30 is substantially a low-pass filtering circuit formed by a combination of a resistive element and a capacitive element, regardless of whether it is a passive type or an active type.

  By the way, according to the PLL control theory, the response bandwidth of the PLL is preferably set to a frequency of about 1/10 of the input clock at the maximum. According to this theory, in a PLL that receives a reference clock having a relatively low frequency, it is necessary to reduce the cut-off frequency of the loop filter and narrow the response bandwidth. Therefore, the loop filter in the conventional PLL has a relatively large time constant (that is, CR product). In order to realize this large CR product, it is common to increase the capacity element.

  However, increasing the capacity element causes an increase in circuit scale. This is a serious problem particularly in a semiconductor integrated circuit having a large number of PLLs, for example, a microprocessor. In particular, in the case of an IC card, from the viewpoint of reliability, it is necessary to avoid mounting parts larger than the thickness of the card, and it is practically impossible to take measures such as attaching a large capacitive element. .

Therefore, in order to reduce the capacity element of the loop filter, Patent Document 1 discloses a loop filter configuration shown in FIG. 9 as a conventional technique. The loop filter inputs two currents obtained by internally dividing the current Ip into a predetermined ratio (α: 1−α, for example, α = 0.1). Specifically, the loop filter inputs currents Ip / 10 and 9Ip / 10 from the input terminals IN1 and IN2, respectively. Then, the voltage generated at the input terminal IN1 is output. As a result, it is possible to significantly reduce the capacitance element 31 while ensuring a transfer characteristic equivalent to that of the passive filter shown in FIG. Here, the power supply 34 prevents the MOS transistor (not shown) that controls the supply / stop of the current to the input terminal IN2 from being unable to operate stably because the potential of the input terminal IN2 is close to the ground potential. Yes. Further, by applying a voltage equal to or higher than the threshold voltage of the MOS capacitor to both ends of the capacitive element 33, the voltage dependency of the MOS capacitance value is eliminated, and the MOS capacitor is easily used as the capacitive element.
JP 2005-20618 A

  However, in the conventional loop filter configuration, when a MOS capacitor is used for the capacitive element 31, if the voltage of the loop filter in the PLL locked state (the voltage at the input terminal IN1) is lowered as the power supply voltage is lowered, the MOS Since the voltage applied to the capacitor (capacitor 31) (difference voltage between the input terminal IN1 and the power supply 34 at the time of locking) is equal to or lower than the threshold voltage, the voltage dependency of the capacitance value increases, and the response characteristic of the PLL varies greatly. There was a problem.

  Further, the capacitor element 31 needs to hold a potential when the PLL is in a locked state, but when a low voltage transistor (thin film gate transistor) having the largest capacity per unit area is used for cost reduction, Since the gate leakage current is larger than that of other capacitive elements, there is a problem that the potential cannot be held due to the influence and the jitter characteristics deteriorate.

  The present invention solves the above-described conventional problems, and its object is to suppress variation in PLL response characteristics caused by voltage dependence of capacitance values when a MOS capacitor is used as the capacitance element, and to reduce the voltage as a capacitance element. An object of the present invention is to provide a low-pass filter circuit that reduces deterioration of jitter characteristics due to gate leakage current when a transistor (thin film gate transistor) is used.

  In order to achieve the above-described object, the present invention maintains a constant voltage at a low voltage when a low-voltage transistor (thin film gate transistor) is used as a capacitive element in a low-pass filtering circuit. Control.

  Specifically, the low-pass filtering circuit according to the first aspect of the present invention includes a first element block having a first capacitive element, a resistance element, and a variable voltage source connected in series to the resistance element. , A second element block having one end connected to the first element block and the other end connected to a reference potential; and a second capacitor element connected in parallel to the second element block. An element block; a first input terminal that receives a first current connected to a terminal of the first element block to which the second element block is not connected; and the first to third element blocks. A voltage generated at a second input terminal connected to a connection location and receiving a second current corresponding to a predetermined multiple of the first current in the same direction and a first input terminal of the first element block is output. And voltage control for controlling the voltage of the variable voltage source And having a child.

  According to a second aspect of the present invention, in the low-pass filtering circuit according to the first aspect, the variable voltage source is connected in series with the variable current source controlled by the voltage control terminal and the variable current source. And a voltage generated in the resistance element due to a current from the variable current source is used as an output.

  According to a third aspect of the present invention, in the low-pass filtering circuit according to the second aspect, the variable current source includes a current output type digital-analog conversion circuit in which the voltage control terminal is a digital control signal input terminal. It is characterized by that.

  According to a fourth aspect of the present invention, in the low-pass filtering circuit according to the second aspect, the variable current source includes a gate electrode as the voltage control terminal, a source electrode as the power supply terminal, and a drain electrode as the resistance element. It is characterized by comprising P-channel transistors connected to each other.

  According to a fifth aspect of the present invention, in the low-pass filter circuit according to any one of the first to third aspects, a voltage comparator that compares the output voltage of the output terminal with the output voltage of the variable voltage source. And a voltage control circuit for controlling the voltage of the variable voltage source based on the comparison result of the voltage comparator.

  According to a sixth aspect of the present invention, in the low-pass filtering circuit according to the fourth aspect, the negative input terminal is at the output terminal of the low-pass filtering circuit, and the positive input terminal is the voltage of the variable voltage source. The output point includes operational amplifiers each having an output terminal connected to the voltage control terminal.

  A seventh aspect of the present invention is the low-pass filter circuit according to any one of the first to sixth aspects, wherein a part or all of the resistance elements constituting the second element block are the variable voltage. It is also used as a resistance element constituting the source.

  As described above, according to the first to seventh aspects of the present invention, the voltage of the variable voltage source constituting the second element block is controlled in accordance with the output voltage of the low-pass filter circuit, whereby the first capacitor element is added. Since the voltage can be kept constant, variation in capacitance value due to voltage dependency when a MOS capacitor is used as the capacitor is minimized. Further, since the voltage applied to the first capacitor element can be made substantially zero, the gate leakage current when a low voltage transistor (thin film gate transistor) is used for the MOS capacitor can be minimized.

  As described above, according to the first to seventh aspects of the present invention, in the low-pass filter circuit, the variation in the capacitance value due to the voltage dependency when the MOS capacitor is used as the capacitive element is minimized, and the PLL response characteristic is obtained. In addition, the gate leakage current in the case where a low voltage transistor (thin film gate transistor) is used for the MOS capacitor is minimized, and the jitter characteristic deterioration due to the influence is prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows a configuration of a PLL according to the first embodiment of the present invention. The PLL according to the present embodiment is a PLL including a phase comparator 10, a charge pump circuit 20A, a loop filter 30A, a voltage controlled oscillator 40 as output clock generation means, and a frequency divider 50. Among these, the phase comparator 10, the voltage controlled oscillator 40, and the frequency divider 50 are as already described. Hereinafter, the charge pump circuit 20A and the loop filter 30A will be described in detail.

  The charge pump circuit 20A includes charging current sources 21 and 23 that supply currents αIp and (1-α) Ip, and discharging current sources 22 and 24, respectively. When the signal UP is supplied from the phase comparator 10, the control switches SW1 and SW3 are turned on, and the currents αIp and (1-α) Ip are discharged. On the other hand, when the signal DOWN is given, the control switches SW2 and SW4 are turned on, and the currents αIp and (1-α) Ip are sucked. That is, from the charge pump circuit 20A, two systems of current corresponding to the current Ip divided internally by α: (1-α) are input / output.

  The loop filter 30A inputs currents αIp and (1-α) Ip input / output from the charge pump circuit 20A to the first input terminal IN1 and the second input terminal IN2, respectively. In the loop filter 30A, a capacitive element 31 as a first element block is provided between the first input terminal IN1 and the second input terminal IN2. Between the second input terminal IN2 and the reference potential (ground potential), a resistance element 32 and a variable voltage source 35 connected in series as a second element block are connected in parallel to this. A capacitive element 33 as a third element block is provided. The loop filter 30A outputs the voltage generated at the input terminal IN1, that is, the voltage generated at one end of the capacitive element 31 from the output terminal Vout. Hereinafter, the output voltage at the output terminal Vout is also used for the sake of convenience.

  In the loop filter 30A, the current αIp given to the first input terminal IN1 flows through the capacitive element 31, the resistive element 32, and the capacitive element 33 connected in parallel. The second input terminal IN2 is supplied with a current (1-α) Ip in the same direction as the current αIp applied to the first input terminal IN1, and the resistor element 32 and the capacitor element 33 connected in parallel. Flowing. Accordingly, since only a part of the current flowing through the resistance element 32 and the capacitance element 33 connected in parallel flows in the capacitance element 31, the capacitance can be relatively reduced. The voltage generated between the capacitive element 31 and the resistive element 32 when the capacitive element 31 is downsized gives a current Ip to the input terminal IN1 when the input terminal IN2 is not provided and the capacitive element 31 is not downsized. There is no difference from the voltage that sometimes occurs.

に従って各素子値を変換することにより、図２（ｂ）に示した受動フィルタを得る。そして、この受動フィルタにおいて、入力端ＩＮ１とグランドとを入れ換えると共に、容量素子３１と抵抗素子３２との間に入力端ＩＮ２を設けて、２つの入力端ＩＮ１、ＩＮ２にそれぞれ電流Ｉｐ／１０及び９Ｉｐ／１０を与えるようにする。これにより、図２（ｃ）に示した容量素子３１が、従来の１／１０倍に縮小された受動フィルタ、すなわち、本実施形態に係るループフィルタ３０Ａを得る。 Here, a conversion method from a general passive filter to the loop filter 30A according to the present embodiment will be described with reference to FIG. The passive filter shown in FIG. 2A is nothing but the passive filter shown in FIG. In this passive filter, when the capacitance value of the capacitive element 31 is Cx, the resistance value of the resistive element 32 is Rx, and the capacitive value of the capacitive element 33 is C3x, the following conversion equations (1) to (3)

The passive filter shown in FIG. 2B is obtained by converting each element value according to the above. In this passive filter, the input terminal IN1 and the ground are interchanged, and the input terminal IN2 is provided between the capacitive element 31 and the resistance element 32, and currents Ip / 10 and 9Ip are respectively supplied to the two input terminals IN1 and IN2. / 10 is given. As a result, the passive element in which the capacitive element 31 shown in FIG. 2C is reduced to 1/10 times the conventional value, that is, the loop filter 30A according to the present embodiment is obtained.

  Returning to FIG. 1, in the loop filter 30 </ b> A according to the present embodiment, a variable voltage source 35 is connected in series with the resistance element 32. Here, the voltage of the variable voltage source 35 is controlled by the voltage control terminal 36 in accordance with the output voltage Vout of the loop filter 30A in the PLL locked state so that the voltage applied to both ends of the capacitive element 31 is kept constant. To. As a result, the voltage applied to the capacitive element 31 can be kept constant, so that there is no voltage dependency when a MOS capacitor is used as the capacitive element, and variations in PLL response characteristics can be suppressed. Further, by making the voltage of the variable voltage source 35 equal to the output voltage Vout of the loop filter 30A, the voltage applied to the first capacitor element 31 can be made substantially zero, so that the low voltage transistor (thin film gate) is added to the MOS capacitor. When the transistor is used, the gate leakage current can be minimized, and deterioration of jitter characteristics due to the influence can be prevented. As the method for controlling the voltage control terminal 36, the simplest method is to obtain the output voltage Vout in the locked state of the PLL in advance by simulation or evaluation and control it from the outside.

  A specific circuit configuration of the variable voltage source 35 in FIG. 1 is shown in FIG. In the figure, a variable voltage source 35 is composed of a variable current source 37 controlled by a voltage control terminal 36 and a resistance element 38 connected in series to the variable current source 37, and the variable current source 37 to the resistance element 38. The voltage generated at one end of the resistance element 38 is supplied as an output voltage.

  With such a configuration, the internal resistance value of the variable voltage source 35, that is, the resistance value Rv of the resistance element 38 is changed to the resistance value of the resistance element 32 constituting the low-pass filter circuit shown in FIG. It can be used as a part or all of R. Therefore, the combined resistance of the resistance value Rv of the resistance element 38 and the resistance value Rr of the resistance element 32 shown in FIG. 3 needs to be the resistance value R of the resistance element 32 shown in FIG. For example, by setting the resistance value Rv of the resistance element 38 to the resistance value R, the resistance element 32 can be omitted.

  4A and 4B show a configuration example of the variable current source 37 in FIG. 4A shows a current output type digital analog in which the voltage control terminal 36 is used as a digital control signal input terminal, and the output current of the variable current source 37 is controlled by a digital control signal from the digital control signal input terminal 36. An example configured with a conversion circuit is shown. In FIG. 4B, the variable current source 37 is connected to the current control terminal 36, the source electrode is connected to the power supply terminal, and the drain electrode is connected to the current output terminal of the variable current source 37 which is one end of the resistance element 38. An example in which the P-channel transistor is configured is shown.

(Second Embodiment)
Hereinafter, a low-pass filter circuit according to a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 5 shows a configuration of a low-pass filtering circuit (loop filter) in the second embodiment of the present invention. In FIG. 5, those having the same configuration as in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 5, the difference from the first embodiment is that in the loop filter 30A, a voltage comparator 60 that compares the output voltage Vout of the loop filter 30A and the output voltage of the variable voltage source 35, and the voltage comparator 60. A voltage control circuit 61 that controls the output voltage of the variable voltage source 35 based on the comparison result is provided.

  Here, the voltage control circuit 61 controls the voltage control terminal 36 so as to increase the output voltage of the variable voltage source 35 when the comparison result of the output voltage Vout of the loop filter 30A is higher from the voltage comparator 60, If the comparison result is lower than the output voltage Vout of the loop filter 30A from the voltage comparator 60, the voltage control terminal 36 is controlled so as to lower the output voltage of the variable voltage source 35. The response of the output voltage of the variable voltage source 35 to the change of the output voltage Vout of the loop filter 30A is designed to be sufficiently slow with respect to the PLL response characteristics so as not to affect the PLL characteristics.

  With the configuration as described above, the output voltage of the variable voltage source 35 becomes substantially equal to the output voltage Vout of the loop filter 30A, and the voltage applied to the capacitive element 31 is kept at a constant value of almost zero. . That is, when a MOS capacitor is used as the capacitive element 31, the voltage applied to both ends of the capacitive element 31 is constant, so that the voltage dependence of the capacitance value is eliminated, and variations in PLL response characteristics are suppressed. Further, when a low voltage transistor (thin film gate transistor) is used for the MOS capacitor 31, the applied voltage can be made almost zero, so that the gate leakage current can be minimized and the deterioration of the jitter characteristics due to the influence of the gate leakage current is prevented. be able to.

  Further, in the present embodiment, like the method for controlling the voltage control terminal 36 described in the first embodiment, the output voltage Vout in the PLL locked state is obtained in advance by simulation or evaluation, and is controlled from the outside. There is no need.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG.

  In FIG. 6, those having the same configuration as that of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  6 differs from the first embodiment in that the variable current source 37 shown in FIG. 4B is a P-channel transistor, and the negative input terminal is connected to the output terminal Vout of the loop filter. An operational amplifier 62 having an output terminal connected to the voltage control terminal 36 is added to the voltage output point that is one end of the resistance element 38 of the variable voltage source 35.

  Here, the operational amplifier 62 controls the gate electrode of the P-channel transistor that constitutes the variable current source 37, so that the output voltage Vout of the loop filter 30A that is the negative voltage and the variable voltage source that is the positive voltage. It operates so that the voltage of 35 becomes equal. As in the second embodiment, the response characteristic of the output voltage of the variable voltage source 35 with respect to the change of the output voltage Vout of the loop filter 30A corresponds to the response characteristic of the PLL so as not to affect the characteristic of the PLL. Design to be slow enough.

  As a result, the voltage applied to the capacitive element 31 is maintained at a constant value of almost zero, and voltage dependence when a MOS capacitor is used as the capacitive element 31 is eliminated, and variations in PLL response characteristics are suppressed. In addition, when a low voltage transistor (thin film gate transistor) is used for the MOS capacitor 31, the applied voltage can be made almost zero, so that the gate leakage current can be minimized and the jitter characteristics are deteriorated due to the influence of the gate leakage current. Can be prevented.

  Further, in the present embodiment, like the method for controlling the voltage control terminal 36 described in the first embodiment, the output voltage Vout in the PLL locked state is obtained in advance by simulation or evaluation, and is controlled from the outside. There is no need.

  As described above, the low-pass filtering circuit of the present invention has an effect of suppressing variation in the response characteristics of the PLL due to voltage dependence of the capacitance value that occurs when a MOS capacitor is applied to the capacitive element. Since it has an effect of reducing deterioration of jitter characteristics due to gate leakage current generated when a high low voltage transistor (thin film gate transistor) is used, it is useful as a low-pass filter circuit of a PLL circuit mounted on a semiconductor integrated circuit.

1 is a configuration diagram of a phase locked loop (PLL) including a low-pass filter circuit (loop filter) according to a first embodiment of the present invention. It is a figure which shows the conversion process from the general passive filter to the loop filter which concerns on the 1st Embodiment of this invention. It is a figure which shows the specific circuit of the variable voltage source with which the loop filter which concerns on the 1st Embodiment of this invention is equipped. (A) is a figure showing an example of a concrete circuit of the variable current source, and (b) is a figure showing another example of a concrete circuit of the variable current source. It is a block diagram of the loop filter which concerns on the 2nd Embodiment of this invention. It is a block diagram of the loop filter which concerns on the 3rd Embodiment of this invention. It is a block diagram of the conventional general charge pump type PLL. (A) is a circuit diagram of a conventional general loop filter, and (b) is a circuit diagram of another conventional general loop filter. It is a block diagram of the conventional low-pass filter circuit disclosed by patent document 1. FIG.

Explanation of symbols

10 PLL (phase comparator)
20, 20A Charge pump circuit 30, 30A Loop filter (low-pass filter circuit)
31 capacitive element (first capacitive element, first element block)
32 resistance element (component of second element block)
33 capacitive element (second capacitive element, third element block)
35 variable voltage source 36 voltage control terminal 37 variable current source 38 resistance element (component of variable voltage source, internal resistance of variable voltage source)
60 voltage comparator 61 voltage control circuit 62 operational amplifier circuit IN1 first input terminal IN2 second input terminal

Claims (7)

A first element block having a first capacitive element;
A second element block having a resistance element and a variable voltage source connected in series to the resistance element, one end connected to the first element block and the other end connected to a reference potential;
A third element block having a second capacitive element connected in parallel to the second element block;
A first input terminal connected to a terminal to which the second element block is not connected in the first element block and receiving a first current;
A second input terminal connected to a connection location of the first to third element blocks and receiving a second current corresponding to a predetermined multiple of the first current in the same direction;
An output terminal for outputting a voltage generated at a first input terminal of the first element block;
And a voltage control terminal for controlling the voltage of the variable voltage source. In the low-pass filtering circuit according to claim 1,
The variable voltage source is:
A variable current source controlled by the voltage control terminal;
A resistance element connected in series to the variable current source,
A low-pass filtering circuit characterized in that a voltage generated in the resistance element due to a current from the variable current source is output. In the low-pass filtering circuit according to claim 2,
The variable current source is:
A low-pass filtering circuit comprising a current output type digital-analog conversion circuit having the voltage control terminal as a digital control signal input terminal. In the low-pass filtering circuit according to claim 2,
The variable current source is:
A low-pass filtering circuit comprising a P-channel transistor in which a gate electrode is connected to the voltage control terminal, a source electrode is connected to a power supply terminal, and a drain electrode is connected to the resistance element. In the low-pass filter circuit according to any one of claims 1 to 3,
A voltage comparator for comparing the output voltage of the output terminal and the output voltage of the variable voltage source;
And a voltage control circuit that controls a voltage of the variable voltage source based on a comparison result of the voltage comparator. In the low-pass filtering circuit according to claim 4,
An operational amplifier having a negative input terminal connected to the output terminal of the low-pass filtering circuit, a positive input terminal connected to the voltage output point of the variable voltage source, and an output terminal connected to the voltage control terminal; Low-pass filter circuit characterized by In the low-pass filter circuit according to any one of claims 1 to 6,
A part of or all of the resistance elements that constitute the second element block also serve as the resistance elements that constitute the variable voltage source.

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