JP2009194302A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive semiconductor integrated circuit having a small area. <P>SOLUTION: A semiconductor integrated circuit comprises a plurality of wiring layers laminated on a semiconductor substrate 1, a 2-GHz inductor 4 of a 2-GHz frequency band formed on one of the wiring layers, and a 5-GHz inductor 5 of a 5-GHz frequency band which is higher than the 2-GHz frequency band formed on the identical wiring layer on which the 2-GHz inductor 4 is formed. The 5-GHz inductor 5 is formed in the opening of the 2-GHz inductor 4. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor integrated circuit including a plurality of wiring layers stacked on a semiconductor substrate.

  In recent years, with the progress of miniaturization of silicon semiconductor processes, the frequency of transistors has been increased. For this reason, there are increasing examples in which the CMOS process or the like that has been used for manufacturing a digital IC has been used as a process for manufacturing a high frequency IC for communication. By using a silicon semiconductor process such as a CMOS process, a semiconductor integrated circuit including a plurality of wiring layers and in which passive elements such as an inductor, a capacitor, and a resistor are integrally formed can be manufactured.

  In addition, in order to realize a portable information terminal corresponding to a plurality of communication means having different frequency bands, such as a mobile phone and a wireless LAN, an amplifier, a mixer, an oscillator and the like corresponding to each frequency band are included in a high frequency IC for communication. Are required to be formed on a single integrated circuit. In addition, a plurality of inductors corresponding to each of these active elements are also required to be formed on one integrated circuit.

In a conventional high frequency IC, a spiral inductor for 2 GHz band, a spiral inductor for 5 GHz band, an active circuit for 2 GHz band, and an active circuit for 5 GHz band are formed on one integrated circuit. (For example, refer nonpatent literature 1).
Here, the spiral inductor for the 5 GHz band is arranged next to the spiral inductor for the 2 GHz band on the same plane as the spiral inductor for the 2 GHz band.

Kisho Rama Rao et al. "A CMOS RF Front-End for a Multi-standard WLAN Receiver", IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 15, NO. 5, MAY 2005, p. 321-323

However, the prior art has the following problems.
That is, the spiral inductor for the 5 GHz band is arranged next to the spiral inductor for the 2 GHz band on the same plane as the spiral inductor for the 2 GHz band, so that the area of the semiconductor integrated circuit is increased and the cost is increased. There was a problem of becoming.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a semiconductor integrated circuit having a small area and a low cost.

  The semiconductor integrated circuit according to the present invention includes a plurality of wiring layers stacked on a semiconductor substrate and a first spiral formed in one wiring layer of the plurality of wiring layers corresponding to the first frequency band. An inductor and a second spiral inductor formed in the same wiring layer as the wiring layer in which the first spiral inductor is formed, corresponding to a second frequency band higher than the first frequency band; The spiral inductor is formed inside the opening of the first spiral inductor.

  The semiconductor integrated circuit according to the present invention includes a plurality of wiring layers stacked on a semiconductor substrate, a first spiral inductor formed in a first wiring layer that is one of the plurality of wiring layers, and a plurality of wiring layers. A second spiral inductor formed in a third wiring layer different from the first wiring layer of the plurality of wiring layers, and a second wiring layer different from the first wiring layer and the third wiring layer of the plurality of wiring layers And a first shield that blocks a magnetic field generated by the first spiral inductor and the second spiral inductor, the first wiring layer and the third wiring layer are stacked via the second wiring layer, The first spiral inductor, the second spiral inductor, and the first shield overlap each other when viewed from the stacking direction of the wiring layers.

According to the semiconductor integrated circuit of the present invention, the first higher frequency band than the first frequency band is provided inside the opening of the first spiral inductor corresponding to the first frequency band and in the same wiring layer as the first spiral inductor. A second spiral inductor corresponding to the second frequency band is formed. Alternatively, the first wiring layer in which the first spiral inductor is formed and the third wiring layer in which the second spiral inductor is formed are connected to the first spiral inductor through the second wiring layer in which the first shield is formed. The second spiral inductor and the first shield are arranged to overlap each other.
Therefore, a semiconductor integrated circuit with a small area and low cost can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts will be described with the same reference numerals.
In the following embodiments, the first frequency band and the second frequency band will be described by taking 2 GHz and 5 GHz as examples. However, the present invention is not limited to this, and if there is a difference between the frequency bands, the frequency band May be another value.

Embodiment 1 FIG.
FIG. 1A is a plan view showing a semiconductor integrated circuit according to Embodiment 1 of the present invention. FIG. 1B is a cross-sectional view taken along line II of the semiconductor integrated circuit shown in FIG.
In FIG. 1A and FIG. 1B, a first wiring layer 31 is laminated on a semiconductor substrate 1 made of, for example, silicon or the like via an interlayer insulating film 2. A second wiring layer 32 is stacked on the first wiring layer 31 with an interlayer insulating film 2 interposed therebetween.

In the second wiring layer 32, a metal spiral inductor 4 (first spiral inductor, hereinafter referred to as “2G inductor 4”) corresponding to a frequency band (first frequency band) of 2 GHz is formed. .
The second wiring layer 32 is formed with a metal spiral inductor 5 (second spiral inductor, hereinafter referred to as “5G inductor 5”) corresponding to a frequency band of 5 GHz (second frequency band). ing.

  Each of the 2G inductor 4 and the 5G inductor 5 is a differential spiral inductor. The differential spiral inductor is an inductor having a symmetrical structure having two terminals at both ends of the inductor and one terminal taken out from the midpoint of the inductor.

  Further, the wiring patterns of the 2G inductor 4 and the 5G inductor 5 have crossing portions when viewed from the lamination direction of the wiring layers (see hatched portions in the figure). At this intersection, one pattern passes through a via hole (not shown) formed in the interlayer insulating film 2 and a detour pattern (not shown) formed in the first wiring layer 31. It bypasses and returns to the pattern of the second wiring layer 32 through another via hole.

  Further, an active circuit 6 (first active circuit, hereinafter referred to as “2G active circuit 6”) corresponding to a frequency band of 2 GHz is formed on the surface of the semiconductor substrate 1 and connected to the 2G inductor 4. Yes. Further, an active circuit 7 (second active circuit, hereinafter referred to as “5G active circuit 7”) corresponding to a frequency band of 5 GHz is formed on the surface of the semiconductor substrate 1 and connected to the 5G inductor 5. Yes.

Each of the 2G active circuit 6 and the 5G active circuit 7 includes an active element such as a transistor, and amplifies current or voltage.
1A and 1B, the connection between the 2G inductor 4 and the 2G active circuit 6 and the connection between the 5G inductor 5 and the 5G active circuit 7 are not shown. ing.

Here, the 5G inductor 5 is formed inside the opening of the 2G inductor 4 having a larger outer dimension. The reason why the outer dimension of the 2G inductor 4 is larger than the outer dimension of the 5G inductor 5 will be described below.
In general, for example, the inductor value of an inductor used for impedance matching of a transistor or the like is 4 nH for the 2G inductor 4 and 2 nH for the 5G inductor, and the required inductor value increases as the frequency decreases. For this reason, the outer dimensions of the inductor also increase as the frequency decreases.

  Note that the 2G inductor 4 and the 5G inductor 5 have different distances between inductors, inductor values, etc. in consideration of the frequency bands of other inductors so that they are not affected by the magnetic fields generated by the other inductors. Is set.

According to the semiconductor integrated circuit of the first embodiment of the present invention, the 5G inductor 5 is formed inside the opening of the 2G inductor 4 and on the same second wiring layer 32 as the 2G inductor 4. Yes.
Therefore, the area of the semiconductor integrated circuit can be reduced as compared with the case where the 5G inductor is arranged next to the 2G inductor on the same plane as the 2G inductor. Further, the cost of the semiconductor integrated circuit can be reduced by reducing the area.
Therefore, a semiconductor integrated circuit with a small area and low cost can be obtained.

In the semiconductor integrated circuit of the first embodiment, the 2G active circuit 6 and the 5G active circuit 7 are separate circuits, but the present invention is not limited to this.
A part of or all of the elements constituting the 2G active circuit 6 and the 5G active circuit 7 is changed to a wide band corresponding to the frequency bands of 2 GHz and 5 GHz, and as shown in FIG. A circuit 8 (shared active circuit) may be provided.
Thereby, the area of the active circuit can be reduced, and the area of the semiconductor integrated circuit can be further reduced.

In the first embodiment, two spiral inductors, the 2G inductor 4 and the 5G inductor 5, are described. However, the present invention is not limited to this.
For example, a third spiral inductor corresponding to a frequency band other than 2 GHz and 5 GHz is formed in the second wiring layer 32, and the outer periphery of the 2G inductor 4, between the 2G inductor 4 and the 5G inductor 5, or for 5G It may be arranged inside the inductor 5.
At this time, the active circuit connected to the third spiral inductor may be integrated with the 2G / 5G shared active circuit 8.
In these cases, the same effect as in the first embodiment can be obtained.

Embodiment 2. FIG.
FIG. 3A is a plan view showing a semiconductor integrated circuit according to Embodiment 2 of the present invention. FIG. 3B is a cross-sectional view taken along the line II-II of the semiconductor integrated circuit shown in FIG.
3A and 3B, a first wiring layer 31 is laminated on a semiconductor substrate 1 made of, for example, silicon or the like with an interlayer insulating film 2 interposed therebetween. A second wiring layer 32 is stacked on the first wiring layer 31 with an interlayer insulating film 2 interposed therebetween. A third wiring layer 33 is laminated on the second wiring layer 32 with the interlayer insulating film 2 interposed therebetween.

The first wiring layer 31 is formed with a metal spiral inductor 4 (first spiral inductor, hereinafter referred to as “2G inductor 4”) corresponding to a frequency band of 2 GHz (first frequency band). .
In the third wiring layer 33, a metal spiral inductor 5 (second spiral inductor, hereinafter referred to as “5G inductor 5”) corresponding to a frequency band of 5 GHz (second frequency band) is formed. .

The second wiring layer 32 is formed with a shield 9 (first shield) for blocking a part of the magnetic field generated by the 2G inductor 4 and the 5G inductor 5.
The shield 9 is made of a metal such as polysilicon, copper, or aluminum, for example, and has a predetermined wiring pattern. The shield 9 is connected to the ground.

Here, the 2G inductor 4, the 5G inductor 5, and the shield 9 are arranged so as to overlap each other when viewed from the lamination direction of the wiring layers.
Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

According to the semiconductor integrated circuit according to the second embodiment of the present invention, the shield 9 is formed between the first wiring layer 31 in which the 2G inductor 4 is formed and the third wiring layer 33 in which the 5G inductor 5 is formed. The second wiring layer 32 is stacked. The 2G inductor 4, the 5G inductor 5, and the shield 9 are arranged so as to overlap each other when viewed from the lamination direction of the wiring layers.
Therefore, the area of the semiconductor integrated circuit can be reduced as compared with the case where the 5G inductor is arranged next to the 2G inductor on the same plane as the 2G inductor. Further, the cost of the semiconductor integrated circuit can be reduced by reducing the area.
Therefore, a semiconductor integrated circuit with a small area and low cost can be obtained.

In the semiconductor integrated circuit of the second embodiment, the 2G active circuit 6 and the 5G active circuit 7 are separate circuits, but the present invention is not limited to this.
As in the case of the first embodiment described above, a 2G / 5G shared active circuit 8 may be provided as shown in FIG.
Thereby, the area of the active circuit can be reduced, and the area of the semiconductor integrated circuit can be further reduced.

In the second embodiment, the two spiral inductors, the 2G inductor 4 and the 5G inductor 5, are described. However, the present invention is not limited to this.
For example, a fourth wiring layer in which a shield is formed on the third wiring layer 33 and a fifth wiring layer in which a third spiral inductor corresponding to a frequency band other than 2 GHz and 5 GHz is formed are respectively provided as interlayer insulating films. You may laminate through.
At this time, the 2G inductor 4, the 5G inductor 5, the third spiral inductor, the shield 9, and the shield of the fourth wiring layer are arranged so as to overlap each other when viewed from the lamination direction of the wiring layers.
Also in this case, the same effects as those of the second embodiment can be obtained.

In the second embodiment, the 2G inductor 4 is formed in the first wiring layer 31, and the 5G inductor 5 is formed in the third wiring layer 33. Here, even when the 2G inductor 4 and the 5G inductor 5 are formed in opposite wiring layers, a semiconductor integrated circuit having a small area and low cost can be obtained.
However, generally, when the distance between the inductor and the semiconductor substrate 1 is shortened, the Q value of the inductor is lowered, and the corresponding inductor having a higher frequency band is more strongly affected by this. Therefore, it is considered appropriate to form the 2G inductor 4 in the first wiring layer 31.

  In the first and second embodiments, a new wiring layer is provided between the semiconductor substrate 1 and the first wiring layer 31, and a shield for blocking a part of the magnetic field is formed on the wiring layer. The Q value of the spiral inductor can be increased.

Embodiment 3 FIG.
FIG. 5A is a plan view showing a semiconductor integrated circuit according to the third embodiment of the present invention. FIG. 5B is a cross-sectional view taken along the line III-III of the semiconductor integrated circuit shown in FIG.
5A and 5B, a first wiring layer 31 is stacked on the semiconductor substrate 1 made of, for example, silicon or the like with an interlayer insulating film 2 interposed therebetween. A second wiring layer 32 is stacked on the first wiring layer 31 with an interlayer insulating film 2 interposed therebetween. A third wiring layer 33 is laminated on the second wiring layer 32 with the interlayer insulating film 2 interposed therebetween. A fourth wiring layer 34 is stacked on the third wiring layer 33 with the interlayer insulating film 2 interposed therebetween.

The first wiring layer 31 is formed with a shield 10 (second shield) for blocking a part of the magnetic field generated by the 2G inductor 4 and the 5G inductor 5.
The shield 10 is made of metal like the shield 9 and has a predetermined wiring pattern. The shield 10 is connected to the ground.

The second wiring layer 32, the third wiring layer 33, and the fourth wiring layer 34 have the same configuration as the first wiring layer 31, the second wiring layer 32, and the third wiring layer 33 of the second embodiment described above, respectively. (See FIG. 3).
Further, a 2G / 5G shared active circuit 8 corresponding to the frequency bands of 2 GHz and 5 GHz is formed on the surface of the semiconductor substrate 1 and connected to the 2G inductor 4 and the 5G inductor 5.

Here, the 2G inductor 4, the 5G inductor 5, the shield 9, the shield 10, and the 2G / 5G shared active circuit 8 are arranged so as to overlap each other when viewed from the lamination direction of the wiring layers.
Other configurations are the same as those in the second embodiment, and the description thereof is omitted.

According to the semiconductor integrated circuit according to the third embodiment of the present invention, the 2G / 5G shared active circuit 8 provided on the surface of the semiconductor substrate 1 includes the 2G inductor 4, the 5G inductor 5, the shield 9 and the shield 10. They are arranged so as to overlap each other.
Therefore, the area of the semiconductor integrated circuit can be reduced. Further, the cost of the semiconductor integrated circuit can be reduced by reducing the area.

In the third embodiment, the 2G / 5G shared active circuit 8 is formed on the surface of the semiconductor substrate 1. However, the present invention is not limited to this, and the 2G active circuit 6 and the 5G active circuit 7 are formed. Good.
Also in this case, the same effect as in the third embodiment can be obtained.

  In the third embodiment, the case where the 2G inductor 4 and the 5G inductor 5 are formed in different wiring layers has been described. However, the present invention is not limited to this. Even when the 2G inductor 4 and the 5G inductor 5 are formed in the same wiring layer, the same effect as in the third embodiment can be obtained.

  In the first to third embodiments, the differential spiral inductor is described as an example of the inductor. However, the same effect can be obtained even when a single-phase spiral inductor is used.

  In the first to third embodiments, the spiral inductor has been described by taking a quadrangular shape as an example, but the same effect can be obtained even when, for example, an octagonal or circular spiral inductor is used. Can play.

  In the first to third embodiments, the spiral inductor has been described as an example. However, the same effect can be obtained for a balun formed of a metal wiring layer on a semiconductor substrate.

(A) is a top view which shows the semiconductor integrated circuit which concerns on Embodiment 1 of this invention, (b) is arrow sectional drawing along the II line | wire of the semiconductor integrated circuit shown to (a). It is. It is another top view which shows the semiconductor integrated circuit which concerns on Embodiment 1 of this invention. (A) is a top view which shows the semiconductor integrated circuit which concerns on Embodiment 2 of this invention, (b) is arrow sectional drawing along the II-II line | wire of the semiconductor integrated circuit shown to (a). It is. It is another top view which shows the semiconductor integrated circuit based on Embodiment 2 of this invention. (A) is a top view which shows the semiconductor integrated circuit which concerns on Embodiment 3 of this invention, (b) is arrow sectional drawing along the III-III line | wire of the semiconductor integrated circuit shown to (a). It is.

Explanation of symbols

  1 Semiconductor substrate, 4G inductor (first spiral inductor), 5G inductor (second spiral inductor), 62G active circuit (first active circuit), 75G active circuit (second active circuit), 8 2G / 5G shared active circuit (shared active circuit), 9 shield (first shield), 10 shield (second shield), 31 first wiring layer, 32 second wiring layer, 33 third wiring layer, 34 fourth Wiring layer.

Claims (5)

A plurality of wiring layers stacked on a semiconductor substrate;
Corresponding to the first frequency band, a first spiral inductor formed in one wiring layer of the plurality of wiring layers;
Corresponding to a second frequency band higher than the first frequency band, a second spiral inductor formed in the same wiring layer as the wiring layer in which the first spiral inductor is formed,
2. The semiconductor integrated circuit according to claim 1, wherein the second spiral inductor is formed inside an opening of the first spiral inductor. Formed in a wiring layer provided closer to the semiconductor substrate than the wiring layer in which the first spiral inductor and the second spiral inductor are formed, and blocks a magnetic field generated by the first spiral inductor and the second spiral inductor. A second shield that,
A first active circuit formed on a surface of the semiconductor substrate and connected to the first spiral inductor;
A second active circuit formed on the surface of the semiconductor substrate and connected to the second spiral inductor,
The first spiral inductor, the second spiral inductor, the second shield, the first active circuit, and the second active circuit overlap each other when viewed from the stacking direction of the wiring layers. The semiconductor integrated circuit according to claim 1. A plurality of wiring layers stacked on a semiconductor substrate;
A first spiral inductor formed in a first wiring layer that is one of the plurality of wiring layers;
A second spiral inductor formed in a third wiring layer different from the first wiring layer of the plurality of wiring layers;
The first wiring layer is formed in a second wiring layer different from the first wiring layer and the third wiring layer among the plurality of wiring layers, and blocks a magnetic field generated by the first spiral inductor and the second spiral inductor. A shield, and
The first wiring layer and the third wiring layer are stacked via the second wiring layer, and the first spiral inductor, the second spiral inductor, and the first shield are stacked wiring layers. A semiconductor integrated circuit characterized by overlapping each other when viewed from the direction. A second shield formed on a wiring layer provided closer to the semiconductor substrate than the first wiring layer and blocking a magnetic field generated by the first spiral inductor and the second spiral inductor;
A first active circuit formed on a surface of the semiconductor substrate and connected to the first spiral inductor;
A second active circuit formed on the surface of the semiconductor substrate and connected to the second spiral inductor,
The first spiral inductor, the second spiral inductor, the second shield, the first active circuit, and the second active circuit overlap each other when viewed from the stacking direction of the wiring layers. The semiconductor integrated circuit according to claim 3.   3. A shared active circuit using circuit elements corresponding to both a frequency band corresponding to the first active circuit and a frequency band corresponding to the second active circuit is provided. 5. The semiconductor integrated circuit according to 4.

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