JP2009193616A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device having a small refresh busy rate or low current consumption during holding of data, and advantageous in miniaturization. <P>SOLUTION: The semiconductor memory device includes a memory cell including a source layer, a drain layer, an electrically floating body area which is provided between the source layer and the drain layer and accumulates charges so as to store logical data or discharges charges, and a gate electrode provided on the body area with a gate insulating film being interposed therebetween, a bit line connected to the drain layer of the memory cell, a word line which is connected to a gate electrode of the memory cell or function as a gate electrode, and a word line driver connected to the word line. The word line driver writes first logical data to the memory cell via the gate insulating film by electron valence band tunneling. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, for example, an FBC (Floating Body Cell) memory that stores information by accumulating majority carriers in a floating body of a field effect transistor.

  2. Description of the Related Art In recent years, there is an FBC memory device as a semiconductor memory device that is expected to replace a 1T (Transistor) -1C (Capacitor) type DRAM. In the FBC memory device, an FET (Field Effect Transistor) having a floating body (hereinafter also referred to as a body) is formed on an SOI (Silicon On Insulator) substrate, and depending on the number of majority carriers accumulated in the body. Data “1” or data “0” is stored. For example, in an FBC composed of an N-type FET, a state where the number of holes accumulated in the body is large is data “1”, and a state where the number is small is data “0”. A memory cell storing data “0” is called a “0” cell, and a memory cell storing data “1” is called a “1” cell.

  The FBC is superior to the conventional DRAM in size reduction. However, the capacitance of the body that stores the charge is smaller than the capacitance of the conventional DRAM capacitor. For this reason, although the leakage current from the body of the FBC is smaller than the leakage current from the capacitor of the DRAM, the FBC is shorter than that of the DRAM with respect to the data retention time. Therefore, the refresh operation must be frequently executed in the FBC memory. As a result, in the FBC memory, the ratio of time during which normal reading / writing is prohibited (refresh busy rate) increases, and further, the current required to hold data increases compared to the conventional DRAM. Problems arise. In particular, in a portable device, a large current consumption during data retention is a serious problem.

In the conventional FBC memory, the amplitude ΔVBL of the bit line is determined by the difference between the bit line potential VBLH at the time of writing “1” and the bit line potential VBLL at the time of writing “0”. That is, ΔVBL = VBLH−VBLL. Therefore, in order to make the signal difference between the “1” cell and the “0” cell sufficiently large, the bit line amplitude ΔVBL must be increased. In the FBC memory, it is necessary to pass a current through the bit line during writing. For this reason, when the bit line amplitude is large, for example, when data is simultaneously written in a large number of memory cells, there is a problem that a large amount of current flows through the bit line and power consumption increases.
WCLee and C. Hu, “Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction and valence-band electron tunneling”, IEEE Trans. Electron Device, vol. 48, pp.1366-1373, July 2001.

  Provided is a semiconductor memory device that has low current consumption when data is held and is excellent in miniaturization.

A semiconductor memory device according to an embodiment of the present invention is provided between a source layer, a drain layer, and between the source layer and the drain layer, and accumulates charges to store logic data, or charges A memory cell including an electrically floating body region that emits a gate electrode and a gate electrode provided on the body region via a gate insulating film,
A bit line connected to a drain layer of the memory cell;
A word line connected to or functioning as a gate electrode of the memory cell; and
A word line driver connected to the word line;
The word line driver writes first logic data into the memory cell by electron valence band tunneling through the gate insulating film.

A semiconductor memory device according to an embodiment of the present invention is provided between a source layer, a drain layer, and between the source layer and the drain layer, and accumulates charges to store logic data, or charges A memory cell including an electrically floating body region that emits a gate electrode and a gate electrode provided on the body region via a gate insulating film,
A bit line connected to a drain layer of the memory cell;
A word line connected to or functioning as a gate electrode of the memory cell; and
A word line driver connected to the word line;
When writing the first logic data to the memory cell, the word line driver is higher than the threshold voltage of the memory cell under a state where the potential of the bit line is substantially equal to the potential of the source layer, In addition, a first potential higher than the potential of the word line at the time of data reading is applied to the word line.

  The semiconductor memory device according to the present invention has low current consumption during data retention and is excellent in miniaturization.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
FIG. 1 is a diagram showing a configuration of an FBC memory according to the first embodiment of the present invention. The FBC memory includes a memory cell MC, dummy cells DC0 and DC1, word lines WLLi and WLRi (i is an integer) (hereinafter also referred to as WL), dummy word lines DWLL and DWLR (hereinafter also referred to as DWL), bit Lines BLLi and BLRi (hereinafter also referred to as BL), a sense amplifier S / A, equalizing lines EQLL and EQLR (hereinafter also referred to as EQL), equalizing transistors TEQL and TEQR (hereinafter also referred to as TEQ), and a row decoder RD, WL driver WLD, column decoder CD, and CSL driver CSLD are provided.

  The memory cells MC are two-dimensionally arranged in a matrix and constitute memory cell arrays MCAL and MCAR (hereinafter also referred to as MCA). The word line WL extends in the row direction and is connected to the gate of the memory cell MC. Alternatively, the word line WL is integrated with the gate electrode of the memory cell MC and also has a function as a gate electrode. 256 word lines WL are provided on the left and right sides of the sense amplifier S / A, respectively, and are indicated by WLL0 to WLL255 and WLR0 to WLR255 in FIG. The bit line BL extends in the column direction and is connected to the drain of the memory cell MC. 1024 bit lines BL are provided on the left and right of the sense amplifier S / A, respectively, and are indicated by BLL0 to BLL1023 and BLR0 to BLR1023 in FIG. The word line WL and the bit line BL are orthogonal to each other, and a memory cell MC is provided at each intersection. This is called a cross-point type cell. Note that the row direction and the column direction are referred to for convenience, and the names of the row direction and the column direction may be interchanged.

  Prior to the data read / write operation, dummy cells DC0 and DC1 store data "0" and data "1" having opposite polarities, respectively. Data writing to the dummy cells DC0 and DC1 is usually performed immediately after the power is turned on or immediately after the write operation is performed on the memory cell array. The polarity indicates a logical value “0” or “1” of data. The dummy cells DC0 and DC1 are used to generate the reference current Iref by an averaging circuit not shown in FIG. 1 when detecting data of the memory cell MC. The reference current Iref is a current approximately halfway between the current flowing through the “0” cell and the current flowing through the “1” cell. A current load circuit in the sense amplifier S / A causes a current to flow to the memory cell MC via the bit line BL. As a result, a current corresponding to the data in the memory cell MC flows through the sense node in the sense amplifier S / A. Based on whether the current flowing through the sense node is higher or lower than the reference current Iref, the sense amplifier S / A identifies the logical value “1” or “0” of the data.

  Note that the dummy cells DC0 and DC1 are alternately arranged in the extending direction (row direction) of the word lines WL. In order to generate the reference current Iref, the same number of dummy cells DC0 and dummy cells DC1 are provided.

  The dummy word line DWL extends in the row direction and is connected to the gates of the dummy cells DC0 and DC1. One dummy word line DWL is provided on each side of the sense amplifier S / A.

  The equalizing line EQL is connected to the gate of the equalizing transistor TEQ. The equalizing transistor TEQ is connected between the bit line BL and the ground (VSL). In equalizing, the potential of each bit line BL is made equal to the ground potential by connecting the bit line BL to the ground.

  The row decoder RD decodes a row address in order to select a specific word line among the plurality of word lines WL. The WL driver WLD activates the selected word line by applying a voltage to the selected word line. The column decoder CD decodes a column address in order to select a specific column among a plurality of columns. The CSL driver CSLD applies a potential to the column selection line CSL of the selected column. As a result, data is read from the sense amplifier S / A to the outside of the memory device via the DQ buffer, or data from the outside of the memory device is written to the sense amplifier S / A via the DQ buffer.

  The sense amplifier S / A is connected to a pair of bit lines BLL and BLR provided one by one on the left and right. Each sense amplifier S / A is provided corresponding to each bit line pair BLL and BLR. Thus, in this embodiment, an open bit line configuration is adopted. At the time of data reading, one of the bit line BLL and the bit line BLR transmits data, and the other transmits reference data. The sense amplifier S / A is configured to read the logical data stored in the memory cell MC or write the logical data to the memory cell MC by comparing the read data with the reference data. The memory configuration is not limited to the open bit line configuration, but may be other configurations (for example, a folded bit line configuration). Further, the circuit configuration of the sense amplifier S / A is not particularly limited.

  Activation means turning on or driving the element or circuit, and deactivation means turning off or stopping the element or circuit. Therefore, it should be noted that a HIGH (high potential level) signal may be an activation signal, and a LOW (low potential level) signal may be an activation signal. For example, the NMOS transistor is activated by setting the gate to HIGH. On the other hand, the PMOS transistor is activated by setting the gate to LOW.

  FIG. 2 is a cross-sectional view showing the structure of the memory cell MC. The dummy cell DC has a configuration similar to that of the memory cell MC. Memory cell MC is provided on an SOI substrate including support substrate 10, BOX layer 20, and SOI layer 30. A source 60 and a drain 40 are provided in the SOI layer 30. A floating body (hereinafter referred to as body) 50 is formed in the SOI layer 30 between the source 60 and the drain 40. The body 50 is a semiconductor having a conductivity type opposite to that of the source 60 and the drain 40.

  In the present embodiment, the memory cell MC is an N-type FET. The gate electrode 80 is provided on the body 50, and the gate electrode 80 is provided on the body 50 via the gate insulating film 70. The gate electrode 80 is connected to the word line WL or functions as the word line WL.

  The thickness of the gate insulating film 70 is thin enough to allow electrons to tunnel, for example, several nm. The body 50 is partially or entirely surrounded by the source 60, the drain 40, the BOX layer 20, the gate insulating film 70, and STI (Shallow Trench Isolation) (not shown). Thereby, the body 50 is in an electrically floating state. The body 50 can accumulate majority carriers or release majority carriers to store logical data. The FBC memory can store logical data (binary data) according to the number of majority carriers in the body 50. When the memory cell MC is an N-type FET, the majority carrier is a hole.

  An example of a method for reading data from the memory cell MC will be described below. In the data read operation, the memory cell MC is operated in a linear region. For example, the word line WL is set to 1.5 V, and a current is passed through the bit line BL. The memory cell MC that stores data “0” and the memory cell MC that stores data “1” differ in the threshold voltage of the memory cell MC due to the difference in the number of holes accumulated in the body 50. The sense amplifier S / A discriminates between data “1” and data “0” by detecting a difference in threshold voltage via the bit line BL.

  3 to 5 are band diagrams showing a method of writing data “1” to the memory cell MC using electron valence band tunneling (hereinafter also referred to as EVB tunneling). Here, the gate electrode 80 of the memory cell MC is made of n-type silicon having a sufficiently high impurity concentration, and is hardly depleted. Ev indicates the energy level of the valence band, and Ec indicates the energy level of the conduction band. Ef indicates the Fermi level, and Ei indicates the intrinsic Fermi level.

  FIG. 3 shows a band diagram of the memory cell MC in the data holding state. In the data holding state, the gate potential Vgs is set to a deep negative potential VWLL with reference to the source potential VSL in order to hold a hole in the body 50 of the “1” cell. In the data holding state, the surface of the body 50 made of P-type silicon is in an accumulation state. Therefore, holes in the body 50 are accumulated at the interface between the body 50 surface and the gate insulating film 70.

  FIG. 4 shows a band diagram of the memory cell MC in a state where the gate potential Vgs is substantially equal to the threshold voltage Vth of the memory cell (which may be either “1” cell or “0” cell). At this time, an inversion layer (channel) is formed on the surface of the body 50. The energy band on the body 50 side is bent by 2φB (2φ = 2 (Ef−Ei)). In this state, electrons in the inversion layer leak through the gate insulating film 70. This leakage current is an electron conduction band tunneling (hereinafter also referred to as ECB tunneling) current, and does not cause holes on the body 50 side.

  FIG. 5 shows a band diagram of the memory cell MC in a state where the gate potential Vgs is higher than the threshold voltage Vth of the memory cell. At this time, the edge of the energy band Ev of the valence band on the body 50 side becomes equal to or higher than the energy band Ec of the conduction band on the gate electrode 80 side. In this case, in addition to the gate leakage current due to ECB tunneling, electrons existing in the valence band of the body 50 are tunneled through the gate insulating film 70. This tunneling phenomenon due to electrons existing in the valence band is EVB tunneling. When electrons are generated by EVB tunneling, holes that form a pair remain in the body 50. This hole is accumulated in the body 50. As described above, the word line driver WLD can write the data “1” as the first logic data to the memory cell MC by setting the potential of the gate voltage 80 higher than Vth.

  FIGS. 6A and 6B are timing diagrams showing a write operation using EVB tunneling. FIG. 6A shows a word line potential, a bit line potential, and a source line potential. FIG. 6B shows the potentials of the sense nodes SNL and SNR in the sense amplifier S / A.

  “Write operation” is an operation in which the sense amplifier S / A writes to the memory cell MC. The “write operation” is an operation of writing data received from the outside of the memory device to the memory cell MC. When reading data of the memory cell MC to the outside of the memory device, data read by the sense amplifier S / A is written to the memory cell MC. The restore operation and the operation in which the sense amplifier S / A restores data to the memory cell MC in the refresh operation are included.

  Here, the refresh operation is an operation for recovering the deterioration of the logical data of the memory cell MC. As the refresh operation, data is temporarily read from the memory cell MC, this data is latched in the sense amplifier S / A, and the same logical data as this data is written back to the same memory cell. There is an autonomous refresh operation in which the memory cell is autonomously refreshed using the body potential difference between the “0” cell and the “1” cell while applying the same voltage to the “1” cell. As will be described later, the present invention can be applied to both a normal refresh operation and an autonomous refresh operation.

  6A and 6B, data having the same logic as the data read from the memory cell MC to the sense amplifier S / A via the bit line BLLj is written in the memory cell MC ( Has been restored). In the data holding state (˜t1), the source potential and the bit line potential are both set to the ground potential (0 V). The potentials of all the word lines are set to a deep negative potential VWLL.

[Read operation from memory cell to sense amplifier]
The read operation from the memory cell MC to the sense amplifier S / A is executed for the memory cells MC in all columns connected to the selected word line. For example, from t2 to t3, the word line driver WLD raises the potential of a certain selected word line WLLi to the potential VWLHR. The potential VWLHR is higher than the threshold voltage of the “0” cell and “1” cell. At this time, the bit lines BLL and BLR of all the columns are connected to the corresponding sense nodes SNL and SNR, respectively. Therefore, the current load circuit (not shown) of the sense amplifier S / A can flow current to the memory cell MC and the dummy cell DC via the bit lines BLLj and BLRj, respectively.

  In FIG. 6A and FIG. 6B, the sense amplifier S / A detects the “1” cell connected to the bit line BLLj. Then, the sense amplifier S / A detects the “1” cell connected to the bit line BLLj. Since the threshold voltage of the “1” cell is lower than that of the “0” cell, the potentials of the bit line BLLj and the sense node SNLj connected to the “1” cell are the potentials of the bit line BLRj and the sense node SNRj through which the reference current Iref flows. It becomes higher than the potential (smaller as an absolute value). When the potential difference between the sense nodes SNLj and SNRj sufficiently develops (t3), the transfer gate between the bit line and the sense node is closed, and further, a latch circuit (not shown) in the sense amplifier S / A. ). Thereby, as shown in FIG. 6B, the potential difference between the sense nodes SNLj and SNRj is amplified. The sense amplifier S / A latches this amplified potential difference between the sense nodes SNLj and SNRj. Similarly, the sense amplifiers S / A of all the columns read the data of all the memory cells MC connected to the selected word line WLLi.

  If the memory cell connected to the bit line BLLj is a “0” cell, the potential of the selected bit line BLLj is the reference current Iref as shown in parentheses in FIGS. It becomes lower than the potential of the bit line BLRj to flow. Similarly, in this case, the potential of the sense node SNLi is lower than the potential of the sense node SNRj through which the reference current Iref flows.

  In the present embodiment, the current load circuit is composed of an n-type FET and is connected to a low potential source lower than the source potential VSL. In this case, current flows from the memory cell MC toward the current load circuit. Therefore, the potentials of the bit line and the sense node are lowered to the negative potential side lower than the source potential VSL. Of course, the current load circuit may be composed of a p-type FET and connected to a high potential source higher than the source potential VSL. In this case, the current flows from the current load circuit toward the memory cell MC, and the potentials of the bit line and the sense node rise to the positive potential side higher than the source potential VSL. The potential of the sense node connected to the “1” cell is lower (smaller as an absolute value) than the potential of the sense node through which the reference current Iref flows.

["1" write operation from sense amplifier to memory cell]
In the “1” write operation from the sense amplifier S / A to the memory cell MC, the word line driver WLD writes data “1” to the memory cells MC of all the columns connected to the selected word line WLLi. For example, at t4, the potential of the selected word line WLLi is raised to the write potential VWLHW (first potential) of the data “1”. The first potential VWLHW is higher than any of the threshold voltage of the “1” cell, the threshold voltage of the “0” cell, and the word line potential VWLHR at the time of data reading. As a result, all the memory cells MC connected to the selected word line WLLi are in the state shown in FIG. As a result, data “1” is written to all the memory cells MC connected to the selected word line WLLi by EVB tunneling. Since EVB tunneling occurs due to a potential difference between the body and the gate, the bit line potential may be equal to the source potential.

["0" write operation from sense amplifier to memory cell]
When the data read from the selected bit line BLLj is “1”, the data “1” has already been restored to the memory cell MC connected to the selected bit line BLLj from t4 to t5. Therefore, as indicated by the solid lines from t5 to t6, both the selected bit lines BLLj and BLRj are maintained at VSL. At this time, the selected bit line BLLj may be connected to the sense node SNLi and the bit line BLRj may be in a precharge state.

  When the data read from the selected bit line BLLj is “0”, a “0” write operation is performed on the memory cells MC connected to the selected bit line BLLj.

  That is, the word line driver WLD and the sense amplifier S / A selectively write the data “0” only to the memory cell MC to which the data “0” is to be written among the memory cells MC connected to the selected word line WLLi. For example, at t5, the word line driver WLD returns the potential of the selected word line WLLi to the potential VWLHR. As a result, the memory cell MC returns from the state shown in FIG. 5 to the state shown in FIG. 4, and current due to EVB tunneling does not flow.

  As indicated by broken lines and parentheses in FIG. 6, when the selected bit line BLLj is connected to the memory cell MC to which data “0” is to be written, the sense amplifier S / A has a negative potential VBLL lower than the source potential VSL. Apply. The negative potential VBLL is a potential for writing data “0”. In the specific examples of FIGS. 6A and 6B, the sense amplifier S / A may connect the selected bit line BLLi to the sense node SNLj. As a result, the potential of the bit line BLLj drops to the negative potential VBLL. Note that the bit line BLRj may be in a precharge state and is maintained at VSL.

  By applying a negative potential VBLL to the selected bit line BLLj, a forward bias is applied between the body and the drain of the memory cell MC connected to the selected bit line BLLj. Holes in the body 50 of the memory cell MC connected to the selected bit line BLLj are discharged by the forward current between the body and the drain. As a result, data “0” is written to the memory cell MC connected to the selected bit line BLLj.

  Thereafter, at t6, the memory device returns to the data holding state.

  FIG. 7A and FIG. 7B are timing diagrams showing a write operation using EVB tunneling. In FIGS. 7A and 7B, at t4a, data having a logic opposite to the read data is written from the outside of the memory device to the sense amplifier S / A. Therefore, at t4a, the logic of the sense nodes SNLj and SNRj is inverted. The other operations in FIGS. 7A and 7B are basically the same as the operations shown in FIGS. 6A and 6B.

  In the operation of writing data “0” in the “1” cell, the logic of the sense nodes SNLj and SNRj is inverted with respect to the read data, and the low potential VBLL is applied to the selected bit line BLLj. At this time, the selected bit line BLLj is connected to the sense node SNLj, and the bit line BLRj only needs to be in a precharged state.

  In the operation of writing data “1” to the “0” cell, as indicated by broken lines and parentheses in FIGS. 7A and 7B, the logic of the sense nodes SNLj and SNRj is inverted with respect to the read data, The potential VSL is applied to the selected bit line BLLj. This is because the data “1” is written into the memory cell MC that was originally “0” cell. At this time, the selected bit line BLLj is connected to the sense node SNLj, and the bit line BLRj only needs to be in a precharged state.

  When data is read out of the memory device, the operation shown in FIGS. 6A and 6B is executed, and the data latched by the sense amplifier S / A is passed through a DQ buffer (not shown). Output to the outside.

  In the case of the normal refresh operation, the operations shown in FIGS. 6A and 6B are executed. At this time, the data latched by the sense amplifier S / A is not output to the outside.

  When data is written from outside the memory device, the operations shown in FIGS. 6A and 6B or the operations shown in FIGS. 7A and 7B are executed. When the external data is the same as the data stored in memory cell MC, the operations shown in FIGS. 6A and 6B are performed. When the external data is different from the data stored in memory cell MC, the operations shown in FIGS. 7A and 7B are performed.

  As described above, in this embodiment, after the word line driver WLD once writes the data “1” to the memory cells MC of all the columns connected to the selected word line, the word line driver WLD and the sense amplifier S / A The data “0” is written only to the memory cell MC of the selected column among the memory cells MC connected to the selected word line. EVB tunneling is used for writing data “1”, and forward bias between the body and the drain is used for writing data “0”.

  FIG. 8 is a graph showing the relationship between the forward current and the current due to EVB tunneling when data “1” is written. The vertical axis represents current. The horizontal axis represents the body potential Vb. IEVBT indicates a current flowing from the gate electrode 80 to the body 50 by EVB tunneling. IPNFWD indicates a current flowing from the body 50 to the source 60 or the drain 40. In the present embodiment, the writing of data “1” is executed under the condition that the source potential and the bit line potential are equal. Therefore, the forward current when data “1” is written can flow to either the source 60 or the drain 40.

  When the body potential Vb is low, the potential difference between the body and the gate becomes large, so that the EVB tunneling current is relatively large. Accordingly, holes are accumulated in the body 50 of the memory cell MC. On the other hand, when the body potential Vb is low, a reverse bias is applied to the pn junction between the body and the source and the pn junction between the body and the drain. For this reason, the forward current is only a negative leakage current due to the reverse bias.

  When the body potential Vb increases, the potential difference between the body and the gate decreases, so that the EVB tunneling current decreases. On the other hand, when the body potential Vb exceeds the source potential VSL, the forward current starts to flow in the positive direction. When the body potential Vb is equal to Vb1w, the EVB tunneling current and the forward current are substantially equal and are balanced at I1w. At this time, the number of holes accumulated in the body 50 by the EVB tunneling current is substantially equal to the number of holes flowing out of the body 50 by the forward current. Thus, the fact that the EVB tunneling current and the forward current are in an equilibrium state means that the writing of the data “1” is completed.

  The EVB tunneling current and forward current at the time of writing data “1” are very small compared to the impact ionization current. Therefore, the data “1” write operation according to the present embodiment consumes less power than the conventional one.

  In the “1” write operation using the conventional impact ionization, it is necessary to set the bit line potential to the high level potential VBLH. The gate voltage Vg of the unselected memory cell connected to the selected bit line is set to a deep negative potential VWLL in order to hold data. Therefore, when the potential of the selected bit line is set to a high level potential, the voltage difference Vgd (Vg (gate voltage) −Vd (drain voltage)) between the gate and the drain of the non-selected memory cell connected to the selected bit line. Becomes very large. As the voltage difference Vgd increases, GIDL occurs in an unselected “0” cell connected to the selected bit line. As a result, holes are accumulated in the body 50 of the “0” cell, and the data “0” deteriorates. This phenomenon is called bit line “1” disturb because it degrades the data during the write operation of data “1”. The bit line “1” disturb is considered to be caused by GIDL. GIDL is a deep depletion state in the overlap region between the drain 60 and the gate 80 when the gate-drain voltage difference Vgd is set to a large negative potential, and band-to-band tunneling (band to band tunneling). ) Is a phenomenon in which holes flow into the body 50.

  On the other hand, the write operation of data “0” normally reduces the bit line BL to a negative voltage. As a result, the pn junction between the body 50 and the drain 40 is largely biased in the forward direction, and the holes accumulated in the body 50 are discharged to the drain 40. As a result, data “0” is stored in the memory cell MC. At this time, the gate of the non-selected “1” cell connected to the selected bit line is maintained at the negative potential VWLL, but its drain 40 is lowered to the negative potential. Therefore, although a strong forward bias is not applied to the pn junction between the body and drain of this non-selected “1” cell, there is a possibility that a weak forward bias is applied. If this state continues for a long period of time or this state occurs many times, holes are gradually emitted from the body 50 of the “1” cell, and the data “1” is deteriorated. This phenomenon is called bit line “0” disturb because it degrades the data during the write operation of data “0”.

  The bit line “1” disturb and the bit line “0” disturb are in a trade-off relationship with respect to the holding level potential VWLL of the word line WL. That is, if the absolute value of the negative potential VWLL is reduced, the GIDL in the non-selected “0” cell is relaxed, so that the bit line “1” disturb is suppressed (the “0” cell is unlikely to deteriorate). However, if the absolute value of the negative potential VWLL is decreased, the forward bias between the body and the drain of the non-selected “1” cell is increased, so that the bit line “0” disturb is generated (the “1” cell is easily deteriorated). ).

  On the contrary, when the absolute value of the negative potential VWLL is increased, the GIDL in the non-selected “0” cell increases, so that the bit line “1” disturb is generated (the “0” cell is easily deteriorated). However, when the absolute value of the negative potential VWLL is increased, the forward bias between the body and the drain of the non-selected “1” cell is reduced, so that the bit line “0” disturb is suppressed (the “1” cell is deteriorated). It becomes difficult.)

  On the other hand, in this embodiment, when writing data “1”, the bit line potential may be equal to the source potential. Therefore, the bit line “1” disturb does not occur. Therefore, the trade-off problem regarding the word line potential VWLL in the data holding state is solved. That is, in the present embodiment, the word line potential VWLL can be adjusted in order to suppress the bit line “0” disturbance without considering the bit line “1” disturbance.

  Further, when data “1” is written, since the word line potential is a potential VWLHW higher than the threshold voltage of the memory cell MC, a channel is formed between the source and drain of the memory cell MC. However, since the potential difference between the source and the drain is 0 V, no channel current flows. Therefore, as described above, the power consumption required for the data “1” write operation of the present embodiment is lower than the power consumption by the conventional write method using the impact ionization current or the power consumption required for the peripheral circuit. .

(Second Embodiment)
The FBC memory according to the second embodiment executes the data “1” write operation and the data “0” write operation in the same cycle. The configuration of the second embodiment may be the same as the configuration of the first embodiment.

  FIG. 9A and FIG. 9B are timing charts showing a write operation using EVB tunneling according to the second embodiment. In FIG. 9A and FIG. 9B, data having the same logic as the data read from the memory cell MC to the sense amplifier S / A via the bit line BLLj is written in the memory cell MC ( Has been restored). The read operation from the memory cell MC to the sense amplifier S / A according to the second embodiment is the same as that of the first embodiment. Therefore, the description is omitted.

[Data write operation from sense amplifier to memory cell]
At t14, the word line driver WLD raises the potential of the selected word line WLLi to the write potential VWLHW (first potential) of the data “1”. When the memory cell MC connected to the selected word line WLLi and the selected bit line BLLj is a “1” cell, the voltage VSL is applied to the selected bit line BLLj (see the solid line in FIG. 9A). When the memory cell MC connected to the selected word line WLLi and the selected bit line BLLj is a “0” cell, a low level voltage VBLL (second potential) is applied to the selected bit line BLLj (FIG. 9A). (See dashed line).

  That is, among the memory cells MC connected to the selected word line WLLi, VSL is applied to the bit line connected to the memory cell MC to which data “1” is to be written and connected to the memory cell MC to which data “0” is to be written. VBLL is applied to the bit line. For example, in FIGS. 9A and 9B, the bit line BLLj may be connected to the sense node SNLj and the bit line BLRj may be in a precharge state. Thus, in the second embodiment, the bit line bit line BLLj connected to the memory cell MC to which data “0” is to be written is on the side opposite to the first potential VWLHW with respect to the source potential VSL. A second potential VBLL is applied.

  As a result, the EVB tunneling current IEVBT and the forward current IPNFWD1 shown in FIG. 11 flow through the memory cell MC that is connected to the bit line BLRj and to which data “1” is to be written. IPNFWD1 is the same curve as IPNFWD shown in FIG. As a result, the body potential of the memory cell MC connected to the bit line BLRj becomes Vb1w, which is an equilibrium point between the EVB tunneling current IEVBT and the forward current IPNFWD1. That is, data “1” is written in the memory cell MC connected to the bit line BLRj.

  On the other hand, the EVB tunneling current IEVBT and the forward current IPNFWD0 shown in FIG. 11 flow in the memory cell MC connected to the bit line BLLj and to which data “0” is to be written. The reason why forward current IPNFWD0 is larger than forward current IPNFWD1 is because potential VBLL of bit line BLLj is lower than potential VSL of bit line BLRj. As a result, the body potential of the memory cell MC connected to the bit line BLLj becomes Vb0w, which is an equilibrium point between the EVB tunneling current IEVBT and the forward current IPNFWD0. Vb0w is a lower potential than Vb1w. Data “0” is written in the memory cell MC connected to the bit line BLLj.

  At t15, the memory device returns to the data holding state.

  FIG. 10A and FIG. 10B are timing diagrams showing a write operation using EVB tunneling according to the second embodiment. 10A and 10B, at t14a, data having a logic opposite to that of the read data is written to the sense amplifier S / A from the outside of the memory device. Therefore, at t14a, the logic of the sense nodes SNLj and SNRj is inverted. The other operations in FIGS. 10A and 10B are basically the same as the operations illustrated in FIGS. 9A and 9B.

  When data “0” is written in the “1” cell, the logic of the sense nodes SNLj and SNRj is inverted with respect to the read data, and the low potential VBLL is applied to the selected bit line BLLj. At this time, the selected bit line BLLj is connected to the sense node SNLj, and the bit line BLRj only needs to be in a precharged state.

  When data “1” is written to the “0” cell, the logic of the sense nodes SNLj and SNRj is inverted with respect to the read data as shown by the broken lines and parentheses in FIGS. 10A and 10B. A potential VSL is applied to the bit line BLLj. At this time, the selected bit line BLLj is connected to the sense node SNLj, and the bit line BLRj only needs to be in a precharged state.

  When data is read out of the memory device, the operations shown in FIGS. 9A and 9B are executed, and the data latched by the sense amplifier S / A is passed through a DQ buffer (not shown). Output to the outside. In the case of the normal refresh operation, the operations shown in FIGS. 9A and 9B are executed. At this time, the data latched by the sense amplifier S / A is not output to the outside. When data is written from outside the memory device, the operations shown in FIGS. 9A and 9B or the operations shown in FIGS. 10A and 10B are executed. When the external data is the same as the data stored in memory cell MC, the operations shown in FIGS. 9A and 9B are performed. When the external data is different from the data stored in the memory cell MC, the operations shown in FIGS. 10A and 10B are performed.

  FIG. 11 is a graph showing the relationship between the forward current and the current due to EVB tunneling during data writing. The vertical axis represents current. The horizontal axis represents the body potential Vb. IEVBT indicates a current flowing from the gate electrode 80 to the body 50 by EVB tunneling. IPNFWD0 indicates a current flowing from the body 50 of the memory cell MC to which data “0” is written to the source 60 or the drain 40. IPNFWD1 indicates a current flowing from the body 50 of the memory cell MC to which data “1” is written to the source 60 or the drain 40.

  In the second embodiment, data “1” is written under the condition that the source potential and the bit line potential are equal. Therefore, the forward current at the time of writing data can flow to either the source 60 or the drain 40.

  The equilibrium point of the body potential of the memory cell MC to which data “0” is to be written is Vb0w. The equilibrium point of the body potential of the memory cell MC to which data “1” is to be written is Vb1w. Since Vb0w <Vb1w, data “1” and data “0” can be simultaneously written in the memory cells MC connected to the selected word line WLLi.

  In the second embodiment, since data “1” and data “0” are written simultaneously, the write cycle (t14 to t15) is shortened compared to the write cycle (t4 to t6) of the first embodiment. The second embodiment can further obtain the effects of the first embodiment.

(Third embodiment)
The third embodiment shows an autonomous refresh operation using EVB tunneling. In the autonomous refresh operation, the memory cell is refreshed autonomously using the body potential difference between the “0” cell and the “1” cell while applying a voltage equal to the “0” cell and the “1” cell.

  FIG. 12A is a band diagram of a “0” cell during autonomous refresh. FIG. 12B is a band diagram of the “1” cell at the time of autonomous refresh. The word line connected to the “1” cell and the word line connected to the “0” cell are both VWLHOLD. VWLHOLD is higher than the threshold voltage Vth1 of the “1” cell and lower than the threshold voltage Vth0 of the “0” cell. As a result, as shown in FIG. 12B, the EVB tunneling current flows through the “1” cell, but as shown in FIG. 12A, the EVB tunneling current does not flow through the “0” cell.

  The potentials of the source 60 and the drain 40 may be equal. However, the potentials of the source 60 and the drain 40 are not necessarily equal.

  FIG. 13 is a graph showing the relationship between the EVB tunneling current IEVBT and the forward currents IPNBL and IPNSL when the potentials of the source 60 and the drain 40 are both equal to VSDHOLD. VSDHOLD is a negative potential lower than the source potential VSL at the time of data retention. IPNBL indicates a current flowing from the body 50 to the drain 40. In IPNBL, the current direction from the body 50 to the drain 40 is positive. IPNSL indicates the current that flows from the body 50 to the source 60. In the IPNSL, the current direction from the body 50 to the source 60 is negative. A broken line It0 indicates the sum of the EVB tunneling current IEVBT and the forward current IPNSL (It0 = IEVBT + IPNSL).

  The body potential of the “1” cell almost converges to the body potential Vb1h at the equilibrium point between the broken line It0 and the forward current IPNBL. This is because, at the body potential Vb1h, the current IEVBT entering the body 50 by EVB tunneling is equal to the current flowing out by the total forward current (IPNBL + IPNSL).

  Since EVB tunneling does not occur in the “0” cell, only the forward currents IPNBL and IPNSL need be considered. Therefore, the body potential of the “0” cell almost converges to the body potential Vb0h at the equilibrium point between the forward currents IPNBL and IPNSL. In FIG. 13, Vb0h is equal to VSDHOLD.

  FIG. 14 is a graph showing the relationship between the EVB tunneling current IEVBT and the forward currents IPNBL and IPNSL when the potential of the source 60 is VSL (ground potential) and the potential of the drain 40 is VSDHOLD.

  The body potential of the “1” cell almost converges to the body potential Vb1h at the equilibrium point between the broken line It0 and the forward current IPNBL. The body potential of the “0” cell almost converges to the body potential Vb0h at the equilibrium point between the forward currents IPNBL and IPNSL.

  Thus, in the third embodiment, the refresh operation is performed by EVB tunneling for the “1” cell, and at the same time, the junction between the body and the source or the body-drain is applied to the “0” cell. A refresh operation is performed by passing a forward current through the junction between the two.

  FIG. 15 is a band diagram of the memory cell MC when VWLHOLD is set to a voltage higher than Vth1 and Vth0 in the third embodiment. In this case, the EVB tunneling current IEVBT flows not only in the “1” cell but also in the “0” cell. However, if the EVB tunneling current IEVBT0 flowing in the “0” cell is sufficiently smaller than the EVB tunneling current IEVBT1 flowing in the “1” cell due to the difference between the body potential of the “1” cell and the “0” cell, It is possible to perform an autonomous refresh operation on the “1” cell and the “0” cell. In this way, the “1” cell and the “0” cell can be autonomously refreshed by supplying different EVB tunneling currents to the “1” cell and the “0” cell.

  FIG. 16 is a graph showing EVB tunneling currents IEVBT0 and IEVBT1 and forward current IPNBL when VWLHOLD is set to a voltage higher than Vth1 and Vth0. In FIG. 16, EVB tunneling currents IEVBT0 and IEVBT1 are shown with the forward current IPNSL taken into account. Therefore, the body potential of the “1” cell almost converges to the body potential Vb1h at the equilibrium point between the EVB tunneling current IEVBT1 and the forward current IPNBL. The body potential of the “0” cell almost converges to the body potential Vb0h at the equilibrium point between the EVB tunneling current IEVBT0 and IPNBL. Thus, even if the word line potential VWLHOLD at the time of refreshing is higher than Vth0, it is possible to perform an autonomous refresh operation on the “1” cell and the “0” cell.

  Hereinafter, the effect of the autonomous refresh operation will be described.

  The inventor of the present invention paid attention to that the memory cell MC itself has a function of amplifying data. By utilizing this function, the memory cell MC itself can amplify and rewrite data. The advantage of this autonomous refresh is that the sense amplifier S / A does not need to detect data during refresh. Therefore, the autonomous refresh according to the present embodiment can simultaneously refresh a plurality of memory cells MC connected to the same bit line BL. Thereby, as will be described later, the power consumption can be reduced and the refresh busy rate can be reduced as compared with the conventional refresh method.

  FIG. 17 is a graph showing the relationship between the number of word lines WL activated simultaneously and the current in the data holding mode. The horizontal axis indicates the number of word lines WL that are simultaneously activated at the time of refresh, and the vertical axis indicates data of a 1 gigabit FBC memory having 32 × 16 units (2 Mb × 32 × 16) of a 2 megabit memory cell array MCA. The current in the holding mode is shown. The current in the data holding mode is a current required for autonomously refreshing the 1 gigabit FBC memory. Two 2-megabit memory cell arrays are provided on the left and right of the sense amplifier S / A as shown in FIG. Each memory cell array includes, for example, 512 word lines WL and 4096 bit lines BL.

  As an example, the capacitance CWL of the word line WL is 300 fF, the voltage amplitude ΔVWL of the word line WL is 1 V, the capacitance of the bit line BL is 100 fF, the voltage amplitude ΔVBL of the bit line BL is 3.5 V, and the peripheral circuit related to the refresh operation Assume that the charge capacity CPERI is 200 pF and the voltage amplitude ΔVPERI of the peripheral circuit is 1.8V. The worst cell retention time TRET is set to 5 ms. Also, it is assumed that the refresh cycle time τref is 50 ns.

  Sixteen 64-Mbit memory cells MC are refreshed in parallel in units of 64 Mbits. In the 64 Mbit memory, refresh is executed for every two 2 Mbit memory cell arrays sharing the row decoder RD. It was assumed that the DC current flowing through the “1” cell during refresh was 2 μA, and the time τ1 for refreshing the memory cell was 3 ns. The influence of the DC current flowing through the memory cell on the current in the data holding mode depends on the retention time (for example, 5 ms) of the memory cell and does not depend on the number of word lines and bit lines activated simultaneously. If half of the “1” cells and “0” cells exist, the average value of the DC current flowing through the 1 gigabit FBC memory in the data holding mode is 0.644 mA.

  FIG. 17 shows the current consumption in the data holding mode of the 1 Gbit memory with respect to the number of word lines activated simultaneously in the 2 Mbit memory cell array. For each of 512, 1024, 2048, and 4096 bit lines activated simultaneously, the current consumption in the data holding mode of the 1 Gbit memory is shown by curves L1 to L4.

  In the conventional refresh operation, one word line is activated and memory cells connected to 4096 bit lines are activated. In this case, the current in the data holding mode is about 70 mA. On the other hand, in the autonomous refresh operation according to the above embodiment, 512 word lines can be activated and memory cells connected to 4096 bit lines can be activated. That is, in the autonomous refresh operation, all the memory cells in the 2Mbit memory cell array can be refreshed simultaneously. In this case, the current in the data holding mode is about 0.84 mA. That is, the current consumption in the data holding mode by the autonomous refresh operation is about 1/100 that of the conventional refresh.

  Note that there is an offset current that does not depend on the number of word lines and bit lines that are simultaneously activated but depends on the degree of integration of the memory cells. This offset current is due to the DC current of the memory cell. Therefore, in this embodiment, the DC current of the memory cell for 1 Gbit becomes the offset current. Therefore, in order to further reduce the current consumption in the data holding mode, it is necessary to reduce the offset current. In order to decrease the offset current, the DC current may be decreased or the refresh period may be lengthened.

Of the currents required in the data holding mode, the current Iret1 (also referred to as AC component) required for charging the bit line and the word line can be generalized as follows. Consider an N × M bit memory array consisting of N word lines and M bit lines. If the minimum value of the retention time of all memory cells is TRET, M bit lines must be charged / discharged every TRET / N in the same refresh operation as that of a conventional DRAM. Assuming that the word line capacitance and voltage amplitude are CWL and VWL, and the bit line capacitance and voltage amplitude are CBL and VBL, respectively, the AC component Iret1 of the current required for data retention of the entire memory cell array is expressed as shown in Equation 1. The
Iret1 = (CWL.VWL + M.CBL.VBL) / (TRET / N) = N (CWL.VWL + M.CBL.VBL) / TRET (Formula 1)

On the other hand, when all memory cells are refreshed simultaneously, all word lines WL and all bit lines BL are activated every time TRET elapses. Therefore, the AC component Iret2 of the current necessary for holding data relating to the memory cell array in this case is expressed as in Expression 2.
Iret2 = (N · CWL · VWL + M · CBL · VBL) / TRET (Formula 2)

The difference ΔIret = Iret1−Iret2 of the AC component of the data holding current is expressed as Equation 3.
ΔIret = (NM−1) · CBL · VBL / TRET≈ (N · M) · CBL · VBL / TRET (Formula 3)
This is almost the same value as the charge / discharge current of the bit line in the conventional refresh operation. Since N · CWL · VWL << (N · M) M · CBL · VBL, the AC component of the data holding current in the autonomous refresh according to the present embodiment is almost negligible when compared with the data holding current in the conventional refresh. Small enough.

  Further, regarding current consumption in a peripheral circuit (also referred to as a column-related peripheral circuit) provided for driving the bit line BL, the conventional refresh requires charging / discharging the peripheral circuit N times during TRET. In the autonomous refresh according to the present embodiment, it is sufficient to charge and discharge the peripheral circuit once during TRET. Also in the column peripheral circuit, the current consumption of the column peripheral circuit in the autonomous refresh according to the present embodiment is small enough to be ignored as compared with the current consumption of the column peripheral circuit in the conventional refresh. In the above calculation, the influence of the DC current flowing in the memory cell during refresh is ignored.

  FIG. 18 is a graph showing the relationship between the number of simultaneously activated word lines WL and the refresh busy rate. The horizontal axis indicates the number of word lines WL that are simultaneously activated during refresh, and the vertical axis indicates the refresh busy rate. The refresh busy rate means a time ratio of the autonomous refresh period to the one cycle period TRET in the data holding mode. For example, a refresh busy rate of 100% is a state in which a refresh operation is always required in a data holding state. Therefore, the lower the refresh busy rate, the better as long as data can be held.

  When the number of word lines WL simultaneously activated in the refresh operation is 1, the refresh busy rate is about 8% or more even if the bit lines BL (4096 lines) of all the columns are activated simultaneously. In the conventional refresh operation, only one word line must be activated at the same time. In this case, even if the bit lines BL (4096 lines) of all the columns are activated simultaneously, the refresh busy rate cannot be made lower than about 8%.

  The autonomous refresh operation according to the present embodiment can simultaneously activate a plurality of word lines. For example, when the number of word lines WL simultaneously activated in the refresh operation is 512 and the number of bit lines BL simultaneously activated in the refresh operation is 4096 (all memory cells in the memory cell array are simultaneously When refreshing), the refresh busy rate can be reduced to about 0.016%.

  If the number of memory cells to be refreshed at the same time is large, the current peak becomes large, and noise may become a problem. When such a problem occurs, the memory cell array may be divided into certain blocks and refreshed for each block. For example, a 64 megabit memory cell may be divided into 128 and 512 Kbit memory cells may be refreshed simultaneously. In this case, the current peak is reduced and the refresh busy rate is increased. However, the refresh busy rate is about 2% (0.016% × 128), and is still within a practical range.

(Autonomous refresh operation in active mode)
In the data holding mode (standby state) in which the operation of writing data from the outside or reading the data to the outside is not executed for a certain period or longer, access to the memory cell MC does not occur. On the other hand, in the active mode, it is necessary to access the memory cells MC irregularly in order to read data to the outside or write data from the outside. The active mode is a state in which a period from an access for reading data to the outside or writing data from the outside to the next access is less than a certain period. In the data read / write operation, the sense amplifier S / A executes a conventional refresh operation in which data in the memory cell MC is once read and this data is written back to the memory cell MC. Therefore, even when access to the memory cell MC frequently enters, the autonomous refresh may be executed in the same cycle as the cycle in the data holding mode.

  Originally, when the access for reading / writing data does not enter for a predetermined period or more, the data deterioration of the memory cell MC becomes a problem. Therefore, in a situation where access frequently enters the memory cell MC, the autonomous refresh functions in the same manner as in the data holding mode.

  However, when access for reading / writing data enters fairly frequently, there is a concern about disturbing the memory cell MC. In such a case, it is effective to change the operation voltage of the autonomous refresh so that the component of the current component that fluctuates due to disturbance can be ignored (so as to be relatively small).

  FIG. 19 is a timing chart showing the operation of the word line WL in the active mode and the data holding mode. For example, as shown in FIG. 19, the word line potential VWL and the bit line potential VBL in the active mode are raised as absolute values than those in the data holding mode. That is, the word line potential VWL and the bit line potential VBL in the active mode are separated from the source potential VSL more than those in the data holding mode. Alternatively, the refresh cycle in the active mode may be shorter than that in the data holding mode. Furthermore, the word line potential VWL and the bit line potential VBL in the active mode may be separated from the source potential VSL than those in the data holding mode, and the refresh period in the active mode may be shorter than that in the data holding mode. Thereby, the EVB tunneling current and the forward current in the active mode can be increased more than those in the data holding mode.

  Since the current component due to the disturbance increases in the active mode compared to the data holding mode, it is effective to increase the EVB tunneling current and the forward current. At this time, the DC current passed through the memory cell MC also increases, but a large average current flows originally in the active mode. For this reason, the increments of EVB tunneling current and forward current are negligible.

  However, in the data holding mode, since it is necessary to realize a low data holding current, an increase in the EVB tunneling current and the forward current becomes relatively remarkable. Therefore, the EVB tunneling current and the forward current in the data holding mode are preferably lower than that in the active mode.

  At the time of autonomous refresh, the number of word lines WL activated simultaneously and the number of bit lines BL activated simultaneously are arbitrary. For example, one word line WL and all bit lines BL may be activated as in a conventional refresh operation, and all memory cells MC connected to the activated word line WL may be simultaneously refreshed. In this case, the current consumption in the data holding mode is the same as the conventional one.

  All the word lines WL and one bit line BL may be activated, and all the memory cells MC connected to the activated bit line BL may be refreshed simultaneously. In this case, the current consumption in the data holding mode is as follows: the number 2n of the word lines WL, the capacity CWL of the word lines WL, the drive amplitude ΔVWL of the word lines WL, the number of bit lines 2 m, the capacity CBL of the bit lines, and the drive amplitude of the bit lines Depends on ΔVBL. The current consumption in the data holding mode may be decreased or increased as compared with the conventional case.

  All the word lines WL and all the bit lines BL may be activated to refresh all the memory cells MC in the memory cell array at the same time. In this case, the current consumption in the data holding mode is lower than in the conventional case. In this case, the current required for the operation of the peripheral circuit can also be reduced. The third embodiment can further obtain the effects of the first embodiment.

  The FBC memory device according to the third embodiment can be used as an SRAM (Static Random Access Memory) that does not require refresh. In this case, for the “1” cell, holes are replenished to the body 50 by EVB tunneling. At the same time, for the “0” cell, holes are excluded from the body 50 by passing a forward current through the junction between the body and the source or the junction between the body and the drain. As a result, the body potential of the “1” cell can be maintained at Vb1h, and the body potential of the “0” cell can be maintained at Vb0h. By maintaining the voltage on the word line WL and the bit line BL so as to maintain the body potential of the “1” cell at Vb1h and the body potential of the “0” cell at Vb0h, the third embodiment The FBC memory device according to can function as SRAM.

  When the FBC memory is used as the SRAM, as shown in FIGS. 15A and 15B, the potential of the word line may be higher than the threshold voltage Vth0 of the “0” cell. In this case, due to the difference between the EVB tunneling current flowing in the “1” cell and the EVB tunneling current flowing in the “0” cell, the “1” cell and the “0” cell stabilize the data “1” and the data “0”, respectively. Can be retained. Even when the FBC memory is used as an SRAM, the potential of the word line at the time of data writing may be different from the potential of the word line at the time of data holding.

1 is a diagram showing a configuration of an FBC memory according to a first embodiment of the present invention. Sectional drawing which shows the structure of memory cell MC. The band diagram which shows the method of writing data "1" in the memory cell MC using EVB tunneling. The band diagram which shows the method of writing data "1" in the memory cell MC using EVB tunneling. The band diagram which shows the method of writing data "1" in the memory cell MC using EVB tunneling. The timing diagram which shows the write-in operation | movement using EVB tunneling. The timing diagram which shows the write-in operation | movement using EVB tunneling. The graph which shows the relationship between the forward electric current at the time of writing of data "1", and the electric current by EVB tunneling. The timing diagram which shows the write-in operation | movement using EVB tunneling by 2nd Embodiment. The timing diagram which shows the write-in operation | movement using EVB tunneling by 2nd Embodiment. The graph which shows the relationship between the forward current at the time of data writing, and the electric current by EVB tunneling. Band diagram of “0” cell during autonomous refresh. The graph which shows the relationship between EVB tunneling current IEVBT and the forward currents IPNBL and IPNSL. The graph which shows the relationship between EVB tunneling current IEVBT and the forward currents IPNBL and IPNSL. 9 is a band diagram of a memory cell MC when VWLHOLD is set to a voltage higher than Vth1 and Vth0 in the third embodiment. The graph which shows EVB tunneling current IEVBT0, IEVBT1, and forward current IPNBL. The graph which shows the relationship between the number of the word lines WL activated simultaneously, and the electric current in data retention mode. The graph which shows the relationship between the number of the word lines WL activated simultaneously, and the refresh busy rate. FIG. 5 is a timing chart showing an operation of a word line WL in an active mode and a data holding mode.

Explanation of symbols

WL ... word line BL ... bit line SL ... source line MC ... memory cell S / A ... sense amplifier WLD ... word line driver 40 ... drain 50 ... body 60 ... source 70 ... gate insulating film 80 ... gate electrode

Claims (6)

A source layer, a drain layer, an electrically floating body region that is provided between the source layer and the drain layer to store or release charges to store logic data; and a gate A memory cell including a gate electrode provided on the body region via an insulating film;
A bit line connected to a drain layer of the memory cell;
A word line connected to or functioning as a gate electrode of the memory cell; and
A word line driver connected to the word line;
The semiconductor memory device, wherein the word line driver writes first logical data to the memory cell by electron valence band tunneling through the gate insulating film. A source layer, a drain layer, an electrically floating body region that is provided between the source layer and the drain layer to store or release charges to store logic data; and a gate A memory cell including a gate electrode provided on the body region via an insulating film;
A bit line connected to a drain layer of the memory cell;
A word line connected to or functioning as a gate electrode of the memory cell; and
A word line driver connected to the word line;
When writing the first logic data to the memory cell, the word line driver is higher than the threshold voltage of the memory cell under a state where the potential of the bit line is substantially equal to the potential of the source layer, And a first potential higher than the potential of the word line at the time of data reading is applied to the word line. Connected to the bit line, reads logical data stored in the memory cell at the time of data reading, or writes second logical data having a reverse logic to the first logical data to the memory cell at the time of data writing. A sense amplifier,
The word line driver writes the first logic data to all the memory cells connected to the word line corresponding to the word line driver;
3. The sense amplifier according to claim 1, wherein the sense amplifier writes the second logic data only to a selected memory cell among the memory cells in which the first logic data is written. Semiconductor memory device. Connected to the bit line, reads logical data stored in the memory cell at the time of data reading, or writes second logical data having a reverse logic to the first logical data to the memory cell at the time of data writing. A sense amplifier,
While the word line driver applies the first potential to the word line, the sense amplifier has a potential of the source layer on the bit line connected to the memory cell to which the first logic data is to be written. And the bit line connected to the memory cell to which the second logic data is to be written is on the opposite side to the first potential with respect to the potential of the source layer. The semiconductor memory device according to claim 1, wherein a second potential is applied.   When performing a refresh operation for recovering the deterioration of the logical data of the memory cell, the memory cell storing the first logical data is refreshed by valence band tunneling through the gate insulating film. At the same time, for the memory cell storing the second logic data having the opposite logic to the first logic data, the junction between the body region and the source layer or the 3. The semiconductor memory device according to claim 1, wherein the refresh operation is performed by passing a current through a junction between the body region and the drain layer. The semiconductor memory device is a static semiconductor memory device,
For the memory cell storing the first logical data, charge is replenished to the body region by valence band tunneling through the gate insulating film, and at the same time, the first logical data is supplied to the memory cell. For the memory cell storing the second logic data of reverse logic, a current is applied to the junction between the body region and the source layer or the junction between the body region and the drain layer. 3. The semiconductor memory device according to claim 1, wherein the charge is excluded from the body region by flowing the semiconductor memory device. 4.

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