JP2009193525A - Interruption control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interruption control device, capable of consistently and efficiently processing interruption. <P>SOLUTION: The device includes an interruption receiving part which receives an interruption signal and holds it as an interruption factor; an interruption selection part which selects one interruption factor to be reported to a processor from interruption factors held by the interruption receiving part; and a reported interruption factor recording part to which the interruption factor completed in report to the processor of the interruption factors held by the interruption receiving part is recorded as a reported interruption factor. The interruption selection part selects and reports, upon receipt of a report request of interruption factor from the processor, one interruption factor which is not recorded in the reported interruption factor recording part of the interruption factors held by the interruption receiving part, and records this reported interruption factor to the interruption factor recording part. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an interrupt control device mounted on a computer system including one or more processors.

  In a computer system, it is necessary to appropriately process interrupts from various peripheral devices mounted on the computer system. In particular, in recent years, multiprocessor systems that are rapidly spreading are required to handle interrupts more efficiently without any contradiction among a plurality of installed processors.

  For example, if an interrupt process from a certain peripheral device is simultaneously performed by a plurality of processors, the processor does not operate correctly. Therefore, an interrupt process must be performed exclusively by one of the processors.

  Therefore, in this type of conventional computer system, interrupt processing is performed only by a specific processor, or interrupt processing from each peripheral device is divided and notified so as not to overlap each processor. In some cases, a distributed method is used by a plurality of processors.

  However, in this case, interrupt processing concentrates on a specific processor and a bottleneck in system performance occurs. Therefore, it is preferable that the interrupt processing is performed flexibly by a plurality of processors.

  For this purpose, check the load status of each processor, the priority of the program being executed, etc., select the processor with the lightest load from the results, notify the processor of the interrupt, and execute the interrupt processing. There was a method to perform (for example, Patent Document 1).

  In addition, there is a method in which an interrupt is notified to all the processors, and the processor that responds the earliest acquires the interrupt by some kind of exclusive control means and performs the interrupt processing (for example, Patent Document 2).

JP-A-9-81528 JP-A-61-103268

  However, in the method of notifying each processor of the interrupt as disclosed in Patent Document 1, means for notifying each processor of the interrupt independently and means for selecting which processor to notify of the interrupt are provided. Therefore, there is a problem that the apparatus becomes complicated and the scale becomes large. When the number of processors is changed, there is a problem that a large change is required, and it is necessary to recreate it each time.

  Further, in the method for notifying all processors as shown in Patent Document 2, it is necessary to have an exclusive control means for preventing interrupt processing by each processor from competing, and in addition, each processor In the interrupt processing executed in step 1, there is a problem that it is necessary to make use of the exclusive control means provided. Since the processing overhead increases as the exclusive control means is used in the interrupt processing executed by each processor, there is a problem that the system performance deteriorates.

  The present invention has been made in view of the above, and even when a computer system includes a plurality of processors, independent interrupt notification to each processor and interrupt processing executed by each processor. It is an object of the present invention to obtain an interrupt control device that processes interrupts efficiently without contradiction without performing exclusive control.

  In order to solve the above-described problems and achieve the object, the present invention is mounted on a computer system including one or more processors, receives an interrupt signal generated from a peripheral device, and sends the interrupt signal to the processor. An interrupt control device for notifying an interrupt factor for identifying which peripheral device is generating an interrupt in response to a notification request from the processor, wherein an interrupt signal from the peripheral device is received. An interrupt reception unit that receives and holds as an interrupt factor, an interrupt selection unit that selects one interrupt factor to be notified to the processor from the interrupt factors held by the interrupt reception unit, and the interrupt reception The interrupt factor recording unit records the interrupt factor already notified to the processor among the interrupt factors held by the processor as a notified interrupt factor, and receives an interrupt factor notification request from the processor , The recording interrupt selection unit selects one interrupt factor that is not recorded in the notified interrupt factor recording unit among the interrupt factors held by the interrupt reception unit, and notifies the processor of the selected interrupt factor. The interrupt factor thus recorded is recorded in the notified interrupt factor recording unit.

  According to the present invention, even when a plurality of interrupt factors are accepted, when an interrupt factor notification request is received from a processor, one interrupt factor that has not yet been notified to the processor is selected and the processor is selected. Since it is configured to notify and record the notified interrupt factor as already notified, even if the computer system has a plurality of processors, each processor is notified of an interrupt factor that does not overlap, and each processor There is an effect that it is possible to obtain an interrupt control device that can efficiently process an interrupt without contradiction without performing independent interrupt notification and exclusive control in an interrupt process executed by each processor. .

  Embodiments of an interrupt control device according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration of a computer system to which the interrupt control device according to the first embodiment of the present invention is applied.

  In FIG. 1, a computer system 100 according to the first embodiment includes at least one (here, three) processors 11 to 13, a processor unit 1 that performs an operation and an interrupt process, and a plurality (here, five). ) And the peripheral devices 31 to 35, the interrupt signal 4 is transmitted to the processor unit 1 to cause the processors 11 to 13 to refer to the interrupt factor, and the processors 11 to 13 are transmitted. An interrupt control device 2 that makes any one of them recognize an interrupt. A general computer system including the computer system 100 according to the first embodiment of the present invention includes a device such as a memory, but is not an essential part of the computer system 100 according to the first embodiment of the present invention. Omitted.

  The interrupt control device 2 further includes an interrupt reception unit 21, an interrupt selection unit 22, a notified interrupt factor recording unit 23, and an interrupt factor register 24.

  The interrupt receiving unit 21 receives an interrupt signal from the peripheral devices 31 to 35, and holds the interrupt factor of the interrupt signal as an accepted interrupt factor. When the interrupt reception unit 21 receives the interrupt signal, the interrupt control device 2 transmits the received interrupt signal as the interrupt signal 4 to the processor unit 1.

  The interrupt selection unit 22 selects one interrupt factor to be notified when referenced from the processors 11 to 13 among the accepted interrupt factors, and sets a value for identifying the interrupt factor in the interrupt factor register 24. Set. When the processor unit 1 receives the interrupt signal 4, the processors 11 to 13 refer to the interrupt factor register 24 and read which interrupt factor is generated. When one of the processors 11 to 13 reads the value set in the interrupt factor register 24, the interrupt selection unit 22 determines that the interrupt factor of the read value has been notified and the value of the interrupt factor register 24 And the value of the notified interrupt factor recording unit 23 is set so that it can be seen that this interrupt factor has been notified. Then, if there is an interrupt factor that has not been notified yet among the interrupt factors accepted by the interrupt factor register 24, the interrupt selection unit 22 selects one and sets the value of the interrupt factor register 24. .

  When the interrupt processing of the interrupt factor by one of the processors 11 to 13 is completed and the interrupt is cleared from the peripheral devices 31 to 35 that have generated the interrupt factor, the interrupt selection unit 22 accepts The value of the part corresponding to the interrupt factor of the interrupt factor and the notified interrupt factor recording unit 23 is restored.

  Here, how the value of the interrupt factor register 24 is determined by the interrupt selection unit 22 will be described more specifically. FIG. 2 is a diagram for explaining how the value of the interrupt factor register 24 is determined by the interrupt selection unit 22.

  In FIG. 2, the interrupt factor accepted by the interrupt factor accepting unit 21 is 1 when an interrupt signal is input from each peripheral device and received by the interrupt accepting unit 21, and the interrupt factor is received from each peripheral device. When no signal is input, it is represented by 0. Here, as an example, it means that an interrupt signal is input from the peripheral devices 31, 32, and 34, and no interrupt signal is input from the peripheral devices 33 and 35. Note that 0 may be input when an interrupt signal is input, and 1 may be input when an interrupt signal is not input.

  In the notified interrupt factor recorded by the notified interrupt factor recording unit 23, one of the processors 11 to 13 refers to the interrupt factor register 24, and any peripheral device among the peripheral devices 31 to 35. 1 indicates that an interrupt has occurred, and 0 indicates that it has not yet been recognized. Here, as an example, it is recognized that an interrupt signal is input from the peripheral device 31, and it means that interrupt signals from other peripheral devices 32 to 35 have not been recognized yet. The case where the processor recognizes it may be 0, and the case where it is not recognized may be 1.

  In the unreported interrupt factor, 1 indicates that there is an interrupt signal from a peripheral device that is not recognized by any of the processors 11 to 13, and 0 indicates otherwise. In other words, it is 1 when the accepted interrupt factor is 1 and the notified interrupt factor recording unit 23 is 0, and 0 in other cases. Here, since the interrupt signals from the peripheral devices 32 and 34 have not yet been recognized by the processors 11 to 13, this is 1 and the others are 0. Note that an interrupt signal from a peripheral device not yet recognized by the processor may be set to 0, and otherwise 1 may be set.

In the interrupt factor register 24, 1 indicates that there is an interrupt signal from a peripheral device to be notified to the processor, and 0 indicates otherwise. Here, among the interrupt signals from the peripheral devices 32 and 34 that have not been notified, it is determined that the interrupt signal from the peripheral device 32 is to be notified to the processor and is set in the interrupt factor register. ing.

  In this way, the interrupt selection unit 22 responds to the interrupt signal from each peripheral device received by the interrupt reception unit 21 and has already recorded the interrupt recorded in the notified interrupt factor recording unit 23 to the processor. With reference to the interrupt factor, an unreported interrupt factor is extracted, and if there are a plurality of unreported interrupt factors, one of them is selected and set in the interrupt factor register 24.

  Next, the operation of causing the computer system 100 of the first embodiment configured as described above to process an interrupt from the peripheral devices 31 to 35 to any one of the processors 11 to 13 is described in a specific scenario. A description will be given along an example. FIG. 3 is a diagram for specifically explaining an operation for processing an interrupt of the computer system 100 according to the first embodiment.

  In FIG. 3, the received interrupt factor, the notified interrupt factor recorded in the notified interrupt factor recording unit 23, and each value of the interrupt factor register 24 are the last four digits of FIG. , 32, 33, and 34, the states of the interrupt factors generated are extracted and shown.

  First, in the initial state, no interrupt has occurred, and the accepted interrupt factor, the notified interrupt factor, and the value of the interrupt factor register 24 are all “0000” (in the figure). Scenario column number 1). Here, if an interrupt is generated from the peripheral device 31, the accepted interrupt factor changes to “0001” (scenario column number 2 in the figure). At this time, since the processors 11 to 13 have not been notified yet, the notified interrupt factor remains “0000”. As a result, the value of the interrupt factor register 24 is set to “0001”.

  When an interrupt is generated from the peripheral device 31, the interrupt signal 4 is output to the processor unit 1, and the processors 11 to 13 recognize that the interrupt has occurred. As a result, the processors 11 to 13 try to refer to the interrupt factor register 24 in order to check which interrupt factor has occurred.

  Here, if the processor 11 responds to the interrupt earliest and references the interrupt factor register 24, “0001” is referred to the processor 11 as the value of the interrupt factor register 24. As a result, the processor 11 recognizes the interrupt factor from the peripheral device 31 and starts the interrupt process.

  On the other hand, in the interrupt selection unit 22, since the interrupt factor register 24 is referred to by the processor 11, the value “0001” at that time is reflected in the notified interrupt factor, and as a result, the notified interrupt factor Becomes "0001", and the interrupt factor register 24 is set to "0000" (scenario column number 3 in the figure).

  Therefore, when the processors 12 and 13 that responded to the interrupt later than the processor 11 refer to the interrupt factor register 24, “0000” is referred to as the value thereof, and there is no interrupt to be processed. I will not.

  When the interrupt processing in the processor 11 is completed and the interrupt from the peripheral device 11 is cleared, the accepted interrupt factor returns to “0000” and at the same time, the notified interrupt factor also returns to “0000” (in the figure). Scenario column number 4).

  Subsequently, it is assumed that an interrupt is generated from the peripheral device 32 and an interrupt is generated from the peripheral device 34 before the processor responds. In this case, the accepted interrupt factor is “0010” when an interrupt occurs from the peripheral device 32 (scenario column number 5 in the figure), and “1010” when an interrupt occurs from the peripheral device 34. Change (scenario column number 6 in the figure). The notified interrupt factor is “0000” and does not change. The interrupt factor register 24 becomes “0010” when an interrupt is generated from the peripheral device 32 (scenario column number 5 in the figure), and remains “0010” when an interrupt is generated from the peripheral device 34 ( Scenario column number 6).

  When an interrupt is generated from the peripheral device 32, the interrupt signal 4 is output to the processor unit 1, and the processors 11 to 13 recognize that the interrupt has occurred. As a result, the processors 11 to 13 try to refer to the interrupt factor register 24 in order to check which peripheral device generated the interrupt.

  Here, if the processor 11 responds to the interrupt earliest and references the interrupt factor register 24, “0010” is referred to as the value of the interrupt factor register 24 by the processor 11. As a result, the processor 11 recognizes that an interrupt has occurred from the peripheral device 32 and starts the interrupt process.

  On the other hand, in the interrupt selection unit 22, since the interrupt factor register 24 is referred to by the processor 11, the value “0010” at that time is reflected in the notified interrupt factor, and as a result, the notified interrupt factor Becomes “0010”, and the interrupt factor register 24 reflects the remaining unreported interrupt signals of the peripheral device 34 and is set to “1000” (scenario column number 7 in the figure).

  If the processor 12 responds to the interrupt after the processor 11, “1000” is referred to as the value of the interrupt factor register 24 by the processor 12. As a result, the processor 12 recognizes that an interrupt has occurred from the peripheral device 34 and starts the interrupt process.

  In the interrupt selection unit 22, since the interrupt factor register 24 is referred to by the processor 12, the value “1000” at that time is reflected in the notified interrupt factor. As a result, the notified interrupt factor is “1010”. In the interrupt factor register, since there are no remaining unreported interrupt factors, “0000” is set (scenario column number 8 in the figure).

  Therefore, even if the remaining processors refer to the interrupt factor register 24, “0000” is referred to as the value thereof, and there is no interrupt to be processed, so that no interrupt processing is performed.

  When the interrupt processing in the processor 11 is completed and the interrupt from the peripheral device 32 is cleared, the accepted interrupt factor is changed to “1000”, and at the same time, the notified interrupt factor is also changed to “1000” ( Scenario column number 9).

  Here, if an interrupt is generated from the peripheral device 33, the accepted interrupt factor changes to “1100”. The notified interrupt factor remains “1000”. As a result, the interrupt factor register 24 is set to “0100” (scenario column number 10 in the figure).

  When an interrupt is generated from the peripheral device 33, the interrupt signal 4 is output again, and the processors 11 to 13 recognize that the interrupt has occurred. If the processor 13 responds to the interrupt earliest and references the interrupt factor register 24, “0100” is referred to as the value of the interrupt factor register 24, and the peripheral device 33 receives the interrupt. Recognize that an interrupt has occurred and start the interrupt process.

  In the interrupt selection unit 22, since the interrupt factor register 24 is referred to by the processor 13, the value “0100” at that time is reflected in the notified interrupt factor, and as a result, the notified interrupt factor is “1100. Further, the interrupt factor register is set to “0000” (scenario column number 11 in the figure).

  Even if the other processor refers to the interrupt factor register 24, “0000” is referred to as the value thereof, and there is no interrupt to be processed, so the interrupt processing is not performed.

  Thereafter, when the interrupt processing in the processor 12 is completed and the interrupt from the peripheral device 34 is cleared, the accepted interrupt factor changes to “0100”, and at the same time, the notified interrupt factor also changes to “0100”. Change (scenario column number 12 in the figure). Next, when the interrupt processing in the processor 13 is completed and the interrupt from the peripheral device 33 is cleared, the accepted interrupt factor returns to “0000” and at the same time, the notified interrupt factor also returns to “0000” ( Scenario column number 13).

  As described above, according to the first embodiment, even when a plurality of interrupt factors are accepted, when an interrupt factor read request is received from the processor, the interrupt factors that have not yet been notified to the processor are 1 The selected interrupt factor is notified and the notified interrupt factor is recorded as notified. Therefore, even when the computer system has a plurality of processors, interrupts that do not overlap each processor Get an interrupt control device that processes the interrupts efficiently without contradiction, without the cause being notified and without performing independent interrupt notification to each processor and exclusive control in the interrupt processing executed by each processor be able to. In other words, since independent interrupt notification to each processor is unnecessary, even if the number of processors is changed, an interrupt signal and its control circuit for notifying each processor of interrupts are created. There is no change and it can be used as it is. In addition, since exclusive control in the interrupt processing executed by each processor is unnecessary, processing overhead associated with exclusive control does not occur, and system performance does not deteriorate.

Embodiment 2. FIG.
In Embodiment 2 of the present invention, when priority is set for interrupt factors, and there are a plurality of unreported interrupt factors, the interrupt selection unit 22 selects the interrupt factor with the highest priority. It is characterized by being set in the interrupt factor register 24.

  In the interrupt control device according to the second embodiment, the accepted interrupt factor held in the interrupt acceptance unit 21, the notified interrupt factor recorded by the notified interrupt factor recording unit 23, and the interrupt factor register 24 The locations for storing the values corresponding to the interrupt signals of the peripheral devices 31 to 35 are arranged so that the peripheral device having a higher priority is on the right side. For example, the priority of the interrupt factors from the peripheral devices 31 to 35 is, in order from the highest, the interrupt factor from the peripheral device 34, the interrupt factor from the peripheral device 32, the interrupt factor from the peripheral device 31, Assuming that there are interrupt factors from the peripheral device 33 and interrupt factors from the peripheral device 35, the value arrangement method is as follows. Arranged in advance from the lowest (right side).

  Then, when there are a plurality of unreported interrupt factors, the interrupt selection unit 22 is configured to select a lower (right) interrupt factor. As a result, the interrupt selection unit 22 always selects an interrupt factor having a higher priority.

  In this example, the lower priority (right side) is arranged in order from the highest priority, but the higher order (left side) is arranged, and the higher order (left side) interrupt signals are selected. But there is no problem.

  Further, when a higher priority interrupt occurs, the interrupt selection unit 22 resets the value of the interrupt factor register 24 within a range that does not conflict with the reference of the interrupt factor register 24 by the processor. It may be configured.

  For example, in the first embodiment, when an interrupt is generated from the peripheral device 34 after an interrupt is generated from the peripheral device 32 and before the processor refers to the interrupt factor register 24, the interrupt factor register 24 The value of “0010” is not changed but is changed to “1000” in order to transmit an interrupt from the peripheral device 34 having a higher priority. (When arranged as shown in FIG. 4, it is changed from “0010” to “0001”.)

  As described above, according to the second embodiment, in addition to the effect obtained by the interrupt control device according to the first embodiment, there is an effect that processing is performed by the processor in order from higher priority interrupts. It is done.

Embodiment 3 FIG.
In Embodiment 3 of the present invention, a priority table that defines priorities for interrupt factors from each peripheral device is provided, and the interrupt selection unit 22 refers to the priority table and has a high priority. A feature is that the interrupt is set in the interrupt factor register 24.

  FIG. 5 is a diagram showing the configuration of the interrupt control device according to Embodiment 3 of the present invention. In FIG. 5, the interrupt control device 2 includes a priority table in which the priority of interrupt factors of the peripheral devices 31 to 35 is described in addition to the configuration of the interrupt control device 2 of the first and second embodiments. 25. When there are a plurality of interrupt factors not notified to the processors 11 to 13, the interrupt selection unit 22 refers to the priority table 25, selects an interrupt factor having a higher priority, and generates an interrupt factor register 24. Set to.

  FIG. 6 shows an example of the priority table 25. Thus, the priority table 25 holds the priority of the interrupt factor. In this example, following the first embodiment, each peripheral device 31 to 35 generates one interrupt factor, and the priority of the interrupt factor is such that the smaller the number, the higher the priority. The interrupt factor from the device 34 has the highest priority, and is followed by the peripheral devices 32, 33, 31, 35.

  The configuration of the priority table 25 may be a priority table of any configuration as long as the priority can be understood. As for the priority, a numerical value with a large numerical value may be set with a high priority, or an interrupt signal may be simply arranged in order of priority.

  Further, it is desirable that the priority of the interrupt factors does not overlap, that is, it is desirable not to set the same priority for a plurality of interrupt factors, but the same priority may be set for a plurality of interrupt signals. In this case, when there are a plurality of interrupt signals not notified to the processor and they have the same priority, any one of the interrupt signals is selected by some method and set in the interrupt factor register 24. Configure.

  A method for selecting any one of a plurality of interrupt signals having the same priority is not limited here, but, for example, the one defined in the upper level of the priority table 25 is selected and defined in the lower level. Various methods can be considered, such as selecting the one that has been interrupted first, selecting the one that has been interrupted later, selecting from the frequency and period of occurrence of the interrupt, etc. .

  As described above, according to the third embodiment, the priority table 25 that defines the priority with respect to the interrupt factor is provided, and the interrupt selection unit 22 refers to the priority table 25 and determines the interrupt with a high priority. Since the interrupt is set in the interrupt factor register 24, the priority of the interrupt signals from the peripheral devices 31 to 35 can be easily changed only by changing the contents of the priority table. As compared with the interrupt control device, an optimum interrupt priority can be set more flexibly in accordance with the operation of the system.

Embodiment 4 FIG.
By the way, in the interrupt control device according to the third embodiment of the present invention, the priority of the interrupt signals from the peripheral devices 31 to 35 is set by providing the priority table 25. In the interrupt control device according to mode 4, the priority table 25 can be changed from the processors 11 to 13. By enabling the change from the processors 11 to 13, the interrupt priority can be set dynamically in accordance with the operation of the system.

Embodiment 5 FIG.
In the interrupt control device according to the fifth embodiment of the present invention, the interrupt selection unit 22 clears the contents of the notified interrupt factor recording unit 23 after a certain period of time, and interrupts from the peripheral devices 31 to 35. The processor 11 to 13 is notified again of the error factor.

  FIG. 7 is a configuration diagram of the interrupt control device 2 according to the fifth embodiment of the present invention. In FIG. 7, the interrupt control device 2 includes a timer 26, and when the interrupt selection unit 22 recognizes that a certain time has elapsed in the timer 26, the contents of the notified interrupt factor recording unit 23 are cleared, Reset the value of interrupt factor register 24.

  When the processors 11 to 13 refer to the interrupt factor register 24, the interrupt selection unit 22 reflects the content of the interrupt factor register 24 in the notified interrupt factor recording unit 23 and sets the value of the interrupt factor register 24. At the same time, the timer 26 is started.

  The timer 26 notifies the interrupt selection unit 22 when a preset time has elapsed. When receiving the notification from the timer 26, the interrupt selection unit 22 clears the contents of the notified interrupt factor recording unit 23. By clearing the notified interrupt factor, interrupt factors from each peripheral device received by the interrupt receiving unit 21 that have not been previously set in the interrupt factor register 24 as being notified The interrupt factor register 24 can be set again.

  When the interrupt selection unit 22 receives the notification from the timer 26 and clears the contents of the notified interrupt factor recording unit 23, the interrupt selection unit 22 reexamines the unreported interrupt factor and determines one of them as the interrupt factor. Set in register 24.

  As described above, according to the fifth embodiment, in addition to the effect obtained by the interrupt control device according to the first embodiment, there is a case where some failure occurs in the processors 11 to 13 that are executing the interrupt processing. However, the interrupt processing can be started again by another processor, and the system operating rate can be increased.

Embodiment 6 FIG.
The interrupt control device according to the fifth embodiment includes a timer 26, and the interrupt selection unit 22 clears the contents of the notified interrupt factor recording unit 23 when a certain period of time elapses. A different timer may be provided for each of the 31 to 35 interrupt factors.

  Therefore, the interrupt control device according to the sixth embodiment of the present invention includes a different timer for each interrupt factor from each of the peripheral devices 31 to 35. When the processors 11 to 13 refer to the interrupt factor register 24, the interrupt selection unit 22 reflects the contents in the notified interrupt factor recorded by the notified interrupt factor recording unit 23 and indicates the contents thereof. The timer 26 prepared for an interrupt factor from the peripheral device being started is started.

  When the interrupt selection unit 22 receives a notification from the timer 26, only the interrupt factor associated with the timer is displayed as the content of the notified interrupt factor recorded in the notified interrupt factor recording unit 23. Clear from. The interrupt factor from another peripheral device is not cleared from the contents of the notified interrupt factor recorded in the notified interrupt factor recording unit 23.

  As described above, according to the sixth embodiment, compared with the interrupt control device according to the fifth embodiment, it is possible to obtain a more flexible computer system against the failure of the processors 11 to 13. Is obtained.

Embodiment 7 FIG.
In addition, the timer 26 may be configured to be able to set and change the time from activation until notification to the interrupt selection unit 22, that is, the timeout time, from the processors 11 to 13. Therefore, the interrupt control device according to the seventh embodiment of the present invention enables the timeout time to be set from the processors 11 to 13.

  As described above, according to the seventh embodiment, the time-out time of the timer can be dynamically changed by the processors 11 to 13 in accordance with the operation of the system. Therefore, compared with the interrupt control device according to the sixth embodiment. Thus, it is possible to obtain a more flexible computer system against a processor failure or the like.

Embodiment 8 FIG.
Further, the notified interrupt factor recording unit 23 may be configured to be referred from a processor. In the interrupt control device according to the eighth embodiment, the processors 11 to 13 refer to the notified interrupt factor recording unit 23.

  As described above, according to the eighth embodiment, since it is possible to know the interrupt signal from each peripheral device that is being interrupted by another processor, the interrupt control device according to the first embodiment In comparison, it is possible to obtain a more flexible computer system against a processor failure or the like.

Embodiment 9 FIG.
Moreover, you may comprise so that the notified interruption factor recording part 23 can be cleared from the processors 11-13. The interrupt control device according to the ninth embodiment clears the notified interrupt factor recording unit 23 when the processors 11 to 13 detect a failure or the like of another processor by some means. The interrupt selection unit 22 resets the value of the interrupt factor register 24 again by clearing the notified interrupt factor recording unit 23 by the processors 11 to 13. By referring to the updated interrupt factor register 24, the processor can refer to an interrupt factor that has been notified so far and could not be referred to, and can start the interrupt process.

  As described above, according to the ninth embodiment, the notified interrupt factor recorded in the notified interrupt factor recording unit 23 can be cleared dynamically by the processors 11 to 13 according to the operation of the system. Therefore, a more flexible computer system can be obtained with respect to the failure of the processors 11 to 13 and the like than the interrupt control device of the first embodiment.

Embodiment 10 FIG.
The interrupt control device according to the tenth embodiment is configured so that interrupt factors from all the peripheral devices 31 to 35 accepted by the interrupt accepting unit 21 can be referred to by the processors 11 to 13. In this case, the notified interrupt factor recording unit 23 may be updated or may not be updated.

  The processors 11 to 13 can acquire the unreported interrupt factor selected by the interrupt selection unit 22 from the interrupt factor register 24 and all the peripheral devices 31 to 35 received by the interrupt reception unit 21. By acquiring interrupt factors, a wider variety of interrupt processing can be realized.

  For example, in a certain application, it is possible to fix an interrupt factor to be processed by each of the processors 11 to 13. In this case, each of the processors 11 to 13 may acquire all the interrupt factors received by the direct interrupt receiving unit 21 and confirm whether or not an interrupt factor to be processed by itself has occurred.

  For example, some interrupt factors may be processed by a specific processor, and other interrupt factors may be processed by any processor. In this case, each of the processors 11 to 13 first obtains all the interrupt factors accepted by the interrupt accepting unit 21 and confirms whether or not an interrupt factor to be processed by itself has occurred. If it does, interrupt processing for the interrupt factor is performed, and if it does not occur, the interrupt factor register 24 is referred to and interrupt processing for the obtained interrupt factor is performed.

  As described above, according to the tenth embodiment, since the interrupt factors from all the peripheral devices 31 to 35 received by the interrupt receiving unit 21 are configured to be referred to from the processors 11 to 13, the embodiment is provided. Compared with the interrupt control device 1, a more flexible computer system according to the operation of the system can be obtained.

It is a figure which shows the structure of the computer system to which the interrupt control apparatus by Embodiment 1 of this invention is applied. It is a figure which shows a mode that the value of an interruption factor register is determined. It is a figure explaining operation | movement of the interruption control apparatus by Embodiment 1 of this invention. It is a figure which shows a mode that the value of the interruption factor register of the interruption control apparatus by Embodiment 2 of this invention is determined. It is a figure which shows the structure of the interruption control apparatus which is Embodiment 3 of this invention. It is a figure which shows the structural example of a priority table. It is a figure which shows the structure of the interrupt control apparatus by Embodiment 5 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Processor part 2 Interrupt control apparatus 4 Interrupt signal 11-13 Processor 21 Interrupt reception part 22 Interrupt selection part 23 Notified interrupt factor recording part 24 Interrupt factor register 25 Priority table 26 Timer 31-35 Peripheral device 100 computer system

Claims (10)

Mounted in a computer system having one or more processors, accepts an interrupt signal generated from a peripheral device, generates an interrupt signal to the processor, and interrupts from which peripheral device in response to a notification request from the processor An interrupt control device that notifies an interrupt factor for identifying whether or not an error has occurred,
An interrupt reception unit that receives an interrupt signal from a peripheral device and holds it as an interrupt factor;
An interrupt selection unit for selecting one interrupt factor to be notified to the processor from the interrupt factors held by the interrupt reception unit;
Of the interrupt factors held by the interrupt reception unit, a notified interrupt factor recording unit that records an interrupt factor already notified to the processor as a notified interrupt factor;
With
When receiving the interrupt factor notification request from the processor, the interrupt selection unit sets the interrupt factor that is not recorded in the notified interrupt factor recording unit by the interrupt factor held by the interrupt reception unit. Selecting one and notifying the processor, and recording the notified interrupt factor in the notified interrupt factor recording unit,
An interrupt control device characterized by that. When the interrupt acceptance unit accepts an interrupt factor, the interrupt factor is held in association with the priority,
When the interrupt factor notification request is received from the processor, the interrupt selection unit selects the interrupt factor that is not recorded in the notified interrupt factor recording unit by the interrupt factor held by the interrupt reception unit. Selecting one of the highest priority interrupt factors from the processor and notifying the processor, and causing the notified interrupt factor to be recorded as the notified interrupt factor recording unit,
The interrupt control apparatus according to claim 1. A priority table that holds a correspondence between the interrupt factor and the priority of the interrupt factor;
When receiving the interrupt factor notification request from the processor, the interrupt selection unit refers to the priority table and records it in the notified interrupt factor recording unit with the interrupt factor held by the recording interrupt reception unit. One interrupt factor with the highest priority is selected from the interrupt factors that have not been notified and notified to the processor, and the notified interrupt factor is recorded in the notified interrupt factor recording unit as notified Let
The interrupt control apparatus according to claim 1.   4. The interrupt control device according to claim 3, wherein the priority table can be changed by a processor. It further has a timer for measuring a predetermined time,
The interrupt selection unit, when notifying the interrupt factor to the processor, starts the timer and records the notified interrupt factor in the notified interrupt factor as being notified, and the timer When the time measurement ends, the notified interrupt factor recorded in the notified interrupt factor recording unit is deleted.
The interrupt control apparatus according to any one of claims 1 to 4, wherein There is a different timer for each interrupt factor,
The interrupt selection unit, when notifying the interrupt factor to the processor, activates the timer corresponding to the notified interrupt factor and sets the notified interrupt factor as notified to the notified interrupt factor. When the timer finishes measuring the predetermined time, the information corresponding to the notified interrupt factor is deleted from the information recorded in the notified interrupt factor recording unit,
The interrupt control apparatus according to claim 5.   The interrupt control apparatus according to claim 5 or 6, wherein the predetermined time can be changed by a processor for each timer.   The interrupt control device according to any one of claims 1 to 7, wherein a record of the notified interrupt factor recorded in the notified interrupt factor recording unit can be referred to by a processor. .   The interrupt control apparatus according to any one of claims 1 to 8, wherein a record of the notified interrupt factor recorded in the notified interrupt factor recording unit is erasable by a processor. .   The interrupt control apparatus according to any one of claims 1 to 9, wherein an interrupt factor held by the interrupt receiving unit can be directly read by a processor.

Images