JP2009193479A - Multi-cpu device and its boot processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a boot system of a versatile multi-CPU structure variable to allow versatile boot processing to perform inexpensively with respect to the multi-CPU device and its boot processing method. <P>SOLUTION: Information on the boot system of a CPU including start-up sequence of CPUs 11 and 12 is stored to a plurality of kinds of boot pattern tables as boot patterns, one boot pattern is selected by a boot system switch setting part 15 and set to a boot system control unit 14. A CPU bus control unit 13 gives the CPU a right of bus access for reading the boot program from a nonvolatile memory 18 in start-up sequence designed by the boot pattern. An address conversion part 17 converts an address signal output by the CPU into an address signal of a boot program storage region of the nonvolatile memory according to the boot pattern. A data width conversion part 16 converts a data signal read from the nonvolatile memory into a data bus width following the boot pattern and outputs it to the CPUs 11 and 12. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multi-CPU device that is mounted on a card, a system device, or the like that requires various controls and includes a plurality of CPUs and a boot processing method for initially starting the plurality of CPUs.

  A configuration example of a conventional multi-CPU device is shown in FIG. In general, n (n ≧ 2) CPUs are mounted on the multi-CPU device, but the configuration example of FIG. 4 shows a configuration example of a multi-CPU device on which n = 2, that is, two CPUs. In FIG. 4, 11 is a first CPU (# 1), 12 is an nth CPU (#n), 21 is an arbiter, 31 is a non-volatile memory, 41 is an arbitration signal, and 51 is a common bus.

  A boot process in this configuration example will be described. When the reset signal for the CPU (# 1) 11 and the CPU (#n) 12 is released, a control signal for accessing the common bus 51 is received from each of the CPU (# 1) 11 and the CPU (#n) 12. The arbiter 21 arbitrates which of the CPU (# 1) 11 and the CPU (#n) 12 is given the bus access right.

  The arbiter 21 generates an arbitration signal 41 for giving permission to use the common bus 51 (bus access right), and the CPU (# 1) 11 that has received the arbitration signal 41 is nonvolatile via the common bus 51. The memory 31 is accessed and the boot program for activation is read out. The boot program is normally stored in the nonvolatile memory 31 corresponding to each of the CPU (# 1) 11 and the CPU (#n) 12.

  As an example of storing the boot program, for example, the boot program of the CPU (# 1) 11 is stored in the nonvolatile memory 31 (# 1) corresponding to the CPU (# 1) 11, and the boot program of the CPU (#n) 12 is the CPU. It is stored in the non-volatile memory 31 (#n) corresponding to (#n) 12. However, the non-volatile memory 31 (# 1) and the non-volatile memory 31 (#n) can be configured so as to be divided into areas in one non-volatile memory 31.

  The CPU (# 1) 11 and the CPU (#n) 12 access the common bus 51 by fixed arbitration by the arbiter 21, read the boot program from each divided area of the nonvolatile memory 31, and execute the boot program The boot (initial startup) is completed.

  In the following Patent Document 1, in a multi-CPU processing device including a plurality of microprocessors that execute a program, a memory that stores the program, and a common bus, a program that the plurality of microprocessors execute after reset is shared. When there are conflicting addresses that are stored in the memory and accessed by multiple microprocessors after resetting, each program is stored in a different address area, and the conflicting addresses are converted to different addresses by an address translation device. Describes a multi-CPU processor that reads from a common bus.

Further, the following Patent Document 2 includes a main processor and a local processor, and an initial startup program stored in a system memory common to each processor is converted into an address by an address conversion circuit, via a system bus. An initial activation control method for the data processing device to be read is described.
JP-A-10-289220 JP 59-206923 A

  In the conventional multi-CPU device, in the boot process, the signal line used by each CPU to access the non-volatile memory and read the boot program is a common bus. Therefore, if a failure occurs in the common bus, all the CPUs The obstacle will spill over. Further, in the conventional multi-CPU device, it is necessary to provide a non-volatile main memory storing each boot program individually for each CPU, which is not necessarily the best in terms of cost and mounting. .

  Furthermore, in the boot processing of the conventional multi-CPU device, since the boot program of each CPU is read by acquiring the bus access right by the arbiter, the CPU startup order is fixed according to the priority of the bus access right grant by the arbiter. When the boot process procedure and method can be applied only to a fixed and fixed format, and the boot process procedure and method are different for each multi-CPU device, the boot process is performed according to each device. It was necessary to remodel the implementation method.

  The present invention makes it possible to change the boot method of a device having a multi-CPU configuration such as a multi-card having high versatility, to perform inexpensive and highly versatile boot processing, and to initially start (boot) each CPU. There are provided a multi-CPU device and a boot processing method thereof in which a nonvolatile main memory for storing the boot program can be constituted by a single memory common to the CPUs.

  The multi-CPU device includes a boot method control unit having a boot pattern table in which a plurality of types of CPU boot method information including a CPU activation order are stored in advance as boot patterns, and a boot pattern stored in the boot pattern table. Boot pattern switching setting means for setting the selected boot pattern in the boot method control unit, and the boot order in the boot order specified by the boot pattern set in the boot method control unit. CPU bus control means for giving the CPU a bus access right for reading the program from the nonvolatile memory.

  The boot processing method of the multi-CPU device includes a step of previously storing a plurality of types of CPU boot method information including the CPU activation order in a boot pattern table of a boot method control unit as a boot pattern, and the boot pattern A boot pattern is selected from the boot patterns stored in the table, the selected boot pattern is set in the boot method control unit, and specified by the boot pattern set in the boot method control unit And providing the CPU with a bus access right for reading the boot program from the nonvolatile memory in the startup order.

  According to the present invention, various boot methods can be selected with the same multi-CPU device, and versatile boot processing can be performed with an inexpensive configuration with a small number of components. In addition, since each CPU reads the boot program without directly accessing the common bus, even if a failure occurs in the signal line connecting one CPU and the common bus, the spread of the failure to the activation of other CPUs is avoided. be able to.

  FIG. 1 shows a configuration example of a multi-CPU device according to the present invention. In the figure, 11 is the first CPU (# 1), 12 is the nth CPU (#n), 13 is the CPU bus control unit, 14 is the boot system control unit, 15 is the boot system switching setting unit, and 16 is A data width conversion unit, 17 is an address conversion unit, and 18 is a large-capacity nonvolatile memory.

  When the reset signals for the CPU (# 1) 11 and the CPU (#n) 12 are canceled, the boot method control unit 14 reads the boot method set by the boot method switching setting unit 15 at the timing of the release. Determine the boot method. The CPU bus control unit 13 arbitrates bus access of the CPU (# 1) 11 and the CPU (#n) 12 in accordance with the boot method determined by the boot method control unit 14.

  The above operation will be described in more detail. First, when the reset signal is released, the CPU (# 1) 11 and the CPU (#n) 12 start a predetermined boot processing operation. The start of the operation is constantly monitored by the CPU bus control unit 13, and the CPU bus control unit 13 may or may not have a time difference in the start of the boot processing operations of the CPU (# 1) 11 and the CPU (#n) 12. Gives a bus access permission to one CPU in the order according to the boot method determination by the boot method control unit 14.

  The CPU bus control unit 13 sends an address signal and a control signal from the CPU that has permitted the bus access to the address conversion unit 17, and the address conversion unit 17 is an area of a large-capacity nonvolatile memory in which the boot program of the CPU is stored. Then, the address signal is converted into the address, and the converted address signal and control signal are output to the large-capacity nonvolatile memory 18.

  The large-capacity nonvolatile memory 18 outputs the boot program data read from the area specified by the address signal from the address converter 17 to the data width converter 16. The data width conversion unit 16 arranges the data signals in the data bus width designated by the boot method described above, and sends an external data signal to the CPU that has permitted the bus access. Such a series of processing is repeatedly executed for each CPU, and the boot processing of each CPU is completed.

  FIG. 2 shows a main part of a characteristic configuration of the multi-CPU device of the present invention. The figure shows the boot method control unit 14, the boot method switching setting unit 15, the data width conversion unit 16, the address conversion unit 17, and the large-capacity nonvolatile memory 18 in FIG. Hereinafter, these configurations will be mainly described.

  The boot method control unit 14 includes a boot pattern table 14-1. The boot pattern table 14-1 is a table in which information on various boot methods is stored as a plurality of types of boot patterns. Based on the boot pattern identification signal input from the boot method switching setting unit 15, the boot pattern information stored in the boot pattern table 14-1 is read, and the boot control signal specified by the boot pattern information is The data is output to the CPU bus control unit 13, the data width conversion unit 16, and the address conversion unit 17.

  The boot method switching setting unit 15 includes a boot pattern selection unit 15-1 and a decoder 15-2. The boot pattern selection unit 15-1 has a configuration capable of selecting one boot pattern from a plurality of boot patterns. The decoder 15-2 decodes the identification signal of the selected boot pattern and outputs it to the boot method control unit 14.

  The data width conversion unit 16 includes a data alignment table 16-1. The data alignment table 16-1 aligns data read from the large-capacity nonvolatile memory 18 into data signals having a predetermined data width according to boot pattern information. Data alignment information for storing the data is stored.

  The address conversion unit 17 includes an area conversion unit 17-1, a large-capacity nonvolatile memory address conversion unit 17-2, and an access control unit 17-3. The area conversion unit 17-1 converts an address signal and a control signal output from the CPU into an address of an area of the large-capacity nonvolatile memory 18 in which the corresponding boot program is stored according to the boot pattern information.

  In addition, since a large-capacity nonvolatile memory is usually configured to read, for example, 256 bytes of data with one address, an address signal is cyclically output each time data is read in units of 1 to 4 bytes. In order to maintain consistency with the operation of the CPU, a large capacity nonvolatile memory address conversion unit 17-2 is provided.

  The access control circuit 17-3 generates various signals for access control of the large-capacity nonvolatile memory 18 and causes the boot program to be read from the large-capacity nonvolatile memory 18. The large-capacity nonvolatile memory 18 has a program area 18-1 storing a plurality of types of boot programs.

  The boot processing of the multi-CPU device depends on various multi-CPU configurations and their uses, etc., the CPU startup order, the boot program storage area of each CPU, and the data signal width of each CPU (for example, 8 bits, 16 bits) , 32 bits), etc., different boot methods are assumed. The boot pattern switching setting means for supporting such different boot methods is the boot pattern table 14-1 and the boot pattern selection unit 15-1.

  These signals are selected by the boot pattern selection unit 15-1 and the boot pattern identification signal decoded by the decoder 15-2 is sent to the boot method control unit 14 by releasing the reset signal of the CPU. A plurality of boot patterns assumed in advance are prepared in the boot pattern table 14-1, and one boot pattern is output according to the signal selected by the boot pattern selection unit 15-1. The boot pattern selection unit 15-1 may be manually selected or automatically selected by upper software.

  Since there are a large number of boot patterns, the boot pattern selection unit 15-1 can select and set one boot pattern from the boot pattern table 14-1 in which a large number of patterns are stored. The boot method can be selected while being narrowed down in order by item or item, and the combination information of the selected type or item is converted into an identification signal of one boot pattern by the decoder 15-2. You can also.

  The boot pattern table 14-1 includes boot method information such as a bus arbitration procedure (in the order of startup of the CPU), a type or storage area of a boot program, and a data signal width. It is the role of the boot method control unit 14 to convert this boot method information into a boot control signal and send it to the data width conversion unit 16, the address conversion unit 17 and the large-capacity nonvolatile memory 18 through the CPU bus control unit 13. .

  The area conversion circuit 17-1 of the address conversion unit 17 stores an address signal and a control signal from the CPU that has undergone access arbitration according to the boot pattern by the CPU bus control unit 13, and the corresponding boot program is stored in accordance with the boot pattern. This is converted into an address signal in the area of the capacity nonvolatile memory 18.

  The converted address signal is sent to a non-volatile memory address conversion unit 17-2 that converts the converted address signal into an address of the large-capacity non-volatile memory 18. As described above, in an ordinary nonvolatile memory, an address is cyclically converted and data is read, but a large-capacity nonvolatile memory reads a data of, for example, 256 bytes by one address. This is to ensure consistency with the read operation.

  Then, the access control circuit 17-3 generates various signals for access control of the large-capacity nonvolatile memory 18, and the boot program is read from the large-capacity nonvolatile memory 18. The read boot program data is sent to the data width converter 16, and the data width converter 16 selects the data alignment information corresponding to the boot pattern from the data alignment table 16-1, and the data alignment information. The boot program data is converted into the data signal width according to the above and sent to the CPU to complete the boot process.

  If the boot process is not normally completed, the boot pattern selection by the boot pattern selection unit 15-1 is switched to another selection candidate by switching by software or hardware, and a different boot is performed by resetting the CPU again. A boot process in which data alignment or the like by a pattern is changed can be configured to cope with a failure in the boot process.

  FIG. 3 shows an example of the boot processing operation of the multi-CPU device of the present invention. In the figure, (a) is a reset signal, (b) is an address signal output from the first CPU (# 1), (c) is an address signal output from the nth CPU (#n), (d ) Is an operation stop (WAIT) signal for the first CPU (# 1), (e) is an operation stop (WAIT) signal for the nth CPU (#n), and (f) is the first CPU (# 1). The address signal after revision (conversion) of the address signal from, (g) is the address signal after revision (conversion) of the address signal from the nth CPU (#n), and (h) is a large capacity non-volatile Memory address, (i) is read data of a large-capacity nonvolatile memory, (j) is data to be output to the first CPU (# 1), and (k) is data to be output to the nth CPU (#n). is there.

  The operation example shown in FIG. 3 is as follows: “Distributed boot, first CPU (# 1) (first place in boot order) bus width 8 bits, nth CPU (#n) bus width 32 bits, different boot for each CPU It is an operation example in the case of the “program boot method”. Suppose that the boot pattern identification number of this boot method is 3. In FIG. 2, the number 3 is selected by the boot pattern selection unit 15-1, and the decoder 15-2 gives this number 3 to the boot method control unit 14 with a hexadecimal code, for example.

  The boot method control unit 14 reads the information of the boot pattern 3 in the boot pattern table 14-1, and generates a boot control signal according to the information. The operation of FIG. 3 is performed based on this boot control signal.

  First, when the reset signal (a) is canceled, the address signals (A + A0, B + B0) are output from each CPU as shown in (b) and (c). In order to hold the output address signal, the CPU (# 1) WAIT signal and the CPU (#n) WAIT signal are once sent to each CPU as shown in (d) and (e). Stop operation.

  On the other hand, in order to recognize that the first CPU (# 1) is first in the boot order from the boot pattern information and to read the boot program of the first CPU (# 1), Thus, the first CPU (# 1) revised address signal (AA + A0) revised to the address of the boot program area of the first CPU (# 1) is generated.

  Then, as shown in (h), the generated first CPU (# 1) revised address signal (AA + A0) is further converted into an indirect address of the large-capacity nonvolatile memory, and the large-capacity nonvolatile memory address signal (AAA + A0). Is generated. At the same time, data read for 256 bytes is started, and 256 bytes of data (A + D0 to A + D255) are read from the large-capacity nonvolatile memory as shown in (i).

  When this reading is finished, the operation stop (WAIT) signal of the first CPU (# 1) is canceled as shown in (d), and the first CPU (# 1) is made operable. When the first CPU (# 1) is in an operable state, the first CPU (# 1) reads the normal 8-bit data and boots, so that the address signal (A + A0-A0) as shown in (b). A + A255) is incremented (increased by one address because it is an 8-bit bus), and the boot program data (A + D0 to A + D255) is read as shown in (j). When this is completed, as shown in (d), the first CPU (# 1) is again brought into a stopped state.

  Next, booting of the nth CPU (#n) is started. The read operation of the boot program (B + D0 to B + D255) from the nonvolatile memory of the nth CPU (#n) to the data width conversion unit is performed by the first CPU (# 1) as shown in (i). It is done from the stage of doing. The previous operations such as address conversion are the same as in the case of the first CPU (# 1).

  The output of the boot program to the nth CPU (#n) is the operation of the nth CPU (#n) as shown in (e) when the read from the large-capacity nonvolatile memory to the data width conversion unit is completed. The stop (WAIT) signal is canceled to make the nth CPU (#n) operable, and the nth CPU (#n) reads the boot program (B + D0 to B + D255).

  However, unlike the first CPU (# 1), the n-th CPU (#n) has a 32-bit data width, so that 8-bit data is aligned with 32-bit data according to the boot pattern parameters. As shown in (k), the nth CPU (#n) increments the address (B + A0, B + A4,... B + A252) by 4 addresses in normal operation as shown in (c). By passing (B + D0, B + D4,..., B + D252) to the nth CPU (#n), the boot process is completed.

  Thereafter, similarly to the first CPU (# 1), the n-th CPU (#n) is also stopped. This operation is repeated according to the data amount of the boot program, and the boot processing of the first CPU (# 1) and the nth CPU (#n) is completed.

It is a figure which shows the structural example of the multi CPU apparatus by this invention. It is a figure which shows the principal part of the characteristic structure of the multi CPU device of this invention. It is a figure which shows the operation example of the boot process of the multi CPU apparatus of this invention. It is a figure which shows the structural example of the conventional multi CPU apparatus.

Explanation of symbols

11 First CPU (# 1)
12 nth CPU (#n)
13 CPU bus control unit 14 Boot system control unit 15 Boot system switching setting unit 16 Data width conversion unit 17 Address conversion unit 18 Large capacity nonvolatile memory

Claims (4)

In a multi-CPU device composed of a plurality of CPUs,
A boot method control unit having a boot pattern table in which a plurality of types of boot method information including a CPU activation order are stored in advance as a boot pattern;
A boot pattern switching setting means for selecting one boot pattern from the boot patterns stored in the boot pattern table and setting the selected boot pattern in the boot method control unit;
CPU bus control means for giving the CPU a bus access right for reading the boot program from the nonvolatile memory in the boot order specified by the boot pattern set in the boot method control unit;
A multi-CPU device comprising:   The boot pattern includes the type of boot program of each CPU or the storage area information in the nonvolatile memory, and specifies the boot program read address signal output from the CPU to which the bus access right is given by the boot pattern. 2. The multi-CPU device according to claim 1, further comprising address conversion means for converting into an address signal in a boot program storage area of the non-volatile memory to be sent to the non-volatile memory.   The boot pattern includes information on the data bus width of each CPU, converts the data signal of the boot program read from the nonvolatile memory into a data signal of the data bus width specified by the boot pattern, and the bus access The multi-CPU device according to claim 1, further comprising a data width converting means for sending to a CPU to which the right is given. In a boot processing method of a multi-CPU device composed of a plurality of CPUs,
A step of storing a plurality of types of CPU boot method information including the CPU activation order in the boot pattern table of the boot method control unit in advance as a boot pattern;
Selecting one boot pattern from the boot patterns stored in the boot pattern table, and setting the selected boot pattern in the boot method control unit;
Giving the CPU a bus access right for reading the boot program from the nonvolatile memory in the boot order specified by the boot pattern set in the boot method control unit;
A boot processing method for a multi-CPU device including:

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