JP2009193051A - Lateral electric field type liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a lateral electric field type LCD device which makes it possible to increase the flexibility in designing and to improve the aperture ratio easily compared with the related-art LCD structure. <P>SOLUTION: A common electrode 72 covers each of a plurality of drain bus lines 56 entirely, and also covers a gate bus lines 55 corresponding to a plurality of pixel regions except for predetermined areas. The predetermined area of the gate bus line 55 corresponding to each of the pixel region is covered with a storage capacitor electrode 73 of another pixel region adjacent to the gate bus line 55. The storage capacitor electrode 73 is put over the gate bus line 55 beyond one side edge 55b, and preferably the common electrode 72 is put over the gate bus line 55 beyond the other side edge 55a. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device, and more particularly to an in-plane switching (IPS) type active matrix liquid crystal display device. The present invention can be applied to a computer monitor, a liquid crystal television, a mobile phone terminal, a GPS terminal, a car navigation system, a game machine, a bank / convenience store terminal, a medical diagnostic apparatus, and the like using a horizontal electric field type liquid crystal display device.

  In general, a liquid crystal display (LCD) has features such as a thin and light weight and low power consumption. In particular, an active matrix liquid crystal display device (AM-LCD), in which individual pixels arranged in a matrix of vertical and horizontal dimensions are driven by active elements, has been recognized as a high-quality flat panel display. As an active element, a thin-film transistor (TFT-LCD) using a thin-film transistor (TFT) is widely used.

  Many active matrix type liquid crystal display devices use the electro-optic effect of twisted nematic (TN) type liquid crystal, and an electric field generally perpendicular to the substrate surface is applied to the liquid crystal sandwiched between two substrates. The image is displayed by applying and displacing the molecules of the liquid crystal. This is called “vertical electric field method”. On the other hand, a “horizontal electric field type” liquid crystal display device that displays an image by displacing liquid crystal molecules in a plane substantially parallel to the substrate surface by an electric field substantially parallel to the substrate surface has also been known. . Various improvements have been made to the horizontal electric field type liquid crystal display device as well as the vertical electric field type.

  For example, in Patent Document 1 (Japanese Patent Laid-Open No. 2000-089240) and Patent Document 2 (Japanese Patent Laid-Open No. 2004-062145), a drain bus line and a gate bus line are covered with a common electrode through an interlayer insulating film. A horizontal electric field type liquid crystal display device having the above is disclosed. The structure of the liquid crystal display device described in Patent Document 2 is shown in FIGS.

  9 is a plan view showing a configuration of an active matrix substrate (TFT substrate) of the liquid crystal display device, FIG. 10 is a plan view showing a three-layer structure constituting the substrate, and FIG. 11 is a diagram of gate bus lines of the substrate. It is a partial enlarged plan view showing the detailed configuration of the periphery. In the active matrix liquid crystal display device, the configuration of a plurality of pixels is the same, and therefore the configuration for one pixel is shown in FIGS.

  As shown clearly in FIGS. 10A, 10B and 10C, the active matrix substrate of the conventional liquid crystal display device shown in FIG. A plurality of gate bus lines 155 and a plurality of common bus lines 152 formed in the same layer on the same layer, and a plurality of gate bus lines formed in the same layer on a gate insulating film (not shown) covering them. Drain bus line 156, a plurality of pixel electrodes 171, a plurality of thin film transistors (TFTs), a plurality of storage capacitor electrodes 173, and a protective insulating film (not shown) that covers these 1 The common electrode 172 is provided. The pixel electrode 171 and the common electrode 172 are usually formed by patterning a transparent conductive metal film such as ITO (Indium Tin Oxide).

  A plurality of gate bus lines 155 extending in parallel at equal intervals in the horizontal (left and right) direction in FIG. 9 and a plurality of drain bus lines 156 extending in parallel in the vertical (vertical) direction in FIG. 9 at equal intervals. Each of the rectangular areas surrounded by a pixel area is a pixel area, and a plurality of pixel areas (pixels) are arranged in a matrix as a whole. The thin film transistor 145 is disposed in the vicinity of one of the intersections of the two gate bus lines 155 and the two drain bus lines 156 (lower left intersection in FIG. 9) that defines each pixel region. Similar to the gate bus line 155, the common bus line 152 extends in the horizontal direction in FIG. Each of the common bus lines 152 is disposed on the opposite side (upper end portion in FIG. 9) from the thin film transistor 145 in the pixel region, and is from the thin film transistor 145 of the two gate bus lines 155 that defines the pixel region. It is located in the vicinity of a distant one (in FIG. 9, the upper gate bus line 155). Therefore, each of the common bus lines 152 is disposed with a gap in the vicinity of the thin film transistor 145 in the previous pixel region adjacent to the upper side along the extending direction (vertical direction) of the drain bus line 156. I can say that.

  The drain electrode 144, the source electrode 142, and the semiconductor layer 143 of the thin film transistor 145 are formed in the patterns (shapes) shown in FIGS. 10A and 10B, respectively. A gate electrode (not shown) of the thin film transistor 145 is formed integrally with the gate bus line 155 (in other words, the gate electrode is a part of the gate bus line 155), and the drain electrode 144 and the source electrode 142 are formed. Between the semiconductor layer 143 and the semiconductor layer 143. As the semiconductor layer 143, an amorphous silicon film is usually used.

  The pixel electrode 171 and the common electrode 172 that generate the liquid crystal driving electric field have patterns (shapes) as shown in FIGS. 10B and 10C, respectively, and mesh with each other in the form shown in FIG. Comb-like portions (thin strip portions protruding into the pixel regions) 171a and 172a are provided. Here, the number of the comb-like portions 171a of the pixel electrode 171 is three, and the number of the comb-like portions 172a of the common electrode 172 is two. An opening (window) 172 b is formed in the common electrode 172 at a position overlapping the channel region of the thin film transistor 145. For this reason, the entire channel region is exposed from the opening 172b and does not overlap the common electrode 172. This is to avoid a change in characteristics of the thin film transistor 145 due to the back gate effect.

  The pixel electrode 171 is mechanically and electrically connected to the source electrode 142 of the thin film transistor 145 at the base end (source electrode 142 side) in the pixel region. Further, the pixel electrode 171 is mechanically and electrically connected to the storage capacitor electrode 173 at the tip portion (the side opposite to the source electrode 142) of the three comb-like portions 171a. The common electrode 172 is used in common for all pixels, and is electrically connected to the common bus line 152 directly below through a contact hole 162 that penetrates the gate insulating film and the protective insulating film in the pixel region. It is connected.

  The storage capacitor electrode 173 is located in a position overlapping with the common bus line 152 directly below the storage capacitor electrode 173 via the gate insulating film, and a storage capacitor is formed by the overlapping portion. That is, the storage capacitor is composed of the storage capacitor electrode 173, the common bus line 152 immediately below the storage capacitor electrode 173, and the gate insulating film interposed therebetween. As shown in FIG. 11, the storage capacitor electrode 173 does not overlap with the adjacent gate bus line 155.

  As is clear from FIGS. 10B and 10C and FIG. 11, the common electrode 172 covers the entire surface of the drain bus line 156 extending in the vertical direction of FIG. The entire surface of the extended gate bus line 155 is also covered (except for the opening 172b). In addition, the common electrode 172 is not only a region directly above the gate bus line 155 but also the gate bus line 155 and the common bus line 152 disposed adjacent thereto (this is the extending direction of the drain bus line 156 (vertical direction). ), A gap between the gate bus line 155 and the source electrode 142, and a gap between the gate bus line 155 and the storage capacitor electrode 173. Further, it is formed so as to cover (overlap) the peripheral regions of the edges of the source electrode 142 and the storage capacitor electrode 173. For this reason, the electric field generated in the vicinity of the gate bus line 155 can be shielded by the common electrode 172. An edge 172c (which extends along the adjacent gate bus line 155) of the common electrode 172 on the side of the storage capacitor electrode 173 does not overlap the gate bus line 155.

  In FIG. 11, reference numeral 181 denotes a black matrix layer formed on the counter substrate. The black matrix layer 181 has a rectangular light shielding area indicated by a broken line in FIG. 11 for each pixel area. The light shielding region is large enough to cover the entire thin film transistor 145 and is formed in a rectangular island shape in the region directly above the thin film transistor 145. As described above, the area occupied by the light blocking region of the black matrix layer 181 is suppressed to the minimum necessary for preventing the light from entering the thin film transistor 145. The reason for preventing light from entering the thin film transistor 145 (channel region thereof) by this light shielding region is to prevent the function of the thin film transistor 145 from being impeded by the incident light.

  As described above, in the active matrix substrate of the conventional liquid crystal display device shown in FIGS. 9 to 11, the electric field generated around the gate bus line 155 can be shielded by the common electrode 172 disposed on the upper layer. Therefore, the liquid crystal molecules in the peripheral region of the gate bus line 155 do not change its direction from the initial alignment state, and therefore light leakage does not occur in the peripheral region. Therefore, it is not necessary to shield the peripheral area on the counter substrate side, and a light shielding area having a minimum size as shown in FIG. 11 can be obtained.

  Incidentally, in the conventional active matrix substrate shown in FIGS. 9 to 11, the pixel electrode 171 can be formed of the same transparent conductive metal as the common electrode 172. The configuration in that case will be described with reference to FIGS.

  12 is a plan view showing a configuration of an active matrix substrate of a liquid crystal display device having the above configuration, FIG. 13 is a plan view showing a structure of three layers constituting the substrate, and FIG. 14 is a periphery of a gate bus line of the substrate. FIG. 15 is a partial cross-sectional view of the liquid crystal display device taken along line AA ′ of FIG. 14, and FIGS. 16A and 16B are B- It is a fragmentary sectional view of the said liquid crystal display device along a B 'line and CC' line. FIG. 17 is a plan view in which the pixel electrode 171 and the common electrode 172 are omitted in FIG. 12 to make the lower structure easy to understand, and FIG. 18 is a pixel electrode 171, common electrode 172, and black matrix layer 181 in FIG. FIG. 5 is a partially enlarged plan view in which the contact holes 161 and 162 are omitted and the lower structures thereof are made easier to understand. These figures also show the configuration for one pixel.

  As understood from FIG. 13, the configuration shown in FIGS. 12 to 18 is different from the configuration shown in FIGS. 9 to 11 in that (a) the pixel electrode 171 has the same transparent conductivity as the common electrode 172. The pixel auxiliary electrode 170 is formed in the same layer as the common electrode 172, (b) the pixel auxiliary electrode 170 is formed in the same layer as the drain bus line 156, and (c) the pixel electrode 171. Is electrically connected to the storage capacitor electrode 173 in the lower layer through a contact hole 161 that penetrates the protective insulating film 159 (see FIGS. 15 to 16), and further, the source electrode 142 through the pixel auxiliary electrode 170. The other configurations are the same. Therefore, the same components as those of the conventional active matrix substrate described with reference to FIGS. 9 to 11 are denoted by the same reference numerals as those used in FIGS. 9 to 11, and the description thereof is omitted.

  The pixel electrode 171 and the common electrode 172 each have a pattern (shape) as shown in FIG. 13C, and comb-like portions (in each pixel region) that mesh with each other in the form as shown in FIG. And a protruding thin band-like portion) 171a and 172a. Here, the number of the comb-like portions 171a of the pixel electrode 171 is three, and the number of the comb-like portions 172a of the common electrode 172 is two.

  The pixel auxiliary electrode 170 formed in the same layer as the drain bus line 156 corresponds to the pixel electrode 171 having the base end portion and the central comb-like portion 171a in the configuration shown in FIGS. . The base end portion of the pixel auxiliary electrode 170 is electrically and mechanically connected to the source electrode 142, and the distal end portion thereof is electrically and mechanically connected to the storage capacitor electrode 173. In this way, the pixel electrode 171 is electrically connected to the source electrode 142 via the storage capacitor electrode 173 and the pixel auxiliary electrode 170 in the pixel region.

  As shown in FIGS. 17 and 18, the storage capacitor electrode 173 overlaps with the common bus line 152 immediately below, but does not overlap with the adjacent gate bus line 155. The common electrode 172 covers the entire gate bus line 155. Therefore, in the pixel region, an edge 172c on the storage capacitor electrode 173 side of the common electrode 172 (this extends along the adjacent gate bus line 155). ) Does not overlap with the gate bus line 155. This point is the same as the configuration shown in FIGS.

  Next, the overall structure of the conventional liquid crystal display device shown in FIGS. 12 to 18 will be described with reference to FIGS.

  In this liquid crystal display device, an active matrix substrate and a counter substrate are joined and integrated with a liquid crystal layer 120 interposed therebetween.

  The active matrix substrate includes a transparent glass substrate 111, a common bus line 152, a gate bus line 155, a drain bus line 156, a thin film transistor 145, a pixel auxiliary electrode 170, and a pixel electrode 171 formed on the inner surface of the glass substrate 111. , A common electrode 172 and a storage capacitor electrode 173. The common bus line 152 and the gate bus line 155 are directly formed on the inner surface of the glass substrate 111, and they are covered with the gate insulating film 157 except for the contact hole 162. The drain electrode 144, the source electrode 142 and the semiconductor layer 143, the pixel auxiliary electrode 170, the storage capacitor electrode 173, and the drain bus line 156 of the thin film transistor 145 are formed on the gate insulating film 157. Therefore, the common bus line 152 and the gate bus line 155 are electrically insulated from the drain electrode 144, the source electrode 142, the semiconductor layer 143, the pixel auxiliary electrode 170, the storage capacitor electrode 173, and the drain bus line 156 by the gate insulating film 157. Has been. These structures formed on the glass substrate 111 are covered with a protective insulating film 159 except for the portions of the contact holes 161 and 162.

  The pixel electrode 171 and the common electrode 172 are formed over the protective insulating film 159. As described above, the pixel electrode 171 is electrically connected to the storage capacitor electrode 173 directly below through the contact hole 161 (which penetrates the protective insulating film 159) in the pixel region, and further the pixel auxiliary electrode 170 is connected to the pixel electrode 171. And is electrically connected to the source electrode 142. In the pixel region, the common electrode 172 is electrically connected to the common bus line 152 directly below through a contact hole 162 (which penetrates the protective insulating film 159 and the gate insulating film 157). The pixel electrode 171 and the common electrode 172 are both formed by patterning a transparent conductive metal film such as ITO.

  The surface of the active matrix substrate having the above configuration (the surface on which the pixel electrode 171 and the common electrode 172 are formed) is covered with an alignment film 131 made of an organic polymer film. The surface of the alignment film 131 is subjected to an alignment process for directing the initial direction of the liquid crystal molecules in the liquid crystal layer 120 in a desired direction.

  On the other hand, the counter substrate (color filter substrate) includes a transparent glass substrate 112 and red (R) / green (G) / blue (corresponding to each pixel region formed on the inner surface of the glass substrate 112). B) a color filter (not shown) composed of the color layers 182R, 182G, and 182B, and a black matrix layer 181 for light shielding. The black matrix layer 181 has a rectangular light-shielding region indicated by a broken line in FIG. 14 for each pixel region, similarly to the configuration shown in FIGS. The three color layers 182R, 182G, and 182B are collectively referred to as a color layer 182.

  The color layer 182 (color filter) and the black matrix layer 181 are covered with an acrylic overcoat layer 185. On the inner surface of the overcoat layer 185, columnar spacers (not shown) for controlling the distance between the active matrix substrate and the counter substrate are formed. The inner surface of the overcoat layer 185 is covered with an alignment film 132 made of an organic polymer film. The surface of the alignment film 132 is subjected to an alignment process for directing the initial direction of the liquid crystal molecules in the liquid crystal layer 120 to a desired direction.

  The active matrix substrate and the counter substrate having the above-described configuration are opposed to each other with the surfaces on which the alignment film 131 and the alignment film 132 are formed facing each other, and are overlapped at a predetermined interval. A liquid crystal layer 120 is formed in the gap between the two substrates, and the periphery of the two substrates is sealed with a sealing material (not shown) in order to confine the liquid crystal material present in the liquid crystal layer 120. A pair of polarizing plates (not shown) are arranged on the outer surfaces of both substrates.

In Patent Document 3 (Japanese Patent Laid-Open No. 2000-029014) and Patent Document 4 (Japanese Patent Laid-Open No. 2002-082630), the end portions of adjacent color layers of the color filter are overlapped in place of the black matrix layer. Discloses a technique for forming a light shielding layer. In this case, the step of forming the black matrix layer can be omitted, and the cost can be reduced.
JP 2000-089240 A JP 2004-062145 A JP 2000-029014 A JP 2002-082630 A

  In the configuration of the two conventional liquid crystal display devices described above, the entire surface of each gate bus line 155 is covered with the common electrode 172 on the upper layer, but this occurs at the periphery of the gate bus line 155 and the thin film transistor 145. This is to prevent the liquid crystal molecules in the peripheral portion from changing from the initial alignment state and causing light leakage due to the applied electric field. However, when the entire surface of each gate bus line 155 is covered with the common electrode 172 as described above, the degree of freedom in designing the pattern and layout of each component of the liquid crystal display device is narrow, and therefore it is difficult to improve the aperture ratio. There's a problem.

  As another method for preventing such light leakage, there is a method in which a light blocking region of the black matrix layer 181 is arranged wider in a region on the counter substrate overlapping the gate bus line 155. However, in this case, it is necessary to allow the light-shielding region to have a sufficient size in consideration of the margin of misalignment that occurs when the active matrix substrate and the counter substrate (color filter substrate) are overlaid. Also in this case, it is difficult to realize a high aperture ratio.

  As disclosed in Patent Document 3 and Patent Document 4, when the light shielding region is formed by overlapping the color layers having different color filters instead of the black matrix layer 181, the step of forming the black matrix layer 181 is omitted. By doing so, the cost can be reduced. However, also in this case, it is necessary to provide a sufficiently large light-shielding region on the counter substrate in consideration of the margin of displacement between the active matrix substrate and the counter substrate, so that it is difficult to realize a high aperture ratio. . In addition, there is a problem that a large level difference caused by overlapping different color layers affects the alignment of liquid crystal molecules, and the time required for the liquid crystal injection process becomes long.

  The present invention has been made in consideration of such points, and the object of the present invention is to increase the degree of design freedom as compared with the conventional configuration shown in FIGS. It is an object of the present invention to provide a horizontal electric field type liquid crystal display device which can easily improve the aperture ratio.

  Another object of the present invention is to provide a horizontal electric field type liquid crystal display device which can achieve higher luminance or lower power consumption than the conventional configuration shown in FIGS.

  Other objects of the present invention which are not specified here will be apparent from the following description and the accompanying drawings.

(1) The horizontal electric field type liquid crystal display device of the present invention is
A first substrate and a second substrate disposed to face each other at a substantially constant interval;
A liquid crystal layer disposed between the first substrate and the second substrate;
A plurality of drain bus lines formed on the first substrate;
A plurality of gate bus lines formed on the first substrate so as to intersect the drain bus lines;
A plurality of pixel regions formed in a matrix by the drain bus lines and the gate bus lines;
A plurality of first liquid crystal driving electrodes and at least one second liquid crystal driving electrode formed on the first substrate;
A plurality of thin film transistors formed for each of the pixel regions on the first substrate;
A plurality of storage capacitor electrodes formed for each of the pixel regions on the first substrate;
By applying a liquid crystal driving electric field to the liquid crystal layer using the first liquid crystal driving electrode and the second liquid crystal driving electrode, the orientation direction of liquid crystal molecules in the liquid crystal layer is changed for each pixel region by the first substrate and A horizontal electric field type liquid crystal display device for performing display by rotating in a plane substantially parallel to the second substrate,
The first liquid crystal driving electrode covers the entire surface of each of the drain bus lines, and covers the gate bus line corresponding to each of the pixel regions except for a predetermined region in a portion not overlapping with the thin film transistor. And
The predetermined region of the gate bus line corresponding to each of the pixel regions is covered with the storage capacitor electrode of another pixel region adjacent to the gate bus line.

  (2) In the horizontal electric field type liquid crystal display device of the present invention, the first liquid crystal driving electrode (corresponding to the common electrode) covers the entire surface of each of the drain bus lines, and is provided in each of the pixel regions. The corresponding gate bus line is covered except for a predetermined region in a portion not overlapping with the thin film transistor. The predetermined region of the gate bus line corresponding to each of the pixel regions (a region not covered with the first liquid crystal driving electrode in a portion not overlapping with the thin film transistor) is adjacent to the gate bus line. The pixel region is covered with the storage capacitor electrode. Therefore, similarly to the conventional configuration shown in FIGS. 12 to 18, the electric field generated in the vicinity of the gate bus line can be effectively shielded by the first liquid crystal driving electrode.

  As a result, as in the conventional configuration shown in FIGS. 12 to 18, the shape of the first liquid crystal driving electrode is limited to a shape covering the entire surface of the gate bus line (except for the portion overlapping the thin film transistor). There is no need to do this, and a part of the gate bus line may not be covered with the first liquid crystal driving electrode. Accordingly, in the conventional configuration shown in FIGS. 12 to 18, since there is no restriction that the entire surface of the gate bus line is covered with the first liquid crystal driving electrode in a portion not overlapping with the thin film transistor, the degree of freedom in design is improved.

  In addition, because the above-described restrictions are eliminated, the position of the contact hole and the position of the end of the second liquid crystal drive electrode (corresponding to the pixel electrode) can be sequentially moved to the peripheral side of the pixel region. A higher aperture ratio than the conventional configuration shown in FIGS. 12 to 18 can be easily realized.

  If the amount of light emitted from the backlight is not changed by improving the aperture ratio, the brightness can be increased as compared with the conventional configuration shown in FIGS. 12 to 18, and if the brightness is not changed, compared with the conventional configuration. And lower power consumption.

  Furthermore, by appropriately adjusting the shape and position of the storage capacitor electrode, a desired storage capacitor can be easily secured without decreasing the aperture ratio or improving the aperture ratio.

  (3) In a preferred example of the liquid crystal display device of the present invention, the gate bus line corresponding to each of the pixel regions is disposed below the storage capacitor electrode covering the predetermined region, and the first liquid crystal A drive electrode is disposed in an upper layer than the storage capacitor electrode covering the predetermined region, and the storage capacitor electrode is overlapped so as to get over one side edge of the gate bus line. Electrodes are stacked over the other side edge of the gate bus line.

  In this example, it is preferable that the first liquid crystal driving electrode is partially overlapped with the storage capacitor electrode. Further, it is preferable that the first liquid crystal driving electrode does not get over the one side edge of the gate bus line.

  In another preferred example of the liquid crystal display device of the present invention, the first liquid crystal drive electrode has a plurality of openings formed so as to expose each channel region of the thin film transistor.

  In this example, the width of the edge formed in the first liquid crystal driving electrode by the opening is preferably made smaller than the width of the gate bus line.

  In still another preferred example of the liquid crystal display device of the present invention, a light-shielding region having an isolated pattern is formed corresponding to each of the pixel regions at a position facing the channel region of the thin film transistor on the second substrate. .

  In this example, it is preferable that the light-shielding region is formed by overlapping a plurality of color layers constituting a color filter. Further, the OD value of the light shielding region is set to 1.5 or more and 3.0 or less.

  According to the horizontal electric field type liquid crystal display device of the present invention, (a) the degree of freedom of design can be increased and the aperture ratio can be easily improved as compared with the conventional configuration shown in FIGS. (B) The effect that higher luminance or lower power consumption can be obtained as compared with the conventional configuration shown in FIGS.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings.

(First embodiment)
1 to 7 show the configuration of a horizontal electric field type liquid crystal display device according to a first embodiment of the present invention.

  FIG. 1 is a plan view showing a configuration of an active matrix substrate (TFT substrate) of a liquid crystal display device according to a first embodiment of the present invention, FIG. 2 is a plan view showing a structure of three layers constituting the substrate, and FIG. Is a partially enlarged plan view showing a detailed configuration around the gate bus line of the substrate, FIG. 4 is a partial cross-sectional view taken along line DD ′ of FIG. 3, and FIGS. 5 (a) and 5 (b) are FIG. It is a fragmentary sectional view along the EE 'line and FF' line. 6 is a plan view in which the pixel electrode 71 and the common electrode 72 are omitted in FIG. 1 to make their lower structures easy to understand. FIG. 7 is a plan view of the pixel electrode 71, the common electrode 72, and the black matrix layer 81 in FIG. FIG. 6 is a plan view in which the contact holes 61 and 62 are omitted and the lower structures thereof are easily understood. In the active matrix liquid crystal display device, the configuration of a plurality of pixels is the same, and therefore the configuration for one pixel is shown in FIGS.

6 and 7, the storage capacitor electrode 73 is depicted as translucent in order to facilitate understanding of the positional relationship among the common bus line 52, the gate bus line 55, the storage capacitor electrode 73, and the common electrode 72. The liquid crystal display device of the first embodiment is formed by joining and integrating an active matrix substrate and a counter substrate with a liquid crystal layer 20 in between, as shown in FIGS. Yes.

  As shown in FIG. 2, the active matrix substrate includes a transparent glass substrate 11, a plurality of common bus lines 52, a plurality of gate bus lines 55, a plurality of pieces formed on the inner surface of the glass substrate 11. A drain bus line 56, a plurality of thin film transistors 45, a plurality of pixel auxiliary electrodes 70, a plurality of pixel electrodes 71, a common electrode 72, and a plurality of storage capacitor electrodes 73 are provided. The common bus line 52 and the gate bus line 55 are directly formed on the inner surface of the glass substrate 11, and they are covered with a gate insulating film 57 except for the portion of the contact hole 62. The drain electrode 44, the source electrode 42, the semiconductor layer 43, the pixel auxiliary electrode 70, the storage capacitor electrode 73, and the drain bus line 56 of the thin film transistor 45 are formed on the gate insulating film 57. Therefore, the common bus line 52 and the gate bus line 55 are electrically insulated from the drain electrode 44, the source electrode 42, the semiconductor layer 43, the pixel auxiliary electrode 70, the storage capacitor electrode 73, and the drain bus line 56 by the gate insulating film 57. Has been. These structures formed on the glass substrate 11 are covered with a protective insulating film 59 except for the contact holes 61 and 62.

  The pixel electrode 71 and the common electrode 72 are formed on the protective insulating film 59. The pixel electrode 71 is electrically connected to the storage capacitor electrode 73 directly thereunder through a contact hole 61 (which penetrates the protective insulating film 59) in the pixel region, and further, the source is connected through the pixel auxiliary electrode 70. The electrode 42 is electrically connected. In the pixel region, the common electrode 72 is electrically connected to the common bus line 52 immediately below it through a contact hole 62 (which penetrates the protective insulating film 59 and the gate insulating film 57). The pixel electrode 71 and the common electrode 72 are both formed by patterning a transparent conductive metal film such as ITO.

  The surface of the active matrix substrate having the above configuration (the surface on which the pixel electrode 71 and the common electrode 72 are formed) is covered with an alignment film 31 made of an organic polymer film. The surface of the alignment film 31 is subjected to an alignment process for directing the initial direction of the liquid crystal molecules in the liquid crystal layer 20 in a desired direction.

  On the other hand, the counter substrate (color filter substrate) includes a transparent glass substrate 12 and red (R) / green (G) / blue (corresponding to each pixel region formed on the inner surface of the glass substrate 12. B) a color filter composed of the three color layers 82R, 82G and 82B, and a black matrix layer 81 for light shielding. The three color layers 82R, 82G, and 82B are collectively referred to as a color layer 82.

  The color layer 82 (color filter) and the black matrix layer 81 are covered with an acrylic overcoat layer 85. On the inner surface of the overcoat layer 85, columnar spacers (not shown) for controlling the distance between the active matrix substrate and the counter substrate are formed. The inner surface of the overcoat layer 85 is covered with an alignment film 32 made of an organic polymer film. The surface of the alignment film 32 is subjected to an alignment treatment for directing the initial direction of the liquid crystal molecules in the liquid crystal layer 20 in a desired direction.

  The active matrix substrate and the counter substrate having the above-described configuration are opposed to each other with the surfaces on which the alignment film 31 and the alignment film 32 are formed facing each other, and are overlapped at a predetermined interval. A liquid crystal layer 20 is introduced into the gap between the two substrates, and the periphery of both substrates is sealed with a sealing material (not shown) in order to confine the liquid crystal material present in the liquid crystal layer 20. A pair of polarizing plates (not shown) are arranged on the outer surfaces of both substrates.

  Next, the configuration of the active matrix substrate will be described in more detail with reference to FIGS.

  A plurality of gate bus lines 55 extending in parallel at equal intervals in the horizontal (left and right) direction of FIG. 1 and a plurality of drain bus lines 56 extending in parallel in the vertical (vertical) direction of FIG. Each of the rectangular areas surrounded by a pixel area is a pixel area, and a plurality of pixel areas (pixels) are arranged in a matrix as a whole. The thin film transistor 45 is disposed in the vicinity of one of the intersections (the lower left intersection in FIG. 1) of the two gate bus lines 55 and the two drain bus lines 56 that define each pixel region. Similar to the gate bus line 55, the common bus line 52 extends in parallel to the gate bus line 55 in the horizontal direction of FIG. Each of the common bus lines 52 is disposed in the pixel region on the opposite side (upper end portion in FIG. 1) from the thin film transistor 45, and from the thin film transistor 45 of the two gate bus lines 55 defining the pixel region. It is located in the vicinity of a distant one (in FIG. 1, the upper gate bus line 55). Accordingly, each of the common bus lines 52 is disposed with a gap in the vicinity of the thin film transistor 45 in the preceding pixel region adjacent to the upper side along the extending direction (vertical direction) of the drain bus line 56. I can say that.

  The storage capacitor electrode 73 is disposed on the opposite side (upper end in FIG. 1) from the thin film transistor 45 in the pixel region, and is located farther from the thin film transistor 45 in the two gate bus lines 55 that define the pixel region. (In FIG. 1, the upper gate bus line 55). The storage capacitor electrode 73 is formed so as to overlap with the common bus line 52 directly below it via the gate insulating film 57. A storage capacitor is formed by the storage capacitor electrode 73, the common bus line 52 immediately below the storage capacitor electrode 73, and the gate insulating film 57 between the two.

  The above configuration is the same as that of the conventional liquid crystal display device shown in FIGS.

  A part of the storage capacitor electrode 73 (upper end in FIG. 1) is a front stage adjacent to the upper side along the extending direction of the drain bus line 56 as compared with the conventional liquid crystal display device shown in FIGS. As shown in FIGS. 3, 6, and 7, the adjacent gate bus lines 55, that is, two gate buses that define the pixel region are projected to the pixel region side (upward in FIGS. 1 and 2). The line 55 is overlapped with the one located farther from the thin film transistor 45 (the gate bus line 55 at the upper level in FIG. 1) via the gate insulating film 57 to form a gate storage structure. That is, the storage capacitor electrode 73 constitutes one storage capacitor by overlapping with the common bus line 52 directly below (this is the same as the case of the above-described conventional liquid crystal display device), but also adjacent gates. By partially overlapping the bus line 55, another storage capacity (gate storage) is formed. Here, the storage capacitor electrode 73 has a substantially rectangular pattern (see FIG. 2B).

  As described later, the protruding portion of the storage capacitor electrode 73 is a predetermined region that does not overlap the common electrode 72 of the adjacent gate bus line 55 in a portion that does not overlap the thin film transistor 45 (in other words, in the vicinity of the contact hole 61). (Notch portion of the common electrode 72). That is, as shown in FIGS. 3 and 7, the gate bus line 55 adjacent to the storage capacitor electrode 73 is not adjacent to the contact hole 61 and does not overlap the common electrode 72 (not covered by the common electrode 72). And the portion overlaps the storage capacitor electrode 73. That is, the predetermined region that does not overlap with the thin film transistor 45 and does not overlap with the common electrode 72 of the gate bus line 55 is covered with the storage capacitor electrode 73 instead of the common electrode 72. Therefore, the electric field generated from the periphery of the gate bus line 55 can be shielded as in the conventional liquid crystal display device in which the entire surface of the gate bus line 55 overlaps the common electrode 72. With this configuration, the position of the contact hole 61 is shifted to a position close to the periphery of the pixel region as shown in FIG. 3 while designing, while shielding the electric field generated from the periphery of the gate bus line 55. Therefore, it is easy to improve the aperture ratio.

  The pixel auxiliary electrode 70 is formed on the same layer (on the gate insulating film 57) as the drain bus line 56, and is arranged at the base end portion and the center of the pixel electrode 171 in the conventional liquid crystal display device shown in FIGS. This corresponds to the one in which only the comb-like portion 171a is left. The base end portion of the pixel auxiliary electrode 70 is electrically and mechanically connected to the source electrode 42 of the thin film transistor 45, and the distal end portion thereof is electrically and mechanically connected to the storage capacitor electrode 73 (FIG. 2B). )).

  The drain electrode 44, the source electrode 42, and the semiconductor layer 43 of the thin film transistor 45 are respectively formed on the gate insulating film 57 in the pattern (shape) shown in FIG. The gate electrode (not shown) of the thin film transistor 45 is formed integrally with the gate bus line 55 (in other words, the gate electrode is a part of the gate bus line 55), and the drain electrode 44 and the source electrode 42 are formed. Between the semiconductor layer 43 and the semiconductor layer 43. As the semiconductor layer 43, an amorphous silicon film is used.

  The pixel electrode 71 and the common electrode 72 that generate the liquid crystal driving electric field have a pattern (shape) as shown in FIG. 2C, and mesh with each other in the form shown in FIG. Comb-like portions (thin strip portions protruding into the pixel region) 71a and 72a. Here, the comb-like portions 71a of the pixel electrode 71 are three, and the comb-like portions 72a of the common electrode 72 are two.

  One pixel electrode 71 is provided for each pixel region. The common electrode 72 is used in common for all the pixel regions, but two comb-like portions 72a are provided for each pixel region.

  The pixel electrode 71 is a base end portion (on the side opposite to the source electrode 42) of the three comb-like portions 71 a and is connected to the storage capacitor electrode 73 directly below through the contact hole 61 that penetrates the protective insulating film 59. Electrically connected. Since the storage capacitor electrode 73 is electrically connected to the source electrode 42 of the thin film transistor 45 through the pixel auxiliary electrode 70, the pixel electrode 71 is connected to the source electrode 42 through the storage capacitor electrode 73 and the pixel auxiliary electrode 70. It will be electrically connected.

  The common electrode 72 is electrically connected to the common bus line 52 directly below through a contact hole 62 that penetrates the gate insulating film 57 and the protective insulating film 59 in the pixel region.

  In the common electrode 72, a rectangular opening (window) 72b is formed at a position overlapping the channel region of the thin film transistor 45. For this reason, the entire channel region is exposed from the opening 72 b and does not overlap the common electrode 72. This is to avoid a change in characteristics of the thin film transistor 45 due to the back gate effect. The width of the edge formed in the common electrode 72 by the opening 72 b is smaller than the width of the gate bus line 55.

  As described above, the common electrode 72 covers the entire surface of each drain bus line 56 extending in the vertical direction in FIGS. 1 and 3, and includes an opening 72 b and a notch in the vicinity of the contact hole 61. The gate bus lines 55 extending in the horizontal direction in FIG. In order to form this notch, the edge 72c of the common electrode 72 on the side of the storage capacitor electrode 73 (which extends along the gate bus line 55) is stepped. This notch is covered with a storage capacitor electrode 73. Similarly to the conventional liquid crystal display device shown in FIGS. 12 to 18, the common electrode 72 is disposed not only in the region immediately above the gate bus line 55 but also adjacent to the gate bus line 55. Between the common bus line 52 (which is in the pixel region of the lower stage adjacent to the lower side along the extending direction (vertical direction) of the drain bus line 56), the gate bus line 55 and the source electrode 42. And the gap between the gate bus line 55 and the storage capacitor electrode 73, and the vicinity of the edge of the source electrode 42 and the vicinity of the edge of the storage capacitor electrode 73. Yes. For this reason, the electric field generated in the vicinity of the gate bus line 55 is shielded by the storage capacitor electrode 73 at a portion covered by the storage capacitor electrode 73 and shielded by the common electrode 72 at a portion not covered by the storage capacitor electrode 73. Is done. A fringe electric field generated between the edge of the storage capacitor electrode 73 and the gate bus line 55 is shielded by the common electrode 72.

  The gate bus line 55 is disposed in a lower layer (a layer closer to the substrate 11) than the storage capacitor electrode 73, and the common electrode 72 is disposed in an upper layer (a layer farther from the substrate 11) than the storage capacitor electrode 73. . Further, as shown in FIG. 7, the storage capacitor electrode 73 is overlapped with the gate bus line 55 so as to get over one side edge 55b of the gate bus line 55 from the lower side to the upper side in FIG. However, the storage capacitor electrode 73 does not get over the side edge 55 a of the gate bus line 55. The common electrode 72 is overlapped with the gate bus line 55 so as to get over the other side edge 55a of the gate bus line 55 from the upper side to the lower side of FIG. The common electrode 72 partially overlaps the storage capacitor electrode 73.

  1 and 3, reference numeral 81 denotes a black matrix layer formed on the counter substrate. The black matrix layer 81 has a rectangular light shielding region indicated by a broken line in FIGS. 1 and 3 for each pixel region. The light shielding region is not formed in a continuous shape such as a band shape or a mesh shape, but is large enough to cover the entire thin film transistor 45 and is formed in a rectangular island shape directly above the thin film transistor 45. Yes. As described above, the area occupied by the light shielding region of the black matrix layer 81 is suppressed to the minimum necessary for preventing the light from entering the thin film transistor 45. The reason for preventing light from entering the thin film transistor 45 (channel region thereof) by this light shielding region is to prevent the function of the thin film transistor 45 from being disturbed by the incident light.

  As described above, in the horizontal electric field type liquid crystal display device of the first embodiment, as shown in FIGS. 3 and 7, the common electrode 72 is not only in the opening 72b but also in the vicinity of the contact hole 61. The gate bus line 55 is not covered with the common electrode 72 in the notch. Therefore, unlike the conventional liquid crystal display device shown in FIGS. 12 to 18, the common electrode 72 does not have a shape covering the entire surface of each gate bus line 55 (except for the opening 72b). However, the portion not covered with the common electrode 72 of the gate bus line 55 in the vicinity of the contact hole 61 (the portion overlapping the notch portion of the common electrode 72) is covered with the storage capacitor electrode 73 under the common electrode 72. It has been broken. Therefore, as in the conventional liquid crystal display device, the electric field generated around the gate bus line 55 is effectively shielded by the cooperative action of the storage capacitor electrode 73 and the common electrode 72. As a result, even if the common electrode 72 is provided with a notch in the vicinity of the contact hole 61, no light leaks in the vicinity of the contact hole 61.

  Further, in the conventional liquid crystal display device, since the electric field generated around the gate bus line 155 is shielded only by the common electrode 172 in the upper layer, the shape of the common electrode 172 is limited, and the degree of freedom in design is limited. It had been. On the other hand, in the liquid crystal display device of the first embodiment, a part of the storage capacitor electrode 73 is overlapped with the gate bus line 55 via the gate insulating film 57, so that the shape of the common electrode 72 is the gate bus line 55. The shape is not limited to a shape that covers the entire surface (except for the opening 72b), but may be a shape that does not cover a part of the gate bus line 55 if necessary. A portion of the gate bus line 55 that is not covered with the common electrode 72 may be covered with the storage capacitor electrode 73. Thus, by using the storage capacitor electrode 73 for both electric field shielding and light shielding, it is not necessary to cover the entire surface of the gate bus line 55 excluding the opening 72b with the common electrode 72 as in the conventional liquid crystal display device. , Design flexibility is improved.

  Further, since it is not necessary to cover the entire surface of the gate bus line 55 excluding the opening 72b with the common electrode 72, the position of the contact hole 61 and the position of the end of the pixel electrode 71 are sequentially moved to the peripheral side of the pixel region. Therefore, a high aperture ratio can be easily realized as compared with the conventional liquid crystal display device.

  And by improving the aperture ratio, if the amount of light emitted from the backlight is not changed, it is possible to easily increase the brightness compared to the conventional liquid crystal display device, and if the brightness is not changed, the power consumption is easily reduced. Is possible.

  Furthermore, by appropriately adjusting the shape and position of the storage capacitor electrode 73, a desired storage capacitor can be easily secured without reducing the aperture ratio or improving the aperture ratio.

  Next, a supplementary description will be given of the rectangular opening 72b formed in the common electrode 72 for each pixel region.

  As described above, the opening 72 b of the common electrode 72 is formed so that the entire channel region of the thin film transistor 45 (the region between the source electrode 42 and the drain electrode 44 of the semiconductor layer 43) is exposed from the common electrode 72. At the same time, the entire edge of the common electrode 72 (rectangular edge along the outline of the opening 72b) formed on the gate bus line 55 by the opening 72b is formed by the gate electrode of the thin film transistor 45. It is formed so as to overlap with the gate bus line 55 in the formed portion. In other words, the width of the edge of the common electrode 72 (the length along the drain bus line 56) generated at the periphery of the opening 72b is sufficiently larger than the width of the gate bus line 55 (the width of the gate electrode) at that location. It is formed to be smaller. Thus, not only can the characteristic change of the thin film transistor 45 due to the back gate effect of the thin film transistor 45 be avoided, but also the liquid crystal molecules in the vicinity change the orientation direction due to the fringe electric field generated at the edge of the common electrode 72 generated at the periphery of the opening 72b. Even if this is done, incident light from the backlight side is blocked by the gate bus line 55 made of an opaque metal so that no light leaks around the edge.

  Therefore, as shown in the first embodiment, it is only necessary to form a minimum light-shielding region for preventing light from the outside (counter substrate side) from entering the thin film transistor 45 on the counter substrate side. Further, not only the size of the light shielding area but also the OD (Optical Density) value of the light shielding area, as in the conventional case, for example, an OD value of 4.0 or more, or 3.5 or more. A high value for the purpose of blocking incident light from the light side is not required, and it is possible to set OD value = 3.0 or less, and further OD value = about 2.0. As a result, the demand for the black matrix layer 81 is eased, and there is an advantage that the room for material selection is widened, or the thickness of the black matrix layer 81 can be reduced. However, in order to prevent external light from entering the channel region of the thin film transistor 45 and hindering the function of the thin film transistor 45, it is desirable that the OD value = 1.5 or more.

  The width of the edge of the common electrode 72 generated at the periphery of the opening 72b is not considered in the conventional liquid crystal display device.

  Further, in place of the configuration of the first embodiment, as shown in the second embodiment described below, the OD value formed by overlapping each color layer of the color filter without using a general black matrix material. It is also possible to use a low light shielding layer. Also in this case, it is desirable that the OD value is 1.5 or more, and it is particularly desirable that light on the short wavelength side such as blue is blocked as much as possible. Therefore, when the light shielding layer is formed by overlapping the color layers of the color filter, it is preferable to dispose at least the color layer for the red pixel in a region facing the channel region of the thin film transistor 45.

  The liquid crystal display device of the first embodiment having the above configuration can be manufactured, for example, as follows.

  The active matrix substrate is manufactured as follows. First, by forming, for example, a Cr film on one surface of the glass substrate 11 and patterning it, a common bus line 52 and a gate bus line 55 having a shape as shown in FIG. The Thereafter, a gate insulating film 57 made of, for example, SiNx is formed over the entire surface of the glass substrate 11 so as to cover the common bus line 52 and the gate bus line 55. Subsequently, the semiconductor layer 43 (usually an amorphous silicon layer) of the thin film transistor 45 is formed in an island pattern on the gate insulating film 57 so as to overlap the corresponding gate bus line 55 through the gate insulating film 57. The Further, a drain film line 56, a drain electrode 44, a source electrode 42, a storage capacitor electrode 73 and a pixel auxiliary electrode 70 are simultaneously formed by forming, for example, a Cr film on the gate insulating film 57 and then patterning it. Is done. Thereafter, a protective insulating film 59 made of, for example, SiNx is formed on the gate insulating film 57 so as to cover these structures. Subsequently, a rectangular contact hole 61 penetrating the protective insulating film 59 and a rectangular contact hole 62 penetrating the gate insulating film 57 and the protective insulating film 59 are formed. A pixel electrode 71 and a common electrode 72 are formed on the protective insulating film 59 by forming an ITO film, which is a transparent electrode material, on the protective insulating film 59 and then patterning the ITO film. The pixel electrode 71 is electrically connected to the source electrode 42 through the contact hole 61. The common electrode 72 is electrically connected to the common bus line 52 through the contact hole 62. Thus, an active matrix substrate is manufactured.

  The counter substrate (color filter substrate) is manufactured as follows. First, an R, G, B color layer 82 for color filters and a black matrix layer 81 for light shielding are formed on one surface of the glass substrate 12, and then the color layer is formed over the entire surface of the glass substrate 12. An overcoat layer 85 is formed so as to cover 82 and the black matrix layer 81. Then, columnar spacers (not shown) are formed on the overcoat layer 85. Thus, the counter substrate is manufactured.

  Alignment films 31 and 32 made of polyimide are formed on the surfaces of the active matrix substrate and the counter substrate manufactured as described above, respectively. Thereafter, the surfaces of the alignment films 31 and 32 are uniformly processed. Subsequently, the two substrates are overlapped with each other at a constant interval, and then the peripheral edges of both substrates are sealed with a sealing material except for the liquid crystal injection hole. Then, after a predetermined liquid crystal material is injected into the gap between the two substrates from the liquid crystal injection hole in the vacuum chamber, the liquid crystal injection hole is closed. After the two substrates are joined and integrated in this way, a polarizing plate (not shown) is bonded to the outer surface of both substrates, whereby the liquid crystal display device of the first embodiment shown in FIGS. 1 to 7 is completed. .

  As described above, according to the horizontal electric field type liquid crystal display device of the first embodiment, the degree of freedom of design can be widened and the aperture ratio can be increased as compared with the conventional configuration shown in FIGS. It is easy to improve. In addition, by improving the aperture ratio, higher luminance than before can be achieved when the amount of light emitted from the backlight is not changed, and lower power consumption than before can be achieved when luminance is not changed.

(Second Embodiment)
FIG. 8 shows the configuration of a horizontal electric field type liquid crystal display device according to the second embodiment of the present invention.

  FIG. 8 is a partial cross-sectional view along the line E-E ′ similar to FIG. 5B, showing the configuration of the counter substrate (color filter substrate) of the liquid crystal display device according to the second embodiment of the present invention.

  The configuration of the second embodiment is the same as the configuration of the first embodiment described above except that the light shielding portion is formed by overlapping a plurality of color layers of the color filter instead of forming the black matrix layer 81. .

  As shown in FIG. 8, another region is formed by overlapping the red layer 82R and the green layer 82G in a predetermined region that overlaps the thin film transistor 45 of the counter substrate, that is, a portion that should be a light shielding region of the black matrix layer 81 in FIG. A rectangular light shielding region (light shielding layer) having a light shielding property higher than that is formed. This light shielding region may be not only a combination of the red layer 82R and the green layer 82G but also a combination of other colors. For example, a combination of the red layer 82R and the blue layer 82B or a combination of the green layer 82G and the blue layer 82B may be used. A combination of the three color layers of the red layer 82R, the green layer 82G, and the blue layer 82B may be used.

  Such a light shielding region can be easily formed by using a known method as disclosed in Patent Document 3 or 4, for example.

  According to the test by the inventor, in the light-shielding region in which the three color layers of the red layer 82R, the green layer 82G, and the blue layer 82B are combined, the OD value is, for example, a color that can display a chromaticity region of NTSC ratio 40% In the case of the specification, it was about 1.9, and in the case of the color specification capable of displaying a chromaticity range of 60% NTSC, it was about 2.3. In any case, no light leakage occurred around the gate bus line 55 and the thin film transistor 45. As for the influence of incident light from the external environment, no troubles such as an abnormal operation of the thin film transistor 45 were confirmed even in a severe environment where the illuminance on the display surface was about 100,000 lux.

  As described above, the liquid crystal display device according to the second embodiment of the present invention has the same configuration as the liquid crystal display device according to the first embodiment except for the configuration of the light shielding region on the counter substrate. It is clear that the same effect as the liquid crystal display device according to the first embodiment can be obtained.

  In addition, since the liquid crystal display device according to the second embodiment of the present invention has a structure without a black matrix (BM-less structure), a synergistic effect can be obtained. That is, the formation process of the black matrix layer 81 can be omitted without significantly degrading display quality such as display contrast and crosstalk characteristics, and the cost can be reduced. This is because, in the case of the BM-less structure, if the alignment state of the liquid crystal molecules is affected by the leakage electric field from the peripheral portion of the gate bus line 55 and the thin film transistor 45, as a result, the light leakage in the peripheral portion causes contrast. However, in the case of the configuration of the second embodiment, light leakage due to a leakage electric field from the peripheral portion of the gate bus line 55 and the thin film transistor 45 is caused. Since it can be surely avoided, even if the BM-less structure is adopted, the cost can be reduced without degrading the display quality.

  Further, since the light-shielding region formed by overlapping a plurality of color layers may be provided with a minimum size in a region corresponding to the channel region of the thin film transistor 45, a large wide step is not formed. For this reason, it is possible to avoid the problem that the light shielding region affects the liquid crystal alignment or the process time for liquid crystal injection becomes long. In this way, it is possible to simultaneously achieve a high aperture ratio and a low cost.

(Modification)
The first and second embodiments described above show examples embodying the present invention. Therefore, the present invention is not limited to these embodiments, and it goes without saying that various modifications can be made without departing from the spirit of the present invention.

  For example, the shape (pattern) of the storage capacitor electrode 73 can be arbitrarily changed according to the shape (pattern) of the portion that does not overlap the common electrode 72 of the gate bus line 55. In addition, the common electrode 72 covers the entire surface of each of the plurality of drain bus lines 56, and the gate bus line 55 corresponding to each of the plurality of pixel regions is removed from the thin film transistor 45 except for the predetermined region. Other than that the predetermined region of the gate bus line 55 corresponding to each of the plurality of pixel regions is covered with the storage capacitor electrode 73 of another pixel region adjacent to the gate bus line 55. As for, the configuration of the liquid crystal display device is arbitrary.

1 is a plan view showing a configuration of an active matrix substrate of a horizontal electric field type liquid crystal display device according to a first embodiment of the present invention. FIG. 2 is a plan view showing a three-layer structure constituting an active matrix substrate of the horizontal electric field type liquid crystal display device according to the first embodiment of the present invention. 1 is a partially enlarged plan view showing a detailed configuration around a gate bus line of an active matrix substrate of a horizontal electric field type liquid crystal display device according to a first embodiment of the present invention; FIG. 4 is a partial cross-sectional view of the liquid crystal display device taken along line D-D ′ in FIG. 3. (A) And (b) is a fragmentary sectional view of the said liquid crystal display device along the E-E 'line and F-F' line of FIG. 3, respectively. FIG. 2 is a plan view in which a pixel electrode 71 and a common electrode 72 are omitted in FIG. 1 and their lower structures are easily understood. FIG. 4 is a plan view in which a pixel electrode 71, a common electrode 72, a black matrix layer 81, and contact holes 61 and 62 in FIG. FIG. 6 is a partial cross-sectional view along the line E-E ′ similar to FIG. 5B, showing the configuration of a horizontal electric field type liquid crystal display device according to a second embodiment of the present invention. It is a top view which shows the structure of the active matrix substrate of the conventional liquid crystal display device of a horizontal electric field system. It is a top view which shows the structure of the three layers which comprise the active matrix substrate of the conventional liquid crystal display device of a horizontal electric field system. FIG. 6 is a partially enlarged plan view showing a detailed configuration around a gate bus line of an active matrix substrate of a conventional horizontal electric field type liquid crystal display device. FIG. 10 is a plan view showing a configuration of an active matrix substrate when a pixel electrode 171 for generating a liquid crystal driving electric field is formed of the same transparent conductive metal as a common electrode 172 in the conventional lateral electric field type liquid crystal display device of FIG. . FIG. 13 is a plan view showing a three-layer structure constituting an active matrix substrate of the conventional horizontal electric field type liquid crystal display device of FIG. FIG. 13 is a partially enlarged plan view showing a detailed configuration around a gate bus line of an active matrix substrate of the conventional horizontal electric field type liquid crystal display device of FIG. FIG. 15 is a partial cross-sectional view of the liquid crystal display device taken along line A-A ′ of FIG. 14. (A) And (b) is a fragmentary sectional view of the said liquid crystal display device along the B-B 'line and C-C' line | wire of FIG. 14, respectively. FIG. 13 is a plan view in which a pixel electrode 171 and a common electrode 172 are omitted in FIG. 12 and their lower structures are easily understood. FIG. 13 is a plan view in which a pixel electrode 171, a common electrode 172, a black matrix layer 181, and contact holes 161 and 162 are omitted from FIG.

Explanation of symbols

11, 12 Glass substrate 20 Liquid crystal layer 31, 32 Alignment film 42 Source electrode 43 Semiconductor layer 44 Drain electrode 45 Thin film transistor 52 Common bus line 55 Gate bus lines 55a, 55b Side edge 56 of gate bus line 56 Drain bus line 57 Gate insulation film 59 Protective insulating films 61 and 62 Contact hole 71 Pixel electrode 71a Comb-like portion 72 of pixel electrode Common electrode 72a Comb-like portion 72b of common electrode 72c of common electrode Edge 73 of common electrode Storage capacitor electrode

Claims (9)

A first substrate and a second substrate disposed to face each other at a substantially constant interval;
A liquid crystal layer disposed between the first substrate and the second substrate;
A plurality of drain bus lines formed on the first substrate;
A plurality of gate bus lines formed on the first substrate so as to intersect the drain bus lines;
A plurality of pixel regions formed in a matrix by the drain bus lines and the gate bus lines;
A plurality of first liquid crystal drive electrodes and at least one second liquid crystal drive electrode formed on the first substrate;
A plurality of thin film transistors formed for each of the pixel regions on the first substrate;
A plurality of storage capacitor electrodes formed for each of the pixel regions on the first substrate;
By applying a liquid crystal driving electric field to the liquid crystal layer using the first liquid crystal driving electrode and the second liquid crystal driving electrode, the orientation direction of liquid crystal molecules in the liquid crystal layer is changed for each pixel region by the first substrate and A horizontal electric field type liquid crystal display device for performing display by rotating in a plane substantially parallel to the second substrate,
The first liquid crystal driving electrode covers the entire surface of each of the drain bus lines, and covers the gate bus line corresponding to each of the pixel regions except for a predetermined region in a portion not overlapping with the thin film transistor. And
The horizontal electric field type liquid crystal, wherein the predetermined region of the gate bus line corresponding to each of the pixel regions is covered with the storage capacitor electrode of another pixel region adjacent to the gate bus line Display device. The gate bus line corresponding to each of the pixel regions is disposed below the storage capacitor electrode covering the predetermined region, and the first liquid crystal driving electrode covers the predetermined region. It is arranged in the upper layer than
The storage capacitor electrode is overlaid so as to cross over one side edge of the gate bus line, and the first liquid crystal driving electrode is overlaid over the other side edge of the gate bus line. Item 2. A liquid crystal display device according to item 1.   The liquid crystal display device according to claim 1, wherein the first liquid crystal driving electrode is partially overlapped with the storage capacitor electrode.   The liquid crystal display device according to claim 3, wherein the first liquid crystal driving electrode does not get over the one side edge of the gate bus line.   5. The liquid crystal display device according to claim 1, wherein the first liquid crystal driving electrode has a plurality of openings formed so as to expose each channel region of the thin film transistor. 6.   The liquid crystal display device according to claim 5, wherein a width of an edge formed in the first liquid crystal driving electrode by the opening is smaller than a width of the gate bus line.   7. The light-shielding region having an isolated pattern is formed corresponding to each of the pixel regions at a position facing the channel region of the thin film transistor on the second substrate. Liquid crystal display device.   The liquid crystal display device according to claim 7, wherein the light shielding region is formed by overlapping a plurality of color layers constituting a color filter.   The liquid crystal display device according to claim 7, wherein an OD value of the light shielding region is 1.5 or more and 3.0 or less.

Images