JP2009192652A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display device for immediately responding to a request to increase density and definition and displaying an image with a stable operation. <P>SOLUTION: An image signal processing part 40 includes a nonvolatile memory 54 storing parameter data used for image signal processing, a master LSI 50 and slave LSI 51 capturing parameter data from the nonvolatile memory 54 and performing image signal processing in parallel using the parameter data. Each of the master LSI 50 and the slave LSI 51 calculates a checksum value of the captured parameter data. A control part 45 compares the checksum value stored in advance and the checksum value calculated in each of the master LSI 50 and the slave LSI 51, and determines an error in the captured data on the basis of the comparison results. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a plasma display device using a plasma display panel.

  In the field of image display devices that display images, flat display devices with a reduced thickness, such as plasma display devices and liquid crystal display devices, are common.

  For example, a plasma display panel (hereinafter abbreviated as “panel”) has a large number of pixels arranged in a plane, and a large number of discharge cells as pixels between a front plate and a back plate arranged opposite to each other. Is formed. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the rear plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of RGB colors are excited and emitted by the ultraviolet light to perform color display.

  In recent years, there has been an increasing demand for higher density and higher definition of pixels in a flat display device using such a panel. In order to advance such high density and high definition, it is required to reduce the above-described discharge cells and increase the number of discharge cells, that is, the number of pixels. The signal processing unit that generates a signal for driving the panel also requires signal processing accompanying an increase in the number of pixels. In general, such a signal processing unit is realized by a large-scale integrated circuit called an LSI. For this reason, it is conceivable to develop a new LSI corresponding to the increase in the number of pixels.

  On the other hand, in order to develop a new LSI whenever such a panel specification is changed, a development period is required and a huge cost is also required. For this reason, conventionally, an optimized display control device has been proposed in which the display control LSI and the amount of memory corresponding to the display control LSI are changed according to the specifications of the required display system (for example, see Patent Document 1). .

  Such a conventional display control apparatus includes a plurality of LSIs, one LSI is used as a master chip, and the other LSIs are used as slave chips, and the timing of the slave LSIs is synchronized with the operation timing of the master LSIs. The signal processing circuit according to is realized. That is, the conventional display control device can configure a processing circuit with a one-chip LSI when the required specification may be a normal image quality. A processing circuit corresponding to the image quality can be configured. As described above, since the conventional display control device can perform signal processing according to the required specifications with only one type of LSI, the development cost of the LSI can be reduced and the combination of the LSIs can be adapted to the required specifications. Quick response to the panel specifications is possible.

In addition, the LSI as described above is often used in combination with an external memory provided outside the LSI. At this time, for example, a transfer error may occur in data transfer between the LSI and the memory. For this reason, conventionally, as one method for preventing a transfer error, a method of calculating a checksum value of data to be transferred and detecting an error in data transfer has been proposed (for example, Patent Documents). 2).
Japanese Patent Laid-Open No. 9-244587 JP 2005-505827 A

  As described above, an LSI is often used in combination with an external memory. At this time, generally, fixed data such as parameters for signal processing is stored in a nonvolatile memory such as a flash memory. Further, changing data such as an image signal is temporarily stored as a buffer memory or the like in a volatile memory such as a RAM.

  Also, as in Patent Document 1, when performing signal processing on a plurality of LSIs in parallel, assuming that one common external memory is used as an external memory for temporarily storing data being processed, an arbitration function between the LSIs Inconveniences such as being unable to respond quickly to the required specifications may occur. For this reason, it is preferable that an external memory for temporarily storing data is provided for each LSI. On the other hand, as the external memory storing fixed data such as parameters, each LSI only needs to read data, so it is effective to reduce the number of parts by using a single common memory. is there.

  In other words, a buffer memory is provided for each LSI, and a memory for storing parameters common to each LSI is configured as one external memory, thereby increasing the density and definition of the display device. In addition to meeting requests quickly, the number of parts can be reduced.

  However, with such a configuration, when each LSI reads data from the common memory, if an error occurs during reading in at least one LSI, synchronization in the processing between the LSIs is disturbed, and in the processing of the entire signal processing unit. There were problems such as problems. That is, for example, when each LSI individually performs processing for an error, a time difference in processing occurs between the LSIs, which may cause image deterioration such as an image being shifted depending on a display area.

  The plasma display device of the present invention has been made in view of these problems, and can quickly respond to the demand for higher density and higher definition, and can perform image display with stable operation. The purpose is to provide.

  A plasma display device of the present invention includes a plasma display panel, an image signal processing unit that performs image signal processing on a supplied image signal and generates a signal for driving the plasma display panel, and an image signal processing unit. And a control unit for controlling the plasma display device, wherein the image signal processing unit fetches the parameter data from the nonvolatile memory and stores the parameter data for performing signal processing, and uses the parameter data A plurality of integrated circuits that perform image signal processing in parallel, each of the integrated circuits calculates a checksum value of the captured parameter data, and the control unit stores the checksum value stored in advance and the integrated circuit Are compared with the checksum value calculated for each of the It is configured to perform the error judgment in the data capture Te.

  With this configuration, signal processing is performed on a plurality of integrated circuits in parallel, so that it is possible to quickly respond to demands for higher density and higher definition. In addition, since a configuration including one nonvolatile memory may be used as a memory for storing parameter data commonly used by each integrated circuit, the number of memories can be reduced. In each integrated circuit, the checksum value is calculated in parameter data transfer, and the control unit performs error determination using the checksum value calculated in each integrated circuit. Even if a transfer error occurs in the LSI, for example, control such as parameter re-transfer to all the integrated circuits can be performed, thereby enabling image display with stable operation.

  The plasma display device of the present invention further includes a buffer memory provided for each integrated circuit, and each of the integrated circuits fetches parameter data from the nonvolatile memory in synchronization with each other, and the fetched parameter data is stored in the buffer memory. It is the structure to store.

  With this configuration, parameter data can be stored in a high-speed buffer memory, and signal processing can be speeded up.

  Moreover, the plasma display apparatus of this invention is a structure which a control part performs an error determination regularly at a predetermined period interval.

  With this configuration, it is possible to check whether or not the integrated circuit has been reset, and the effect of suppressing problems caused by parallel processing can be enhanced.

  ADVANTAGE OF THE INVENTION According to this invention, while being able to respond rapidly to the request | requirement of high density and high definition, the plasma display apparatus which can display an image by stable operation | movement can be provided.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing a main part of a panel according to an embodiment of the present invention. The panel 10 is configured such that a glass front substrate 21 and a rear substrate 31 are arranged to face each other and a discharge space is formed therebetween. On the front substrate 21, a plurality of scanning electrodes 22 and sustaining electrodes 23 constituting the display electrode pair 28 are formed in parallel with each other. A dielectric layer 24 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 25 is formed on the dielectric layer 24. A plurality of data electrodes 32 are formed on the rear substrate 31 in parallel. An insulating layer 33 is formed so as to cover the data electrode 32, and a grid-like partition wall 34 is provided on the insulating layer 33. A phosphor layer 35 is provided on the surface of the insulator layer 33 and the side surfaces of the partition walls 34. The front substrate 21 and the rear substrate 31 are arranged to face each other so that the scan electrode 22 and the sustain electrode 23 and the data electrode 32 intersect each other, and in the discharge space formed therebetween, for example, neon And a mixed gas of xenon. Note that the structure of the panel is not limited to the above-described structure, and for example, a structure having a stripe-shaped partition may be used.

  FIG. 2 is an electrode array diagram of panel 10 used in the embodiment of the present invention. N scanning electrodes 22 and n sustaining electrodes 23 are arranged in the row direction, and m data electrodes 32 are arranged in the column direction. A discharge cell is formed at a portion where a pair of scan electrode and sustain electrode intersects with one data electrode, and m × n discharge cells are formed in the discharge space. The area where the m × n discharge cells are formed is a screen area where an image is displayed.

  The panel 10 thus configured is driven based on the subfield method. The subfield method is a method of displaying an image by dividing one field period into a plurality of subfields and causing each discharge cell to emit light or not emit light in each subfield. Each subfield has an initialization period, a writing period, and a sustain period. In the initializing period, initializing discharge is performed in the discharge cells, and wall charges necessary for the subsequent writing operation are formed. In the writing period, a scanning pulse voltage is sequentially applied to the scanning electrode 22 and a writing pulse voltage corresponding to an image signal to be displayed is applied to the data electrode 32 so that the scanning electrode 22 and the data electrode 32 are selectively selected. Then, a write discharge is caused to selectively form wall charges. In the subsequent sustain period, a predetermined number of sustain pulse voltages corresponding to the display luminance to be emitted is applied between the scan electrode 22 and the sustain electrode 23 to selectively select the discharge cells in which wall charges are formed by the write discharge. Discharge to emit light. A relationship indicating in which subfield the discharge cell emits light with respect to the input image signal is abbreviated as “coding”.

  FIG. 3 is a circuit block diagram of the plasma display device according to the embodiment of the present invention. The plasma display device according to the present embodiment includes a panel 10, an image signal processing unit 40, a data electrode drive circuit 41, a scan electrode drive circuit 42, a sustain electrode drive circuit 43, a timing generation circuit 44, a control unit 45, and each circuit block. A power supply circuit (not shown) for supplying necessary power is provided.

  The timing generation circuit 44 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal, and supplies them to the respective circuit blocks. Scan electrode drive circuit 42 supplies a drive voltage waveform to each scan electrode 22 based on the timing signal, and sustain electrode drive circuit 43 supplies a drive voltage waveform to each sustain electrode 23 based on the timing signal.

  The image signal processing unit 40 converts the input image signal into drive data indicating light emission / non-light emission for each subfield. The input image signals are red, green, and blue RGB signals, and each of the RGB signals is an 8-bit digital signal. The data electrode drive circuit 41 converts the drive data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm. In addition, the control unit 45 includes, for example, a microcomputer and performs control in the plasma display apparatus and processing related to the entire apparatus.

  FIG. 4 is a circuit block diagram of the image signal processing unit 40 and the control unit 45 of the plasma display device according to the embodiment of the present invention. The image signal processing unit 40 includes a master LSI 50 and a slave LSI 51 that perform image signal processing in parallel, a buffer memory 52 that temporarily stores data for processing of the master LSI 50, and data for processing of the slave LSI 51 temporarily. A buffer memory 53 for storing data and a nonvolatile memory 54 for storing parameter data are provided. In addition, the control unit 45 includes a microcomputer 55. This plasma display apparatus is configured so that data can be transmitted and received between the microcomputer 55 and the master LSI 50 and slave LSI 51.

  The master LSI 50 and the slave LSI 51 are LSIs that are one of integrated circuits, and are the same LSI. In this embodiment, such a two-chip configuration can be applied to the panel 10 having a high pixel count. The master LSI 50 performs signal processing on the left screen area of the panel 10 (the left half area of the screen area), and the slave LSI 51 performs signal processing on the right screen area (the right half area of the screen area).

  The nonvolatile memory 54 is a flash memory which is a writable nonvolatile memory, for example. In the nonvolatile memory 54, parameter data required for image signal processing is written in advance. The parameter data includes drive parameters for a conversion table that converts an image signal into drive data based on coding. The buffer memory 52 and the buffer memory 53 are volatile memories such as a RAM that can be written and read at random.

  The master LSI 50 captures necessary parameter data from the nonvolatile memory 54 and performs image signal processing on the left screen area while temporarily storing the data being processed in the buffer memory 52. In parallel with the processing of the master LSI 50, the slave LSI 51 takes in the necessary parameter data from the nonvolatile memory 54, and temporarily stores the data being processed in the buffer memory 53, while the image signal for the right screen area is received. Process.

  FIG. 5 is a circuit block diagram showing an example of the internal configuration of the master LSI 50 of the plasma display device according to the present embodiment. FIG. 5 also shows an example in which the master LSI 50, the nonvolatile memory 54, and the buffer memory 52 are connected. Note that the slave LSI 51 also has the same internal configuration as the master LSI 50.

  In the master LSI 50, the input image signal is first supplied to the data selection unit 60. The data selection unit 60 is provided for distributing data when a plurality of chips are configured. That is, in the master LSI 50, only the image signal corresponding to the left screen area is selected by the data selection unit 60. The selected image signal is supplied to the gamma processing unit 61 and subjected to inverse gamma correction by the gamma processing unit 61. The image signal subjected to inverse gamma correction is supplied to the error diffusion unit 62. The error diffusion unit 62 performs a process of limiting the gradation in each pixel to a predetermined number of gradations and diffusing an error caused by this limitation to surrounding pixels. The error diffusion unit 62 holds the number of gradations in a pseudo manner by such processing. The signal output from the error diffusion unit 62 is supplied to the MPD processing unit 63. The MPD processing unit 63 performs a process of suppressing a moving image pseudo contour that appears while displaying a moving image by dithering or the like. The signal output from the MPD processing unit 63 is supplied to the subfield conversion processing unit 64. The subfield conversion processing unit 64 converts the supplied signal into drive data based on predetermined coding. The master LSI 50 supplies the drive data generated in this way to the data electrode drive circuit 41.

  Further, the master LSI 50 includes a parameter reading unit 65 connected to a nonvolatile memory 54 provided outside, a checksum calculation unit 66 that calculates a checksum value of data read from the nonvolatile memory 54, and an externally provided LSI. A buffer I / F unit 67 that interfaces with the buffer memory 52, a microcomputer I / F unit 68 that interfaces with the microcomputer 55, and an LSI control unit 69 that controls the inside of the master LSI 50 are provided.

  When the parameter reading unit 65 receives a parameter reading instruction from the LSI control unit 69, the parameter reading unit 65 outputs an address signal storing the read parameter to the nonvolatile memory 54. As a result, parameter data having a predetermined data amount, for example, in units of blocks, is sequentially supplied from the nonvolatile memory 54 to the parameter reading unit 65. Further, the supplied parameter data is stored in the buffer memory 52 via the buffer I / F unit 67 under the control of the LSI control unit 69.

  For example, in FIG. 5, when the LSI control unit 69 instructs to read the drive parameter A, the parameter read unit 65 reads all parameter data from the block area set as the drive parameter A in the nonvolatile memory 54. Each parameter data is temporarily stored in the drive parameter data area of the buffer memory 52. As described above, the plasma display apparatus reads the parameter data from the nonvolatile memory 54 in units of blocks and temporarily stores the parameter data in the buffer memory 52. The reason is that the buffer memory 52, which is a RAM, can be accessed at a higher speed than the non-volatile memory 54 such as a flash memory. That is, by storing the parameter data in the high-speed buffer memory 52, the signal processing can be speeded up.

  In addition to the drive parameter data, the buffer memory 52 temporarily stores image frame data, which is data for a frame of an image signal, subfield data, which is data during subfield processing, and the like.

  Further, when the parameter data supply from the nonvolatile memory 54 is started, the checksum calculation unit 66 calculates the checksum value for the parameter data for the supplied data amount. The checksum value is a remainder value when data is divided. More specifically, the checksum calculation unit 66 cumulatively adds sequentially supplied parameter data, fetches, for example, 8 bits of lower bits of the data that is the cumulative addition result, and uses the fetched data as a checksum value. . This checksum value is notified to the microcomputer 55 via the microcomputer I / F unit 68.

  On the other hand, as shown in FIG. 4, only the data bus is connected between the slave LSI 51 and the nonvolatile memory 54. That is, the read control from the nonvolatile memory 54 is performed by the master LSI 50, and the slave LSI 51 only takes in parameter data supplied in synchronization with the master LSI 50. Similarly to the master LSI 50, the slave LSI 51 also stores the acquired parameter data in the buffer memory 53. At this time, the slave LSI 51 also calculates a checksum value and notifies the microcomputer 55 of it. As described above, the plasma display apparatus is configured to store data shared by the master LSI 50 and the slave LSI 51 such as drive parameters in one nonvolatile memory 54. For this reason, the number of memories can be reduced in a configuration in which the image signal processing unit is realized by a multi-chip LSI.

  As described above, when the reading process of the nonvolatile memory 54 is executed under the control of the master LSI 50, the parameter data is sequentially supplied to the master LSI 50 and the slave LSI 51. Then, the master LSI 50 and the slave LSI 51 each calculate a checksum value and notify the microcomputer 55 of the checksum value. The microcomputer 55 performs an error determination process in the reading process of the nonvolatile memory 54 with reference to each notified checksum value.

  FIG. 6 is a flowchart showing the procedure of the error determination process in the reading process of the nonvolatile memory 54 of the plasma display device in the embodiment of the present invention. The microcomputer 55 executes such an error determination process according to the procedure shown in FIG. That is, the microcomputer 55 takes in the checksum value from the master LSI 50 (step S80). Next, the microcomputer 55 takes in the checksum value from the slave LSI 51 (step S82). Then, the microcomputer 55 compares the normal checksum value, which is a preset correct checksum value, with the checksum value notified from the master LSI 50. Further, the microcomputer 55 compares the normal checksum value with the checksum value notified from the slave LSI 51. The microcomputer 55 determines that it is normal if both match in each comparison. Further, the microcomputer 55 determines that there is an abnormality when at least one of the comparisons does not match (step S84). If the microcomputer 55 determines that it is normal, the microcomputer 55 returns to step S80 and repeats the above-described processing. When normal in this way, the microcomputer 55 periodically performs error determination processing at predetermined time intervals. If the microcomputer 55 determines that there is an abnormality, the microcomputer 55 notifies the master LSI 50 to execute the reading process of the nonvolatile memory 54 again (step S86). In other words, if the microcomputer 55 determines that there is an abnormality, the parameter data is supplied again to the master LSI 50 and the slave LSI 51 (step S88). Thus, the present plasma display apparatus is configured to reload the parameters to the master LSI 50 and the slave LSI 51 when the microcomputer 55 determines that there is an abnormality. This prevents a data reading abnormality caused by a synchronization shift in processing between LSIs. The normal checksum value may be set in the external nonvolatile memory in advance, and the microcomputer 55 may read the checksum value to determine the checksum value.

  As described above, in the plasma display device of the present embodiment, the image signal processing unit 40 captures parameter data from the nonvolatile memory 54 storing the parameter data, and uses the parameter data to capture an image. A master LSI 50 and a slave LSI 51 that perform signal processing in parallel are provided. The master LSI 50 and the slave LSI 51 calculate a checksum value of the acquired parameter data, and the microcomputer 55 of the control unit 45 stores a check stored in advance. The sum value is compared with the checksum value calculated in each of the master LSI 50 and the slave LSI 51, and an error determination in data capture is performed based on the comparison result.

  As described above, since the master LSI 50 and the slave LSI 51 that perform image signal processing in parallel are provided, it is possible to quickly respond to demands for higher density and higher definition. Further, since the parameter data used in common is one nonvolatile memory 54, the number of memories can be reduced. Each of the master LSI 50 and the slave LSI 51 calculates the checksum value in the parameter data transfer, and the microcomputer 55 is configured to perform error determination using the respective checksum value. Even if a transfer error occurs, control such as parameter retransfer for each of the master LSI 50 and the slave LSI 51 can be performed. Therefore, according to the plasma display device of the present invention, it is possible to provide a plasma display device capable of quickly responding to the demand for higher density and higher definition and capable of displaying an image with stable operation.

  In the present embodiment, the example of the two-chip configuration of the master LSI 50 and the slave LSI 51 has been described. However, the present invention can be applied to a multiple-chip configuration. Further, although an example in which the image signal processing is performed by dividing the screen into the left and right has been described, a configuration in which the screen is divided into upper and lower parts or divided into lines or pixels may be used.

  Since the plasma display device of the present invention can display an image with stable operation, it is useful as a display device used for a wall-mounted television or a large monitor.

The disassembled perspective view which shows the principal part of the panel in embodiment of this invention Electrode arrangement of the panel Circuit block diagram of plasma display device in accordance with exemplary embodiment of the present invention Circuit block diagram of image signal processing unit and control unit of same plasma display device Circuit block diagram showing an example of the internal configuration of the master LSI of the plasma display device The flowchart which showed the procedure of the error determination process in the reading process of the non-volatile memory of the plasma display apparatus

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Panel 21 Front substrate 22 Scan electrode 23 Sustain electrode 24 Dielectric layer 25 Protective layer 28 Display electrode pair 31 Back substrate 32 Data electrode 33 Insulator layer 34 Partition 35 Phosphor layer 40 Image signal processing part 41 Data electrode drive circuit 42 Scan Electrode drive circuit 43 Sustain electrode drive circuit 44 Timing generation circuit 45 Control unit 50 Master LSI
51 Slave LSI
52, 53 Buffer memory 54 Non-volatile memory 55 Microcomputer 60 Data selection unit 61 Gamma processing unit 62 Error diffusion unit 63 MPD processing unit 64 Subfield conversion processing unit 65 Parameter reading unit 66 Checksum calculation unit 67 Buffer I / F unit 68 Microcomputer I / F unit 69 LSI control unit

Claims (3)

A plasma display panel, an image signal processing unit that performs image signal processing on the supplied image signal and generates a signal for driving the plasma display panel, and a control unit that controls the image signal processing unit A plasma display device comprising:
The image signal processor is
A nonvolatile memory storing parameter data for performing the image signal processing;
A plurality of integrated circuits that fetch the parameter data from the nonvolatile memory and perform the image signal processing in parallel using the parameter data;
Each of the integrated circuits calculates a checksum value of the captured parameter data,
The control unit compares a checksum value stored in advance with a checksum value calculated in each of the integrated circuits, and performs error determination in data capture based on the comparison result apparatus. A buffer memory provided for each integrated circuit;
2. The plasma display apparatus according to claim 1, wherein each of the integrated circuits fetches the parameter data from the nonvolatile memory in synchronization with each other, and stores the fetched parameter data in the buffer memory. The plasma display apparatus according to claim 1, wherein the controller periodically performs the error determination at predetermined time intervals.

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