JP2009188347A - Electric fuse circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electric fuse circuit which mitigates degradation due to current carrying during reading processing and maintain the reliability of an electric fuse element for a long time. <P>SOLUTION: The electric fuse circuit includes: an electric fuse element H1 to connect a power supply terminal VDD and a node NC1; an electric fuse element H2 to connect a ground terminal VSS and a node NC2; a switch circuit SWC to connect the node NC1 and the node NC2; a PMOS transistor TP1 with a gate terminal connected with a node ND1, a source terminal to a power supply terminal VDD, and a drain terminal to a node NC2, respectively; an NMOS transistor TN1 with a gate terminal connected with a node ND2, a source terminal to a ground terminal VSS, and a drain terminal to the node NC1, respectively; a PMOS transistor TP2 with a gate terminal is connected with a node NC1, a source terminal to a power supply terminal VDD, and a drain terminal to a node ND2, respectively; and a NMOS transistor TN2 with a gate terminal connected with a node NC2, a source terminal to a ground terminal VSS, and a drain terminal to a node ND1, respectively. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electric fuse circuit using an electric fuse element that is programmable by being electrically cut.

  2. Description of the Related Art Conventionally, for example, a variable power supply device that can arbitrarily set an output voltage is equipped with an OTP (One Time Program) memory having a storage capacity of about several bits for adjusting the voltage value of the output voltage. There is. As an OTP memory, for example, there is an electric fuse circuit that stores data using an electric fuse element that is programmable by being electrically disconnected (see, for example, Patent Document 1). Here, FIG. 11 shows a schematic configuration example of a conventional electric fuse circuit.

  As shown in FIG. 11, a conventional electric fuse circuit 1000 has an electric fuse element 1001 having one end connected to the power supply voltage terminal VDD and the other end connected to the internal node N, and a program control signal Vpro input to the gate terminal. An N-type MOS transistor 1003 for program control having a drain terminal connected to the internal node N and a source terminal connected to the ground voltage terminal VSS, a read control signal Vr input to the gate terminal, a drain terminal connected to the internal node N, and a source The read control N-type MOS transistor 1004 whose terminal is connected to the ground voltage terminal VSS and a comparison circuit 1002 for comparing the voltage value of the internal node N with a predetermined threshold voltage value are configured. .

  The electrical fuse element 1001 is electrically disconnected to increase the resistance when a program current having a predetermined magnitude or larger is supplied. By reading the resistance value of the electrical fuse element, it can be determined whether or not the electrical fuse element is programmed.

  More specifically, in the writing process for the conventional electric fuse circuit shown in FIG. 11, the N-type MOS transistor 1003 is turned on, the N-type MOS transistor 1004 is turned off, and a program current is supplied to the electric fuse element 1001. The electrical fuse element 1001 is melted to increase the resistance.

  Further, in the reading process for the conventional electric fuse circuit shown in FIG. 11, the N-type MOS transistor 1003 is turned off, the N-type MOS transistor 1004 is turned on, and the electric fuse element 1001 is energized. This is done by comparing the voltage value of internal node N with the threshold voltage value.

JP 2006-253353 A

  However, in the electric fuse circuit 1000 described in Patent Document 1, since the electric fuse element 1001 is energized during the reading process, the number of times of execution of the reading process for the electric fuse circuit 1000 in which the electric fuse element 1001 is not blown is particularly high. If the number is very large, there is a problem that the electrical fuse element 1001 deteriorates and increases in resistance according to the number of times of execution of read processing, and there is a possibility that data may be corrupted.

  Further, when the electrical fuse element 1001 to be blown in the writing process is not sufficiently blown, the voltage value of the internal node N is higher than that in the case where the electrical fuse element 1001 is normally blown during the read process. As a result, an error may occur in the read data.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an electric fuse circuit capable of reducing deterioration due to energization during a reading process and maintaining the reliability of the electric fuse element for a longer period. In the point.

  To achieve the above object, an electrical fuse circuit according to the present invention includes a first electrical fuse element having one end connected to a power supply voltage terminal and the other end connected to a first detection node, one end connected to a ground voltage terminal, and the other. A second electrical fuse element having an end connected to the second detection node; a control switch circuit having one end connected to the first detection node and the other end connected to the second detection node; A first switch circuit comprising a first P-type MOS transistor having a gate terminal connected to a first positive feedback node, a source terminal connected to the power supply voltage terminal, and a drain terminal connected to the second detection node; A second switch circuit comprising a first N-type MOS transistor having a terminal connected to a second positive feedback node, a source terminal connected to the ground voltage terminal, and a drain terminal connected to the first detection node. A third switch circuit comprising a second P-type MOS transistor having a gate terminal connected to the first detection node, a source terminal connected to the power supply voltage terminal, and a drain terminal connected to the second positive feedback node; A fourth switch circuit comprising a second N-type MOS transistor having a terminal connected to the second detection node, a source terminal connected to the ground voltage terminal, and a drain terminal connected to the first positive feedback node; During the write process, the control switch circuit is turned off to program the first electric fuse element in accordance with write data for each of the first positive feedback node and the second positive feedback node. The first data signal or the second data signal for programming the second electric fuse element is input, and the control is performed during the reading process To the switching circuit to the ON state to the first feature.

  In the electric fuse circuit according to the present invention having the above characteristics, the gate terminal is supplied with the first control signal, the source terminal is at one end of the first electric fuse element, and the drain terminal is at the other end of the first electric fuse element. The second control signal is input to the connected third P-type MOS transistor, the gate terminal, the source terminal is connected to one end of the second electric fuse element, and the drain terminal is connected to the other end of the second electric fuse element. A third N-type MOS transistor, and the first control signal is configured to turn on the third P-type MOS transistor for a predetermined period after the read process or the write process. A second feature is that the control signal is configured to turn on the third N-type MOS transistor during the predetermined period.

  The electrical fuse circuit according to the present invention having any one of the above features is connected to the first positive feedback node via a fifth switch circuit, connected to the second positive feedback node via a sixth switch circuit, A third feature is provided with a latch circuit configured to be able to store at least one of write data and read data read by the read processing.

  The electrical fuse circuit according to the present invention having the above-described characteristics includes an exclusive OR circuit for calculating an exclusive OR of the voltage value of the first positive feedback node and the voltage value of the second positive feedback node, and the exclusive logic. According to a fourth aspect of the present invention, there is provided a latch control circuit that turns off the fifth switch circuit and the sixth switch circuit in accordance with a change in the output of the sum circuit.

  The electrical fuse circuit according to the present invention having any one of the above features includes an exclusive OR circuit that calculates an exclusive OR of the voltage value of the first positive feedback node and the voltage value of the second positive feedback node, A fifth feature is that, during the determination process, the control switch circuit is turned on, and it is determined whether or not the write data is written based on the logical value of the exclusive OR circuit.

  The electrical fuse circuit according to the present invention having any one of the above features includes a first resistance element having one end connected to the first positive feedback node and the other end connected to the power supply voltage terminal, and one end connected to the second positive feedback node. A sixth feature is that the node includes a second resistance element having the other end connected to the ground voltage terminal.

  In the electrical fuse circuit according to the present invention having the above characteristics, the third control signal is input to the gate terminal, the source terminal is connected to one end of the first resistance element, and the drain terminal is connected to the other end of the first resistance element. A fourth N-type MOS transistor, a fourth N-type transistor having a gate terminal connected to a fourth control signal, a source terminal connected to one end of the second resistance element, and a drain terminal connected to the other end of the second resistance element. And the third control signal turns on the fourth P-type MOS transistor in a predetermined period after the read process or the write process, and the fourth control signal is in the predetermined period. A seventh feature is that the fourth N-type MOS transistor is configured to be turned on.

  According to the electrical fuse circuit of the above feature, two electrical fuse elements connected in series via a control switch circuit are provided, and each of the electrical fuse elements is configured to synthesize an output signal into an input signal by positive feedback Therefore, it is possible to significantly reduce the amount of current applied to the unfused electrical fuse element during the reading process. This makes it possible to maintain the reliability of the electric fuse element for a longer period.

  Furthermore, according to the electrical fuse circuit having the above characteristics, the output signal is combined with the input signal by positive feedback for each of the two electrical fuse elements connected in series via the control switch circuit. At the time of processing, a voltage can be applied to the write-processed (fused) electrical fuse element, and the voltage application time for the unfused electrical fuse element can be greatly reduced. With this configuration, as a result, the writing process is performed again on the electric fuse element that was not sufficiently blown during the writing process. That is, according to the electric fuse circuit having the above characteristics, it is possible to more accurately execute the reading process for the electric fuse element that is insufficiently blown, and at the time of the reading process, the electric fuse element that is to be blown is reproduced. The writing process can be executed, and the reliability of the electric fuse circuit can be improved.

  According to the electric fuse circuit of the second feature, the third P-type MOS transistor that electrically bypasses one end and the other end of the first electric fuse element, and the one end and the other end of the second electric fuse element are electrically connected. Since the third N-type MOS transistor to be bypassed is provided, it is possible to stop energization of each of the electric fuse elements at a steady time other than the execution period of the writing process and the reading process. As a result, it is possible to more effectively reduce the aging deterioration of the electric fuse element at the normal time.

  According to the electrical fuse circuit of the third feature, since the latch circuit capable of outputting or receiving data is provided at the first positive feedback node and the second positive feedback node, write data and read data of the electrical fuse element are provided. By using it as a common temporary storage device, the circuit configuration can be simplified and the circuit area can be reduced.

  Further, if the connection state between the latch circuit and the electric fuse circuit is controlled based on the voltage values of the first positive feedback node and the second positive feedback node as in the electric fuse circuit of the fourth feature, the comparison With a simple configuration, it is possible to optimize the data input time to the electric fuse circuit during the writing process, and it is possible to prevent an excessive voltage application to the electric fuse circuit.

  According to the electric fuse circuit of the fifth feature, the exclusive logic for comparing the voltage values of the first positive feedback node and the second positive feedback node, that is, the detection results of the first electric fuse element and the second electric fuse element. Since the sum circuit is provided, the first positive feedback node and the second positive feedback node take different logical values until the write data is normally written, and after the write data is normally written by the write process, Since the first positive feedback node and the second positive feedback node have the same logical value, it is possible to determine whether or not the write data has been normally written based on the logical value of the output signal of the exclusive OR circuit. . In the electric fuse circuit according to the prior art shown in FIG. 11, when the electric fuse element is not blown, it is an electric fuse circuit in which the writing process is not normally completed or the electric fuse element is not blown. However, in the electric fuse circuit of the fifth feature, it can be determined whether or not the writing process has been completed normally based on the logical value of the exclusive OR circuit. As a result, the electrical fuse circuit can be inspected more accurately.

  According to the electric fuse circuit of the sixth feature, the first positive feedback node is connected to the power supply voltage terminal via the first resistance element, and the second positive feedback node is connected to the ground voltage terminal via the second resistance element. With this configuration, it is possible to turn off the first P-type MOS transistor and the first N-type MOS transistor during the steady state, and it is possible to stop energization of the electric fuse element during the steady state. Furthermore, if the fourth fuse type MOS transistor and the fourth N type MOS transistor that bypass the first resistance element and the second resistance element are provided as in the electrical fuse circuit of the seventh feature, the electrical fuse element in a steady state The energization to the can be stopped more reliably.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of an electric fuse circuit according to the present invention (hereinafter, abbreviated as “the present circuit” where appropriate) will be described below with reference to the drawings.

<First Embodiment>
A first embodiment of the circuit of the present invention will be described with reference to FIGS.

  First, the configuration of the circuit of the present invention will be described with reference to FIG. Here, FIG. 1 shows a schematic configuration example of the circuit 1A of the present invention.

  As shown in FIG. 1, the circuit 1A of the present invention includes a first electric fuse element H1 having one end connected to the power supply voltage terminal VDD and the other end connected to the first detection node NC1, and one end connected to the ground voltage terminal VSS. A second electrical fuse element H2 having the other end connected to the second detection node NC2, a control terminal having one end connected to the first detection node NC1 and the other end connected to the second detection node NC2, and having a predetermined resistance value. Switch circuit SWC, and a first P-type MOS transistor TP1 having a gate terminal connected to the first positive feedback node ND1, a source terminal connected to the power supply voltage terminal VDD, and a drain terminal connected to the second detection node NC2. A first switch circuit having a gate terminal connected to the second positive feedback node ND2, a source terminal connected to the ground voltage terminal VSS, and a drain terminal connected to the first detection node NC1; A second switch circuit comprising a MOS transistor TN1, a second P-type MOS having a gate terminal connected to the first detection node NC1, a source terminal connected to the power supply voltage terminal VDD, and a drain terminal connected to the second positive feedback node ND2. A third switch circuit including a transistor TP2, a second N-type MOS transistor having a gate terminal connected to the second detection node NC2, a source terminal connected to the ground voltage terminal VSS, and a drain terminal connected to the first positive feedback node ND1; And a fourth switch circuit including TN2. The inventive circuit 1A of the present embodiment further includes a first resistance element R1 having one end connected to the first positive feedback node ND1, the other end connected to the power supply voltage terminal VDD, and one end connected to the second positive feedback node ND2. , And a second resistance element R2 having the other end connected to the ground voltage terminal VSS.

  More specifically, the control switch circuit SWC of the circuit 1A of the present invention is configured by connecting a resistor element Ra, a switch circuit SW1, and a resistor element Rb in series in this order. The resistance values of the resistance element Ra and the resistance element Rb are the same. Further, the characteristics of the first electric fuse element H1 and the second electric fuse element H2, that is, the current values for fusing are the same.

  Hereinafter, the operation of the circuit 1A of the present invention will be described with reference to FIG. Here, FIG. 2A shows the state of each node of the circuit 1A of the present invention in the write process, and FIG. 2B shows the state of each node of the circuit 1A of the present invention in the read process.

  First, the writing process of the circuit 1A of the present invention of this embodiment will be described with reference to FIG.

  As shown in FIG. 2A, the first positive feedback node ND1 is at the H level because it is connected to the power supply voltage terminal VDD via the first resistance element R1 during the steady state before the writing process. Since the second positive feedback node ND2 is connected to the ground voltage terminal VSS via the second resistance element R2, it is at the L level. Since the first positive feedback node ND1 is at H level, the first P-type MOS transistor TP1 is turned off, and since the second positive feedback node ND2 is at L level, the first N-type MOS transistor TN1 is turned off. Thus, no current flows through either the first electric fuse element H1 or the second electric fuse element H2.

  At the time of execution of the write process, as shown in FIG. 2A, the control switch circuit SWC is turned off, and each of the first positive feedback node ND1 and the second positive feedback node ND2 corresponds to the write data. The first data signal for programming the first electrical fuse element H1 or the second data signal for programming the second electrical fuse element H2 is input.

  More specifically, for example, when the write data is at the H level, an H level first data signal is input to each of the first positive feedback node ND1 and the second positive feedback node ND2, and the first P-type MOS transistor TP1. Is turned on, and the first N-type MOS transistor TN1 is maintained in the off state. When the first P-type MOS transistor TP1 is turned on, the control switch circuit SWC is turned off, so that a voltage is applied only to the second electric fuse element H2 and blown.

  When the write data is at the L level, an L level second data signal is input to each of the first positive feedback node ND1 and the second positive feedback node ND2, and the first N-type MOS transistor TN1 is turned on. The first P-type MOS transistor TP1 is maintained in the off state. When the first N-type MOS transistor TN1 is turned on, the control switch circuit SWC is turned off, so that a voltage is applied only to the first electric fuse element H1 and blown.

  Next, the reading process of the circuit 1A of the present invention according to this embodiment will be described with reference to FIG.

  As shown in FIG. 2B, the first positive feedback node ND1 is at the H level because it is connected to the power supply voltage terminal VDD via the first resistance element R1 during the steady state before the reading process. Since the second positive feedback node ND2 is connected to the ground voltage terminal VSS via the second resistance element R2, it is at the L level. Since the first positive feedback node ND1 is at H level, the first P-type MOS transistor TP1 is turned off, and since the second positive feedback node ND2 is at L level, the first N-type MOS transistor TN1 is turned off. Thus, no current flows through either the first electric fuse element H1 or the second electric fuse element H2.

  When the reading process is executed, the control switch circuit SWC is turned on as shown in FIG.

  Here, for example, when the first electrical fuse element H1 is blown (when the write data is at the H level), when the control switch circuit SWC is turned on, the first detection node NC1 is switched to the control switch. It is connected to the ground voltage terminal VSS via the circuit SWC and the second electric fuse element H2, and the voltage value of the first detection node NC1 decreases toward the ground voltage. When the voltage value of the first detection node NC1 decreases, the voltage value of the control gate of the second P-type MOS transistor TP2 decreases toward the ground voltage and is turned on. Since the source terminal of the second P-type MOS transistor TP2 is connected to the power supply voltage terminal VDD, an H level voltage is applied to the second positive feedback node ND2. When an H level voltage is applied to the second positive feedback node ND2, the first N-type MOS transistor TN1 is turned on, and the voltage value of the first detection node NC1 decreases toward the ground voltage. Further, when the control switch circuit SWC is turned on, the second detection node NC2 is connected to the ground voltage terminal VSS via the second electric fuse element H2, and the second N-type MOS transistor TN2 is turned off. As a result, the first positive feedback node ND1 is connected to the power supply voltage terminal VDD via the first resistor element R1. Through a series of positive feedback operations, a voltage having the same level as the write data (here, H level) is finally output to the first positive feedback node ND1 and the second positive feedback node ND2.

  By the series of positive feedback operations, the first electric fuse element H1 is finally connected to the power supply voltage terminal VDD and the voltage value of the first detection node NC1 to which the other end is connected is the ground voltage. Therefore, the power supply voltage is applied. For this reason, even if the first electrical fuse element H1 is not sufficiently melted, the power supply voltage is applied in the read process, and as a result, the rewrite process is executed simultaneously with the execution of the read process. Thus, improvement in the accuracy of the writing process can be expected. The second electrical fuse element H2 has one end connected to the ground voltage terminal VSS and the other end connected via the control switch circuit SWC to the voltage value of the first detection node NC1 serving as the ground voltage value. Therefore, no voltage is applied and no current flows. Therefore, the deterioration of the second electrical fuse element H2 can be prevented more effectively. Further, the circuit 1A of the present invention operates by the difference between the resistance value of the first electric fuse element H1 that is blown and the resistance value of the second electric fuse element H2 that is not blown. Even if fusing is insufficient, the accuracy of the reading process can be improved.

  Further, for example, when the second electrical fuse element H2 is blown (when the write data is at L level), when the control switch circuit SWC is turned on, the second detection node NC2 becomes the control switch circuit. It is connected to the power supply voltage terminal VDD via the SWC and the first electric fuse element H1, and the voltage value of the second detection node NC2 rises toward the power supply voltage. When the voltage value of the second detection node NC2 increases, the voltage value of the control gate of the second N-type MOS transistor TN2 increases toward the power supply voltage and is turned on. Since the source terminal of the second N-type MOS transistor TN2 is connected to the ground voltage terminal VSS, an L level voltage is applied to the first positive feedback node ND1. When an L level voltage is applied to the first positive feedback node ND1, the first P-type MOS transistor TP1 is turned on, and the voltage value of the second detection node NC2 rises toward the power supply voltage. Further, when the control switch circuit SWC is turned on, the first detection node NC1 is connected to the power supply voltage terminal VDD via the first electric fuse element H1, and the second P-type MOS transistor TP2 is turned off. As a result, the second positive feedback node ND2 is connected to the ground voltage terminal VSS via the second resistance element R2. Through a series of positive feedback operations, a voltage having the same level as the write data (here, H level) is finally output to the first positive feedback node ND1 and the second positive feedback node ND2.

  Through a series of these positive feedback operations, finally, the second electric fuse element H2 has one end connected to the ground voltage terminal VSS and the voltage value of the second detection node NC2 to which the other end is connected becomes the power supply voltage. Thus, the power supply voltage is applied. For this reason, even if the second electrical fuse element H2 is blown up, the power supply voltage is applied in the read process, and as a result, the rewrite process is executed, and the accuracy of the write process is increased. Improvement can be expected. In addition, the first electric fuse element H1 has one end connected to the power supply voltage terminal VDD and the other end connected to the second detection node NC2 via the control switch circuit SWC as the power supply voltage value. Therefore, no voltage is applied and no current flows. Therefore, the deterioration of the first electric fuse element H1 can be prevented more effectively. Further, the circuit 1A of the present invention operates based on the difference between the resistance value of the first electric fuse element H1 that is not blown and the resistance value of the second electric fuse element H2 that is blown. Even if fusing is insufficient, the accuracy of the reading process can be improved.

Second Embodiment
A second embodiment of the circuit of the present invention will be described with reference to FIGS. In the present embodiment, a case where the circuit configuration is different from that of the first embodiment will be described.

  First, the configuration of the circuit of the present invention according to this embodiment will be described with reference to FIG. Here, FIG. 3 shows a schematic configuration example of the circuit 1B of the present invention of the present embodiment. More specifically, the circuit 1B of the present embodiment of the present embodiment includes a circuit for stopping energization of the electric fuse element in a steady state in addition to the components of the first embodiment.

  As shown in FIG. 3, the circuit 1B of the present invention includes the circuits of the first embodiment, that is, the first electric fuse element H1, the second electric fuse element H2, the control switch circuit SWC, and the first P-type MOS transistor TP1. (First switch circuit), first N-type MOS transistor TN1 (second switch circuit), second P-type MOS transistor TP2 (third switch circuit), second N-type MOS transistor TN2 (fourth switch circuit), first resistance element R1 and the second resistance element R2 are provided. The configuration of each circuit is the same as that in the first embodiment.

  In the inventive circuit 1B of the present embodiment, the first control signal SC1 is further input to the gate terminal, the source terminal is connected to one end of the first electrical fuse element H1, and the drain terminal is connected to the other end of the first electrical fuse element H1. The third P-type MOS transistor TP3 connected to each other, the second control signal SC2 is inputted to the gate terminal, the source terminal to one end of the second electric fuse element H2, and the drain terminal to the other end of the second electric fuse element H2. The third control signal SC3 is input to the third N-type MOS transistor TN3 connected to the gate terminal, the source terminal is connected to one end of the first resistance element R1, and the drain terminal is connected to the other end of the first resistance element R1. The fourth control signal SC4 is input to the gate terminal of the fourth P-type MOS transistor TP4, the source terminal is one end of the second resistance element R2, and the drain terminal is And the 4N-type MOS transistor TN4 which are respectively connected to the other end of the second resistance element R2, and is configured with a.

  The first control signal SC1 is configured to turn on the third P-type MOS transistor TP3 during a predetermined period after the read process or the write process. The second control signal SC2 is configured to turn on the third N-type MOS transistor TN3 during the predetermined period. The third control signal SC3 is configured to turn on the fourth P-type MOS transistor TP4 during the predetermined period. The fourth control signal SC4 is configured to turn on the fourth N-type MOS transistor TN4 during the predetermined period.

  Hereinafter, the operation of the circuit 1B according to the present embodiment will be described with reference to FIG. 4A shows the state of each node of the circuit 1B of the present embodiment in the write process, and FIG. 4B shows the state of each node of the circuit 1B of the present embodiment in the read process. Each state is shown.

  The third P-type MOS transistor TP3, the third N-type MOS transistor TN3, the fourth P-type MOS transistor TP4, and the fourth N-type MOS transistor TN4 are configured to be in an off state during the execution of the writing process and the reading process. The operation of the circuit 1B of the present invention in the writing process and the reading process is the same as that in the first embodiment. Hereinafter, the operation of the circuit 1B of the present embodiment of the present embodiment at the normal time when the writing process and the reading process are not executed will be described.

  As shown in FIGS. 4 (a) and 4 (b), the third P-type MOS transistor TP3 is constantly generated by the first control signal SC1, the second control signal SC2, the third control signal SC3, and the fourth control signal SC4. The third N-type MOS transistor TN3, the fourth P-type MOS transistor TP4, and the fourth N-type MOS transistor TN4 are configured to be turned on. In a steady state, the current of the first electric fuse element H1 can be cut by turning on the third P-type MOS transistor TP3, and the current of the second electric fuse element H2 can be cut by turning on the third N-type MOS transistor TN3. Current can be cut. Further, by turning on the fourth P-type MOS transistor TP4, the first P-type MOS transistor TP1 can be surely turned off, and by turning on the fourth N-type MOS transistor TN4, the first N-type MOS transistor TN1. Can be reliably turned off.

<Third Embodiment>
A third embodiment of the circuit of the present invention will be described with reference to FIGS. In the present embodiment, a case where the circuit configuration is different from the first and second embodiments will be described.

  First, the configuration of the circuit of the present invention according to this embodiment will be described with reference to FIG. Here, FIG. 5 shows a schematic configuration example of the inventive circuit 1C of the present embodiment. More specifically, the inventive circuit 1C according to the present embodiment includes a latch circuit L1 configured to be able to store write data and read data read by the read process in addition to the components of the second embodiment. Has been.

  As shown in FIG. 5, the circuit 1C of the present invention is a circuit of the first embodiment, that is, the first electric fuse element H1, the second electric fuse element H2, the control switch circuit SWC, and the first P-type MOS transistor TP1. (First switch circuit), first N-type MOS transistor TN1 (second switch circuit), second P-type MOS transistor TP2 (third switch circuit), second N-type MOS transistor TN2 (fourth switch circuit), first resistance element R1, a second resistance element R2, a third P-type MOS transistor TP3, a third N-type MOS transistor TN3, a fourth P-type MOS transistor TP4, and a fourth N-type MOS transistor TN4. The configuration of each circuit is the same as that of the second embodiment.

  The inventive circuit 1C of the present embodiment is further connected to the first positive feedback node ND1 via the fifth switch circuit SW3, connected to the second positive feedback node ND2 via the sixth switch circuit SW2, and write data And a latch circuit L1 configured to store read data. Further, the fifth switch circuit SW3 and the sixth switch circuit SW2 of the present embodiment are configured to be turned on when the voltage value of the output signal of the latch control circuit CL is at the H level and turned off when at the L level. .

  Hereinafter, the operation of the inventive circuit 1C of the present embodiment will be described with reference to FIG. Here, FIG. 6A shows the state of each node of the circuit 1C of the present embodiment in the write process, and FIG. 6B shows the state of each node of the circuit 1C of the present embodiment in the read process. Each state is shown.

  First, the writing process of the inventive circuit 1C of the present embodiment will be described with reference to FIG. The operations of the control switch circuit SWC, the third P-type MOS transistor TP3, the third N-type MOS transistor TN3, the fourth P-type MOS transistor TP4, and the fourth N-type MOS transistor TN4 are the same as those in the first and second embodiments. Here, in particular, the operations of the fifth switch circuit SW3, the sixth switch circuit SW2, and the latch circuit L1 will be described.

  As shown in FIG. 6A, in a steady state before the writing process, the first positive feedback node ND1 is at the H level and the second positive feedback node ND2 is at the L level. Further, the control switch circuit SWC, the fifth switch circuit SW3, and the sixth switch circuit SW2 are in an off state. At the start of the writing process, write data is input from the outside to the node NL of the latch circuit L1, and the voltage value of the node NE becomes a voltage value corresponding to the write data. When the writing process is started, the fifth switch circuit SW3 and the sixth switch circuit SW2 are turned on, and a voltage corresponding to the write data is input to the first positive feedback node ND1 and the second positive feedback node ND2. When the writing process is completed, the fifth switch circuit SW3 and the sixth switch circuit SW2 are turned off.

  Next, the reading process of the circuit 1C of the present invention of this embodiment will be described with reference to FIG. As in the case of the writing process, the operations of the control switch circuit SWC, the third P-type MOS transistor TP3, the third N-type MOS transistor TN3, the fourth P-type MOS transistor TP4, and the fourth N-type MOS transistor TN4 are the same as those described above. The operations of the fifth switch circuit SW3, the sixth switch circuit SW2, and the latch circuit L1 are particularly described here.

  As shown in FIG. 6B, during the steady state before the reading process, the first positive feedback node ND1 is at the H level and the second positive feedback node ND2 is at the L level. Further, the control switch circuit SWC, the fifth switch circuit SW3, and the sixth switch circuit SW2 are in an off state.

  When the read process is started and the control switch circuit SWC is turned on, the voltage values of the first positive feedback node ND1 and the second positive feedback node ND2 are written by the write process as described in the first embodiment. Value. At this time, as shown in FIG. 6B, the read data is stored in the latch circuit L1 by turning on the fifth switch circuit SW3 and the sixth switch circuit SW2.

  As described above, if the write data used in the write process and the read data read in the read process are stored in the same latch circuit L1, the same latch circuit L1 can be shared, so that an increase in circuit area is suppressed. Can do.

<Fourth embodiment>
A fourth embodiment of the circuit of the present invention will be described with reference to FIGS. In the present embodiment, a case where the circuit configuration is different from the first to third embodiments will be described.

  First, the configuration of the circuit of the present invention according to this embodiment will be described with reference to FIG. Here, FIG. 7 shows a schematic configuration example of the inventive circuit 1D of the present embodiment.

  More specifically, the circuit 1D of the present embodiment of the present embodiment includes the components of the third embodiment, that is, the first electric fuse element H1, the second electric fuse element H2, the control switch circuit SWC, and the first P-type MOS. Transistor TP1 (first switch circuit), first N-type MOS transistor TN1 (second switch circuit), second P-type MOS transistor TP2 (third switch circuit), second N-type MOS transistor TN2 (fourth switch circuit), first Resistor element R1, second resistor element R3, third P-type MOS transistor TP3, third N-type MOS transistor TN3, fourth P-type MOS transistor TP4, fourth N-type MOS transistor TN4, fifth switch circuit SW3, sixth switch circuit SW2, The latch circuit L1 is provided. The configurations of these circuits are the same as those in the third embodiment. The inventive circuit 1D of the present embodiment further calculates the exclusive OR of the voltage value of the first positive feedback node ND1 and the voltage value of the second positive feedback node ND2, and outputs the determination signal SD. An OR circuit EXOR1 is provided.

  Hereinafter, the operation of the inventive circuit 1D of the present embodiment will be described with reference to FIG. Here, FIG. 8A shows the state of each node of the circuit 1D of the present embodiment in the write process, and FIG. 8B shows the state of each node of the circuit 1D of the present embodiment in the read process. Each state is shown.

  First, the operation of the circuit 1D of the present invention during the writing process will be described with reference to FIG. The operation of each circuit other than the first exclusive OR circuit EXOR1 is the same as that in the third embodiment, and the operation of the first exclusive OR circuit EXOR1 will be particularly described here.

  Normally, the voltage value of the first positive feedback node ND1 is H level, the voltage value of the second positive feedback node ND2 is L level, and the determination signal SD output from the first exclusive OR circuit EXOR1 The voltage value is at the H level.

  When the writing process is started, as described in the first to third embodiments, write data is input to both the first positive feedback node ND1 and the second positive feedback node ND2, and the first positive feedback node ND1. And the voltage value of the second positive feedback node ND2 both become voltage values according to the value of the write data. As a result, the voltage value of the first positive feedback node ND1 and the voltage value of the second positive feedback node ND2 become the same, so the voltage value of the determination signal SD output from the first exclusive OR circuit EXOR1 is L Become a level.

  When the writing process is completed, as described in the first to third embodiments, the state shifts to a steady state, the voltage value of the first positive feedback node ND1 is H level, and the voltage value of the second positive feedback node ND2 is It becomes L level, and the voltage value of the determination signal SD of the first exclusive OR circuit EXOR1 becomes H level.

  Next, the operation of the circuit 1D of the present invention during the reading process will be described with reference to FIG. The operation of each circuit other than the first exclusive OR circuit EXOR1 is the same as that in the third embodiment, and the operation of the first exclusive OR circuit EXOR1 will be particularly described here.

  In a steady state before the reading process, the voltage value of the first positive feedback node ND1 is H level, the voltage value of the second positive feedback node ND2 is L level, and is output from the first exclusive OR circuit EXOR1. The voltage value of the determination signal SD is at the H level.

  When the write process is not executed in the read process, or when the write data is not normally written in the write process, when the control switch circuit SWC is turned on, the first detection node NC1 It is connected to the power supply voltage terminal VDD via the fuse element H1, and the voltage value becomes H level. As the first detection node NC1 becomes H level, the second P-type MOS transistor TP2 is turned off. Accordingly, the second positive feedback node ND2 is connected to the ground voltage terminal VSS via the second resistance element R2, and the voltage value becomes L level. The second detection node NC2 is connected to the ground voltage terminal VSS via the second electrical fuse element H2, and the voltage value becomes L level. When the second detection node NC2 becomes L level, the second N-type MOS transistor TN2 is turned off. Therefore, the first positive feedback node ND1 is connected to the power supply voltage terminal VDD via the first resistance element R1, and the voltage value becomes H level. As described above, when the write data is not written normally, the voltage value of the first positive feedback node ND1 becomes H level and the voltage value of the second positive feedback node ND2 becomes L level. The voltage value of the determination signal SD of the circuit EXOR1 becomes H level.

  In the read process, when the write data is normally written, when the control switch circuit SWC is turned on, the voltage value of the first positive feedback node ND1 and the second positive feedback are described as described in the first embodiment. The voltage value of the node ND2 is a voltage value corresponding to the write data. Since the voltage value of the first positive feedback node ND1 and the voltage value of the second positive feedback node ND2 take the same voltage value, the determination signal of the first exclusive OR circuit EXOR1 when the write data is normally written The voltage value of SD becomes L level.

  Therefore, when the control switch circuit SWC is turned on during the read process, the voltage value of the determination signal SD of the first exclusive OR circuit EXOR1 is set to the L level when the write data is normally written. When the write data is not normally written, it becomes H level. Accordingly, it is possible to determine whether or not the write data is normally written in the present invention circuit 1D by turning on the control switch circuit SWC and detecting the determination signal SD of the first exclusive OR circuit EXOR1. . In the inventive circuit 1D of the present embodiment, when the determination signal SD of the first exclusive OR circuit EXOR1 indicates that the write data is written, here, in the case of the L level, the fifth switch circuit SW3 Then, the sixth switch circuit SW2 is turned on, and the read data is stored in the latch circuit L1.

  In a steady state after the reading process, the voltage value of the first positive feedback node ND1 is H level, the voltage value of the second positive feedback node ND2 is L level, and is output from the first exclusive OR circuit EXOR1. The voltage value of the determination signal SD is at the H level.

  As described above, in this embodiment, since the first exclusive OR circuit EXOR1 that compares the voltage value of the first positive feedback node ND1 and the voltage value of the second positive feedback node ND2 is provided, the write data is normally Whether or not data has been written can be determined. This facilitates the inspection of the circuit 1D of the present invention.

<Fifth Embodiment>
A fifth embodiment of the circuit of the present invention will be described with reference to FIGS. In the present embodiment, a case where the circuit configuration is different from the first to fourth embodiments will be described.

  First, the configuration of the circuit of the present invention according to this embodiment will be described with reference to FIG. Here, FIG. 9 shows a schematic configuration example of the circuit 1E of the present invention of the present embodiment.

  More specifically, the circuit 1E of the present embodiment of the present embodiment includes the components of the fourth embodiment, that is, the first electric fuse element H1, the second electric fuse element H2, the control switch circuit SWC, and the first P-type MOS. Transistor TP1 (first switch circuit), first N-type MOS transistor TN1 (second switch circuit), second P-type MOS transistor TP2 (third switch circuit), second N-type MOS transistor TN2 (fourth switch circuit), first Resistor element R1, second resistor element R3, third P-type MOS transistor TP3, third N-type MOS transistor TN3, fourth P-type MOS transistor TP4, fourth N-type MOS transistor TN4, fifth switch circuit SW3, sixth switch circuit SW2, The latch circuit L1 includes a first exclusive OR circuit EXOR1. The configuration of each circuit is the same as that in the fourth embodiment.

  The inventive circuit 1E according to the present embodiment further includes a latch control circuit CL that turns off the fifth switch circuit SW3 and the sixth switch circuit SW2 in accordance with the output change of the first exclusive OR circuit EXOR1. It is configured.

  More specifically, the latch control circuit CL excludes the voltage value of the determination signal SD output from the first exclusive OR circuit EXOR1 and the voltage value of the read control signal RE that outputs an H level signal during the read process. Second exclusive OR circuit EXOR2 for obtaining a logical OR, and a third exclusive for obtaining an exclusive OR of the voltage value of the read control signal RE and the voltage value of the write control signal WE that outputs a signal at H level during the write process. Logical OR circuit EXOR3, and a logical product circuit for obtaining a logical product of the voltage value of the output signal output from the second exclusive OR circuit EXOR2 and the voltage value of the output signal output from the third exclusive OR circuit EXOR3 AND1 is comprised.

  Hereinafter, the operation of the inventive circuit 1E of the present embodiment will be described with reference to FIG. In the present embodiment, in addition to the operation of the circuit 1E of the present invention during normal write processing and the operation of the circuit 1E of the present invention during read processing, it is determined whether or not write data is normally written. The operation of the circuit 1E of the present invention at the time of processing and the operation of the circuit 1E of the present invention when there is a request to execute the write process (duplicate write process) again when the write data is normally written. explain.

  First, the operation of the circuit 1E of the present invention during the write process and the determination process after the write process will be described with reference to FIGS. 10 (a) and 10 (b). Here, FIG. 10A shows the state of each node of the circuit 1E of the present embodiment of the present embodiment in the writing process, and FIG. 10B shows the voltage value of each control signal and determination signal SD in the determination process. Show. In the write process, the operations of the respective circuits other than the latch control circuit CL and the latch circuit L1 are the same as those in the fourth embodiment, and here, particularly, the operations of the latch control circuit CL and the latch circuit L1. explain.

  In the steady state before the write process, as described above, the determination signal SD of the first exclusive OR circuit EXOR1 is at the H level, and the voltage values of the read control signal RE and the write control signal WE are at the L level. At this time, the output signal of the latch control circuit CL is at L level, and the fifth switch circuit SW3 and the sixth switch circuit that electrically connect the latch circuit L1 to the first positive feedback node ND1 and the second positive feedback node ND2. The switch circuit SW2 is in an off state.

  In the write process, as shown in FIG. 10A, the process is started when the voltage value of the write control signal WE transitions from the L level to the H level. When the voltage value of the write control signal WE becomes H level, the voltage value of the output signal of the latch control circuit CL becomes H level accordingly, and the fifth switch circuit SW3 and the sixth switch circuit SW2 are turned on from the off state. The latch circuit L1 is electrically connected to the first positive feedback node ND1 and the second positive feedback node ND2.

  When the writing process ends, as described above, the voltage value of the determination signal SD of the first exclusive OR circuit EXOR1 changes from the H level to the L level, and accordingly, the voltage of the output signal of the latch control circuit CL The value transits from H level to L level. When the voltage value of the output signal of the latch control circuit CL transitions from the H level to the L level, the fifth switch circuit SW3 and the sixth switch circuit SW2 change from the on state to the off state, and the latch circuit L1 and the first positive feedback node ND1. And the electrical connection of the second positive feedback node ND2 is released.

  In the determination process after the write process, the read control signal RE is set to the H level, and it is determined whether write data is written based on the determination signal SD output from the first exclusive OR circuit EXOR1. Here, when the write data is normally written, as shown in FIG. 10B, the voltage value of the determination signal SD of the first exclusive OR circuit EXOR1 becomes L level. On the other hand, when the write data is not normally written, the voltage value of the determination signal SD of the first exclusive OR circuit EXOR1 becomes H level as shown in FIG. When the voltage value of the determination signal SD is L level, the writing process is terminated. If the voltage value of the determination signal SD is H level in the determination process after the write process, it is determined that the write data is not normally written, and the write process is performed again.

  Next, the operation of the circuit 1E of the present invention in the duplicate writing process will be described with reference to FIG. Here, FIG. 10C shows the state of each node of the circuit 1E of the present invention when the duplicate writing process is executed.

  In the duplicate write process, at the start of the duplicate write process, the voltage value of the write control signal WE changes from the L level to the H level as in the normal write process. At this time, the determination signal SD has a voltage value of L level because write data has already been written. Further, the voltage value of the read control signal RE is maintained at the L level. Then, the output value of the latch control circuit CL becomes L level, and the fifth switch circuit SW3 and the sixth switch circuit SW2 are maintained in the off state as shown in FIG.

  Therefore, in the inventive circuit 1E of the present embodiment, even when the redundant write process is requested, the latch circuit L1 is not electrically connected to the first positive feedback node ND1 and the second positive feedback node ND2, and the write data is the first. It is not input to the first positive feedback node ND1 and the second positive feedback node ND2, and it is possible to prevent redundant write processing.

  Next, the operation of the circuit 1E of the present invention during the reading process will be described with reference to FIGS. 10 (b) and 10 (d). The operation of each circuit other than the latch control circuit CL and the latch circuit L1 is the same as that of the fourth embodiment, and here, the operations of the latch control circuit CL and the latch circuit L1 will be described in particular.

  In the read process, the circuit 1E of the present embodiment of the present embodiment reads the read data to the latch circuit L1 when the write data is normally written, and the write data is not normally written. In this case, reading of read data to the latch circuit L1 is prohibited.

  More specifically, when a read process is requested, the read control signal RE transitions from the L level to the H level as shown in FIG. The write control signal WE is maintained at the L level. Here, when the write data is normally written, as shown in FIGS. 10B and 10C, the voltage value of the determination signal SD of the first exclusive OR circuit EXOR1 becomes L level. Become. In this case, as shown in FIG. 10B, the output signal of the latch control circuit CL becomes H level, and the fifth switch circuit SW3 and the sixth switch circuit SW2 are turned on. As a result, the first positive feedback node ND1 and the second positive feedback node ND2 are connected to the latch circuit L1, and read data is stored in the latch circuit L1.

  On the other hand, when the write data is not written normally, as shown in FIGS. 10B and 10C, the voltage value of the determination signal SD of the first exclusive OR circuit EXOR1 is H level. become. In this case, as shown in FIG. 10B, the output signal of the latch control circuit CL becomes L level, and the fifth switch circuit SW3 and the sixth switch circuit SW2 are maintained in the off state. As a result, the connection between the first positive feedback node ND1 and the second positive feedback node ND2 and the latch circuit L1 is prohibited.

  In the present embodiment, the latch control circuit CL is configured by the second exclusive OR circuit EXOR2, the third exclusive OR circuit EXOR3, and the AND circuit AND1, but is not limited thereto. It is sufficient that the fifth switch circuit SW3 and the sixth switch circuit SW2 are configured to be turned on at the time of the write process excluding the duplicate write process and when the write data is normally written in the read process. . In the present embodiment, the fifth switch circuit SW3 and the sixth switch circuit SW2 are configured to be in the on state at the H level and in the off state at the L level. However, depending on the configuration of the latch control circuit CL, the latch circuit It may be configured such that the voltage value of the output signal of the control circuit CL is turned on at the L level and turned off at the H level.

Schematic circuit diagram showing a schematic configuration example of the first embodiment of the electrical fuse circuit according to the present invention Table showing operations of write processing and read processing in the first embodiment of the electrical fuse circuit according to the present invention. Schematic circuit diagram showing a schematic configuration example of the second embodiment of the electrical fuse circuit according to the present invention Table showing operations of write processing and read processing in the second embodiment of the electrical fuse circuit according to the present invention. The schematic circuit diagram which shows the schematic structural example of 3rd Embodiment of the electrical fuse circuit which concerns on this invention Table showing operations of write processing and read processing in the third embodiment of the electric fuse circuit according to the present invention. Schematic circuit diagram showing a schematic configuration example of the fourth embodiment of the electrical fuse circuit according to the present invention Table showing operations of write processing and read processing in the fourth embodiment of the electric fuse circuit according to the present invention. Schematic circuit diagram showing a schematic configuration example of the fifth embodiment of the electrical fuse circuit according to the present invention Table showing operations of write processing and read processing in the fifth embodiment of the electric fuse circuit according to the present invention. Schematic circuit diagram showing a schematic configuration example of an electrical fuse circuit according to the prior art

Explanation of symbols

1 Electrical fuse circuit 1A according to the present invention Electrical fuse circuit 1B according to the present invention Electrical fuse circuit 1C according to the present invention Electrical fuse circuit 1D according to the present invention Electrical fuse circuit 1E according to the present invention Electrical fuse circuit 1000 according to the present invention Conventionally Technical fuse circuit 1001 Electrical fuse element 1002 Comparison circuit 1003 N-type MOS transistor 1004 N-type MOS transistor AND1 AND circuit CL Latch control circuit EXOR1 First exclusive OR circuit EXOR2 Second exclusive OR circuit EXOR3 Third Exclusive OR circuit H1 First electric fuse element H2 Second electric fuse element L1 Latch circuit NC1 First detection node NC2 Second detection node ND1 First positive feedback node ND2 Second positive feedback node NL Node NE Node Ra Resistance element Rb Resistance element R1 First resistor element R2 Second resistor element RE Read control signal SC1 First control signal SC2 Second control signal SC3 Third control signal SC4 Fourth control signal SD Determination signal SWC Control switch circuit SW1 Switch circuit SW2 Fifth switch circuit SW3 Sixth switch circuit TP1 First P-type MOS transistor (first switch circuit)
TN1 First N-type MOS transistor (second switch circuit)
TP2 Second P-type MOS transistor (third switch circuit)
TN2 Second N-type MOS transistor (fourth switch circuit)
TP3 Third P-type MOS transistor TN3 Third N-type MOS transistor TP4 Fourth P-type MOS transistor TN4 Fourth N-type MOS transistor VDD Power supply voltage terminal VSS Ground voltage terminal WE Write control signal

Claims (7)

A first electrical fuse element having one end connected to the power supply voltage terminal and the other end connected to the first detection node;
A second electrical fuse element having one end connected to the ground voltage terminal and the other end connected to the second detection node;
A control switch circuit having one end connected to the first detection node and the other end connected to the second detection node and having a predetermined resistance value;
A first switch circuit comprising a first P-type MOS transistor having a gate terminal connected to a first positive feedback node, a source terminal connected to the power supply voltage terminal, and a drain terminal connected to the second detection node;
A second switch circuit comprising a first N-type MOS transistor having a gate terminal connected to a second positive feedback node, a source terminal connected to the ground voltage terminal, and a drain terminal connected to the first detection node;
A third switch circuit comprising a second P-type MOS transistor having a gate terminal connected to the first detection node, a source terminal connected to the power supply voltage terminal, and a drain terminal connected to the second positive feedback node;
A fourth switch circuit including a second N-type MOS transistor having a gate terminal connected to the second detection node, a source terminal connected to the ground voltage terminal, and a drain terminal connected to the first positive feedback node. ,
During the write process, the control switch circuit is turned off to program the first electric fuse element in accordance with write data for each of the first positive feedback node and the second positive feedback node. Input a first data signal or a second data signal for programming the second electrical fuse element;
An electrical fuse circuit, wherein the control switch circuit is turned on during a reading process. A third P-type MOS transistor having a first control signal input to a gate terminal, a source terminal connected to one end of the first electric fuse element, and a drain terminal connected to the other end of the first electric fuse element;
A third N-type MOS transistor having a gate terminal receiving a second control signal, a source terminal connected to one end of the second electric fuse element, and a drain terminal connected to the other end of the second electric fuse element; ,
The first control signal is configured to turn on the third P-type MOS transistor in a predetermined period after the read process or the write process;
2. The electric fuse circuit according to claim 1, wherein the second control signal is configured to turn on the third N-type MOS transistor during the predetermined period.   Connected to the first positive feedback node via a fifth switch circuit, connected to the second positive feedback node via a sixth switch circuit, and at least of the write data or read data read in the read process. 3. The electric fuse circuit according to claim 1, further comprising a latch circuit configured to be capable of storing either one of them. An exclusive OR circuit for calculating an exclusive OR of the voltage value of the first positive feedback node and the voltage value of the second positive feedback node;
4. The electrical fuse circuit according to claim 3, further comprising: a latch control circuit that turns off the fifth switch circuit and the sixth switch circuit in response to a change in output of the exclusive OR circuit. 5. . An exclusive OR circuit that calculates an exclusive OR of the voltage value of the first positive feedback node and the voltage value of the second positive feedback node;
5. The determination circuit according to claim 1, wherein, during the determination process, the control switch circuit is turned on to determine whether or not the write data is written based on a logical value of the exclusive OR circuit. The electrical fuse circuit according to any one of the above. A first resistance element having one end connected to the first positive feedback node and the other end connected to the power supply voltage terminal;
The electrical fuse according to claim 1, further comprising: a second resistance element having one end connected to the second positive feedback node and the other end connected to the ground voltage terminal. circuit. A fourth P-type MOS transistor having a gate terminal connected to a third control signal, a source terminal connected to one end of the first resistance element, and a drain terminal connected to the other end of the first resistance element;
A fourth control signal input to the gate terminal, a fourth N-type MOS transistor having a source terminal connected to one end of the second resistance element and a drain terminal connected to the other end of the second resistance element,
The third control signal turns on the fourth P-type MOS transistor in a predetermined period after the read process or the write process;
The electric fuse circuit according to claim 6, wherein the fourth control signal is configured to turn on the fourth N-type MOS transistor during the predetermined period.

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