JP2009187647A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device that applies voltage to a plurality of transistors at the same time and reduces time for a reliability test in the semiconductor memory device which is configured by connecting in series a plurality of memory cells configured with ferroelectric capacitors and transistors. <P>SOLUTION: The semiconductor memory device has a memory block which is configured by connecting in series a plurality of memory cells configured by connecting both electrodes of the ferroelectric capacitors to sources and drains of the transistors, a plurality of word lines connected to gates of the transistors of the memory cells, respectively, a plate line connected to one end of the memory block, a bit line connected to the other end of the memory block via a switching element for block selection and a control circuit that controls the plurality of transistors in the memory block and the switching element for block selection to apply voltage to two or more of the plurality of ferroelectric capacitors at the same time. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device provided with a ferroelectric capacitor.

  A semiconductor memory device using a ferroelectric capacitor having polarization characteristics as a nonvolatile memory cell has been developed. Note that a ferroelectric capacitor is an information storage capacitor using a ferroelectric as an insulating film between electrodes.

  Examples of the semiconductor memory device using the ferroelectric capacitor include a memory cell unit (memory block) in which a plurality of memory cells including one ferroelectric capacitor and one transistor are connected in series. is there.

As a semiconductor memory device including the memory cell unit (memory block), for example, there is a ferroelectric memory described in Patent Document 1. This ferroelectric memory has a normal operation mode and a screening mode. In the screening mode, a larger number of memory cells than the memory cells selected in the normal operation mode are selected simultaneously, and both ferroelectric capacitors in the memory cell are selected. A screening circuit is provided for applying a pulse voltage whose polarity is alternately inverted between the terminals.
JP-A-7-287999

  The present invention reduces the time required for a reliability test by simultaneously applying a voltage to a plurality of transistors in a semiconductor memory device configured by connecting a plurality of memory cells including ferroelectric capacitors and transistors in series. A semiconductor memory device is provided.

  A semiconductor memory device according to an embodiment of the present invention includes a memory block in which a plurality of memory cells configured by connecting both electrodes of a ferroelectric capacitor to the source and drain of a transistor are connected in series; A plurality of word lines connected corresponding to the gates of the transistors, a plate line connected to one end of the memory block, and a bit connected to the other end of the memory block via a block selection switch element And a control circuit that controls the plurality of transistors and the block selection switch element in the memory block and applies a voltage to two or more of the plurality of ferroelectric capacitors at the same time. Features.

  According to the present invention, in a semiconductor memory device configured by connecting a plurality of memory cells including a ferroelectric capacitor and a transistor in series, a voltage is simultaneously applied to the plurality of transistors, thereby reducing the time required for reliability testing. It becomes possible to do.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The semiconductor memory device according to the embodiment will be described here taking a ferroelectric memory as an example. Note that, in the embodiments, the same components are denoted by the same reference numerals, and redundant description among the embodiments is omitted.

(First embodiment)
FIG. 1 is a block diagram showing the overall configuration of a ferroelectric memory according to the first embodiment of the present invention. In FIG. 1, a ferroelectric memory 100 includes a timing control circuit 11, a test mode control circuit 12, a memory cell array 13, a word line driver (hereinafter referred to as a WL driver) 14, a sense amplifier and a bit line driver (hereinafter referred to as a “line amplifier”). , S / A, BL driver) 15, plate line driver (hereinafter referred to as PL driver) 16, I / O bus 17, and address bus 18.

  The timing control circuit 11 is provided in the ferroelectric memory 100 excluding the test mode control circuit 12 in response to an external control signal input from an external electronic device (not shown) to which the ferroelectric memory 100 is connected. The operation timing of each unit is controlled to execute a data write operation, a data read operation, a data erase operation, or the like for the memory cell array 13. In the first embodiment, the data write operation, the data read operation, and the data erase operation are referred to as “normal operation”.

  The test mode control circuit 12 (control circuit) includes a ROM (not shown) that stores a test program for executing a reliability test described later. The test mode control circuit 12 excludes the timing control circuit 11 based on the test program in accordance with a test control signal input from an external test apparatus (not shown) to which the ferroelectric memory 100 is connected. The operation of each unit in the body memory 100 is controlled to execute a reliability test on the memory cell array 13. The details of the reliability test will be described in the flowchart shown in FIG.

  The memory cell array 13 includes a plurality of memory blocks. An example of the circuit configuration of one memory block is shown in FIG. In FIG. 2, the memory block 200 is configured by connecting a plurality of memory cells MC1 to MC4 in series. Each of the memory cells MC1 to MC4 is composed of ferroelectric capacitors C1 to C4 and transistors Tr1 to Tr4, respectively. Each ferroelectric capacitor C1 to C4 has both electrodes connected to the sources and drains of the transistors Tr1 to Tr4. Word lines WL1 to WL4 are connected to the gates of the transistors Tr1 to Tr4, respectively. The memory block 200 has a plate line PL connected to one end (right end in the figure) and a bit line BL connected to the other end (left end in the figure) via a block selection transistor (block selection switch element) BLSW. Yes. A block selection line BS to which a block selection voltage is applied is connected to the gate of the block selection transistor BLSW. In the memory block 200 shown in FIG. 2, the case where the four memory cells MC1 to MC4 are connected in series is shown, but the number of the memory cells connected in series is not limited.

  The WL driver 14 is a circuit that drives the word lines WL1 to WL4. In the normal mode operation, the WL driver 14 is a memory cell to be operated in the memory block 200 based on a control signal input from the timing control circuit 11 and address information input via the address bus 18. A voltage for normally operating the transistor is applied to the block selection line BS connected to the block selection transistor BLSW to be operated and the word line WL connected to the memory cell. The WL driver 14 tests the transistor of the memory cell to be tested in the memory block 200 based on the control signal input from the test mode control circuit 12 during the test mode operation during the reliability test. The voltage to be operated is applied to the block selection line BS connected to the block selection transistor BLSW to be tested and the word line WL connected to the memory cell.

  The S / A, BL driver 15 is a circuit that drives the bit line BL and amplifies the voltage applied to the bit line BL to read data from the operation target memory cell. In the normal mode operation, the S / A, BL driver 15 is configured to use the memory block based on the control signal input from the timing control circuit 11 and the command or write data input via the I / O bus 17. A voltage related to the normal operation of the transistor of the memory cell to be operated in 200 is applied to the bit line BL. Further, the S / A, BL driver 15 is a memory cell to be tested in the memory block 200 based on the control signal input from the test mode control circuit 12 during the test mode operation during the reliability test. A voltage related to the test operation of the transistor is applied to the bit line BL.

  The PL driver 16 is a circuit that drives the plate line PL. During the normal mode operation, the PL driver 16 applies the voltage related to the normal operation of the transistor of the memory cell to be operated in the memory block 200 to the plate line PL based on the control signal input from the timing control circuit 11. Apply. Further, the PL driver 16 tests the transistor of the memory cell to be tested in the memory block 200 based on the control signal input from the test mode control circuit 12 during the test mode operation during the reliability test. A voltage related to the operation is applied to the plate line PL.

  The I / O bus 17 is a bus for exchanging various commands, write data, and read data with an external electronic device to which the ferroelectric memory 100 is connected.

  The address bus 18 is a bus for receiving address information from an external electronic device or the like to which the ferroelectric memory 100 is connected.

  Next, the normal mode operation executed in the ferroelectric memory 100 will be described with reference to an operation example of the memory block 200 shown in FIG.

  FIG. 3 shows a case where data is read from the memory cell MC2 in the memory block 200 during the normal mode operation. In the memory block 200 of FIG. 3, a voltage is applied to the block selection line BS connected to the gate of the block selection transistor BLSW, the block selection transistor BLSW is turned on, the transistor Tr2 of the memory cell MC2 to be read is turned off, and others The transistors Tr1, Tr3, Tr4 of the memory cells MC1, MC3, MC4 are turned on. Thus, by operating the block selection transistor BLSW and the transistors Tr1 to Tr4 in the memory block 200, a voltage is applied to the ferroelectric capacitor C2 to be read, and the data stored in the ferroelectric capacitor C2 is stored. Read by S / A, BL driver 15. That is, in the normal mode operation of the memory block 200, there is one memory cell to be operated.

  By the way, in a ferroelectric memory, a phenomenon called static imprint (hereinafter abbreviated as imprint) is known as one of the causes of poor reliability. Imprinting is a phenomenon in which when a ferroelectric memory is left in a high temperature, the polarization stored in the ferroelectric capacitor is burned, and the polarization in the opposite direction to this polarization becomes difficult to write. This phenomenon is thought to be because the electric charge in the ferroelectric film is fixed by relocation due to the spontaneous polarization stored in the ferroelectric capacitor, and an electric field opposite to the spontaneous polarization is created. . The cause of the rearrangement of charges in the ferroelectric film is the polarization in the ferroelectric, and the greater the polarization, the easier the rearrangement of charges. Therefore, for example, if the electrode inside the ferroelectric capacitor is enlarged by applying an electric field from the outside (in a state where data “0” or “1” is written), imprinting is faster than when no electric field is applied from the outside. proceed.

  In addition, a phenomenon called dynamic imprint is known as another cause of the reliability failure of the ferroelectric memory. Dynamic imprinting is a phenomenon in which if the same data (“0” or “1”) is read or written continuously, the data is burned in the ferroelectric capacitor, making it difficult to write data in the opposite direction. is there. The phenomenon in which imprinting proceeds rapidly under the external electric field described above is a phenomenon similar to dynamic imprinting.

  As described above, in order to accelerate the imprint of the ferroelectric memory, it is effective to apply an electric field in the direction in which the polarization of the ferroelectric capacitor of the cell is increased from the outside, thereby reducing the reliability. Cells that are likely to wake can be screened in advance. However, in the normal mode operation of the memory block 200 shown in FIG. 3, the number of memory cells to be operated is one. For this reason, in order to screen a memory cell that is likely to cause a reliability failure, an external electric field is applied to each memory cell in the memory block 200. As a result, it takes a long time to perform a reliability test before shipment, which increases the cost of the ferroelectric memory.

  Further, as a screening method different from the method described above, a method of applying a minute electric field in a direction that reverses the polarization written in the ferroelectric capacitor is also conceivable. That is, when the ferroelectric capacitor is not sufficiently written, a part of polarization is inverted by applying a minute electric field, and data cannot be normally read in the subsequent data reading operation. Therefore, for example, even if a memory cell in which reliability failure is caused by an operation sequence of “data writing” → “application of a minute inversion electric field” → “data reading” is normally operated in a normal operation test, It is possible to screen as a memory cell that may cause a defect and repair it using a memory cell for redundancy. In order to reduce the reliability test time by applying this operation, it is desirable that an inversion electric field can be simultaneously applied to a plurality of memory cells. However, in the normal mode operation of the memory block 200 shown in FIG. 3, it is difficult to reduce the time for the reliability test because the number of memory cells to be operated is one.

  In the ferroelectric memory 100 shown in FIG. 1 according to the first embodiment, the test mode control circuit 12 is provided so that a test mode operation is executed during a reliability test of the memory block 200, and a plurality of test modes are controlled. By simultaneously applying an electric field to the memory cells, it is possible to shorten the time for screening the memory cells that are likely to cause reliability failures.

  Next, a test method of the reliability test executed in the ferroelectric memory 100 shown in FIG. 1 according to the first embodiment will be described with reference to the flowchart shown in FIG. A test mode operation executed in the test mode control circuit 12 during the reliability test will be described with reference to voltage application examples of the memory block 200 shown in FIGS. This test mode is intended to find cells that are likely to fail in imprinting and dynamic imprinting.

  The test mode control circuit 12 performs a reliability test shown in FIG. 4 based on the test program in accordance with a test control signal input from an external test apparatus (not shown) to which the ferroelectric memory 100 is connected. To start.

  First, in step S1, the test mode control circuit 12 tests each memory cell of a plurality of memory blocks included in the memory cell array 13 as an initial operation test to screen an initial defective memory cell. In this initial operation test, it is assumed that the ferroelectric memory 100 to be tested is housed in a package after an assembly process.

  Next, in step S2, the ferroelectric memory 100 is subjected to a high temperature standing test while applying a voltage to the ferroelectric capacitors C1 to C4 in the memory block 200 in the test mode. In this case, since the ferroelectric capacitor 100 is contained in the package, for example, a high temperature storage test is performed in an environment where a voltage can be simultaneously applied to the plurality of ferroelectric memories 100 using a burn-in device or the like. Prior to the test, it is assumed that predetermined data is written in the memory cell, and the ferroelectric capacitor 100 of each memory cell is polarized according to the data. The voltage applied to the ferroelectric capacitor 100 using the test mode in this test is a direction in which the polarization of the ferroelectric capacitor 100 is increased. In this high temperature storage test, the test mode control circuit 12 outputs a control signal corresponding to the test mode to the WL driver 14, S / A, BL driver 15, and PL driver 16 to test the memory block 200. Control the behavior. An example of the test mode operation in the memory block 200 will be described with reference to FIG.

  In FIG. 5, the test mode control circuit 12 outputs to the WL driver 14 a control signal that turns on the block selection transistor BLSW in the memory block 200 and turns off the transistors Tr1 to Tr4 of the memory cells MC1 to MC4. Based on the control signal input from the test mode control circuit 12, the WL driver 14 applies a voltage for turning on the block selection transistor BLSW to the block selection line BS and a voltage for turning off the transistors Tr1 to Tr4 on the word line WL1. Apply to ~ WL4. At this time, for example, 3V is applied to the block selection line BS, and 0V is applied to the word lines WL1 to WL4.

  Then, with 3V applied to the block selection line BS and 0V applied to the word lines WL1 to WL4, the test mode control circuit 12 controls the voltage applied to the bit line BL and the plate line PL connected to the memory block 200. The control signal is output to the S / A, BL driver 15 and PL driver 16. At this time, for example, 0 V is applied to the bit line BL, and the voltage Vpl is applied to the plate line PL.

  As described above, by applying a voltage to the block selection line BS, the word lines WL1 to WL4, the bit line BL, and the plate line PL, Vpl / 4 is simultaneously applied to the memory cells MC1 to MC4 as shown in FIG. Can be applied. As Vpl, a PL driving voltage at the time of normal data writing or data reading may be used, or a PL driving voltage optimized for this test mode operation may be used.

  Next, after the high temperature storage test in step S2 is completed, in step S3, the operation test of the ferroelectric memory 100 is performed again to screen the memory cells with poor reliability, and the reliability test is completed.

  As described above, in the ferroelectric memory 100 according to the first embodiment, the test mode control circuit 12 is provided, and the test mode operation is executed during the high-temperature storage test of the memory block 200, and a plurality of test modes are performed. An electric field can be simultaneously applied to the memory cell. Since the polarization in the ferroelectric capacitors C1 to C4 is increased by the test mode operation, it is possible to accelerate the deterioration of the memory cell due to imprinting. As a result, it becomes possible to screen a memory cell having an initial reliability failure in a short time, the time for the reliability test can be shortened, and the test cost can be reduced. In the test of the first embodiment, since it is assumed that the semiconductor chip is already contained in the package, the defective bit discovered as a result of the test is an electrically disconnectable fuse (e-fuse). Replace with a redundancy block using and repair. Further, when the number of defective bits is large and cannot be remedied, it is possible to take measures such as canceling the shipment. Further, the test method of the first embodiment can be used for redundancy repair of shipped chips, and can also be used for a life test by sampling inspection at the time of shipment.

(Second Embodiment)
In the ferroelectric memory according to the second embodiment of the present invention, a test mode operation is executed during a reliability test, and an electric field is simultaneously applied to some of the memory cells in the memory block. A case where a stronger electric field than that in the first embodiment is simultaneously applied to a plurality of memory cells will be described. The configurations of the ferroelectric memory 100 and the memory block 200 according to the second embodiment are the same as those shown in FIG. 1 and FIG.

  In the ferroelectric memory 100 shown in FIG. 1 according to the second embodiment, the voltage application of the memory block 200 shown in FIG. 7 is performed for the test mode operation executed in the test mode control circuit 12 during the reliability test. This will be described with reference to an example. The test method of the reliability test executed in the ferroelectric memory 100 shown in FIG. 1 according to the second embodiment is the same as that shown in FIG. Description of S1 and S3 is omitted.

  The test mode control circuit 12 performs a reliability test shown in FIG. 4 based on the test program in accordance with a test control signal input from an external test apparatus (not shown) to which the ferroelectric memory 100 is connected. To start.

  In step S2, the ferroelectric memory 100 is subjected to a high temperature standing test while applying a voltage to the ferroelectric capacitors C1 to C4 in the memory block 200 in the test mode. In this case, since the ferroelectric capacitor 100 is contained in the package, for example, a high temperature storage test is performed in an environment where a voltage can be simultaneously applied to the plurality of ferroelectric memories 100 using a burn-in device or the like. In this high temperature storage test, the test mode control circuit 12 outputs a control signal corresponding to the test mode to the WL driver 14, S / A, BL driver 15, and PL driver 16 to test the memory block 200. Control the behavior. An example of the test mode operation in the memory block 200 will be described with reference to FIG.

  In FIG. 7, the test mode control circuit 12 turns on the block selection transistor BLSW in the memory block 200, turns off the transistors Tr1 and Tr2 of the memory cells MC1 and MC2, and turns on the transistors Tr3 and Tr4 of the memory cells MC3 and MC4. A control signal for turning on is output to the WL driver 14. Based on the control signal input from the test mode control circuit 12, the WL driver 14 applies a voltage for turning on the block selection transistor BLSW to the block selection line BS, and supplies a voltage for turning off the transistors Tr1 and Tr2 to the word lines WL1, A voltage that is applied to WL2 to turn on the transistors Tr3 and Tr4 is applied to the word lines WL3 and WL4. At this time, for example, 3V is applied to the block selection line BS and the word lines WL3 and WL4, and 0V is applied to the word lines WL1 and WL2.

  Then, with 3V applied to the block selection line BS and the word lines WL3 and WL4 and 0V to the word lines WL3 and WL4, the test mode control circuit 12 applies the bit line BL and the plate line PL connected to the memory block 200 to each other. A control signal for controlling the applied voltage is output to the S / A, BL driver 15 and PL driver 16. At this time, for example, 0 V is applied to the bit line BL, and the voltage Vpl is applied to the plate line PL.

  As described above, by applying voltages to the block selection line BS, the word lines WL1 to WL4, the bit line BL, and the plate line PL, the ferroelectric capacitors C1 of the memory cells MC1 and MC2 as shown in FIG. , C2 can be simultaneously applied with Vpl / 2. As Vpl, a PL driving voltage at the time of normal data writing or data reading may be used, or a PL driving voltage optimized for this test mode operation may be used. In this way, by applying Vpl / 2 to the memory cells MC1 and MC2 at the same time, a voltage twice that of the first embodiment is applied to the ferroelectric capacitors C1 and C2. Become. Thereafter, the transistors Tr1 and Tr2 are turned on and the transistors Tr3 and Tr4 are turned off, and the voltage Vpl is applied to the bit line BL and the plate line PL, so that the ferroelectric capacitors C3 and C4 are simultaneously applied. Vpl / 2 can be applied.

  As described above, the deterioration due to the imprint phenomenon of the ferroelectric capacitors C1, C2 or C3, C4 by applying the voltage to the ferroelectric capacitors C1, C2 or C3, C4 simultaneously is the same as that of the first embodiment. The process proceeds faster than the test mode operation shown in the embodiment. However, in the reliability test method according to the second embodiment, voltage is applied to two memory cells at the same time among the four memory cells in the memory block 200. It will take longer than the reliability test method shown. Therefore, the advantage that the deterioration time due to the imprint phenomenon is accelerated by applying twice the voltage to the ferroelectric capacitor exceeds the advantage that the test time becomes longer by dividing one memory block twice. In addition, the reliability test method according to the second embodiment is effective.

  In the second embodiment, the voltage is applied by dividing the four memory cells in one memory block into two. However, the number of memory cells in one memory block is more than four. If there are many, it may be divided into two or more and a voltage may be individually applied to each of the plurality of divided memory cells.

(Third embodiment)
In the ferroelectric memory according to the third embodiment of the present invention, data retention is unstable by applying a minute voltage to the ferroelectric capacitor and inverting the spontaneous polarization stored in the ferroelectric capacitor. A case where a reliability test for extracting a memory cell is executed will be described. Note that the configurations of the ferroelectric memory 100 and the memory block 200 according to the third embodiment are the same as those shown in FIGS. 1 and 2, and therefore illustration and description thereof are omitted.

  During the reliability test in the ferroelectric memory 100 shown in FIG. 1 according to the third embodiment, the test mode control circuit 12 executes a test mode operation to apply a minute voltage to the ferroelectric capacitor. The case will be described with reference to the flowchart shown in FIG.

  The test mode control circuit 12 performs the reliability test shown in FIG. 8 based on the test program in accordance with a test control signal input from an external test apparatus (not shown) to which the ferroelectric memory 100 is connected. To start.

  First, in step S11, as an initial operation test, the test mode control circuit 12 performs a test operation on each memory cell in a plurality of memory blocks included in the memory cell array 13 to screen an initial defective memory cell.

  Next, in step S12, certain data is written to a plurality of memory cells in each memory block, except for the memory cells that are initially defective. In this case, the test mode control circuit 12 outputs write data and a control signal for controlling the write operation to the WL driver 14, S / A, BL driver 15, and PL driver 16, so that an initial failure in each memory block is detected. The data in a plurality of memory cells excluding the memory cell is written.

  Next, in step S13, a minute data breakdown voltage Vtest is applied to the ferroelectric capacitor under the test mode. In this case, the test mode control circuit 12 outputs a control signal for controlling the application of the data destruction voltage Vtest to the WL driver 14, the S / A, the BL driver 15, and the PL driver 16, and the data in each memory block is output. The data destruction voltage Vtest is applied to each written memory cell. As the data destruction voltage Vtest, for example, a voltage of about 0.1 V is used, but it is desirable to set an optimum voltage value using a ferroelectric memory to be actually tested. Since the data breakdown voltage Vtest is applied to each ferroelectric capacitor, for example, as shown in FIG. 3 in the first embodiment, voltages are simultaneously applied to the four ferroelectric capacitors C1 to C4. In this case, the potential difference between the plate line PL and the bit line BL is 4 × Vtest.

  As described above, when the data breakdown voltage Vtest is applied to the ferroelectric capacitor, an electric field is applied to invert the spontaneous polarization stored in the ferroelectric capacitor. For this reason, when the spontaneous polarization is unstable, the data stored in the memory cell is inverted. Therefore, in step S14, a memory cell with unstable data retention can be extracted by performing a data read test in which data is read from the memory block after the application of the data breakdown voltage Vtest.

  A memory cell with unstable data retention is considered to be highly likely to be defective in reliability. Therefore, if a countermeasure such as replacement with a redundancy memory prepared in advance in the memory cell array 13 is taken, a ferroelectric memory The risk of defects after shipment can be reduced.

  In addition, if the potential of the data breakdown voltage Vtest is increased, more unstable memory cells can be extracted. However, if the potential of the data breakdown voltage Vtest is excessively increased, memory cells that are unlikely to cause a reliability failure are included in the extraction target. It is inconvenient to return. Further, if the potential of the data breakdown voltage Vtest is lowered too much, memory cells that may cause a reliability failure cannot be extracted sufficiently. Therefore, the potential of the data breakdown voltage Vtest is set based on the correlation between a memory cell with poor reliability and a data inversion memory cell whose data is inverted by application of the data breakdown voltage based on the result of a reliability test performed in advance. It should be done while checking.

  From the above, in the reliability test shown in FIG. 8, data in the memory cell, for example, “1” is written in step S12, and data is not read by reading data after applying the data breakdown voltage Vtest in steps S13 and S14. After the extraction of the stable memory cell, in step S15, data in the reverse direction, for example, “0” is written in the memory cell, and in steps S16 and S17, the data breakdown voltage Vtest is set as in steps S13 and S14. Unstable memory cells are extracted by reading data after application.

  As described above, by performing the reliability test, it is possible to extract a memory cell that is unstable to hold “1” data and a memory cell that is unstable to hold “0” data.

  In the ferroelectric memory according to the third embodiment, by performing the above-described reliability test, memory cells with unstable data retention can be extracted in a short time. It is possible to provide a ferroelectric memory that can be reduced and is inexpensive and highly reliable. Note that this test differs from the first and second embodiments described above in that the time required for the test using the test mode is relatively short, so it may be performed in a wafer state prior to chip formation. In other words, the test method shown in the third embodiment can be performed as a part of the non-defective product selection test before the packaging process.

(Fourth embodiment)
In the ferroelectric memory according to the fourth embodiment of the present invention, the voltage applied to the memory cell during the test mode operation can be set to a desired voltage from the outside of the ferroelectric memory. This will be described with reference to the configuration diagram of FIG.

  The test mode control circuit 12 has a function of setting a voltage between the bit line BL and the plate line PL to a desired voltage during the test mode operation based on a voltage setting signal input from an external test device. When a voltage setting signal is input from the test apparatus, the test mode control circuit 12 receives a voltage (first voltage) applied to the bit line BL according to the voltage setting signal and a voltage (first voltage) applied to the plate line PL. 2). Therefore, in the above-described first to third embodiments, when the test mode operation is performed during the reliability test, the test mode control circuit 12 applies the set voltage so as to apply the set voltage. A, BL driver 15 and PL driver 16 are controlled. As a result, the voltage between the bit line BL and the plate line PL can be set to a desired voltage during the test mode operation.

  As described above, in the ferroelectric memory according to the fourth embodiment, the voltage applied to the memory cell during the test mode operation can be set to a desired voltage from the outside of the ferroelectric memory. . Therefore, the voltage setting applied to the memory cell during the test mode operation can be appropriately changed based on the result of the initial operation test on the ferroelectric memory, and the reliability test can be performed more efficiently. .

1 is a block diagram showing an overall configuration of a ferroelectric memory according to a first embodiment of the present invention. FIG. 3 is a diagram illustrating an example of a circuit configuration of a memory block according to the first embodiment of the present invention. 4 is a diagram showing an example of a normal mode operation of the memory block according to the first exemplary embodiment of the present invention. FIG. 3 is a flowchart showing a test method of a reliability test executed in the ferroelectric memory according to the first embodiment of the present invention. It is a figure which shows an example of the voltage applied to a memory block at the time of the test mode operation | movement which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of the voltage applied to a memory block at the time of the test mode operation | movement which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of the voltage applied to a memory block at the time of the test mode operation | movement of the ferroelectric memory based on the 2nd Embodiment of this invention. 10 is a flowchart showing a test method of a reliability test executed in a ferroelectric memory according to a third embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 12 ... Test mode control time, 13 ... Memory cell array, 100 ... Ferroelectric memory, 200 ... Memory block, C1-C4 ... Ferroelectric capacitor, MC1-MC4 ... Memory cell, Tr1-Tr4 ... Transistor, BLSW ... Block selection Transistor, BL ... bit line, PL ... plate line, WL ... word line.

Claims (5)

A memory block in which a plurality of memory cells configured by connecting both electrodes of a ferroelectric capacitor to the source and drain of a transistor are connected in series;
A plurality of word lines connected corresponding to the gates of the transistors of the memory cell,
A plate line connected to one end of the memory block;
A bit line connected to the other end of the memory block via a block selecting switch element;
A control circuit that controls the plurality of transistors and the block selection switch element in the memory block to simultaneously apply a voltage to two or more of the plurality of ferroelectric capacitors;
A semiconductor memory device comprising:   The control circuit performs on / off control of the plurality of transistors and the block selecting switch element individually and applies a voltage to two or more of the plurality of ferroelectric capacitors simultaneously. The semiconductor memory device according to claim 1.   The control circuit applies a first voltage to the bit line, applies a second voltage having a potential different from the first voltage to the plate line, and applies the first voltage and the second voltage. 3. The semiconductor memory device according to claim 1, wherein the applied state is maintained for a predetermined time. Comprising a memory cell array composed of a plurality of the memory blocks;
The control circuit controls, for a plurality of memory blocks in the memory cell array, the plurality of transistors and block selection switch elements in each memory block, and a plurality of ferroelectrics in the plurality of memory blocks. 2. The semiconductor memory device according to claim 1, wherein a voltage is simultaneously applied to two or more of the capacitors.   The control circuit controls the first voltage applied to the bit line and the second voltage applied to the plate line according to a control signal input from the outside. 3. The semiconductor memory device according to 3.

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