JP2009182951A - Output emphasis adjusting method, and its circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To determine an adjusting value of output emphasis in a short time. <P>SOLUTION: An output emphasis adjusting circuit includes a comparison circuit that allows a threshold voltage to be variable and a latch circuit that latches the output of the comparison circuit in a phase output from a phase variable circuit on a receiving side. The output emphasis adjusting circuit receives a signal from a transmitting side while varying the threshold value of the comparison circuit and the output phase from phase variable circuit on the receiving side. It defines a target waveform in which a pulse width at a mean value of voltages when a receiving signal is 1 and 0 is 1 bit time-width or less and the waveform of the receiving signal and the phase of the maximum voltage are in the same phase, and which is symmetrical in the direction of time axis, and also controls an output emphasis circuit on the signal transmitting side based on the target waveform. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a transmission circuit for high-speed transmission of digital data, and more particularly to a method and circuit for adjusting output emphasis for correcting high-frequency signal amplitude deterioration in a transmission line.

In recent years, data transmission in a server, a storage that stores data, or a router that controls a transmission / reception destination of data has been required to have a transmission rate of several gigabits per second. In such a high-speed transmission, signal attenuation on the transmission line becomes significant, and data may not be accurately read on the receiving side, so an output driver having an output emphasis function is used.

  In order to accurately receive the transmission signal by the receiving circuit, the output emphasis adjustment stage is increased, and there are cases where there are tens of thousands of combinations of adjustment intensities at each output emphasis adjustment position. For this reason, there is a problem that it takes a long time to complete the adjustment in order to obtain all the adjustment values manually and obtain output emphasis that maximizes the receivable range.

  Conventional techniques for solving this problem are known, for example, as described in JP-A-2006-246191 (Patent Document 1) and JP-A-2007-053648 (Patent Document 2).

  In the output emphasis adjustment method described in Japanese Patent Laid-Open No. 2006-246191 (Patent Document 1), a pulse signal (0/1 pattern) having a known amplitude is transmitted from a transmission circuit, and is received at a reception end by a comparator. Measure the amplitude. The coarse adjustment control unit determines a rough adjustment value (coarse adjustment value) of the output emphasis based on the measured amplitude. After that, the output emphasis strength is adjusted by changing the output emphasis strength within the predetermined range from the coarse adjustment value by the fine adjustment control unit, and the output emphasis is adjusted by obtaining the receivable range of the test signal by the reception availability determination unit To do.

  In the output emphasis adjustment method described in Japanese Patent Laid-Open No. 2007-053648 (Patent Document 2), sample data is received from the transmission control unit of the transmission device while changing the output amplitude and output emphasis of the transmitter within a predetermined range. Send. The reception processing unit of the reception device generates an eye diagram from the sample data received by the receiver, detects phase range data that can be received from the eye diagram, and transmits the detected phase range data. The optimization processing unit of the transmission device writes the phase range data transmitted from the reception device to the table corresponding to the output amplitude and output emphasis whose setting has been changed, and is obtained when the setting change within a predetermined range is completed The optimum values of output amplitude and output emphasis are determined from the table and set in the transmitter of the transmitter. Subsequently, the receiving apparatus becomes the transmitting side and sets the optimum values of output amplitude and output emphasis.

JP 2006-246191 A JP 2007-053648 A

Japanese Patent Laid-Open No. 2006-246191 does not consider a frequency higher than the third harmonic because it is optimized only with a frequency that is 1/2 of the maximum transmission rate. For this reason, fine adjustment is required, and it takes time. Further, since a comparator is required in parallel with the receiving circuit, there is a problem that the input capacity is increased and it is difficult to increase the frequency.

  In Japanese Patent Laid-Open No. 2007-053648, when there are many emphasis adjustment locations, there are tens of thousands of combinations of output emphasis, but since it is necessary to obtain eye pattern tables for all of them, a large memory is required. There is a problem that adjustment takes time.

  An object of the present invention is to provide a method and a circuit for determining an adjustment value of output emphasis in a short time by using a circuit that can be used up to a high frequency in order to solve the above problem.

The output emphasis adjusting method and the circuit thereof according to the present invention are configured as follows. The receiving side includes a variable threshold voltage comparison circuit and a latch circuit that latches the output of the comparison circuit with the phase output from the phase variable circuit. The receiving side receives a signal from the transmitting side while changing the threshold voltage of the comparison circuit and the output phase from the phase variable circuit. The pulse width in the average value of the voltage when the received signal is 1 and the voltage when 0 is less than the time width of 1 bit, the phase of the waveform of the received signal and the maximum voltage value is the same phase, and left and right in the time axis direction A symmetrical target waveform is defined, and the output emphasis circuit on the transmission side is controlled based on the target waveform.

According to the present invention, since the output emphasis adjustment value can be determined by using the target waveform, the output emphasis adjustment value can be determined in a short time.

  The best mode for carrying out the output emphasis adjusting method and the circuit thereof according to the present invention will be described using the following embodiments.

FIG. 1 is a block diagram of a transmission circuit including an output emphasis adjusting circuit according to the first embodiment. The transmission circuit in FIG. 1 transmits transmission data 1 from the transmission device 18 to the reception device 19. The transmission data 1 reaches the input of the receiver circuit 4 by being transmitted to the transmission lines 3 a and 3 b by the driver circuit 2.

  FIG. 2 is a diagram showing an output waveform 20 of the driver circuit 2 and an input waveform 21 of the receiver circuit 4. The output waveform 20 is a signal that is 1 only during a 1-bit period, and the period before and after that is 0 for a sufficiently longer period than the 1-bit period. The output waveform 20 receives a high-frequency signal attenuation by the transmission lines 3a and 3b and becomes a dull input waveform 21. The output waveform 20 is shown in phase with the input waveform 21 for comparison.

Here, emphasis will be described with reference to FIG. Here, the emphasis adjustable range is from the bit at time t _{p to} the bit at time t ₂ . When the time advanced by 1 bit from t ₀ is t ₁ , the time advanced by 2 bits from t ₀ is t ₂ , and the time returned by 1 bit from t ₀ is t _p , the waveform of bit 61 of t ₀ ( 1 bit width centered on t ₀ of the waveform. hereinafter, the same call it for other waveforms.) is the effect on the waveform of each bit 62, 63 and 64 at time t _1, t _2, t _p In order to prevent this, as shown in FIG. 6, it is generally performed to improve the input waveform of the receiver circuit 4 by emphasizing the output waveform of the driver circuit 2.

  In this embodiment, as shown in FIG. 1, by providing the phase variable circuit 8 and the comparison circuit 11 having a variable threshold voltage, these values (the phase by the phase variable circuit 8 and the threshold voltage of the comparison circuit 11) are changed. However, 0/1 of the output waveform of the receiver circuit 4 is determined by the latch circuit 5 and stored in the received data 6 (memory area). FIG. 3 shows the stored received data 6 when the output waveform 20 of the driver circuit 2 shown in FIG. 2 is transmitted.

As shown in FIG. 3, in this embodiment, the phase variable circuit 8 can be adjusted in six steps per 1-bit period (horizontal axis), and the comparison circuit 11 has 16 variable threshold voltage ranges (vertical axis). It shall be adjustable. In FIG. 3, a period corresponding to 5 bits is shown for explanation. While changing the latch phase and threshold voltage using these, the data received by the latch of the latch circuit 5 becomes the 0/1 determination result as shown in FIG. A waveform 30 is obtained by connecting points of 0/1 switching. The waveform 30 reconstructed in this way is a waveform obtained by sampling and quantizing the input waveform 21. Here, assuming that the reconstructed received waveform 30 is a function of time t, this is represented as f (t). The time at which f (t) takes the maximum value is t ₀ .

Next, a target waveform g (t) that can take the widest phase of the latch is defined from f (t ₀ ) and a transmission rate (transmission speed, bit width that is an inverse number). In this embodiment, a Gaussian curve represented by the following equation is used as an example of the target waveform g (t). A is an amplitude f (t ₀ ), and B is a constant that determines the pulse width (bit width).

Also, the difference between f (t) and g (t) at time t is d (t), and the emphasis that the control circuit 10 feeds back to the output-side emphasis control unit 9 as shown in FIG. 7A. an adjustment value, at time _{t 1 d (t 1) 23} , the time _{t 2} Niite _{d (t 2) 24, d} (t 3) at time _{t 3} (not shown), at time _{t p} d _{(t p)} 25. Here, the difference d (t) is described as being fed back as it is, but k · d (t) (k is a constant) is fed back in terms of mounting.

As shown in FIG. 7B, when the output emphasis adjustment value is changed, the waveform of f (t) changes. When this changed waveform is newly set as f ′ (t), a new target waveform g ′ (t) is obtained from f ′ (t). When the difference between f ′ (t) and g ′ (t) at time t is d ′ (t), the emphasis adjustment value fed back to the output-side emphasis control unit 9 by the control circuit 10 is the time t ₁ . _{d (t 2) '(t} 1), d at time t _2', emphasis adjustment value at time t ₃ is the d '(t _3). Although the time elapses between FIGS. 7A and 7B, the center time of the predetermined bit section of the transmission waveforms 20 and 20 ′ is t ₀ for easy understanding.

  Similarly, the output emphasis adjustment is performed a predetermined number of times, so that the difference between the received waveform and the target waveform can be set within an allowable range set in advance.

Further, when receiving the waveform of the actual data after adjustment, as shown in FIG. 8, the phase at which the target waveform is located at the time t ₀ is set as the phase of the latch 5 on the receiving side, and is 1 for a sufficient time. signal of the DC voltage V _hi, the DC voltage of the signal is zero for a time sufficient as V _lo, by the threshold voltage of the comparator circuit 11 the average value of the V _hi and V _lo, latches the phase and threshold The voltage can be determined.

  FIG. 4 is a flowchart showing the output emphasis adjusting method according to the first embodiment. Since the explanation will be repeated, make it simple. First, the allowable value of the difference between the received waveform and the target waveform and the maximum number of repetitions of the following processing are set (S100).

  The change point of 0/1 is measured while changing the phase and threshold voltage, and a reception data table (FIG. 3) is created (S105). A received waveform is reconstructed from the contents of the received data table (S110). A target waveform is defined from the reconstructed received waveform and 1-bit width (S115). An output emphasis adjustment value corresponding to the difference between the received waveform and the target waveform is fed back to the output emphasis control unit 9 (S120). It is determined whether the difference between the received waveform and the target waveform is less than or equal to an allowable value, and whether the number of repetitions of the processes of S105 to S120 exceeds the maximum number of repetitions. If neither is satisfied, the process returns to S105 and the process is repeated. When either one is satisfied, the latch phase and the threshold voltage of the comparison circuit set in S105 at that time are adopted.

  According to the present embodiment, the adjustment value of output emphasis can be set in a short time.

In order to reduce the difference between the received waveform f (t) 21 and the target waveform g (t) 22 in a shorter time than in the first embodiment, using the same configuration as in the first embodiment, as shown in FIG. The amount of feedback to the part is an amount proportional to the integral value of the difference. The control circuit 10 includes first difference integrated value 26 in the bit period of the time t ₁ at bit time width and f (t) and g (t), the difference between the integral value of the bit period from the time t ₂ 27, and the time An adjustment value of output emphasis is set by negatively feeding back an amount proportional to the integral value 28 of the difference in the bit period of t _p to the output waveform.

  According to the present embodiment, the output emphasis adjustment value can be set in a shorter time than the first embodiment.

Using the same configuration as that of the first embodiment, as shown in FIG. 9, the threshold voltage for 0/1 determination of the received data is changed by the comparison circuit 11, and the phase of the latch 5 is changed by the phase variable circuit 8. When the waveform 30 is reconstructed based on the switching point of 0/1, the number of times of measurement of the switching point of 0/1 is, for example, 100 times, and the voltage at which the number of times determined to be 1 exceeds 50 times The received waveform 30 is reconstructed as the threshold voltage.

  According to the present embodiment, by increasing the number of times of measurement, it is possible to remove a temporary influence on the reconstructed received waveform (an influence due to temporary noise, etc.), so that the target waveform can be accurately determined, and the result As a result, the adjustment value of the output emphasis can be set in a short time.

  According to the best mode for carrying out the present invention, it is possible to set an adjustment value of output emphasis in a short time without using a large memory capacity by using a circuit that can be used up to a high frequency without increasing the input capacity. .

FIG. 3 is a transmission circuit block diagram including an output emphasis adjustment circuit according to the first exemplary embodiment. It is the figure which showed the output waveform of the driver circuit, and the input waveform of the receiver circuit. It is a figure which shows the received data in which the received waveform was determined 0/1 and stored. It is a flowchart of an output emphasis adjustment method. It is explanatory drawing of making the amount proportional to the integral value of the difference of Example 2 into a feedback amount. It is explanatory drawing of an output emphasis adjustment range. It is explanatory drawing of repetition of output emphasis adjustment. It is explanatory drawing regarding the phase and threshold voltage of a latch. It is explanatory drawing of reconstruction of the received waveform of Example 3. FIG.

Explanation of symbols

1: Transmission data,
2: driver circuit, 3a, 3b: transmission line, 4: receiver circuit, 5: latch circuit, 6: received data, 7: clock, 8: phase variable circuit, 9: output emphasis control unit, 10: control circuit, 11 : Comparison circuit with variable threshold voltage, 18: Transmitter, 19: Receiver, 20: Output waveform of driver circuit, 21: Input waveform of receiver circuit, 22: Target waveform.

Claims (16)

  An output emphasis circuit on the transmission side, a comparison circuit having a variable threshold voltage on the reception side, and a latch circuit that latches an output of the comparison circuit with a phase output from the phase variable circuit, and a threshold voltage of the comparison circuit on the reception side And a signal from the transmitting side while changing the output phase from the phase variable circuit, and the pulse width in the average value of the voltage when the received signal is 1 and the voltage when 0 is 1 bit. A target waveform whose phase of the received signal waveform and the maximum voltage value is the same phase and symmetrical in the time axis direction is defined below the time width, and the output emphasis circuit on the transmission side is controlled based on the target waveform An output emphasis adjustment method characterized by the above.   2. The output emphasis adjusting method according to claim 1, wherein the threshold voltage and the phase latched by the latch circuit are set based on the phase and voltage of the target waveform.   3. The output emphasis adjustment method according to claim 2, wherein when the target waveform is defined, a signal obtained by reconstructing the reception signal is used as the reception signal.   4. The output emphasis adjustment method according to claim 3, wherein the reconstructed signal is reconstructed based on a 1/0 determination result obtained by latching the received signal in the latch circuit.   5. The output emphasis adjustment method according to claim 4, wherein the 1/0 determination result is based on a predetermined ratio of 1/0 latched by the latch circuit.   5. The output emphasis adjustment method according to claim 4, wherein the output emphasis circuit is controlled so that a difference between the waveform of the reconstructed signal and the target waveform is equal to or less than a predetermined value.   The output emphasis adjustment according to claim 6, wherein the difference between the waveform of the reconstructed signal and the target waveform is a voltage difference in each bit section of the reconstructed signal in an emphasis adjustable range. Method.   The difference between the waveform of the reconstructed signal and the target waveform is a difference in an integral value of a voltage in each bit section of the reconstructed signal in an emphasis adjustable range. Output emphasis adjustment method.   A comparison circuit with variable threshold voltage for inputting a signal while changing the threshold voltage, a latch circuit for latching the output of the comparison circuit with the phase output from the phase variable circuit, and a voltage when the signal is 1 and 0 Define a target waveform whose pulse width is equal to or less than the time width of one bit with respect to the average voltage of the signal, the waveform of the signal and the phase of the maximum voltage value are in phase, and symmetrical in the time axis direction, and based on the target waveform. And an output emphasis adjusting circuit having a control circuit for controlling the output emphasis circuit on the transmitting side.   The output emphasis adjustment circuit according to claim 9, wherein the control circuit sets the threshold voltage and a phase latched by the latch circuit based on a phase and a voltage of the target waveform.   11. The output emphasis adjustment circuit according to claim 10, wherein when the target waveform is defined, the control circuit uses a signal obtained by reconstructing the signal as the signal.   12. The output emphasis adjustment circuit according to claim 11, wherein the control circuit reconstructs the reconstructed signal based on a 1/0 determination result obtained by latching the signal in the latch circuit.   13. The output emphasis adjustment circuit according to claim 12, wherein the control circuit obtains the 1/0 determination result based on a predetermined ratio of 1/0 latched by the latch circuit.   13. The output emphasis adjustment circuit according to claim 12, wherein the control circuit controls the output emphasis circuit so that a difference between a waveform of the reconstructed signal and the target waveform is equal to or less than a predetermined value.   15. The output emphasis adjustment according to claim 14, wherein the difference between the waveform of the reconstructed signal and the target waveform is a voltage difference in each bit section of the reconstructed signal in an emphasis adjustable range. circuit.   15. The difference between the waveform of the reconstructed signal and the target waveform is a difference in integral value of a voltage in each bit section of the reconstructed signal in an emphasis adjustable range. Output emphasis adjustment circuit.

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