JP2009182835A - Decoder and communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve throughput by increasing the speed of decoding processing. <P>SOLUTION: The decoder includes a code word shift series generation part 12 for generating a plurality of code word shift series by shifting bits of the code word series; a syndrome series generation part 13 for generating a syndrome series by EXCLUSIVE-OR of the bits in the code word series and the code word shift series; a syndrome shift series generation part 14 for generating a plurality of syndrome shift series by shifting the bits of the syndrome shift series; and an error series generation part 15 for generating an error series by executing bitwise logic operation in the syndrome series and the syndrome shift series. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a decoding device that receives a codeword sequence that has been subjected to error correction coding using an error correction code and corrects an error in the codeword sequence, and a communication system that implements the decoding device. Is.

In a conventional communication system that employs an error correction code, generally, error correction coding of data is performed using an error correction code, and a codeword sequence that is the error correction coding result of the data is placed on a communication path. An error correction coding device for transmission and a decoding device for receiving a codeword sequence transmitted from the error correction coding device, correcting an error in the codeword sequence, and reproducing data are configured.
Note that the decoding device may include an error in the codeword sequence due to noise superimposed on the codeword sequence on the communication channel or intentional tampering by an attacker. Error correction of word sequence.

A general encoding process in the error correction encoding apparatus will be described.
However, in order to simplify the description, a 0 flat EG (2, 2 ^ 2) code is used here. EG is an abbreviation for “Euclidean geometry”.
Hereinafter, unless otherwise specified, all are expressed on Galois field 2 (GF (2) = {0, 1}).

Here, an information sequence u of length k = (u _k−1 ,..., U ₁ , u ₀ ) to a codeword sequence w of length n = (w _n−1 ,..., W ₁ , Let w ₀ ) be generated.
In the case of a 0 flat EG (2, 2 ^ 2) code, for example, n = 15 and G (x) = x ⁸ + x ⁷ + x ⁶ + x ⁴ +1 corresponds to the generator polynomial of the code word sequence w.
A circulant matrix obtained from the generator polynomial G (x) is converted into a matrix in the following equation (1) by the Gaussian elimination method.

For example, if the information sequence is u = (1, 1, 0, 1, 0, 0, 1), the codeword sequence w is expressed by the following equation (1).

When only the 7 × 8 matrix, which is the parity part, is extracted from the matrix of Expression (1), the codeword sequence w becomes as shown in Expression (2) below.

As is clear from the above, each column in the matrix of the following formula (3) is stored in a register, whether it is encoded by software or hardware, and the value of each column and the information sequence It can be seen that the codeword sequence w can be generated from the information sequence u by obtaining the exclusive OR of u.

Next, a decoding process in the decoding device will be described.
When the generator polynomial of the code word sequence w is G (x) = x ⁸ + x ⁷ + x ⁶ + x ⁴ +1, the check polynomial H (x) becomes “x ⁷ + x ³ + x + 1”, so that the code word sequence w is checked The matrix is as shown in Equation (4) below.

When receiving the codeword sequence w transmitted from the error correction encoding device, the decoding device stores the codeword sequence w in a register and extracts a target bit for syndrome calculation from the register as shown in FIG. Thus, an exclusive OR of the target bits is calculated (see, for example, Patent Document 1).
Then, the decoding device determines the result of the exclusive OR by a majority operation.
That is, when the result of the exclusive OR operation is “1”, it is judged to be incorrect, and when it is “0”, it is judged to be correct. If so, the corresponding bit is determined to be an error.
In the example of FIG. 5, since syndrome calculation and majority operation are performed for each corresponding bit, 15-bit shift operation, 16 exclusive OR operations, and 3 addition operations (4 inputs) for majority operation And two or more logical operations for determination are required.

JP-A-9-130271 (FIG. 5)

  Since the conventional decoding apparatus is configured as described above, in order to correct an error in the codeword sequence transmitted from the error correction encoding apparatus, a number of operations must be performed, and the decoding process can be performed at high speed. There was a problem that it was difficult to make it easier.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a decoding device and a communication system that can increase the throughput by realizing high-speed decoding processing.

  The decoding device according to the present invention shifts the bits of the codeword sequence by a shift amount corresponding to the parity check polynomial of the codeword sequence that is error-corrected encoded using the error correction code, and converts a plurality of codeword shift sequences. Codeword shift sequence generating means for generating, syndrome sequence generating means for generating a syndrome sequence by performing exclusive OR operation between bits in the codeword sequence and the codeword shift sequence, and a shift corresponding to the check polynomial Syndrome shift sequence generation means for generating a plurality of syndrome shift sequences by shifting the bits of the syndrome sequence by a quantity, and an error sequence for generating an error sequence by performing a logical operation between the bits in the syndrome sequence and the syndrome shift sequence Generating means, and the error correcting means uses the error sequence generated by the error sequence generating means. , In which so as to correct errors in the codeword sequence.

  According to the present invention, a plurality of codeword shift sequences are generated by shifting bits of a codeword sequence by a shift amount corresponding to a check polynomial of a codeword sequence that has been error correction encoded using an error correction code. Codeword shift sequence generation means, syndrome sequence generation means for generating a syndrome sequence by performing exclusive OR operation between bits in the codeword sequence and the codeword shift sequence, and a shift amount according to the check polynomial Syndrome shift sequence generation means for generating a plurality of syndrome shift sequences by shifting the bits of the syndrome sequence, and an error sequence generation means for generating an error sequence by performing a logical operation between bits in the syndrome sequence and the syndrome shift sequence And the error correction means uses the error sequence generated by the error sequence generation means, Since it is configured so as to correct an error of the issue codeword sequence, to achieve faster decoding processing, there is an effect that can increase the throughput.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a communication system according to Embodiment 1 of the present invention. In FIG. 1, an error correction coding apparatus 1 uses data that is an error correction code that is a cyclic code or a pseudo cyclic code. Error correction coding of the sequence u is performed, and a code word sequence w that is an error correction coding result of the information sequence u is transmitted on the communication path 2.
The decoding device 3 is connected to the error correction coding device 1 via the communication path 2 and receives the codeword sequence transmitted from the error correction coding device 1 and corrects the error of the codeword sequence. The information series u is reproduced.
In the first embodiment, the error correction coding apparatus 1 uses a length k information sequence u = (u _k−1 ,..., U ₁ , u ₀ ) to a length n codeword sequence w = (w _n−1 ,..., w ₁ , w ₀ ) are generated and the codeword sequence w is transmitted on the communication path 2, but the error vector e = (e _n−1 , .., E ₁ , e ₀ ) are superimposed on the codeword sequence w, the decoding device 3 receives y = w + e as the codeword sequence.

FIG. 2 is a block diagram showing a decoding apparatus according to Embodiment 1 of the present invention.
In FIG. 2, the codeword sequence reception unit 11 performs a process of receiving a codeword sequence y ⁰ (y = w + e) transmitted from the error correction coding apparatus 1. “0” on the right shoulder of y ⁰ indicates that the bits of the codeword sequence are not shifted. The codeword sequence receiving unit 11 constitutes a codeword sequence receiving unit.

The codeword shift sequence generation unit 12 shifts by a shift amount (a power of the check polynomial H (x) corresponding to the check polynomial H (x) of the codeword sequence y ⁰ received by the codeword sequence reception unit 11. an amount), shifts the bits of the codeword sequence y ^0, and carries out a process of generating a plurality of code word shifted sequences ^{y 1, y 3, y 7} . y ^{1, y} 3, "1" bit is 1 bit codeword sequence ^{y 0} in the right shoulder of ^{y 7,} "3" bit 3 bit codeword sequence ^{y 0,} the "7" codeword sequence y It shows that the ⁰ bit is shifted to the right by 7 bits. The codeword shift sequence generator 12 constitutes a codeword shift sequence generator.

The syndrome sequence generation unit 13 excludes bits in the code word sequence y ⁰ received by the code word sequence reception unit 11 and the code word shift sequences y ¹ , y ³ , y ⁷ generated by the code word shift sequence generation unit 12. A process of generating a syndrome series s ⁰ by performing a logical OR operation is performed. “0” on the right shoulder of s ⁰ indicates that the bits of the syndrome series are not shifted. The syndrome series generation unit 13 constitutes a syndrome series generation unit.

Shift syndrome shift sequence generating unit 14 for shifting by the number of powers of the shift amount corresponding to the check polynomial H codeword sequence y ^0, which is received by the codeword sequence receiving unit 11 (x) (check polynomial H (x) ), A process of generating a plurality of syndrome shift sequences s ⁻¹ , s ⁻³ , and s ⁻⁷ is performed by shifting the bits of the syndrome sequence s ⁰ generated by the syndrome sequence generation unit 13. “−1” on the right shoulder of s ⁻¹ , s ⁻³ , and s ⁻⁷ is 1 bit for the syndrome sequence s ⁰ , “−3” is 3 bits for the syndrome sequence s ⁰ , and “ ⁻⁷ ” is It shows that the bits of the syndrome series s ⁰ are shifted to the left by 7 bits. The syndrome shift sequence generation unit 14 constitutes a syndrome shift sequence generation unit.

The error sequence generation unit 15 performs a logical operation between bits in the syndrome sequence s ⁰ generated by the syndrome sequence generation unit 13 and the syndrome shift sequences s ⁻¹ , y ⁻³ , and y ⁻⁷ generated by the syndrome shift sequence generation unit 14. To generate an error sequence DEC. Note that the error sequence generation unit 15 constitutes an error sequence generation means.
The error correction unit 16 uses the error sequence DEC generated by the error sequence generation unit 15 to perform a process of correcting the error of the codeword sequence y ⁰ received by the codeword sequence reception unit 11. The error correction unit 16 constitutes error correction means.

Next, the operation will be described.
In the first embodiment, all cases are expressed on Galois field 2 (GF (2) = {0, 1}) unless otherwise specified.

The error correction coding apparatus 1 performs error correction coding of an information sequence u using an error correction code that is a cyclic code or a pseudo cyclic code, and a codeword sequence that is an error correction coding result of the information sequence u w is transmitted on the communication path 2.
That is, the error correction coding apparatus 1 uses a length k information sequence u = (u _k−1 ,..., U ₁ , u ₀ ) to a length n code word sequence w = (w _n−1 , .., W ₁ , w ₀ ) are generated, and the codeword sequence w is transmitted on the communication path 2.
In the case of a 0 flat EG (2, 2 ^ 2) code, for example, n = 15 and G (x) = x ⁸ + x ⁷ + x ⁶ + x ⁴ +1 corresponds to the generator polynomial of the code word sequence w.

On the communication path 2, there is a possibility that the codeword sequence w contains an error by superimposing noise on the codeword sequence w or intentionally falsifying the attacker.
Assuming that an error vector indicating an error included in the codeword sequence w is e = (e _n−1 ,..., E ₁ , e ₀ ), the decoding device 3 receives the codeword sequence y = w + e. Is done.

Here, if the check matrix H of the EG code is a square matrix and a cyclic code, and the codeword sequence y = w + e is received by the decoding device 3, the syndrome sequence s is obtained by s = H · y.
The check polynomial H (x) corresponding to the generator polynomial G (x) used when the error correction encoding apparatus 1 performs error correction encoding is as follows, and w _{i + 7} + w _{i + 3} + w _{i + 1} + w _i = 0. , I = 0, 1,..., N−1 is established.
H (x) = x ⁷ + x ³ + x ¹ + x ⁰ (5)
On the other hand, the syndrome series s _i can be expressed as follows.
s _i = e _{i + 7} + e _{i + 3} + e _{i + 1} + e _i = 0, i = 0, 1,..., n−1
(6)
However, i considers n to be a modulus. That is, i (mod n) is considered.

Although details of the processing contents of the decoding device 3 will be described later, in the decoding device 3, when calculating the syndrome sequence s from the above relationship, the code word sequence y is shifted by a shift amount corresponding to the check polynomial H (x). shifts the bits to generate a codeword shifted sequences of the next few minutes (including one codeword sequence y ⁰ that does not shift the bits) of check polynomial H (x).
That is, J = 4 series y ⁰ , y ¹ , y ³ , y ⁷ which is the total number of coefficients 1 of the check polynomial H (x) is generated.
y ⁰ = (y _n−1 , y _n−2 ,..., y ₁ , y ₀ )
y ¹ = (y ₀ , y _n−1 ,..., y ₂ , y ₁ )
y ³ = (y ₂ ,..., y ₀ , y _n−1 ,..., y ₄ , y ₃ )
y ⁷ = (y ₆ ,..., y ₀ , y _n−1 ,..., y ₈ , y ₇ )
(7)
Here, y ^j indicates a code word shift sequence (code word vector) in which the bits of the code word sequence y ⁰ are shifted right by j.

By performing an exclusive OR operation for each bit of the same element number in these sequences y ⁰ , y ¹ , y ³ , y ⁷ , a syndrome sequence s _i is obtained (w in the received codeword sequence y This is because the calculation result of the component is “0”).
Hereinafter, the syndrome vector of the syndrome series s _i is s = (s ₀ , s ₁ ,..., S _n−1 ).
The number of shift instructions required to calculate the syndrome series s _i is 3 (= J−1 = 4-1), and the number of exclusive OR instructions is 3 (= J−1 = 4-1). is there.

Next, in the decoding device 3, as shown in the following equation (8), the syndrome orthogonal to the position p (p = 0, 1,..., N−1) of the received codeword sequence y is shown. combine to represent a vector s _p, performs determining majority logic decoding whether the bit position p of the codeword sequence y is incorrect.
_{s p = (s -p, s} 1-p, s 3-p, s 7-p) (8)
E _p = maj [s _p , 0] (9)
Here, maj [●] is a majority function that takes the value of the majority of either “0” or “1” in the set ●.
If the value of the majority function E _p is “0”, the decoding device 3 determines that the bit at the position p is correct, and if the value of the majority function E _p is “1”, the bit at the position p is incorrect. judge. In the case of a 0 flat EG (2, 2 ^ 2) code, “1” is 3 or more and 4 or less, and the bit at the position p is an error.

That is, when performing the majority logic decoding, the decoding device 3 shifts the bits of the syndrome sequence s and sets the syndrome shift sequence corresponding to the order of the parity check polynomial H (x) (the syndrome sequence s ⁰ with no bits shifted to 1). Are included).
That is, J = 4 sequences s ⁰ , s ⁻¹ , s ⁻³ , and s ⁻⁷ that are the total number of coefficients 1 of the check polynomial H (x) are generated.
s ⁰ = (s _n−1 , s _n−2 ,..., s ₁ , s ₀ )
s ⁻¹ = (s _n−2 , s _n−3 ,..., s ₀ , s _n−1 )
s ⁻³ = (s _n−4 ,..., s ₀ , s _n−1 ,..., s _n−2 , s _n−3 )
s ⁻⁷ = (s _n−8 ,..., s ₀ , s _n−1 ,..., s _n−6 , s _n−7 )
(10)
Here, s ^−j indicates a syndrome shift sequence (syndrome vector) in which the bits of the syndrome sequence s ⁰ are shifted left by j.
By performing a logical operation such as exclusive OR or logical product operation for each bit of the same element number in these sequences s ⁰ , s ⁻¹ , s ⁻³ , s ⁻⁷ , the position p of the codeword sequence y It is possible to calculate an error sequence DEC that is an error vector indicating whether or not the bits in are incorrect.

Hereinafter, the processing content of the decoding apparatus 3 is demonstrated concretely.
The codeword sequence reception unit 11 transmits the codeword sequence y = w + e transmitted from the error correction coding apparatus 1, that is, the codeword sequence y ⁰ = (y _n−1 , y _n−2 ,..., Y _1. , Y ₀ ).
Codeword shift sequence generator 12, the codeword sequence receiving unit 11 receives a codeword sequence y ^0, only a few minutes to a shift amount corresponding to the check polynomial H (x) (check polynomial H (x) shifted shift amount) that, by shifting the bits of the codeword sequence ^{y 0,} to produce a plurality of code word shifted sequences ^{y 1, y 3, y 7} .

When the codeword shift sequence generation unit 12 generates the codeword shift sequences y ¹ , y ³ , and y ⁷ , the syndrome sequence generation unit 13 receives the codeword sequence y ⁰ and the codeword shift received by the codeword sequence reception unit 11. A syndrome series s ⁰ is generated by performing an exclusive OR operation of bits in the codeword shift series y ¹ , y ³ , y ⁷ generated by the sequence generator 12.
Hereinafter, the processing contents of the codeword shift sequence generation unit 12 and the syndrome sequence generation unit 13 will be specifically described.
FIG. 3 is an explanatory diagram showing the processing contents of the codeword shift sequence generation unit 12 and the syndrome sequence generation unit 13.

First, the codeword shift sequence generation unit 12 registers the codeword sequence y ⁰ = (y _n−1 , y _n−2 ,..., Y ₁ , y ₀ ) received by the codeword sequence reception unit 11. Store in (1).
Also, codeword shift sequence generator 12, using a barrel shifter, by 1 bit shifted codeword sequence ^{y 0} to the right, the code word shift sequences _{^{y 1 = (y 0, y}} n-1, ··· , Y ₂ , y ₁ ), and the codeword shift sequence y ¹ is stored in the register (2).

Syndrome series generation unit 13, the code word shift sequence generator 12 stores the codeword sequence y ⁰ in the register (1), and stores the code word shifted sequences y ¹ in the register (2), the following equation (11) exclusive OR operation bit units as shown in, i.e., the register (1) and bit codeword sequence y ⁰ that is stored in the bits of the code word shifted sequences y ¹ stored in the register (2) And the result of the operation is stored in the register (1).
y ⁰ EXOR y ¹ (11)
Here, EXOR is a symbol indicating an exclusive OR operation.

When the syndrome sequence generation unit 13 stores the result of the exclusive OR operation in the register (1), the codeword shift sequence generation unit 12 uses the barrel shifter to store the codeword shift sequence stored in the register (2). By shifting y ¹ to the right by 2 bits, a codeword shift sequence y ³ = (y ₂ ,..., y ₀ , y _n−1 ,..., y ₄ , y ₃ ) is generated, and stores the code word shift sequence y ³ in the register (2).

Syndrome series generation unit 13, the code word shift sequence generator 12 stores the code word shift sequence y ³ in the register (2), exclusive OR operation bit units as shown in the following equation (12), i.e. , a bit of the previous exclusive OR operation result stored in the register (1), an exclusive OR operation on the bit of the code word shift sequence y ³ stored in the register (2) was performed, The calculation result is stored in the register (1).
(Y ⁰ EXOR y ¹ ) EXOR y ³ (12)

When the syndrome sequence generation unit 13 stores the result of the exclusive OR operation in the register (1), the codeword shift sequence generation unit 12 uses the barrel shifter to store the codeword shift sequence stored in the register (2). A codeword shift sequence y ⁷ = (y ₆ ,..., y ₀ , y _n−1 ,..., y ₈ , y ₇ ) is generated by shifting y ³ to the right by 4 bits, and stores the code word shift sequence y ⁷ to the register (2).

Syndrome series generation unit 13, the code word shift sequence generator 12 stores the code word shift sequence y ⁷ to the register (2), exclusive OR operation bit units as shown in the following equation (13), i.e. , a bit of the previous exclusive OR operation result stored in the register (1), an exclusive OR operation on the bit of the code word shift sequence y ⁷ which is stored in the register (2) was performed, The calculation result is stored in the register (1) as a syndrome series s ⁰ = (s _n−1 , s _n−2 ,..., S ₁ , s ₀ ).
((Y ⁰ EXOR y ¹ ) EXOR y ³ ) EXOR y ⁷
(13)

When the syndrome sequence generation unit 13 stores the syndrome sequence s ⁰ in the register (1), the syndrome shift sequence generation unit 14 reads out the syndrome sequence s ⁰ from the register (1) and shifts according to the check polynomial H (x). A plurality of syndrome shift sequences s ⁻¹ , s ⁻³ , and s ⁻⁷ are generated by shifting the bits of the syndrome sequence s ^{0 by} an amount (a shift amount that is shifted by an exponent of the check polynomial H (x)). To do.

When the syndrome shift sequence generation unit 14 generates the syndrome shift sequences s ⁻¹ , y ⁻³ , and y ⁻⁷ , the error sequence generation unit 15 generates the syndrome sequence s ⁰ and the syndrome shift sequence generated by the syndrome sequence generation unit 13. An error sequence DEC is generated by performing a logical operation between bits in the syndrome shift sequences s ⁻¹ , y ⁻³ , and y ⁻⁷ generated by the unit 14.
The processing contents of the syndrome shift sequence generation unit 14 and the error sequence generation unit 15 will be specifically described below.
FIG. 4 is an explanatory diagram showing processing contents of the syndrome shift sequence generation unit 14 and the error sequence generation unit 15.

First, the syndrome shift sequence generation unit 14 reads out the syndrome sequence s ⁰ = (s _n−1 , s _n−2 ,..., S ₁ , s ₀ ) stored in the register (1) of FIG. The syndrome series s ⁰ is stored in the register SUM (0) in FIG.
Further, the syndrome shift sequence generation unit 14 shifts the syndrome sequence s ⁰ by 1 bit to the left by using a barrel shifter, so that the syndrome shift sequence s ⁻¹ = (s _n−2 , s _n−3 ,. ., S ₀ , s _n-1 ) are generated, and the syndrome shift sequence s ^-1 is stored in the register S of FIG.

When the syndrome shift sequence generation unit 14 stores the syndrome sequence s ⁰ in the register SUM (0) and the syndrome shift sequence s ⁻¹ in the register S, the error sequence generation unit 15 indicates as shown in the following equation (14). Bitwise exclusive OR operation, that is, exclusive OR of the bits of the syndrome sequence s ⁰ stored in SUM (0) and the bits of the syndrome shift sequence s ⁻¹ stored in the register S The calculation is performed, and the calculation result is stored in SUM (0).
s ⁰ EXOR s ⁻¹ (14)

In addition, the error sequence generation unit 15 performs bitwise AND operation as shown in the following equation (15) simultaneously with the exclusive OR operation of equation (14), that is, the syndrome stored in SUM (0). An AND operation is performed on the bits of the sequence s ^{0 and} the bits of the syndrome shift sequence s ⁻¹ stored in the register S.
s ⁰ AND s ⁻¹ (15)
However, AND is a symbol indicating a logical product operation.

  Further, the error sequence generation unit 15 calculates the bit of the logical product operation result of Expression (15) and the bits stored in the register SUM (1) (all bits are initialized to “0”). An exclusive OR operation is performed, and the operation result is stored in SUM (1). Therefore, at this stage, the logical product operation result of Expression (15) is stored in SUM (1).

Next, the syndrome shift sequence generation unit 14 shifts the syndrome shift sequence s ⁻¹ stored in the register S by 2 bits to the left by using a barrel shifter, so that the syndrome shift sequence s ⁻³ = (s _{n− 4, ···, s 0, s} n-1, ···, s n-2, s n-3) to generate and store the syndrome shift sequence ^{s -3} to register S.

When the syndrome shift sequence generation unit 14 stores the syndrome shift sequence s- ³ in the register S, the error sequence generation unit 15 performs a bitwise exclusive OR operation as shown in the following equation (16), that is, SUM ( 0), an exclusive OR operation is performed on the bit of the exclusive OR operation result of the expression (14) stored in 0) and the bit of the syndrome shift sequence s- ³ stored in the register S, and the operation The result is stored in SUM (0).
(S ⁰ EXOR s ^-1 ) EXOR s ^-3 (16)

In addition, the error sequence generation unit 15 performs the bitwise AND operation as shown in the following equation (17) simultaneously with the exclusive OR operation of the equation (16), that is, the equation stored in the SUM (0). The logical product operation of the bit of the exclusive OR operation result of (14) and the bit of the syndrome shift sequence s ^-3 stored in the register S is performed.
(S ⁰ EXOR s ^-1 ) AND s ^-3 (17)

Further, the error sequence generation unit 15 stores the bitwise exclusive OR operation as shown in the following equation (18), that is, the bit of the logical product operation result of the equation (17) and the SUM (1). The exclusive OR operation with the bit of the logical product operation result of Expression (15) is performed, and the result of the operation is stored in SUM (1).
((S ⁰ EXOR s ^-1 ) AND s ^-3 )
EXOR (s ⁰ AND s ⁻¹ )
(18)

Next, the syndrome shift sequence generation unit 14 shifts the syndrome shift sequence s ⁻³ stored in the register S by 4 bits to the left by using a barrel shifter, so that the syndrome shift sequence s ⁻⁷ = (s _{n− 8, ···, s 0, s} n-1, ···, and generates an _{s n-6, s n-} 7), and stores the syndrome shift sequence ^{s -7} to register S.

When the syndrome shift sequence generation unit 14 stores the syndrome shift sequence s ⁻⁷ in the register S, the error sequence generation unit 15 performs a bitwise exclusive OR operation as shown in the following equation (19), that is, SUM ( 0) The exclusive OR operation of the bit of the exclusive OR operation result of the expression (16) stored in 0) and the bit of the syndrome shift sequence s- ⁷ stored in the register S is performed, and the operation The result is stored in SUM (0).
((S ⁰ EXOR s ^-1 ) EXOR s ^-3 ) EXOR s ^-7
(19)
Hereinafter, the exclusive OR operation of Expression (19) is referred to as “first logical operation”.

In addition, the error sequence generation unit 15 performs bitwise AND operation as shown in the following equation (20), that is, the equation stored in SUM (0) simultaneously with the exclusive OR operation of equation (19). The logical product operation of the bit of the exclusive OR operation result of (16) and the bit of the syndrome shift series s ^{− 7} stored in the register S is performed.
((S ⁰ EXOR s ^-1 ) EXOR s ^-3 ) AND s ^-7
(20)

Further, the error sequence generation unit 15 stores the bitwise exclusive OR operation as shown in the following equation (21), that is, the bit of the AND operation result of the equation (20), and the SUM (1). The exclusive OR operation with the bit of the exclusive OR operation result of Expression (18) is performed, and the operation result is stored in SUM (1).
(((S ⁰ EXOR s ^-1 ) EXOR s ^-3 ) AND s ^-7 )
EXOR
(((S ⁰ EXOR s ^-1 ) AND s ^-3 )
EXOR (s ⁰ AND s ⁻¹ ))
(21)
Hereinafter, the exclusive OR operation of Expression (21) is referred to as “second logical operation”.

Further, the error sequence generation unit 15 stores the bitwise logical product operation as shown in the following equation (22), that is, the bit of the logical product operation result of the equation (20) and SUM (1). The logical product operation with the bit of the exclusive OR operation result of Expression (18) is performed, and the operation result is stored in SUM (2).
(((S ⁰ EXOR s ^-1 ) EXOR s ^-3 ) AND s ^-7 )
AND
(((S ⁰ EXOR s ^-1 ) AND s ^-3 )
EXOR (s ⁰ AND s ⁻¹ ))
(22)
Hereinafter, the logical product operation of Expression (22) is referred to as a “third logical operation”.

When the first logical operation, the second logical operation, and the third logical operation are performed as described above, the error sequence generation unit 15 performs the first logical operation result and the second logical operation as described below. By calculating the logical product of the logical operation result and calculating the logical sum of the logical product result and the third logical operation result, it is possible to determine whether or not the bit at the position p of the code word sequence y is incorrect. Error vector).
Error sequence DEC
= Third logical operation result OR (first logical operation result AND second logical operation result)
(23)

Error correction unit 16, the error sequence generating unit 15 generates an error sequence DEC, by using the error sequence DEC, correcting errors in the received codeword sequence y ⁰ by codeword sequence receiving unit 11.
That is, the error correcting unit 16, the error sequence DEC generated by the error sequence generation unit 15, obtains an exclusive OR of the code word sequence y ^0, which is received by the codeword sequence receiving unit 11, the exclusive OR Is output as an error correction result w.

  As is apparent from the above, according to the first embodiment, the bits of the codeword sequence are shifted by the shift amount corresponding to the parity check polynomial of the codeword sequence that has been error correction encoded using the error correction code. A codeword shift sequence generation unit 12 for generating a plurality of codeword shift sequences, and a syndrome sequence generation unit for generating a syndrome sequence by performing an exclusive OR operation between bits in the codeword sequence and the codeword shift sequence 13, a syndrome shift sequence generation unit 14 that generates a plurality of syndrome shift sequences by shifting the bits of the syndrome sequence by a shift amount corresponding to the parity check polynomial, and a logical operation between bits in the syndrome sequence and the syndrome shift sequence And an error sequence generation unit 15 for generating an error sequence, and an error correction unit 16 serving as an error sequence generation unit 5 using the generated error sequence by, since it is configured to correct an error in the codeword sequence, to achieve faster decoding process, an effect that can increase the throughput.

  That is, in the process of calculating the syndrome series s, the number of shift instructions is 3 (= J−1 = 4-1) and the number of exclusive OR instructions is 3 (= J−1 = 4-1). In the process of generating the error sequence DEC, the number of shift instructions is 3 (= J−1 = 4-1), and the number of exclusive OR instructions is 6 (= (J−1) × 2 = (4-1) × 2) times, the number of logical product operation instructions is four times (= (J−1) + 1 = (4-1) +1) times, and the number of calculations can be greatly reduced.

In the first embodiment, the decoding device 3 is configured by hardware. However, the decoding device 3 may be configured by software.
That is, a program describing the processing contents of the decoding device 3 may be prepared, the program stored in the memory of the computer, and the program stored in the memory may be executed by the CPU of the computer. .

In the first embodiment, the parity check polynomial is x ⁷ + x ³ + x ¹ + x ^0. However, a code that is error-corrected using an error correction code that is a cyclic code or a pseudo-cyclic code is used. As long as it corrects an error in a word sequence, it is not limited to the above check polynomial, and other check polynomials may be applied.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the communication system by Embodiment 1 of this invention. It is a block diagram which shows the decoding apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows the processing content of the codeword shift series production | generation part 12 and the syndrome series production | generation part 13. FIG. It is explanatory drawing which shows the processing content of the syndrome shift series production | generation part 14 and the error series production | generation part 15. FIG. It is explanatory drawing which shows the logical operation in the conventional decoding apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Error correction encoding apparatus, 2 Communication channel, 3 Decoding apparatus, 11 Code word sequence receiving part (code word sequence receiving means), 12 Code word shift sequence generating part (code word shift sequence generating means), 13 Syndrome sequence generating part (Syndrome sequence generation unit), 14 syndrome shift sequence generation unit (syndrome shift sequence generation unit), 15 error sequence generation unit (error sequence generation unit), 16 error correction unit (error correction unit).

Claims (7)

  Codeword sequence receiving means for receiving a codeword sequence that has been subjected to error correction coding using an error correction code that is a cyclic code or a pseudo cyclic code, and a check polynomial for the codeword sequence received by the codeword sequence receiving means Codeword shift sequence generating means for generating a plurality of codeword shift sequences by shifting the bits of the codeword sequence by a shift amount according to the codeword sequence received by the codeword sequence receiving means and the code A syndrome sequence generation means for generating a syndrome sequence by performing an exclusive OR operation between bits in the codeword shift sequence generated by the word shift sequence generation means; and a codeword sequence received by the codeword sequence reception means Shifting the syndrome sequence bits generated by the syndrome sequence generation means by a shift amount corresponding to the check polynomial of A syndrome shift sequence generating means for generating a syndrome shift sequence, an error sequence by performing a logical operation between bits in the syndrome sequence generated by the syndrome sequence generating means and the syndrome shift sequence generated by the syndrome shift sequence generating means; And an error correction unit that corrects an error in the codeword sequence received by the codeword sequence reception unit using the error sequence generated by the error sequence generation unit. apparatus. When the parity check polynomial of the codeword sequence received by the codeword sequence reception unit is x ⁷ + x ³ + x ¹ + x ⁰ , the codeword shift sequence generation unit shifts the bits of the codeword sequence to the right by 1 bit. A first codeword shift sequence is generated, and a bit of the first codeword shift sequence is generated by shifting the bits of the first codeword shift sequence to the right by 2 bits to generate a second codeword shift sequence. The decoding apparatus according to claim 1, wherein a third codeword shift sequence is generated by shifting 4 to the right by 4 bits.   The syndrome sequence generation means includes an exclusive OR of the bits of the codeword sequence, the bits of the first codeword shift sequence, the bits of the second codeword shift sequence, and the bits of the third codeword shift sequence. 3. The decoding apparatus according to claim 2, wherein the result of the exclusive OR is output as a syndrome series.   The syndrome shift sequence generation means generates a first syndrome shift sequence by shifting the bits of the syndrome sequence generated by the syndrome sequence generation means to the left by 1 bit, and sets the bits of the first syndrome shift sequence to the left by 2 4. The third syndrome shift sequence is generated by bit-shifting to generate a second syndrome shift sequence, and shifting the bits of the second syndrome shift sequence to the left by 4 bits. Decoding device. The error sequence generation means includes a first logical operation, a second logical operation, and a third logical operation between bits in the syndrome sequence, the first syndrome shift sequence, the second syndrome shift sequence, and the third syndrome shift sequence. And obtaining a logical product of the result of the first logical operation and the result of the second logical operation, and obtaining a logical sum of the result of the logical product and the result of the third logical operation, 5. The decoding apparatus according to claim 4, wherein the result of the logical sum is output as an error sequence.
• First logical operation = S ⁰ EXOR S ^-1 EXOR S ^-3 EXOR S ^-7
Second logical operation = ((S ⁰ EXOR S ⁻¹ EXOR S ⁻³ ) AND S ⁻⁷ )
EXOR (((S ⁰ EXOR S ^-1 ) AND S ^-3 ) EXOR (S ⁰ AND S ^-1 ))
Third logic operation = ((S ⁰ EXOR S ⁻¹ EXOR S ⁻³ ) AND S ⁻⁷ )
AND (((S ⁰ EXOR S ^-1 ) AND S ^-3 ) EXOR (S ⁰ AND S ^-1 ))
Error sequence = third logical operation result OR (first logical operation result AND second logical operation result)
However,
S ⁰ = syndrome series S ⁻¹ = first syndrome shift series S ⁻³ = second syndrome shift series S ⁻⁷ = third syndrome shift series EXOR: symbol indicating exclusive OR AND: logical product Symbol OR: Symbol indicating logical sum   The error correction unit obtains an exclusive OR of the error sequence generated by the error sequence generation unit and the codeword sequence received by the codeword sequence reception unit, and outputs the result of the exclusive OR as an error correction result. The decoding device according to claim 5, wherein:   An error correction encoding apparatus that performs error correction encoding of data using an error correction code that is a cyclic code or a pseudo cyclic code, and transmits a codeword sequence that is an error correction encoding result of the data, and the error In a communication system including a decoding device that receives a codeword sequence transmitted from a correction encoding device, corrects an error in the codeword sequence, and reproduces data, the decoding device includes the error correction encoding device. A codeword sequence receiving means for receiving a codeword sequence transmitted from the codeword sequence, and shifting the bits of the codeword sequence by a shift amount corresponding to a check polynomial of the codeword sequence received by the codeword sequence receiving means, Codeword shift sequence generation means for generating a plurality of codeword shift sequences, codeword sequences received by the codeword sequence reception means, and codeword shift sequence generation means A syndrome sequence generation means for generating a syndrome sequence by performing an exclusive OR operation between bits in the codeword shift sequence, and a shift amount according to a check polynomial of the codeword sequence received by the codeword sequence reception means Syndrome shift sequence generation means for generating a plurality of syndrome shift sequences by shifting the bits of the syndrome sequence generated by the syndrome sequence generation means; the syndrome sequence generated by the syndrome sequence generation means and the syndrome shift sequence generation An error sequence generating means for generating an error sequence by performing a logical operation between bits in the syndrome shift sequence generated by the means, and the codeword sequence receiving means using the error sequence generated by the error sequence generating means Of the codeword sequence received by Communication system, characterized in that it is composed of an error correction means for correcting Ri.

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