JP2009182267A - Wiring method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring method capable of increasing the total capacitance of wiring to be affected by crosstalk noise without adding a new wiring layer. <P>SOLUTION: The wiring method comprises: a crosstalk noise analysis step of calculating a crosstalk noise level on the basis of the earth capacitance of automatically wired signal wiring and a coupling capacitance with adjacent wiring and extracting the signal wiring whose crosstalk noise level exceeds a stipulated value; an additional capacitance value calculation step of calculating the value of an additional capacitance to be added to the total capacitance of the extracted signal wiring in order to make the crosstalk noise level be equal to or lower than the stipulated value; a floating metal wiring addition step of adding floating metal wiring around the signal wiring; and a judgement step of judging whether or not the value of the parasitic capacitance of the floating metal wiring satisfies the capacitance value of the required additional capacitance. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring method, and more particularly to a wiring method of a semiconductor integrated circuit.

  In recent years, with the progress of higher integration of semiconductor integrated circuits, the wiring interval is gradually narrowed. For this reason, the coupling capacitance between adjacent wirings has increased, and the occurrence of malfunction due to crosstalk noise occurring between adjacent signal wirings has become conspicuous.

The magnitude of the crosstalk noise is expressed by V0 (t) = Cc / (Cc + Cw) · V1 (t) when the voltage level is expressed as V0 (t).
Is calculated as Here, Cc represents the coupling capacitance between the wiring affected by the crosstalk noise and the adjacent wiring, Cw represents the ground capacitance of the wiring affected by the crosstalk noise, and (Cc + Cw) represents the crosstalk. Indicates the total capacity of wiring affected by noise. Further, V1 is a signal voltage of an adjacent wiring that becomes a crosstalk noise generation source, and t represents time.

  From the above equation, it can be seen that in order to reduce the voltage level of the crosstalk noise, it is only necessary to increase the total capacitance of the wiring affected by the crosstalk noise, that is, to increase the ground capacitance Cw.

  Therefore, conventionally, in order to increase the ground capacitance Cw, a wiring pattern of an auxiliary wiring layer including a plurality of auxiliary wirings having a constant capacitance value is created according to the arrangement pattern of the automatically arranged cells, and this wiring An auxiliary wiring layer of a predetermined material with a pattern is inserted into the predetermined layer, automatic wiring is performed between cells, target wiring that generates noise due to crosstalk is detected, and a predetermined number of auxiliary wirings are connected to the target wiring through via holes. An automatic wiring method for connecting wirings has been proposed (see, for example, Patent Document 1).

However, in this conventional automatic wiring method, in order to increase the ground capacitance Cw, it is necessary to newly add an auxiliary wiring layer including a plurality of auxiliary wirings having a certain capacitance value. There is a problem that the manufacturing process increases and the manufacturing cost increases.
JP 2002-151651 A (page 2-3, FIG. 1)

  Accordingly, an object of the present invention is to provide a wiring method capable of increasing the total capacity of wiring affected by crosstalk noise without adding a new wiring layer.

  According to one aspect of the present invention, the crosstalk noise level calculating step for calculating the crosstalk noise level based on the ground capacitance of the automatically routed signal wiring and the coupling capacitance with the adjacent wiring, and the crosstalk noise level are defined. Crosstalk violation wiring extraction step to extract signal wiring exceeding the value, and additional capacity to calculate the value of additional capacity to be added to the total capacity of the extracted signal wiring in order to make the crosstalk noise level below the specified value A value calculating step, a floating metal wiring adding step for adding a floating metal wiring around the extracted signal wiring, and determining whether or not a parasitic capacitance value of the floating metal wiring satisfies a capacitance value of the additional capacitance A wiring method characterized by comprising:

  According to the present invention, the total capacity of wiring affected by crosstalk noise can be increased without adding a new wiring layer.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a flowchart showing an example of the processing flow of the wiring method according to the embodiment of the present invention.

  In the wiring method of the present embodiment, first, crosstalk noise analysis is performed on the result of automatic wiring. In this crosstalk noise analysis, crosstalk noise is calculated based on the ground capacitance and coupling capacitance of each signal wiring (step S01), and signal wiring whose crosstalk noise level exceeds a specified value is extracted (step S02). .

  By this crosstalk noise analysis, for example, it is assumed that the crosstalk noise of the wiring L0 shown in FIG. 2A exceeds the specified value due to the influence of the signal change of the adjacent wiring L1.

At this time, the voltage level V0 (t) of the crosstalk noise of the wiring L0 is
V0 (t) = Cc / (Cc + Cw) · V1 (t)
Is calculated as Here, Cc is a coupling capacitance between the wiring L0 and the wiring L1, Cw is a ground capacitance of the wiring L0, V1 is a signal voltage of the wiring L1, and t is time.

  In this embodiment, for the signal wiring whose crosstalk noise level exceeds the specified value, in this embodiment, a floating metal wiring is added around the wiring, and the target signal wiring is utilized by utilizing the parasitic capacitance of the floating metal wiring. To reduce the crosstalk noise level of the target signal wiring.

  Therefore, in the flow of FIG. 1, for the signal wiring whose crosstalk noise level exceeds the specified value, an additional capacitance value that needs to be added to make the crosstalk noise level smaller than the specified value is calculated ( Step S03).

  Next, a layer to which a floating metal wiring is added is selected. At this time, in this embodiment, priorities are assigned to the layers to which the floating metal wiring is added, and the first priority layer is selected (step S04).

  For example, as shown in FIG. 2B, seven layers M1 to M7 are used as wiring layers, and M1 / M2 is frequently used inside the cell and has almost no free space. M3 / M4 is the layer that is used most often as signal wiring and has less free space. M5 / M6 is used as signal wiring, but there are relatively many empty areas. If M7 is a layer with a full power mesh and a small free area, priorities are assigned as follows.

  The first priority is a layer with a lot of free space other than the layer where the signal wiring whose crosstalk noise exceeds the specified value is arranged.

The second priority is a layer close to power supply wiring or GND (ground) wiring.

The third priority is a layer in which signal wiring having crosstalk noise exceeding a specified value is arranged.

  For example, as shown in FIG. 3, when the signal wiring L0 whose crosstalk noise level exceeds a specified value is arranged in the M4 layer, the M1 layer has the GND wiring, and the M7 layer has the power wiring, the first priority This layer is an M5 layer with a lot of free space. Next, the second priority layers are the M3 layer close to the GND wiring and the M6 layer close to the power supply wiring. The third priority layer is the M4 layer, which is a layer in which the signal wiring L0 is arranged.

  Therefore, in the flow of FIG. 1, first, a floating metal wiring is added to the first priority layer (step S05).

  At this time, it is necessary to determine in what area the floating metal wiring is added. For this purpose, as shown in FIG. 4, the relationship between the target additional capacitance value and the range in which the floating metal wiring is added is calculated in advance. As a result, it is possible to determine the arrangement region of the floating metal wiring necessary for obtaining the target additional capacitance value.

  In FIG. 4, the relationship between the target additional capacitance value and the range in which the floating metal wiring is added is calculated using the wiring density of the floating metal as a parameter. This is because if the wiring density around the floating metal and the wiring density of the floating metal wiring are unbalanced, the flatness of the wiring layer and the interlayer insulating film may be impaired during the manufacture of the semiconductor integrated circuit. This is to prevent it. Therefore, the arrangement region of the floating metal wiring with respect to the target additional capacitance value is determined in accordance with the wiring density of the floating metal that matches the peripheral wiring density.

  Next, in the flow of FIG. 1, the parasitic capacitance value of the arranged floating metal wiring is calculated (step S06).

For example, as shown in FIG. 5, when a floating metal wiring is added to the M5 layer with respect to the signal wiring L0 arranged in the M4 layer, this floating metal wiring has a coupling capacitance C2 with the signal wiring L0. Then, a ground capacitance C3 to the GND wiring is generated as a parasitic capacitance. Therefore, in this case, when the ground capacitance of the signal wiring L0 is C1, the ground capacitance Cw of the signal wiring L0 is
Cw = C1 + C2 / C3 / (C2 + C3)
It becomes.

  That is, due to the addition of the floating metal wiring, the ground capacitance Cw of the signal wiring L0, which was only the ground capacitance C1 before the addition of the floating metal wiring, is increased by C2 / C3 / (C2 + C3).

  Therefore, in the flow of FIG. 1, it is determined whether or not the increase in capacity satisfies the target additional capacity value (step S07).

  If the target additional capacitance value is satisfied (YES), the processing of this flow is terminated. If the target additional capacitance value is insufficient (NO), a floating metal wiring should be added to the next layer. Then, it is confirmed whether or not a layer to which a floating metal wiring can be added remains (step S08).

  If there remains a layer to which a floating metal wiring can be added (YES), the layer to which the floating metal wiring is added is changed to the next priority layer (step S09), the process returns to step S05, and the subsequent processing is performed. repeat.

  On the other hand, in step S08, when there is no remaining layer to which a floating metal wiring can be added, the process of this flow is terminated.

  In this embodiment, when a plurality of floating metal wirings are added adjacent to each other, the capacity can be increased by filling the space of the plurality of floating metal wirings and increasing the area of the metal wiring. it can.

  For example, as shown in FIG. 6A, when a plurality of floating metal wirings FM1 to FM4 are arranged adjacent to each other, a space between the wirings is filled, and one large metal as shown in FIG. An area of floating metal wiring is formed. Thereby, when the area | region which can add a floating metal wiring is narrow, a capacity | capacitance can be increased efficiently.

  Finally, FIG. 7 shows an example of how the wiring layer capacity increases when floating metal wiring is added according to the flow of this embodiment.

  FIG. 7 is a graph in which the total capacity of each signal wiring before the addition of the floating metal wiring after the automatic wiring is plotted on the horizontal axis, and the increase amount of the total capacity of each signal wiring after the addition of the floating metal wiring is plotted. Thereby, it can be seen that the total capacity of each signal wiring is increased by adding the floating metal wiring.

  According to the present embodiment, the floating metal wiring is sequentially added from the layer with a large free space, thereby increasing the total capacity of the wiring affected by the crosstalk noise without adding a new wiring layer. be able to.

The flowchart which shows the example of the flow of a process of the wiring method which concerns on the Example of this invention. The figure which shows the example of the automatic wiring of a semiconductor integrated circuit. The figure which shows the example of the priority of the layer which adds the floating metal wiring of the Example of this invention. The figure which shows the example of the relationship between a target additional capacitance value and the range which adds a floating metal wiring. The figure which shows the additional example of floating metal wiring. The figure which shows the example which filled the space between adjacent floating metal wiring. The figure which plotted the example of the capacity | capacitance increase amount of the signal wiring by floating metal wiring addition.

Explanation of symbols

L0, L1 Signal wiring Cc Coupling capacitance Cw between signal wirings Ground capacitance C1 of signal wiring Ground capacitance C2 of signal wiring Coupling capacitance C3 of floating wiring and signal wiring Ground capacitance of floating wiring

Claims (5)

A crosstalk noise level calculating step for calculating a crosstalk noise level based on the ground capacitance of the automatically routed signal wiring and the coupling capacitance with the adjacent wiring;
A crosstalk violation wiring extraction step for extracting signal wiring whose crosstalk noise level exceeds a specified value;
An additional capacitance value calculating step for calculating a value of an additional capacitance to be added to the total capacitance of the extracted signal wiring in order to make the crosstalk noise level equal to or less than a specified value;
A floating metal wiring adding step of adding a floating metal wiring around the extracted signal wiring;
And a determination step of determining whether or not a parasitic capacitance value of the floating metal wiring satisfies a capacitance value of the additional capacitor. In the floating metal wiring adding step,
Prioritize the layer to which the floating metal wiring is added,
The wiring method according to claim 1, wherein the floating metal wiring is added with a layer having a large free area as a first priority. When it is determined that the determination in the determination step is insufficient,
The wiring method according to claim 2, wherein the floating metal wiring is added with a layer close to a power wiring layer or a ground wiring layer as a second priority. If there is not enough space,
The wiring method according to claim 3, wherein the floating metal wiring is added to the same layer as the extracted signal wiring. 5. The device according to claim 1, wherein when there are a plurality of floating metal wires added adjacently, a space between the floating metal wires is filled to increase an area of the floating metal. 6. Wiring method.

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