JP2009181422A - Data save unit and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve data save processing appropriately even in an environment with a severe time restriction such as a response time. <P>SOLUTION: A data save unit 3, which is a digital circuit for processing a data read request or write request to be transmitted from a CPU 2 to a first memory area 4, reads data from a storage device inside the data save unit 3 or the first memory area 4 and transmits the data to the CPU 2, when the CPU 2 requires to read data. In addition, when the CPU 2 requires to write data, the data save unit 3 stores a write destination address and write data as a set of entries in the inner storage device once, reads the entries, one set at a time, while the CPU 2 requires neither to read nor to write data, saves the data from the first memory area 4 to a second memory area 5, and then writes new data in the first memory area 4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to data read and write control in a microcomputer, a computer system for business use, etc., and relates to a data saving apparatus and data for saving data in a save memory in case a failure occurs in the computer It relates to the evacuation method.

  A phenomenon known as soft error is known, in which part of data handled by a computer is inverted due to cosmic rays and electromagnetic noise. In order to prevent the failure caused by the soft error, various system recovery techniques such as the use of an apologize correction code and the multiplexing of a microcomputer are used in aerospace and business computers. Also in the field of automobile control, electronic control devices related to safety such as brakes, steering, and shifting are progressing, and countermeasures against soft errors are said to be one of the issues.

Conventional soft error countermeasure methods can be broadly classified into methods based on spatial redundancy and methods based on time redundancy.
As a method based on spatial redundancy, a method of correcting data corruption by an error correction code such as ECC, a method of detecting and correcting data corruption by an error detection code such as a parity code, or a system configuration multiplexed and output The method of taking the majority vote is known.

  However, the method using an error correction code or error detection code has a problem that it can cope only when a part of data is inverted. Further, when the system configuration is multiplexed, there is a problem that power consumption and manufacturing cost increase.

  On the other hand, as a method based on time redundancy, focusing on the fact that a soft error occurs temporarily, a method has been devised in which processing is performed a plurality of times and compared to obtain a correct processing result. This method has an advantage that it can be realized at a lower cost than the case where the system configuration is multiplexed.

However, this method has a problem that the execution time of the process becomes long because all the processes are executed a plurality of times, and is not suitable for the control that requires real-time property.
To solve this problem, an apparatus has been devised that returns to a checkpoint only when an error occurs and retries processing of the portion where the error has occurred.

  For example, in the device described in Patent Document 1, the CPU general-purpose register, program counter, and stack pointer values are stored in specific areas of the memory at checkpoints, and after the checkpoint, the CPU does not write to the memory. Then, the data is read from the address to be written, and the read data is stored in the save memory (trace memory).

  When an error occurs, the data stored in the save memory and the values of the general-purpose register, program counter, and stack pointer stored in the memory at the time of the checkpoint are written back to the memory and the CPU.

Soft error is a temporary phenomenon, and the probability of continuous occurrence is very low. Therefore, the system can be recovered by resuming the processing from the time of writing back.
In addition, if the point (checkpoint) at which retry is started is determined in advance, it is only necessary to recover the data at the time of the checkpoint. Therefore, after the data at a certain address is temporarily saved, the data written to that address is There is no need to evacuate.
JP-A-9-81405

  However, when the data is saved by the method of Patent Document 1, the CPU reads the write destination data before the CPU writes the data to the memory, so that the bus cycle is extended for reading the data. There is a problem that the program processing time increases.

  The amount of increase in program processing time at this time is proportional to the number of times the CPU writes data into the memory, and it may be difficult to estimate the amount of increase in processing time depending on the program to be executed.

Because of these problems, it is difficult to apply the method described in Patent Document 1 to embedded system control with severe time constraints such as response time.
The present invention has been made to solve these problems, and it is an object of the present invention to appropriately implement data saving processing even in an environment where time constraints such as response time are severe.

  In order to solve the above-mentioned problem, the invention according to claim 1 is a data saving device connected to an address bus, a data bus, and a control bus for the CPU to transmit various signals to a memory to be accessed. Yes, the memory data is saved in the save memory. The data saving apparatus includes a memory write detection unit, a queue storage unit, a CPU access detection unit, and a queue processing unit.

  In this data evacuation device, the memory write detection means detects a write signal to the memory transmitted from the CPU via the control bus, and the queue storage means detects the write signal by the memory write detection means. The write destination address and write data respectively transmitted from the CPU via the address bus and data bus are stored in the queue as a set of entries.

  On the other hand, the CPU access detection means detects a state in which the CPU does not read or write data to the memory to be accessed, and the queue processing means causes the CPU access detection means to cause the CPU to read and write data. While a state in which neither writing is performed is detected, an entry is taken out from the queue, and the save processing for saving the data stored in the write destination address of the entry from the memory to the save memory is performed. Write processing for storing the write data of the entry at the write destination address is performed.

  According to the first aspect of the present invention, the data saving process is not performed at the timing when the CPU transmits the data write signal, but the write destination address and the write data are temporarily stored as queue entries. Is done. For this reason, the CPU does not stall because the save process is performed as data is written, and a reduction in processing speed due to the data write process can be prevented.

  In a general control program, the ratio of access to all processes is about several percent to 30%, and at least about 7 cycles out of 10 cycles are not accessed. Therefore, if the corresponding cycle is used for the save processing and write processing of the entry stored in the queue, the save processing and write processing are performed using the free CPU cycle, and the queue waits for processing. An increase in processing time hardly occurs.

Therefore, according to the present invention, there is an effect that it is possible to appropriately realize data saving processing even in an environment where time constraints such as response time are severe.
Next, according to a second aspect of the present invention, in the data evacuation device according to the first aspect, the CPU access detecting means monitors the presence or absence of a read signal and a write signal transmitted via the control bus. When neither is transmitted, the CPU detects that neither reading nor writing of data is performed.

  According to such a second aspect of the invention, it is possible to easily detect a state in which neither reading nor writing of data is performed by monitoring the reading signal and the writing signal transmitted via the control bus. Is obtained. As a configuration for realizing this, for example, a NOR circuit having both signals as inputs can be used.

  On the other hand, according to a third aspect of the present invention, in the data saving apparatus according to the first aspect, the CPU access detecting means is connected to an instruction bus to which an instruction signal for the CPU is transmitted. A state in which neither reading nor writing is performed is detected.

  According to the third aspect of the present invention, before the CPU accesses the memory, in order to determine whether or not the CPU accesses the memory, the save process is executed immediately after the access to the memory is started. It becomes possible to do. This makes it possible to increase the clock frequency and achieve a high-speed processing operation compared to the case where the CPU determines access to the CPU after transmitting read and write signals to the memory. Can do.

  According to a fourth aspect of the present invention, in the data evacuation device according to any one of the first to third aspects, the CPU access detecting means further causes the CPU to read data from the memory to be accessed. Is detected. The queue processing means includes the same read address determination means and read data transmission means. When the same read address determination means detects that the data is read by the CPU access detection means, The corresponding read destination address is extracted from the address bus, and the read destination address is compared with the write destination address stored in the queue to determine whether or not the same address exists. When it is determined that the same address exists, the read data transmission means takes out the write data paired with the address from the queue, transmits the write data to the CPU as read data, and the same address If it is determined that the data does not exist, the data stored at the read destination address is taken out from the memory, and the data is transmitted to the CPU as read data.

  According to the invention as set forth in claim 4, since the data stored in the queue is checked for data reading, even if data that has not been saved remains in the queue, the data is read out. The effect that processing is appropriately executed is obtained.

  In particular, in the invention described in claim 5, it is determined in the invention described in claim 4 that the queue processing means further includes the same address selection means, and the same address selection means determines that a plurality of the same addresses exist. In such a case, the write data paired with the address most recently stored in the queue among the same addresses is selected as read data to be transmitted to the CPU.

  According to the fifth aspect of the present invention, since the latest data can be read even when a plurality of write data is stored at the same address in the queue, it is possible to appropriately read the data. Is obtained.

  On the other hand, according to a sixth aspect of the present invention, in the data evacuation device according to any one of the first to fourth aspects, the CPU access detecting means further writes data to a memory to be accessed by the CPU. Is detected. The queue processing means includes the same write address determination means and the data rewrite means. The same write address determination means responds to the writing when the CPU access detection means detects that the data is written. The write destination address and the write data to be performed are respectively taken out from the address bus and the data bus, and the write destination address and the write destination address stored in the queue are compared to determine whether or not the same address exists. Further, when it is determined that the same address exists, the data rewrite means rewrites the write data paired with the address to the write data taken out from the data bus.

  According to the sixth aspect of the present invention, when data is written, the data stored in the queue is checked, and if there is the same address, the paired data is rewritten. A state where there is only one write request for one address can be realized. This eliminates the need for the function of selecting the latest write data from a plurality of writes to the same address (the same address selection means as defined in claim 5), and provides an effect that a small circuit can be configured.

  In particular, according to a seventh aspect of the invention, in the sixth aspect of the invention, the queue storage means further stores an entry validity tag indicating validity or invalidity of the entry as information included in each entry. If the data rewrite means determines that the same address exists by the same write address determination means, instead of rewriting the write data, the entry valid tag paired with the same address stored in the queue Is invalidated, and the write destination address and the write data respectively fetched from the address bus and the data bus are stored in the queue as new entries.

  According to the invention described in claim 7, since the entry can be invalidated by the operation of the entry valid tag, it is not necessary to provide a function for rewriting data in the queue, and the small size that operates at high speed is achieved. The effect that a circuit can be configured is obtained.

  Next, according to an eighth aspect of the present invention, in the data evacuation device according to any one of the first to seventh aspects, the evacuation process and the write process are performed for a part of the memory area of the memory to be accessed. Based on the above, the CPU access detection means detects a state in which the CPU does not read or write data in a part of the memory area where the saving process and the writing process are performed.

  According to the invention described in claim 8, by checking the access destination by the CPU, it is erroneously detected that there is an access even though the CPU does not actually access the memory managed by the data saving device. Can be prevented. As a result, the chance that the data saving apparatus can execute the saving process increases, so that it is possible to make it difficult to cause a situation where the queue is full and the saving process is not in time.

  According to a ninth aspect of the present invention, in the data evacuation apparatus according to any one of the first to eighth aspects, the evacuated address list storage unit and the same evacuated address determination unit are provided. The saved address list storage means stores the write destination address of the data saved in the save memory as a saved address list, and the same saved address determination means stores the write destination address of the data to be newly saved. And the saved address list are compared to determine whether or not the same address exists. In this case, the queue processing means does not perform the save processing when it is determined by the same save address determining means that the same address exists.

  In other words, the invention described in claim 9 prevents time-consuming search for data when there is a large amount of saved data. That is, for example, when a linear search that is a general search method is used for data search, if the number of saved data is N, N / 2 comparison processes are required on average.

  However, it is sufficient for the data evacuation device in this case to reproduce the evacuation data at a certain checkpoint. Once the data is evacuated after a certain checkpoint, the next checkpoint is stored at the address where the data is stored. There is no need to further save data before.

  According to the ninth aspect of the invention, it is possible to omit the process of newly saving data that has already been saved, so that there is an effect that the process of the queue can be advanced accordingly.

  Next, according to the tenth aspect of the present invention, various signals transmitted by the CPU to the memory to be accessed are taken out via the address bus, data bus, and control bus, and the memory data is saved in the save memory. This is a data saving method. This data saving method includes a memory write detection step, a queue storage step, a CPU access detection step, and a queue processing step, and when a write signal to the memory transmitted from the CPU via the control bus is detected in the memory write detection step. In the queue storage step, the write destination address and the write data respectively transmitted from the CPU via the address bus and the data bus are stored in the queue as a set of entries. In the CPU access detection step, a state in which the CPU does not read or write data to the memory to be accessed is detected, and in the queue processing step, the CPU does not read or write data. While the status is detected, the entry is taken out from the queue, and the data stored at the entry write destination address is saved from the memory to the save memory, and the entry is written to the write destination address. Write processing to store data.

According to such a data saving method of the tenth aspect, the same effect as that of the first aspect of the invention can be obtained.
According to an eleventh aspect of the present invention, in the data saving method according to the tenth aspect, in the CPU access detecting step, it is further detected that the CPU reads data from the memory to be accessed. The queue processing step includes an identical read address determination step and a read data transmission step. Here, in the same read address determination step, when it is detected that data is read in the CPU access detection step, the read destination address corresponding to the read is taken out from the address bus and stored in the read destination address and the queue. Is compared with the written write destination address to determine whether or not the same address exists. In the read data transmission step, if it is determined that the same address exists, the write data paired with that address Is read from the queue, the write data is sent to the CPU as read data, and if it is determined in the same read address determination step that the same address does not exist, the data stored in the read destination address is extracted from the memory and the data CPU as read data To send.

According to the eleventh aspect of the invention, the same effect as that of the fourth aspect of the invention can be obtained.
According to a twelfth aspect of the present invention, in the data saving method according to the eleventh aspect, in the read data transmission step, when it is detected that data is read in the CPU access detection step, the same read address determination step is performed. Regardless of the determination, data stored in advance at the read destination address is extracted from the memory.

  According to such a twelfth aspect of the invention, when it is detected that the data is read in the CPU access detecting step, the read data is previously fetched from the memory regardless of whether or not the queue has the same address. Therefore, even when there is no identical address in the queue, read data can be sent to the CPU quickly, and the speed of the read process can be increased.

  The invention according to claim 13 is the data saving method according to claim 11 or 12, wherein the queue processing step further comprises the same address selection step, and the same address selection step includes the same read address determination step. When it is determined that there are a plurality of the same addresses, write data paired with the address stored most recently in the queue among the same addresses is selected as read data to be transmitted to the CPU.

According to such a thirteenth aspect, the same effect as that of the fifth aspect can be obtained.
On the other hand, according to a fourteenth aspect of the present invention, in the data saving method according to any one of the tenth to twelfth aspects, in the CPU access detecting step, the CPU further writes data to the memory to be accessed. Is detected. The queue processing step includes an identical write address determination step and a data rewrite step. In the same write address determination step, when it is detected that data is written in the CPU access detection step, the write destination address and the write data corresponding to the write are taken out from the address bus and the data bus, respectively, and the write destination address and the wait are waited for. It is determined whether or not the same address exists by comparing with the write destination address stored in the matrix. In the data rewriting step, when it is determined that the same address exists, the write data paired with the address is rewritten to the write data taken out from the data bus.

According to such an invention described in claim 14, the same effect as that of the invention described in claim 6 can be obtained.
Further, in the data saving method according to claim 14, in the data saving method according to claim 14, in the queue storing step, an entry valid tag indicating validity or invalidity of the entry is further stored as information included in each entry. . In the data rewrite step, if it is determined that the same address exists in the same write address determination step, the entry valid tag paired with the same address stored in the queue instead of rewriting the write data Is invalidated, and the write destination address and the write data respectively fetched from the address bus and the data bus are stored in the queue as new entries.

  According to such an invention described in claim 15, the same effect as that of the invention described in claim 7 can be obtained.

Embodiments to which the present invention is applied will be described below with reference to the drawings.
[1 First Embodiment]
First, the microcomputer according to the first embodiment (hereinafter referred to as “microcomputer”) will be described.
[1-1 Overall configuration]
FIG. 1 is a block diagram showing the configuration of the microcomputer as the first embodiment. As shown in FIG. 1, the microcomputer includes a ROM 1, a CPU 2, a data saving device 3, a first memory area (MEM 1) 4, and a second memory area (MEM 2) 5.

  In this microcomputer, the CPU 2 is connected to the ROM 1 via an instruction side address bus 6, an instruction side control bus 7 and an instruction side data bus 8. The data saving device 3 is connected to the CPU 2 via the data side address bus 9, the data side control bus 10 and the data side data bus 11, and the first memory side address bus 12, the first memory side control bus 13 and the first side. 1 memory side data bus 14 is connected to the first memory area 4. Further, the data saving device 3 is connected to the second memory area 5 via the second memory side address bus 15, the second memory side control bus 16 and the second memory side data bus 17.

  In this microcomputer, control signals such as data read requests and write requests are sent from the CPU 2 via the data side control bus 10, and address signals corresponding to these read requests or write requests are sent via the data side address bus 9. Sent. Data signals such as read data and write data are sent via the data-side data bus 11.

  The same applies to transmission / reception of data between the data saving device 3 and the first memory area 4 and the second memory area 5, via the first memory side control bus 13 and the second memory side control bus 16, respectively. Then, control signals such as a data read request and a write request are sent, and address signals corresponding to these requests are sent via the first memory side address bus 12 and the second memory side address bus 15. Then, the read data or the write data is sent via the first memory side data bus 14 and the second memory side data bus 17.

Here, the data saving device 3 is a digital circuit that processes a read request and a write request of data sent from the CPU 2 to the first memory area 4. Specifically, when there is a data read request from the CPU 2, the data evacuation device 3 receives the corresponding data from the storage device (queue storage circuit 19 described later) or the first memory area 4 in the data evacuation device 3. Is read and the data is sent to the CPU 2. When the CPU 2 receives a data write request, the data saving device 3 temporarily stores the write destination address and the write data as a set of entries in an internal storage device (a queue storage circuit 19 described later). While neither data read nor write request is performed, the entries are read one by one, and after the data is saved from the first memory area 4 to the second memory area 5, the first New data is written in the memory area 4 of the memory.
[1-2 Internal configuration]
FIG. 2 is a block diagram showing an internal configuration of the data saving device 3. The data saving apparatus 3 includes a memory write request detection circuit 18, a queue storage circuit 19, a CPU access detection circuit 20, and a queue processing circuit 21.

  The memory write request detection circuit 18 is a digital circuit that detects a data write request signal sent from the CPU 2 via the data-side control bus 10 and outputs a detection result to the queue storage circuit 19.

  The queue storage circuit 19 receives the output from the memory write request detection circuit 18 as an input, the write destination address sent from the CPU 2 via the data side address bus 9, and the write sent from the CPU 2 via the data side data bus 11. This is a digital circuit that stores the previous data as a set (entry) as a queue in an internal storage circuit and outputs the contents of the queue to the queue processing circuit 21 in response to a request from the queue processing circuit 21. The queue storage circuit 19 stores a write address and write data for each queue as a set of entries in a FIFO (First-In First-Out) format. The data structure of the queue stored in the queue storage circuit 19 is as shown in FIG. 3, and one set of address A and data D is stored in order from entry 1.

  The CPU access detection circuit 20 detects whether or not a data read request or write request is made by the CPU 2 via the data-side control bus 10 and outputs the result to the queue processing circuit 21 It is.

  FIG. 4 is a digital circuit diagram showing the first half portion close to the input of the CPU access detection circuit 20. This circuit includes one NOR element 22, receives a data read signal and a data write signal from the data side control bus 10, and outputs the calculation result to the output line 23. The CPU access detection circuit 20 outputs a true value only in a cycle in which neither a data read signal nor a write signal is sent. A signal from the output line 23 is sent to the queue processing circuit 21 after passing through a circuit shown in FIG.

FIG. 5 is a digital circuit diagram showing the second half portion close to the output of the CPU access detection circuit 20. This circuit includes an address decoding circuit 24 and an AND element 25.
The address decode circuit 24 inputs the true value only when the address sent from the CPU 2 is within the range of the first memory area 4 connected to the data saving device 3 with the data side address bus 9 as an input. 25 is a digital circuit designed to output to 25. The AND element 25 takes the outputs from the output line 23 and the address decode circuit 24 of the circuit shown in FIG. 4 as inputs and outputs a logical product to the queue processing circuit 21.

  According to the circuit shown in FIG. 5, even if data is read from or written to an address other than the first memory area 4 where the saving process by the data saving device 3 is performed, the CPU access detection circuit 20 As an output result, a state in which neither reading nor writing of data is performed is output.

  Next, the queue processing circuit 21 inputs a signal indicating that the CPU 2 is not accessing from the CPU access detection circuit 20, takes out one set of entries from the queue storage circuit 19, and saves and writes data. To do. In addition, in response to a read request and a write request from the CPU 2, it is compared with the address of the entry, and queue data is exchanged. When data is read in response to a request from the CPU 2, the result is sent to the CPU 2 via the data side data bus 11. The queue processing circuit 21 is connected to the first memory area 4 via the first memory side address bus 12, the first memory side control bus 13, and the first memory side data bus 14, and the second memory side address. It is connected to the second memory area 5 through the bus 15, the second memory side control bus 16 and the second memory side data bus 17.

  FIG. 6 is a block diagram showing a part of the internal configuration of the queue processing circuit 21 and realizes processing for a read request from the CPU 2. This circuit is composed of the same read address determination circuit 26, an Nto1 selector 27, and a 2to1 selector 28, and is connected to the queue storage circuit 19.

  The same read address determination circuit 26 inputs and compares the address sent from the CPU 2 via the data side address bus 9 and the address of the queue entry stored in the queue storage circuit 19 and compares the result. The data is output to the Nto1 selector 27 and the 2to1 selector 28. That is, the same read address determination circuit 26 starts its operation when a read request is received from the CPU 2, compares the address from the CPU 2 with the address of the queue, and if there is an identical address, the Nto1 selector 27 The entry value is sent to the 2 to 1 selector 28 and a selection signal is sent to instruct the CPU 2 to send the queue data to the CPU 2. If there is no identical address, a selection signal is sent to instruct the CPU 2 to send the data stored in the first memory area 4.

  The Nto1 selector 27 inputs the entry value sent from the same read address determination circuit 26, reads data corresponding to the entry value from the queue stored in the queue storage circuit 19, and reads the read data to 2to1. Output to the selector 28.

  The 2to1 selector 28 receives a selection signal sent from the same read address determination circuit 26, and in accordance with the selection signal, the data read from the first memory area 4 via the first memory side data bus 14 or the Nto1 selector One of the data sent from 27 is selected and sent as read data to the CPU 2 via the data-side data bus 11.

  FIG. 7 is a block diagram showing an internal configuration of the same read address determination circuit 26. The same read address determination circuit 26 includes N comparators 29 and one selection signal generation circuit 30, and the N comparators 29 are queues stored in the data side address bus 9 and the queue storage circuit 19. The comparison circuit outputs the comparison result to the selection signal generation circuit 30.

  The selection signal generation circuit 30 is a digital circuit that receives an output from the comparator 29 and outputs a calculation result to the Nto1 selector 27 and the 2to1 selector 28. The truth table realized by the selection signal generation circuit 30 is as shown in FIG. As shown in FIG. 8, the selection signal generation circuit 30 is a priority encoder, and each output of the comparator 29 is handled with a weight. In this example, priority is given to a signal for selecting an entry having a small N number in Ct0-N. To the Nto1 selector 27. Also, a true value is sent to the 2to1 selector 28 as an EXIST signal.

  The 2to1 selector 28 outputs the output value of the Nto1 selector to the CPU when it receives a true value as the EXIST signal, and outputs the value of the first memory side data bus 14 when it is not true. Note that the truth table in FIG. 8 is illustrated when N is eight.

  FIG. 9 is a block diagram showing a part of the internal configuration of the queue processing circuit 21. When a write request is received from the CPU 2, the rewrite processing of the queue data stored in the queue storage circuit 19 is realized. It is a digital circuit.

  A digital circuit that realizes processing when a write request is received from the CPU 2 is not shown in its entirety. However, as in the case where a read request is issued, the comparison circuit shown in FIG. 6 and FIG. The previous address and the queue address are compared, and if the same address exists, an entry request signal for requesting rewriting is sent to the corresponding entry.

  As shown in FIG. 9, the circuit that implements the rewriting process includes N data rewriting circuits 31 and N OR elements 32. The data rewrite circuit 31 inputs write data from the CPU 2 via the data-side data bus 11 not shown in FIG. 2, and when the true value is input to the WE (Write Enable) terminal, the data in the queue is received. This is a digital circuit that outputs a signal to be rewritten with write data to the queue storage circuit 19. A signal indicating that the entry should be rewritten is sent from the OR element 32 to the WE terminal.

The OR element 32 takes a logical sum by inputting a data write signal sent from the CPU access detection circuit 20 and an entry rewrite signal that becomes a true value when rewriting the entry. This entry rewrite signal is sent to the OR element 32 corresponding to the corresponding entry when the same address exists in the queue entry stored in the queue storage circuit 19 for the data write request from the CPU 2. It is done. The data write signal is sent to the OR element 32 corresponding to the new entry in the queue stored in the queue storage circuit 19 when there is no identical address in the queue entry.
[1-3 Processing flow]
Next, the processing flow of the first embodiment will be described.

  FIG. 10 is a flowchart showing a processing flow when there is a read request from the CPU 2 executed by the data saving device 3 of the first embodiment, and is realized by the configuration described so far. When there is a read request from the CPU 2, it is processed in the next step.

  First, in step S <b> 101, the read address sent from the CPU 2 and the address of the queue entry stored in the queue storage circuit 19 are compared by the same read address determination circuit 26. A branching process is performed depending on whether or not there is a matching entry in S102.

  If there is a matching entry in S102 (YES), the data of that entry sent by the Nto1 selector 27 is selected by the 2to1 selector 28 in the next S103. If there is no matching entry in S102 (NO), data corresponding to the read address from the CPU 2 from the first memory area 4 is selected by the 2to1 selector 28 in the next S104.

In the last S105, the data selected in S103 or S104 is output to the CPU 2 via the data-side data bus 11 as read data.
FIG. 11 is a flowchart illustrating a processing flow when the CPU 2 receives a write request in the data saving apparatus 3 according to the first embodiment. When there is a write request from the CPU 2, it is processed in the next step.

  First, in S201, the write address from the CPU 2 is compared with the address of the queue entry stored in the queue storage circuit 19. In S202, branch processing is performed depending on whether or not there is a matching entry. Although the description of the configuration of the comparison circuit is omitted, it is realized by sharing the same circuit as the same read address determination circuit 26 shown in FIGS.

  If there is a matching entry in S202 (YES), the data of the entry is rewritten to the write data from the CPU 2 in the next S203. In this case, no new entry is added.

  On the other hand, if there is no matching entry in S202 (NO), in the next S204, the write destination address and write data corresponding to the write request from the CPU 2 are added to the queue as a set of entries.

  FIG. 12 is a timing chart showing the timing of the operation in which data is written to the queue of the queue storage circuit 19. When the write request signal is detected by the memory write request detection circuit 18, the addresses A1, A2, A3, A4 are sequentially sent from the data side address bus 9 and the write data D1, D2,. D3 and D4 are taken out, and the address and data are stored in the queue as a set of entries. Here, PtrR and PtrW shown in FIG. 12 indicate pointers where the write and read data are stored, respectively. EMPTY also detects whether the queue is empty.

  In this timing chart, when there is a write request from the CPU 2, if the queue is not full, that is, if there is an empty space, the CPU 2 ends the write process without stalling. If the queue is full, a wait signal (not shown) is sent to the CPU 2 so that the CPU 2 is stalled until the queue is empty.

FIG. 13 is a timing chart showing the timing at which the data saving apparatus 3 performs the saving operation. The CPU access detection circuit 20 detects that neither a read request nor a write request is made from the CPU 2 and sends a CPU access signal to the queue processing circuit 21. When a state in which there is no access from the CPU 2 is detected by the CPU access signal from the CPU access detection circuit 20, the queue processing circuit 21 first reads the read data D1 stored in the address A1 from the queue according to the clock signal. 'Is read, and at the next timing, the read data D1' is written to the second memory area 5 for saving, and the write data D1 sent from the CPU 2 is written to the address A1 of the first memory area 4.
[1-4 Effects of the present embodiment]
As described above, according to the data saving apparatus 3 of the first embodiment, the data saving process and the writing process are not performed at the timing when the CPU 2 transmits the data writing signal, but the writing destination address and the writing data are Once stored as a queue entry of the queue storage circuit 19. For this reason, the CPU 2 is not stalled because the save process is performed as data is written, and a reduction in processing speed due to the data write process can be prevented.

  Also, the CPU access detection circuit 20 detects an empty cycle in which the CPU 2 does not access, and the save process and the write process are performed using the cycle (FIG. 13). There is almost no increase.

Therefore, according to the data saving apparatus 3, it is possible to appropriately realize data saving processing even in an environment where time constraints such as response time are severe.
Further, as shown in FIG. 4, the CPU access detection circuit 20 monitors a read signal and a write signal transmitted via the data-side control bus 10 to make a state in which neither reading nor writing of data is performed. It can be easily detected. This detection circuit is composed of one NOR element 22 and is realized simply and at low cost.

  Further, the data saving device 3 of the present embodiment checks the data stored in the queue by the same read address determination circuit 26 for the data read (S101, S102). Therefore, even if data that has not been saved is left in the queue, an effect that the data read process is appropriately executed can be obtained.

  Further, the data saving device 3 of the present embodiment checks the data stored in the queue for data writing (S201, S202), and rewrites the paired data if there is the same address (S203, S202). The circuit shown in FIG. This realizes a state in which the queue has only one write request for one address. For this reason, the function of selecting the latest write data from a plurality of writes to the same address becomes unnecessary, and an effect of being configured with a small circuit can be obtained.

Further, according to the circuit shown in FIG. 5 inside the CPU access detection circuit 20 of the present embodiment, the CPU 2 does not actually access the first memory area 4 by checking the access destination by the CPU 2. It is possible to prevent erroneous detection when there is access. As a result, the chance that the data saving apparatus 3 can execute the saving process increases, so that it is difficult to cause a situation where the queue becomes full and the saving process is not in time.
[1-5 Relationship with Claims]
In the data saving apparatus 3 of the first embodiment, the memory write request detection circuit 18 is a memory write detection means, the queue storage circuit 19 is a queue storage means, the CPU access detection circuit 20 is a CPU access detection means, and a queue process. The circuit 21 corresponds to queue processing means.

The same read address determination circuit 26 corresponds to the same read address determination means, the Nto1 selector 27 and the 2to1 selector 28 correspond to the read data transmission means, and the comparison circuit (not shown) that executes S201 and S202 is the same write address determination means. The data saving device 3 including the digital circuit shown in FIG.
[2 Second Embodiment]
Next, a microcomputer according to the second embodiment will be described.
[2-1 Difference from First Embodiment]
FIG. 14 is a block diagram showing the data saving apparatus 3 provided in the microcomputer as the second embodiment. The data saving apparatus 3 according to the second embodiment is obtained by adding a saved data determination circuit 33 and a saved address list 34 to the data saving apparatus 3 according to the first embodiment. Other configurations are the same as those of the first embodiment. It is the same.

  The saved data determination circuit 33 is connected to the queue processing circuit 21 and the saved address list 34, and exchanges various data. In the saved address list 34, when the data saving device 3 saves data, the address in the first memory area 4 in which the data is stored is saved via a bus (not shown). Is stored as an address.

Then, the saved data determination circuit 33 checks whether or not the write destination address is stored in the saved address list 34 when the entry stored in the queue storage circuit 19 is processed.
[2-2 Processing flow]
Next, the processing flow of the second embodiment will be described. In the second embodiment, when processing each entry, the queue processing circuit 21 sends the address of the entry to be processed to the saved data determination circuit 33 and waits until the determination by the saved data determination circuit 33 is completed. . It is determined whether or not the save operation is performed based on the determination result (unsaved / saved).

FIG. 15 is a timing chart showing the determination process performed by the saved data determination circuit 33.
The saved data determination circuit 33 compares the address sent from the queue processing circuit 21 with the address stored in the saved address list 34 to determine whether there is a matching address. When there is no address that matches the address stored in the saved address list 34 and the determination result is determined to be unsaved (a), the saving operation for the second memory area 5 is performed. When it is determined that the saving has been completed (b), as a result of the determination, a signal indicating that saving has been performed is turned on, and no new saving operation is performed.
[2-3 Effects]
The data saving apparatus 3 according to the second embodiment is designed to prevent the time required for searching for data when there is a large amount of saved data. That is, it is sufficient for the data saving device 3 to be able to reproduce the saved data at a certain checkpoint. Once the data is saved after a certain checkpoint, the address where the data is stored is before the next checkpoint. Further, there is no need to save data.

According to the data evacuation device 3 of the second embodiment, it is possible to omit the process of evacuating data that has already been evacuated, so that it is possible to advance the queue process accordingly.
[2-4 Relationship with Claims]
In the data saving apparatus 3 of the second embodiment, the saved address list 34 corresponds to address list storage means, and the saved data determination circuit 33 corresponds to the same saved address determination means.
[3 Third Embodiment]
Next, a microcomputer according to a third embodiment will be described.
[3-1 Differences from First Embodiment]
The microcomputer of the third embodiment differs from the first embodiment in the data structure of the queue stored in the queue storage circuit 19 of the data saving device 3. Specifically, as shown in FIG. 16, each entry in the queue is provided with a tag indicating whether the entry is valid or invalid in addition to the data value and the address value. In the example of FIG. 16, data (Valid) indicating validity of an entry is stored as a tag of each entry.

  FIG. 17 is a flowchart showing a processing flow when there is a write request from the CPU 2 in the data saving apparatus 3 of the third embodiment. Until the presence / absence of an entry is determined in S302, the processing flow is the same as that in FIG.

  If there is a matching entry in S302, in S303, data indicating invalidity of the entry is stored in the tag of the matching entry instead of rewriting the data. After the process of S303 and when there is no matching entry in S302, the address and data corresponding to the write request from the CPU 2 are added to the queue of the queue storage circuit 19 as a set of entries in S304. The tag of the entry at this time is valid.

The queue processing circuit 21 of the third embodiment takes out the next entry from the queue without performing any processing on the entry when invalid data is written in the entry tag. Process.
[3-2 Effects]
According to the queue processing circuit 21 of the third embodiment, since the entry can be invalidated by operating the valid tag of the entry, there is no need to provide a function for rewriting data in the queue, and the operation is performed at high speed. The effect that a small circuit can be configured is obtained.
[4 Fourth Embodiment]
Next, a microcomputer according to a fourth embodiment will be described.
[4-1 Differences from First Embodiment]
The microcomputer of the fourth embodiment is different from the first embodiment in the internal configuration of the CPU access detection circuit 20 in the data saving apparatus 3. FIG. 18 is a digital circuit diagram illustrating the internal configuration of the CPU access detection circuit 20 of the fourth embodiment. The CPU access detection circuit 20 includes a parallel flip-flop 35, a memory access instruction determination circuit 36, and a two-stage serial flip-flop 37. The parallel flip-flop 35 inputs the instruction side control bus 7 and outputs the result to the memory access instruction determination circuit 36. The memory access instruction determination circuit 36 receives the output from the parallel flip-flop 35 and sends data to the serial flip-flop 37. The serial flip-flop 37 receives the data from the memory access instruction determination circuit 36 and sends the data to the queue processing circuit 21 through a circuit (FIG. 20) described later.

  In the first embodiment, the CPU access detection circuit 20 detects a signal sent from the CPU 2 via the data side control bus 10, but in this fourth embodiment, the instruction side bus connecting the ROM 1 and the CPU 2 is connected. Detect the signal. That is, in the fourth embodiment, a control signal for the CPU 2 is transmitted from the instruction side control bus 7 to the parallel flip-flop 35. Then, the memory access instruction determination circuit 36 determines whether or not a data read or write request is made from the signal sent from the parallel flip-flop 35, and outputs the result to the serial flip-flop 37.

FIG. 19 is an explanatory diagram showing pipeline processing of the CPU 2 used in the fourth embodiment.
In this pipeline processing, an instruction signal is read from the instruction cache by IF (Instruction Fetch), a control signal sent from the CPU 2 is generated by DEC (Instruction Decode / register read), and a register file (not shown) is registered as a register specifier. Refer to. Then, numerical value calculation, data and address / branch destination calculation are performed by EXE (EXecution / address calculation), and data reading or data writing is executed by MA (Memory Access). In WB (Write Back), data is written to a register (not shown).

  The CPU access detection circuit 20 determines the memory access instruction three cycles after the control signal is transmitted to the CPU 2 by IF and the control signal is taken into the parallel flip-flop 35, that is, in a cycle corresponding to the MA stage. The detection signal of the circuit 36 is designed to be output. Specifically, the control signal is taken in by the parallel flip-flop 35, and in the next cycle, the memory access instruction determination circuit 36 determines whether a data read or write signal is sent. Then, the detection signal is output after another two cycles by the two-stage serial flip-flop 37.

  Here, the digital circuit is realized for the pipeline processing in which MA comes after 3 cycles from IF. However, any pipeline processing can be handled by changing the number of serial flip-flops according to the number of cycles. be able to.

FIG. 20 is a digital circuit diagram showing a part of the CPU access detection circuit 20 of the fourth embodiment. This circuit includes an address decoding circuit 24, an AND element 25, and two stages of flip-flops 37 in series. This circuit is the input from the memory access instruction determination circuit 36 shown in FIG. 18, and is the same as the digital circuit shown in FIG. 5 except that it is output to the two-stage serial flip-flop 37. It is the composition.
[4-2 Effects]
According to the data saving device 3 of the fourth embodiment, before the CPU 2 accesses the memory, the instruction side control bus 7 is monitored to determine whether the CPU 2 accesses the memory. The save process can be executed immediately after. As a result, the clock frequency can be made higher than that of the data saving apparatus 3 of the first embodiment for determining the access of the CPU after the CPU 2 transmits the read and write signals to the memory, and the processing can be performed at high speed. The effect that can be realized can be obtained.
[5 Fifth Embodiment]
Next, a microcomputer according to a fifth embodiment will be described.
[5-1 Differences from First Embodiment]
The microcomputer of the fifth embodiment is different from the first embodiment in the content of the processing flow executed by the data saving device 3 when there is a read request from the CPU 2. FIG. 21 is a flowchart showing a processing flow when there is a read request from the CPU 2 in the fifth embodiment.

When there is a read request from the CPU 2, the read address from the CPU 2 is compared with the queue address stored in the queue storage circuit 19 in S401, as in the processing flow shown in FIG. However, in this process, the process of S402 is also performed. That is, in S402, data is read from the first memory area 4 in advance regardless of whether there is a matching entry. The other processing flow is the same as the processing flow of FIG.
[5-2 Effects]
In the fifth embodiment, when the CPU access detection circuit 20 detects reading of data, the read data is taken out from the first memory area 4 in advance regardless of whether or not the queue has the same address. Since the preparation is made, it is possible to quickly transmit the read data to the CPU 2 even when the same address is not in the queue, and the speed of the read process can be increased.
[6 Sixth Embodiment]
Next, a microcomputer according to a sixth embodiment will be described.
[6-1 Differences from First Embodiment]
The microcomputer of the sixth embodiment is different from the first embodiment in the content of the processing flow executed by the data saving device 3 when there is a read request from the CPU 2. FIG. 22 is a flowchart showing a processing flow when there is a read request from the CPU 2 in the sixth embodiment.

  In this processing flow, the processing of S505 is added to the processing flow (FIG. 21) of the fifth embodiment. That is, when it is determined that there is a matching entry in S503, the process is the same as the processing flow of FIG. 21 until the data of the matching entry is selected in S504. However, in S505, the latest entry among the matching entries is selected. Entries are selected. The other processing flow is the same as that shown in FIG.

In this respect, as in the first embodiment, if the data stored in the queue is checked at the stage of data write processing, and if there is the same address, the paired data is rewritten, the queue Since there is only one write request for one address, it is not necessary to provide S505 as a read process. Therefore, in the sixth embodiment, processing such as checking the address in the queue is not performed at the stage of the write processing, and there are a plurality of entries for the same address in the queue. Is assumed.
[6-2 Effects]
According to the data saving apparatus 3 of the sixth embodiment, even when a plurality of write data is stored in the queue at the same address, the newest data can be read, so that the appropriate data can be read. Is obtained.
[6-3 Relationship with Claims]
The queue processing circuit 21 realizing S405 of the sixth embodiment corresponds to the same address selection means.
[7 Other forms]
As mentioned above, although embodiment of this invention was described, this invention is not restricted to described embodiment, Various forms can be taken.

  For example, in the present embodiment, the configuration of the microcomputer is assumed. However, any system can be applied as long as it is a system that executes reading and writing of some memory area and data. That is, when data is exchanged with a hard disk built in or externally attached to a computer, a storage area serving as a server is accessed through a network in a local area or a wide area.

  Further, in the present embodiment, it is premised on the realization by a digital circuit, but the same processing can be realized by software.

It is a block diagram which shows the structure of the microcomputer as 1st Embodiment. It is a block diagram which shows the internal structure of a data evacuation apparatus. It is explanatory drawing which shows the data structure stored in a queue storage circuit. It is the digital circuit diagram which showed the first half part near the input of a CPU access detection circuit. It is the digital circuit diagram which showed the latter half part near the output of a CPU access detection circuit. It is a block diagram which shows a part of internal structure of a queue processing circuit. It is a block diagram which shows the internal structure of the same read address determination circuit. It is explanatory drawing which showed the truth table which a selection signal generation circuit implement | achieves. It is a block diagram which shows a part of internal structure of a queue processing circuit. It is a flowchart which shows the processing flow when there exists a read request from CPU in a data evacuation apparatus. It is a flowchart which shows the processing flow when there exists a write request from CPU in a data evacuation apparatus. It is a timing chart which shows the timing of the operation | movement in which data are written in the queue of a queue storage circuit. It is a timing chart which shows the timing which a data evacuation apparatus performs evacuation operation. It is a block diagram which shows the data evacuation apparatus as 2nd Embodiment. It is a timing chart which shows the determination process performed by the saved data determination circuit. It is explanatory drawing which shows the data structure of the queue stored in a queue storage circuit as 3rd Embodiment. It is a flowchart which shows the processing flow when there exists a write request from CPU in the data evacuation apparatus of 3rd Embodiment. It is a digital circuit diagram explaining the internal structure of the CPU access detection circuit as 4th Embodiment. It is explanatory drawing which shows the pipeline process of CPU used in 4th Embodiment. It is the digital circuit diagram which showed a part of CPU access detection circuit of 4th Embodiment. In a 5th embodiment, it is a flow chart which shows a processing flow when there is a read demand from CPU. In 6th Embodiment, it is a flowchart which shows the processing flow when there exists a read request from CPU.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... ROM, 2 ... CPU, 3 ... Data saving device, 4 ... 1st memory area, 5 ... 2nd memory area, 6 ... Instruction side address bus, 7 ... Instruction side control bus, 8 ... Instruction side data bus 9, data side address bus, 10 ... data side control bus, 11 ... data side data bus, 12 ... first memory side address bus, 13 ... first memory side control bus, 14 ... first memory side data bus, 15 2nd memory side address bus, 16 ... 2nd memory side control bus, 17 ... 2nd memory side data bus, 18 ... Memory write request detection circuit, 19 ... Queue storage circuit, 20 ... CPU access detection circuit, 21 ... Queue processing circuit, 22 ... NOR element, 23 ... output line, 24 ... address decoding circuit, 25 ... AND element, 26 ... same read address determination circuit, 27 ... Nto1 selector, 28 ... 2to DESCRIPTION OF SYMBOLS 1 selector, 29 ... Comparator, 30 ... Selection signal generation circuit, 31 ... Data rewriting circuit, 32 ... OR element, 33 ... Saved data determination circuit, 34 ... Saved address list, 35 ... Parallel flip-flop, 36 ... Memory Access command discriminating circuit, 37 ... series flip-flop

Claims (15)

A data evacuation device that is connected to an address bus, a data bus, and a control bus for the CPU to transmit various signals to a memory to be accessed, and evacuates data in the memory to a evacuation memory,
Memory write detection means for detecting a write signal to the memory transmitted from the CPU via the control bus;
When the write signal is detected by the memory write detection means, a write destination address and write data respectively transmitted from the CPU via the address bus and the data bus are stored in a queue as a set of entries. Matrix storage means;
CPU access detection means for detecting a state in which the CPU does not read or write data to the memory to be accessed;
While the CPU access detecting unit detects that the CPU does not read or write data, the entry is taken out from the queue and stored in the entry write destination address. And a queue processing means for performing a write process for storing the write data of the entry at the write destination address. The CPU access detection means monitors the presence or absence of a read signal and a write signal transmitted via the control bus, and the CPU reads data when neither the read signal nor the write signal is transmitted. The data evacuation apparatus according to claim 1, wherein the data evacuation device is detected as a state where neither writing nor writing is performed. The CPU access detecting means is connected to an instruction bus to which an instruction signal for the CPU is transmitted, and monitors the instruction bus to detect a state in which the CPU does not read or write data. The data saving apparatus according to claim 1. The CPU access detecting means further detects that the CPU reads data from the memory to be accessed,
The queue processing means includes
When it is detected by the CPU access detecting means that the data is read, the read destination address corresponding to the read is taken out from the address bus, and the read destination address and the write destination address stored in the queue are obtained. The same read address determination means for comparing whether or not the same address exists,
When it is determined by the same read address determination means that the same address exists, the write data paired with the address is taken out from the queue, and the write data is transmitted to the CPU as read data, and the same Read data transmission means for taking out data stored in the read destination address from the memory and transmitting the data to the CPU as read data when the read address determination means determines that the same address does not exist. The data evacuation device according to claim 1, wherein The queue processing means further includes:
If the same read address determination means determines that there are a plurality of the same addresses, the write data paired with the address stored most recently in the queue among the same addresses is transmitted to the CPU. 5. The data saving apparatus according to claim 4, further comprising a same address selection unit that selects the read data. The CPU access detecting means further detects that the CPU writes data to the memory to be accessed,
The queue processing means includes
When it is detected by the CPU access detection means that data writing is performed, a write destination address and write data corresponding to the write are taken out from the address bus and the data bus, respectively, and are written to the write destination address and the queue. The same write address determination means for comparing the stored write destination address to determine whether the same address exists,
Data rewriting means for rewriting the write data paired with the address to the write data taken out from the data bus when the same write address judging means judges that the same address exists. The data evacuation device according to any one of claims 1 to 4. The queue storage means further stores an entry valid tag indicating validity or invalidity of the entry as information included in each entry,
If the same address is determined by the same write address determination means, the data rewrite means is valid for the entry paired with the same address stored in the queue instead of rewriting the write data. The data saving apparatus according to claim 6, wherein the tag is invalidated, and the write destination address and the write data respectively fetched from the address bus and the data bus are stored in a queue as new entries. . The data evacuation device performs the evacuation process and the write process for a part of the memory area of the memory to be accessed,
The data according to any one of claims 1 to 7, wherein the CPU access detection unit detects a state in which the CPU does not read and write data to the partial memory area. Evacuation device. A saved address list storage means for storing a write destination address of data saved in the save memory as a saved address list;
The same save address determination means for comparing the write destination address of the data to be newly saved and the saved address list to determine whether or not the same address exists,
9. The data evacuation apparatus according to claim 1, wherein the queue processing unit does not perform the evacuation process when it is determined by the same evacuation address determination unit that the same address exists. A data evacuation method in which various signals transmitted by a CPU to a memory to be accessed are extracted via an address bus, a data bus, and a control bus, and the data in the memory is evacuated to a evacuation memory,
A memory write detection step of detecting a write signal to the memory transmitted from the CPU via the control bus;
When the write signal is detected in the memory write detection step, a write destination address and write data respectively transmitted from the CPU via the address bus and the data bus are stored in a queue as a set of entries. A matrix storage step;
A CPU access detection step of detecting a state in which the CPU does not read or write data to the memory to be accessed;
While the CPU access detection step detects that the CPU is neither reading nor writing data, the entry is taken out from the queue, and the data stored in the write destination address of the entry And a queuing process step for performing a write process for storing the write data of the entry at the write destination address. In the CPU access detection step, the CPU further detects that the CPU reads data from the memory to be accessed,
The queuing step includes
When it is detected that the data is read in the CPU access detection step, a read destination address corresponding to the read is taken out from the address bus, and the read destination address and the write destination address stored in the queue are obtained. The same read address determination step for determining whether or not the same address exists in comparison,
When it is determined in the same read address determination step that the same address exists, the write data paired with the address is taken out from the queue, the write data is transmitted to the CPU as read data, and the same A read data transmission step of extracting data stored in the read destination address from the memory and transmitting the data as read data to the CPU when it is determined in the read address determination step that the same address does not exist; The data saving method according to claim 10. In the read data transmission step, when it is detected that the data is read in the CPU access detection step, the data previously stored in the read destination address is read from the memory regardless of the determination in the same read address determination step. The data saving method according to claim 11, wherein the data saving method is taken out. The queuing step further comprises:
When it is determined in the same read address determination step that there are a plurality of the same addresses, the write data paired with the address most recently stored in the queue among the same addresses is transmitted to the CPU. The data saving method according to claim 11, further comprising a same address selection step of selecting as read data. The CPU access detecting step further detects that the CPU writes data to the memory to be accessed,
The queuing step includes
When it is detected in the CPU access detection step that data writing is performed, a write destination address and write data corresponding to the write are retrieved from the address bus and the data bus, respectively, and are written to the write destination address and the queue. The same write address determination step for comparing the stored write destination address to determine whether the same address exists,
A data rewriting step of rewriting the write data paired with the address to the write data taken out from the data bus when it is determined in the same write address determination step that the same address exists. The data saving method according to claim 10. In the queue storing step, as information included in each entry, an entry valid tag indicating validity or invalidity of the entry is further stored,
In the data rewriting step, if it is determined in the same write address determining step that the same address exists, instead of rewriting the write data, the entry valid paired with the same address stored in the queue is valid. 15. The data saving method according to claim 14, wherein the tag is invalidated, and the write destination address and the write data respectively fetched from the address bus and the data bus are stored in a queue as new entries. .

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