JP2009177833A - Video memory management for mpeg video decoding/display system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video memory management system for decoding/displaying a video bit stream which represents a video image and displays the video image. <P>SOLUTION: A FlexiRam design and a divided memory manager design are combined. A first FlexiRam 1370a is disposed between a first memory manager 1310a and a first memory 1330a. A second FlexiRam 1380a is disposed between a second memory manager 1320a and a second memory 1340a. A FlexiRam technology is used to compress/decompress all stored video memory data. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to MPEG ("Moving Picture Experts Groups") decoding and display systems, and more particularly to reducing the video memory size required in MPEG decoding and display systems for decoding and displaying video images.

  In the late 1980's, it became necessary to load motion video and related audio on a first generation CD-ROM at 1.4 Mbit / s. To this end, in the late 1980s and early 1990s, the ISO (“International Organization for Standardization”) MPEG committee developed a digital compression standard for video and two-channel stereo audio. This standard is commonly known as MPEG-1, officially known as ISO11172.

  Following MPEG-1, there has been a need to compress entertainment television for transmission media such as satellite, cassette tape, broadcast and CATV. Therefore, in order to make available a digital compression method for full resolution standard definition television (SDTV) or high definition television (HDTV) images, ISO is a second standard known as MPEG-2, officially known as ISO 13818. Developed. The bit rates chosen to optimize MPEG-2 were 4 Mbit / sec and 9 Mbit / sec for SDTV and 20 Mbit / sec for HDTV.

  Neither the MPEG-1 nor the MPEG-2 standard defines which encoding method to use, the encoding process, or details of the encoder. These standards only specify a format for representing the data input to the decoder and a rule set for interpreting these data. These formats for representing data are called syntaxes and can be used to construct various valid data streams called bitstreams. The rules for interpreting the data are called decoding semantics. The ordered set of decoding semantics is called the decoding process.

  The MPEG syntax supports a variety of encoding methods that utilize both spatial and temporal redundancy. Spatial redundancy is exploited using block-based discrete cosine transform (“DCT”) coding of 8 × 8 pixel blocks, followed by quantization, zigzag scanning, and zero-quantized indices and their indices. A variable length encoding of the amplitude is performed. A quantization matrix that allows perceptual weighted quantization of DCT coefficients can be used to discard perceptually irrelevant information, thus further improving coding efficiency. On the other hand, temporal redundancy is used by using motion compensation prediction, forward prediction, backward prediction, and bidirectional prediction.

MPEG provides two types of video data compression methods: intraframe coding and interframe coding.
Intraframe coding is for using spatial redundancy. Many of the interactive requirements can be met with intraframe coding alone. However, for some video signals with low bit rates, the image quality that can be achieved with only intra-frame coding is not sufficient.

  Therefore, temporal redundancy is utilized by the MPEG algorithm that calculates the interframe difference signal called the prediction error. In calculating prediction errors, motion compensation techniques are used to correct predictions for motion. As in H.261, the macroblock (MB) approach has been adopted for motion compensation in MPEG. In a one-way motion estimation called forward prediction, the target MB in the picture to be encoded is matched with a set of moved macroblocks of the same size in past pictures called reference pictures. As in H.261, the macroblock in the reference picture that best matches the target macroblock is used as the prediction MB. The prediction error is then calculated as the difference between the target macroblock and the prediction macroblock.

I. Picture Buffer Size (1) Two Reference Frames In summary, MPEG-2 divides a video picture into three types of pictures (ie, intra “I”, prediction “P”, and bi-directional prediction “B”). By definition, all macroblocks in an I picture must be coded intra (like a baseline JPEG picture). Furthermore, the macroblocks in the P picture can be encoded as intra or non-intra. During non-intra coding of a P picture, the P picture is temporarily predicted from a previously reconstructed picture, thereby coding for the immediately preceding I or P picture. Finally, macroblocks within a B (ie bi-directional prediction) picture may be independently selected as non-intra, such as intra or forward prediction, reverse prediction or forward and reverse (interpolated) prediction. During non-intra coding of a B picture, the picture is coded with reference to the immediately preceding I or P picture as well as the immediately following I or P picture. In terms of coding order, P pictures are causal, while B pictures are not causal and use two surrounding pictures that were accidentally coded for prediction. Regarding the compression efficiency, the I picture has the lowest efficiency, the P picture is somewhat better, and the B picture is the most efficient.

  Every macroblock header contains an element called a macroblock type, which can turn these modes on and off like a switch. The macroblock (or motion type as in MPEG-2) type is perhaps the single most powerful element in the overall video syntax. Picture types (I, P and B) simply extend the scope of semantics to allow macroblock mode.

  A sequence of pictures can consist of almost any pattern of I, P and B pictures. Although having a fixed pattern (eg, IBBPBBPBBPBBPBB) is common in the industry, more advanced encoders optimize the placement of three picture types according to local sequence features in the context of more global features Try to make it.

  As previously explained, in order to reconstruct a B picture, the decoder requires two reference frames (ie, two P frames, one P and I frame each, or two I frames). The video decoding and display system must allocate at least two frames of video memory in order to store two reference frames.

(2) Two half-frames (i) Interlaced video In addition, MPEG-2 defines that a frame can be progressively encoded or interlaced and signaled by a “progressive frame” variable.
Progressive frames are a logical choice for video material organized from film, where all “pixels” are integrated, that is, captured almost at the same moment. The optical image of the scene on the picture is scanned one line at a time, left to right and top to bottom. The details that can be represented in the vertical direction are limited by the number of scan lines. Thus, some of the details of the vertical resolution are lost as a result of raster scan degradation. Similarly, because of the sampling of each scan line, some of the horizontal details are lost.

  Scan line selection involves a trade-off between inconsistent requirements of bandwidth, flicker and resolution. Interlaced frame scans attempt to achieve these trade-offs using frames composed of two field lines sampled at different times, and the two field lines are interleaved, so that Two consecutive lines belong to alternating fields. This is a vertical-temporal tradeoff in spatial and temporal resolution.

  For interlaced pictures, MPEG-2 offers a choice of two “picture structures”. A “field picture” is made up of individual fields that are each divided into macroblocks and encoded separately. On the other hand, in a “frame picture”, each interlaced field pair is interleaved together into one frame, which is then divided into macroblocks and encoded. MPEG-2 requires interlaced video to be displayed as alternating top and bottom fields. However, within a frame, one of the top or bottom fields is temporarily encoded first and sent as the first field picture of the frame. The selection of the frame structure is indicated by one of the MPEG-2 parameters.

  In conventional decoding and display systems that process interlaced frame pictures, the bottom field is a representation of the top field, even if both data reconstructed for the top field and the bottom field are generated simultaneously by the decoder. It will only be displayed after completion, or vice versa. Due to this delay in bottom field display, a buffer of one field (half frame) size is required to store the bottom field for the delayed one. This additional video memory requirement of an additional field (half frame) is in addition to the aforementioned requirement of two frames required to store two reference frames (ie, I and / or P frames). Please note that.

(Ii) 3: 2 pulldown The repeat first field should be repeated for the purpose of frame rate conversion, or a field or frame from the current frame (as in the following example of 30 Hz display vs. 24 Hz encoding) Introduced in MPEG-2 to signal. On average, in a 24 frame / second encoded sequence, every other encoded frame signals a repeat first field flag. Thus, a 24 frame / second (or 48 field / second) encoded sequence becomes a 30 frame / second (60 field / second) display sequence. This process has been known as 3: 2 pulldown for decades. Since the advent of television, most movies seen on NTSC displays have been displayed this way. In MPEG-2 format, the repeat first field flag is determined independently in every frame-structured picture, so the actual pattern can be irregular (it doesn't have to be every other frame literally) .

  For MPEG-2 video, the video display and memory controller must determine by itself when to perform 3: 2 pulldown by checking the flag that comes with the decoded video data. MPEG-2 provides two flags (repeat first field and top field first) that explicitly describe whether a frame or field should be repeated. In a progressive sequence, a frame can be repeated 2-3 times. On the other hand, simple and main profiles are limited to repeated fields only. Furthermore, it is a general syntactic limitation that the repeat first field can be signaled only in progressive frame structured pictures (value = 1).

  For example, in the most common scenario, one film sequence includes 24 frames per second. However, the frame rate element in the sequence header indicates 30 frames / second. On average, every other encoded frame sends a repeat field (repeat first field = 1) signal to pad the frame rate from 24 Hz to 30 Hz. That is, (24 encoded frames / second) * (2 fields / encoded frames) * (5 display fields / 4 encoded fields) = 60 display fields / second = 30 display frames / second.

  For systems with 3: 2 pull-down capability, another extra field (half frame) of video memory is needed to store the first displayed field for later repetition (3: 2 pull-down protocol). by). This is because the first displayed field is needed again for display after the second field is displayed. To explain this requirement, if a top field is displayed during decoding, then the bottom field is displayed following the completion of the display of the top field. However, this top field is needed for display again after the system finishes the bottom field display (ie, 3: 2 pulldown). Since the top field is required for display at two different moments (ie before and after the bottom field display), another half frame (one field) of video memory is required to store the top field. In order to display an MPEG-2 video picture, the conventional system adds up the aforementioned 2.5 frames needed to store two reference frames plus a half frame to display an interlaced picture. Requires 3 frames of video memory.

(Iii) Still Frames In some newly designed MPEG-2 video decoding and display systems, the user can also freeze the currently displayed frame. Under the “still frame” condition, the video decoding / display system repeatedly displays the currently displayed picture until further instruction from the user. Since no further decoding and 3: 2 pulldown are required during the pause, the two half-frames described above (ie, display of interlaced pictures and 3: 2 pulldown) are not required. However, if the frozen frame being displayed is a progressive B frame, the entire B frame needs to be stored in the video system, so extra memory in the video memory is needed to store the currently displayed B frame. A frame is needed. It is true that no extra video memory is required if the frozen frame is an I or P frame. This is because these two reference frames are already stored in the video memory (as a forward prediction frame and a backward prediction frame). However, normally B frames are not stored in the video memory for reference, so an extra frame of video memory is needed for B frame display. Thus, in order to display an accurate image of a B-frame picture, in addition to the two frames required to store the reference frame, another full frame of video memory is required.

II. Problems faced by conventional video decoding and display systems The MPEG-2 main profile main level system specifies that it has a sampling limit (720 x 480 x 30 Hz for NTSC and 720 x 576 x 24 Hz for PAL) in CCIR601 parameters Has been. The term “profile” is used to limit the syntax (ie, algorithm) used in MPEG, and the term “level” limits the encoding parameters (sample rate, frame size, encoded bit rate, etc.). Used to do. Along with that, the video main profile main level standardizes complexity with the feasible limitations of 1994 VLSI technology and still meets the requirements of most applications.

  For CCIR 601 rate video, the 3 frames required for the PAL / SECAM decoding and display system exceed the decoder's video memory requirements beyond the normal 16 Mbit (2 Mbyte) limit and 32-Mbit next level memory Push to design. This memory constraint is discussed in US Pat. No. 5,646,693 by Cismas, registered on July 8, 1997 and assigned to the same assignee as the present application. This patent is hereby incorporated by reference in its entirety. As has been well documented in the prior art, increasing video memory beyond 16-Mbits complicates the design of the memory controller and adds to the cost of manufacturing another 16Mbit video memory.

  Patent Document 1 discloses a system and method for decoding and displaying MPEG video using a frame buffer that is smaller in size than normal video memory requirements (ie, three frames of memory). During decoding and display, the system of Patent Document 1 stores only a part of the second field when the first field is being displayed, instead of storing the complete second field. When the second field is required for display, the decoder again decodes the missing portion of the second field to generate the remaining data for the second field display. By reusing the same storage location allocated for the first displayed field to display the second field, the decoding and display system saves up to half a frame of memory (depending on the number of partitions). ). However, even if the system of Patent Document 1 solves the problem of video memory shortage during display, the system of Patent Document 1 performs additional decoding for decoding the missing part of the second field for the second time. Requires power. Therefore, a new video memory management system is desired that can achieve the same purpose as that of US Pat.

  Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

US Pat. No. 5,646,693

  The present invention is directed to an improved video memory control system for handling video memory used for decoding and displaying a bit stream of compressed video data. In particular, the present invention is directed to a video memory management system for receiving a bitstream of compressed video data, decoding the compressed video data, and displaying the images contained therein. .

  One aspect of this memory management system is to provide a modular memory management system or apparatus for handling video memory management. More particularly, the video decoding and display system of the present invention consists of a split memory manager having two separate memory managers. Each of these memory managers handles a specific memory management function. By dividing the memory management function among the various memory managers, decoding and display of video data can be performed more efficiently.

  Another aspect of the present invention provides a novel method for processing and handling video memory, thereby providing an efficient method for handling MPEG-2 data streams. In particular, a segmented reusable video memory management system is disclosed.

  Another aspect of the present invention is to provide an intra-frame video data compression system that can further reduce the size of video memory required for video decoding and display systems.

  The accompanying drawings are included in and constitute a part of this specification and exemplify the preferred embodiments of the present invention, the general description given above and the detailed description of the preferred embodiments given below. At the same time, it helps to explain the principle of the present invention.

1 shows a conventional video decoding / display system. 2 illustrates a preferred embodiment of the split memory manager design of the present invention. 4 illustrates another preferred embodiment of the split memory manager design of the present invention. A method for indirectly addressing video memory using a display segment list and a memory segment list is shown. Details of the memory segment list are shown. The details of the display segment list are shown. FIG. 4 shows the positioning of two write pointers and a read pointer on the display segment list for (a) frame picture format and (b) field picture format. FIG. 2 is a block diagram showing details of a segmented reusable video memory design (named by the inventor as a rolling memory design). Details of initialization of the display segment list for each picture are shown. Fig. 4 shows the writing of the decoded video data of each macroblock row into the video memory. Details of updating the display segment list are shown. 3 shows three preferred embodiments of the FlexiRam design. Fig. 4 shows one of three other preferred embodiments of the FlexiRam design. Fig. 4 shows one of three other preferred embodiments of the FlexiRam design. Fig. 4 shows one of three other preferred embodiments of the FlexiRam design. It is a block diagram which shows the step of video data compression and decompression | restoration. Fig. 4 shows a quartet video data format during various stages of compression and decompression.

  The invention will be described with reference to several preferred embodiments. The preferred embodiment is an apparatus and method for handling and processing video data. The following three aspects of the present invention are discussed in detail. (2) segmented reusable memory design (named by the inventor as “rolling memory design”), and (3) simple fixed low without considering method and application. Bit rate assisted compression technology (named "FlexiRam" by the inventor). All three aspects of the present invention are disclosed for efficient handling of video memory data and can be implemented in a single video decoding and display system.

1. Divided Video Memory Manager FIG. 1 illustrates a conventional video decoding and display system, which comprises a decoder 110, a memory manager 120, a video memory 130, and a display subsystem 140. A continuous bit stream of encoded video data is provided to decoder 110 for decoding and display. A continuous bit stream of video data is supplied at a constant or variable bit rate, depending on the overall system design. Decoder 110 restores the bitstream and then provides the restored data to memory manager 120. The memory manager 120 serves to store the restored video data in the video memory 130 and supply the video data to the display subsystem 140.

  The video memory 130 basically performs two main functions. That is, first, it serves as a video data buffer to buffer different processing measures between decoding the incoming bitstream of video data and displaying the decoded video image. In order to prevent any interruption of the video image display, the decoder 110 is generally required to recover the video data faster than the request from the display subsystem 140. Second, video memory 130 needs to store reference frame data (ie, I and P frames) and provide to decoder 110 to reconstruct the video image from the incoming bitstream of data. . Thus, as shown in FIG. 1, the data bus between the decoder 110 and the memory manager 120 is bi-directional so that the recovered data flows to and from the memory manager 120.

  FIG. 2 illustrates the novel partitioned memory manager design disclosed by the present invention. Instead of the conventional single memory manager design as shown in FIG. 1, the memory manager of the present invention consists of two separate memory managers. That is, the first memory manager 210 and the second memory manager 220. Each memory manager is coupled to a video memory (ie, first memory 230 and second memory 240).

  As discussed in the previous paragraph, there are basically two groups of video data stored in video memory. Reference frame data (ie, I and P frames) and bidirectional frame data (ie, B frames). Since these two groups of video data are handled differently in both decoding and display, the handling of video memory between these two groups of video data is quite different.

  In a preferred embodiment of the present invention, the first memory manager 210 and the combined first memory 230 are allocated to handle and store reference frames (ie, I and P frames), whereas the second memory manager 220 and The combined second memory 240 is allocated to handle and store bi-directional frame (ie, B frame) data. By dividing the video memory controller into two separate and separate memory controllers, each of the two controllers is implemented to perform the most efficient memory management and / or compression method for handling each type of video data. Can be specially designed. By dividing the conventional memory manager into two separate managers, video data can be handled more efficiently than conventional video decoding and display systems, while having the advantage of having a simple system design. Invented by the invention.

  For example, in the video memory management system disclosed in Patent Document 1, the memory management method is directed to the B frame. In a preferred embodiment using a split memory manager design, the first memory manager 210 or 310 and the attached first memory 230 or 330 perform conventional video memory management functions, whereas the second memory manager 220 or 320. And only the attached second memory 240 or 340 can be designed to perform the memory management technique of US Pat. Thus, the ability of the present invention to customize specific video memory management techniques for individual types of video data provides video system designers with greater design flexibility over conventional designs.

Furthermore, in another preferred embodiment, the present invention comprises three memory managers. The first memory manager handles I frames. The second manager handles P frames. Furthermore, the third memory manager handles only B frames.
In another preferred embodiment, the present invention comprises three memory managers. Each of the three memory managers handles one of the three color components (eg, Y, U, and V).

In a further preferred embodiment having multiple memory managers, each of the memory managers can handle different combinations of video data types (eg, color components) and / or groups (eg, reference frames or bi-directional frames). . For example, in a preferred embodiment, the video decoding and display system includes a first memory manager for handling Y chroma components for I pictures, a second memory manager for handling U and V chroma components for B pictures, I and It consists of a third memory manager for handling U and V chroma components for P pictures and a fourth memory manager for handling the remaining video data. Each of the four memory managers can utilize a different memory management technique.
Since the design flexibility provided by the split memory manager design of the present invention is almost unlimited, individual memory managers can be customized to suit a particular type or definition of video data.

  FIG. 3 shows another preferred embodiment of the present invention. Under the MPEG-2 main profile main level definition, the repeat first field is not allowed for B frames for the PAL standard. Thus, in a preferred embodiment designed for an MPEG-2 main profile main level PAL system, the repeat first field need not be provided to the second memory manager 320. This is because the second memory manager 320 processes only B frame pictures. However, the top field first signal is still needed for both the first memory manager 310 and the second memory manager 320 for handling interlaced pictures.

2. Segmented Reusable Video Memory Design Another aspect of the present invention is directed to a method of handling video memory allocation for a video decoding and display system capable of handling both field pictures and frame pictures.
As previously described, MPEG-2 provides a choice of two picture structures for interlaced pictures. A field picture consists of individual fields, each divided into macroblocks and individually encoded. On the other hand, in a frame picture, each interlaced field pair is interleaved together into one frame, which is then divided into macroblocks and encoded. MPEG-2 requires interlaced video to be displayed as alternating top and bottom fields. However, within a frame, one of the top or bottom fields can be temporarily encoded first and sent as the first field picture of the frame according to a predefined definition. Due to differences in the sequence of decoded data for the two picture structures, the reading and writing of the video data defined by these two formats is performed in two different orders.

  FIG. 4 illustrates a preferred embodiment of the present invention. As shown, the video memory 410 is partitioned into a number of memory segments. Each of the memory segments can store eight consecutive lines of video data in one of two fields. The memory manager creates and maintains two lists, MS (memory segment) 420 and DS (display segment) 430. Each memory segment is indirectly addressed by an entry in the display segment list 430 via an entry in the memory segment list 420. The MS list 420 has as many entries as video memory segments, and each entry in the MS list corresponds to one memory segment. In the preferred embodiment, MS list 420 has 48 entries for addressing 48 memory segments into video memory 410. For the PAL case, 48 memory segments in the video memory correspond to 2/3 of the frame. Each entry in the MS list 420 includes a 20-bit address that defines the first cell address of a memory segment in the video memory 410. These addresses may be static or dynamic depending on the system design. For example, in a dedicated system specifically designed for decoding and displaying MPEG-2 video data, the addresses are preferably static and not dynamic to reduce system overhead. However, in a multi-purpose digital decoding and display system, such as a system capable of displaying both MPEG-1 and MPEG-2 video data, these addresses are preferably dynamic so as to accommodate various video memory management methods. Maintained.

  In the preferred embodiment as shown in FIG. 4, the DS list 430 maps the video memory 410 to the display screen. The display screen is logically divided into a number of segments, and each entry in the DS list 430 corresponds to one segment of the display screen. In the preferred embodiment, the DS list 430 includes 72 entries, one corresponding to each display segment. The number 72 was chosen because 576 lines are displayed in the PAL format and contain 8 lines of video data for each segment. Therefore, the number 72 = 576/8 is selected.

  As shown in FIGS. 4 and 5, each entry in the MS list 420 has one additional busy bit 510 (“busy bit”) to indicate whether a particular memory segment of video memory is busy. ) Is included. Specifically, if it is written to a memory segment and it is not displayed, it is indicated as busy. Similarly, a non-busy memory segment means that the memory segment has been displayed but no new data is contained therein. For the present invention, it is very important to use the busy bit 510. This is because the switching of the busy bit 510 on each entry in the MS list 420 can be characterized as defining a logical sliding window in the video memory 410. By setting the busy bit 510 "on" and "off" when data is written to and read from the video memory segment, the logical sliding window is in the MS list with the busy bit "on". Defined as all memory segments with corresponding entries. In addition, the logical sliding window is also maintained by incrementing and updating the two DS write pointers (ie, 710 and 720, or 730 and 740) and the read pointer (ie, 750 or 760), as shown in FIG. Is done.

  Even though the memory segment in the video memory 410 and the physical location of the entries in the MS list 420 are not assigned consecutively as the entries in the DS list 430, the logical sliding window is contiguous in the DS list 430. It is defined by the entry. The logical sliding window increases in size after more decoded data is stored in the memory segment in the video memory 410, whereas after the decoded data is read from the memory segment in the video memory 410, the size increases. Decrease. Furthermore, as video data is read from and written to video memory, the logical sliding window shifts in position (ie, down the DS list 430). The key concept of the present invention is that a logically contiguous memory space corresponding to a portion of the display screen can be defined, and the corresponding decoded video data is stored randomly in physical video memory. If present, it is currently written to video memory and is not displayed. An advantage of the present invention is that the size of the physical video memory can be made smaller than a full picture. In theory, the physical memory size can be as small as half the size required to store a full picture (ie half a frame).

  FIG. 4 illustrates the indirect addressing scheme used by the preferred embodiment of the present invention. Each entry in the DS list 430 stores an index that points to one entry in the MS list 420, whereas each entry in the MS list 420 stores the address of a memory segment in the video memory 410.

  In a preferred embodiment, the video decoding and display system of the present invention handles interlaced pictures in both frame picture format and field picture format. Accordingly, as shown in FIG. 6, the DS list 430 is logically divided into two parts. That is, the top portion 610 corresponding to the top field and the bottom portion 620 corresponding to the bottom field. Entries indexed from 0 to 35 belong to the top field, and entries indexed from 36 to 71 belong to the bottom field. In order to match the DS list 430 to the corresponding video memory segment 420, each entry in the DS list 430 includes a 6-bit index (0 to 47) into the MS list 420. Thus, each entry in the DS list 430 refers to an entry in the MS list 420 and indirectly addresses one segment of video memory (see FIG. 4).

As shown in FIG. 7, in the preferred embodiment, three pointers are maintained for the DS list 430. That is, one read pointer (ie, 750 or 760) for reading and displaying, and two write pointers (ie, 710, 720 or 730, 740) for writing video memory.
For field pictures and frame pictures, these three DS pointers are assigned to different positions.

  FIG. 7 (a) shows the positions of these three pointers when the video system is handling frame pictures. To handle a bitstream of video data for frame picture where data is interleaved between two fields, the two write pointers 710, 720 point to two DS entries with 36 intervals in between Set so that each of the two write pointers points to an entry at the same offset position in a different field (ie, top field and bottom field). Further, the read pointer 750 points to the entry of the DS list 430 to be displayed next. To accommodate both the top and bottom fields of the frame picture, the logical sliding window further comprises a logical top window and a logical bottom window. The logical top window defines a sliding window within the top window, which is indicated by successive entries in the top portion of the DS list that indirectly address the memory segment in the video memory, which memory segment is It has been written but not yet displayed. Similarly, a logical bottom window defines a sliding window in the bottom field, which is indicated by successive entries in the bottom portion of the DS list that indirectly address memory segments in video memory, A memory segment has been written but not yet displayed.

  FIG. 7B shows the positions of these pointers when the video decoding / display system is handling field pictures. Since the video data of the field picture is sequentially decoded and supplied by the decoder, the two write pointers 730, 740 are set to have a fixed interval of 1 between them. Further, the read pointer 760 points to an entry of the DS list 430 to be displayed next. In field pictures, the video data is decoded and supplied sequentially, and there is no need to further divide the logical sliding window into logical top and bottom windows as in frame pictures. Thus, a logical sliding window as discussed in the previous paragraph is maintained.

FIG. 8 shows a flowchart for the present invention.
First, during initialization of the video decoding and display system, all busy bits of the MS entry are initialized by the memory manager to NOT busy (ie, set all busy bits of the MS entry to logic 0) (stage). 810).
When the memory manager detects a new picture in the incoming stream of encoded video data, the memory manager initializes the DS list 430, as shown in FIG. 9 (stage 820).

  FIG. 9 shows in detail the step of initializing the DS list 430 for each picture (step 820). Initially, the memory controller checks the format of the picture in the incoming bitstream and determines whether the picture is a field picture or a frame picture by checking the picture structure parameter value (step 910).

  If the video data is in frame picture format, the memory controller next checks the top field first variable to determine if the flag is set (step 930). If the top field needs to be decoded first, the DS read pointer 750 is initialized to 36, the first DS write pointer 710 is set to 0, and the second DS write pointer 720 is set to 36 (stage 960). . On the other hand, if the bottom field needs to be decoded first, the DS read pointer 750 is set to 0, the first DS write pointer 710 is set to 0, and the second DS write pointer 720 is set to 36 (step 970). ).

  As shown in FIG. 9, if the video data is in a field picture format, the memory controller checks a picture structure parameter to determine whether the incoming video data is a top field picture or a bottom field picture (step 920). If the top field needs to be decoded, the three DS pointers are set as follows: That is, the DS read pointer 760 is set to 36, the first DS write pointer 730 is set to 0, and the second DS write pointer 740 is set to 1 (step 940). On the other hand, if the bottom field needs to be decoded, the DS read pointer 760 is set to 0, the first DS write pointer 730 is set to 36, and the second DS write pointer 740 is set to 37 (step 950).

  As shown in FIG. 8, after the DS list is initialized, the memory manager scans the MS list 420 and checks the busy bit 510 of the entry in the MS list 420 to use it in the video memory 410. Check for possible space (stage 830). The memory manager scans the MS list 420 in order from index 0 to index 47 and finds the first two entries that do not have the busy bit 510 set. If there is no such “not busy” segment, or if there is only one such segment, decoding is stopped until the condition is met. The decoder thereby enters a wait stage waiting for two “not busy” video memory segments. Once the data in the video memory segment has been read and displayed, the memory manager sets the corresponding busy bit 510 of the memory segment to logic 0 to store the newly decoded video data. Free the segment.

  When two non-busy memory segments are found, the DS list 430 pointed to by the first DS write pointer (ie, 710 or 720) will have the MS index 420 of the first available memory segment (ie, 0, 1,. 2,... Or 47) is written and the second available memory segment is written to the DS entry pointed to by the second DS write pointer (ie, 720 or 740), so that the two DS write pointers are Two “non-busy” memory segments in 410 are indirectly addressed.

After the DS entry has been updated, the decoder decodes a new macroblock row containing 16 lines of video data (stage 830).
After the macroblock row of video data is decoded, the memory manager stores the decoded video data in video memory at step 840. FIG. 10 shows details of step 840.

  As shown in FIG. 10, if the picture is a field picture, the memory manager uses the MS segment entry indirectly addressed by the first DS write pointer 730 to store the top 8 lines of video data in each macroblock row. Write to the addressed memory segment (step 1030). The memory manager then writes the bottom eight lines of video data for each macroblock row to the memory segment addressed by the MS segment entry indirectly addressed by the second DS write pointer 740 (step 1030).

On the other hand, if the picture is a frame picture, after the decoder decodes the 16 lines of video data of the incoming bitstream (ie, one macroblock row), the memory manager will return the top field of the currently decoded frame. Are written into the memory segment addressed by the first MS segment entry indirectly addressed by the first DS write pointer 710. The memory manager then writes the eight lines of video data corresponding to the bottom field of the currently decoded frame to the memory segment addressed by the second MS segment entry indirectly addressed by the second DS write pointer 720. (Step 1020).
As shown in FIG. 8, following the writing of the video data to the corresponding memory segment, the DS pointer (ie, 710, 720, and 750 or 730, 740, and 760) is then as shown in FIG. It is updated by a different stage (stage 860).

  FIG. 11 shows details of the update operation (stage 860) of the DS pointer (ie, 710, 720, and 750 or 730, 740, and 760). The memory manager first checks whether the video data is in field picture format or frame picture format (stage 1110), and then the memory manager updates the two DS write pointers accordingly (stages 1120 and 1130). ).

If the video data is a frame picture format, both of the two DS write pointers 710 and 720 are advanced by 1 (step 1120). On the other hand, if the video data is in the field picture format, both of the two DS write pointers 730 and 740 are advanced by 2 (step 1130).
After the DS pointer is updated, the memory manager checks whether there is more incoming video data for the current picture. If there is still an incoming video bitstream, the operation returns to the MS list scanning stage as shown in FIG. 8 (stage 870).

  If the incoming bitstream for the current picture ends, the video system then checks whether there are more pictures to be decoded and displayed (step 880). If there are more incoming pictures for decoding and display, the overall operation returns to step 820. The entire operation is completed when there are no more incoming pictures for display (step 890).

  When the system needs additional video data for display, the next 8 lines of data are stored in the video memory 410 using the MS index addressed by the DS read pointer (ie, 750 or 760). Retrieved from memory segment. The address stored in the MS list entry is used to locate the next memory segment to be displayed from the video memory 410. After a particular memory segment is read for display, the busy bit 510 of that MS entry 420 is set to non-busy and the DS read pointer is then incremented by 1 (modulo 72). After the pointer reaches 71, the DS read pointer is reset to the “0” position.

  In one embodiment of the invention, if the memory controller is not fast enough to handle the “indirect addressing” scheme described above, the DS list 430 entry is increased from 6 bits to 26 bits; Thereby, when the address of the memory segment is selected in the MS entry, it is copied to the DS entry along with the MS list 420 index. By writing the address of the memory segment to the DS list along with the MS list 420 entry, an extra step of addressing and retrieving data from the MS list 420 can be avoided.

3. FLEXIRAM Design Another aspect of the present invention is directed to an intra-frame video memory compression / decompression method.
In the present invention, the video data is compressed lossy or lossless before being stored in the video memory, and the compressed data is decompressed when it is read from the video memory. This video data compression / decompression apparatus is named “FlexiRam” by the present inventors.

FIG. 12 shows three different embodiments of the present invention.
In a preferred embodiment as shown in FIG. 12 (a), the FlexiRam 1220a of the present invention is incorporated into the memory manager 1210a, and all compression and decompression of video data is performed within the memory manager 1210a. The advantage of this embodiment is that there are no special hardware requirements for video memory 1230a and that both compression and decompression of video data are transparent to video memory 1230a.

  FIG. 12 (b) illustrates another preferred embodiment of the present invention, where FlexiRam 1220b is separate from both memory manager 1210b and video memory 1230b. An advantage of this embodiment is that the present invention can be implemented without substantial modification of the entire video decoding and display system.

  FIG. 12 (c) shows another embodiment of the present invention, where the FlexiRam 1220c is incorporated into the video memory 1230c. The advantage of this embodiment is that the entire data compression and decompression operation is transparent to the memory manager 1210c and does not add any overhead to the memory manager 1210c.

  It should be noted that the present invention works with all picture types (I, P and B) and is not limited to any type of picture. Thus, if desired, the present invention can be implemented in a split memory manager design using (a) the second memory manager 240 or (b) both the first memory manager 230 and the second memory manager 240 (FIG. 2).

  Figures 13a, 13b and 13c illustrate three different embodiments of the present invention combining a FlexiRam design and a split memory manager design. FIG. 13a shows one of two preferred embodiments of the present invention. In this embodiment, two FlexiRam compressor / decoders are used. The first FlexiRam 1370a is placed between the first memory manager 1310a and the first memory 1330a. The second FlexiRam 1380a is placed between the second memory manager 1320a and the second memory 1340a, and all stored video memory data is compressed and decompressed using the FlexiRam technology. FIG. 13b shows another embodiment of the present invention. FlexiRam 1370b is placed between the second memory manager 1320b and the second memory 1340b, and only the video data for the bi-directional frame (ie, B) is compressed when stored in the video memory. Finally, FIG. 13c shows yet another embodiment of the present invention. The FlexiRam 1370c is placed between the first memory manager 1310c and the first memory 1330c, and only the video data for the prediction frame (ie, 2I; 1I and 1P; or 2P) is compressed when stored in the video memory. . It should be noted that the present invention does not limit the number of memory managers to two or three. The memory manager may be divided into a number (ie, more than 3) separate memory managers to handle various types and / or groups of video data.

The most important factors when considering which embodiment to implement for a particular system are the amount of video memory available, the available processing speed, the desired image quality, etc. For example, in addition to the embodiments described above The FlexiRam design can be applied to compression and decompression of all three color components or only two chroma color components.

  The design can be further improved by combining all previously disclosed embodiments and aspects. For example, in one embodiment, only the U and V color components in a B picture are compressed with the FlexiRam design. Alternatively, in another embodiment, all three color components for all two picture groups (ie, reference frames or bi-directional frames) are compressed by the FlexiRam design.

  The design flexibility of the present invention in combining split memory manager, FlexiRam, and primary color splits makes system designers most appropriate and effective according to various video system requirements, video memory size, desired image quality, etc. This gives you a great advantage in design freedom, allowing you to choose the right combination.

  FIG. 14 outlines a preferred embodiment of the FlexiRam design. As shown in the figure, data compression consists of two stages. That is, (1) error diffusion (stage 1410) and (2) truncation of one pixel per quartet (stage 1420).

  Initially, the video data is compressed according to an error diffusion algorithm (stage 1410). In a preferred embodiment, a basic compression unit is defined as a “quartet” that includes four consecutive horizontal pixels. The error diffusion compression stage (stage 1410) compresses each pixel of the quartet individually. By using the 1-bit error diffusion algorithm, the quartet of pixels originally having 32 bits (4 pixels * 8 bits / pixel) is compressed to 28 bits (4 pixels * 7 bits / pixel). It should be noted that the present invention is not limited to a 1-bit error diffusion algorithm and that a multi-bit error diffusion algorithm can be implemented as well, but with a perceptible image quality degradation tradeoff.

The second stage of video data compression is “1 pixel truncation per quartet” (stage 1420). The one-pixel truncation algorithm per quartet compresses four 7-bit pixel quartets into a 24-bit quartet. The data compressor calculates the best pixel of the quartet to be truncated and stores the reconstruction method in the last 3 bits of the quartet as a reconstruction descriptor (“RD”). After this compression stage, the compressed quartet of pixels has 24 bits (3 pixels * 7 bits / pixel + 3 bits RD). A detailed algorithm for truncating one pixel per quartet will be described later.
When video data is needed from the video memory, FlexiRam performs decompression on the compressed data read from the memory. The decompression stage is the reverse of the compression stage shown in FIG.

  Initially, one pixel is added back to the 24-bit quartet by the 1-pixel reconstruction algorithm per quartet, which is the inverse of the 1-pixel truncation algorithm per quartet (stage 1430). This restoration phase reconstructs the 7-bit truncated pixel according to the reconstruction method supplied by the RD stored as the last 3 bits of 24 bits representing the quartet. After this restoration stage (stage 1430), the quartet is reshaped and has four 7-bit pixels. A preferred reconstruction algorithm will be described in detail later.

Next, “0” is connected to each 7-bit pixel, and the process returns to the four 8-bit pixel quartets before compression (step 1440). This restoration step (step 1440) reconstructs four 8-bit pixels by concatenating one “0” as the least significant bit for all pixels.
FIG. 15 shows the data format of the quartet of video data (ie, four 8-bit pixels) during various processes in the compression / decompression stage.

Initially, each 8-bit pixel of quartet 1510 is individually compressed using error diffusion algorithm 1520. Intermediate compressed data consists of four 7-bit pixels 1530. These four 7-bit pixels 1530 are then further compressed by a 1 pixel truncation algorithm 1540 per quartet. The final compressed data consists of three 7-bit pixels 1551 and one 3-bit RD1552. The total length of the compressed data is 24 bits.
When video data is needed from the video memory, the compressed data is decompressed in two successive stages:

Initially, one additional pixel is generated according to a one pixel reconstruction algorithm 1560 per quartet. This algorithm is the inverse of the 1 pixel truncation algorithm 1540 based on 3-bit RD1552 of 24-bit compressed data 1550. Intermediate restoration data 1570 consists of four 7-bit pixels. Next, each of the four 7-bit pixels is concatenated with “0” as the least significant bit 1580 to recreate the four 8-bit pixels before compression.
Details of the error diffusion and truncation of one pixel per quartet algorithm are described below.

A. Error diffusion It should be noted that various error diffusion algorithms can be used for this compression stage. The preferred embodiment disclosed below utilizes a 1-bit error diffusion algorithm. However, the present invention is not limited to any particular algorithm used for error diffusion processing. Further, as discussed previously, multiple bits (greater than 1) can be removed by an error diffusion algorithm if more image quality degradation is allowed. Accordingly, the following specific 1-bit error diffusion algorithms are disclosed for illustrative purposes only.

In this preferred embodiment of the invention, the error diffusion (ED) algorithm operates independently on every line in the picture. At the beginning of the line, a 1-bit register labeled “e” is set to 1. “E” stores the currently running error and is updated on a pixel basis. The 1-bit ED algorithm is described by the following two equations.
I _out (j) = 2 * floor [(I _in (j) + e (j)) / 2]
However, if I _in (j) = 255 and e (j) = 1, Iout (j) = 255
e (j + 1) = I _in (j) + e (j) + I _out (j)
Where
j: Index of current pixel in row I _in (j): Original value of pixel I _out (j): New value of pixel (after ED)
e (j): Error accumulator at pixel j time floor (x): After calculating the closest integer I _out (j) less than or equal to x, the least significant bit of I _out (j) is truncated, and this algorithm Quantizes 8-bit pixels to 7-bit pixels while removing pseudo contour effects.

This algorithm can be described, for example, as follows. That is, in one case, assuming that I _in (j) is 182, binary 10010111 and e (j) is 1,
I _out (j) = 2 * floor ((10010111 + 1/2)
= 2 * floor (10011000/2)
= 2 * floor01001100
= 1001100
e (j + 1) = 10010111 + 1-1001100
= 0
By truncating the least significant bit, the stored quantized pixel is = 100110.

  The “e” value is then propagated to the end of the line. Since the ED algorithm of the present invention operates on the raster structure and the picture is written into the block structure memory, it is necessary to store e (j) at the end of the block line. This value is used when the ED continues with the next pixel in the same line (which belongs to the next block). Therefore, an 8-bit latch must be used for all “interrupt” blocks. (Because e can only be 0 or 1, 1 bit is sufficient for every break line).

The decompression stage 1580 is the reverse of the compression stage described above. In the preferred embodiment, the data is concatenated to every pixel with a “0” to recreate four 8-bit pixels.
Each 7-bit pixel is then concatenated with “0” as the least significant bit. For example, “1101101” is reformed to “11011010”. Thus, the resulting data is four 8-bit pixels, similar to the original uncompressed data.

  After the data is compressed using a 1-bit error diffusion algorithm, 4 bits are truncated, thereby compressing a quartet having 4 8-bit pixels into 4 7-bit pixels. It is true that a higher compression ratio can be achieved by executing a “2” bit error diffusion algorithm that can compress a quartet having four 8-bit pixels into four 6-bit pixels. The compression ratio when using the 2-bit error diffusion algorithm is 24/32 × 100% (ie, 75%). However, it is found that there is perceptible image quality degradation after compression and decompression using a 2-bit error diffusion technique. Thus, instead of using a 2-bit error compression technique, the present invention discloses a two-stage compression / decompression process: (1) 1-bit error diffusion, and (2) 1 pixel truncation per quartet. Even if the two techniques have the same compression ratio (ie, 75%), the resulting image quality of the two-stage compression / decompression process disclosed in the present invention is a perceptible improvement over the two-bit error diffusion technique. Bring.

B. One pixel truncation per quartet The second compression stage of the preferred embodiment of the present invention is one pixel truncation per quartet. The one pixel truncation algorithm 1540 compresses four 7-bit pixels into three 7-bit pixels plus a 3-bit reconstruction descriptor (“RD”) (ie, a total of 24 bits).

  It should be noted that various pixel truncation algorithms can be used to reduce the number of pixels stored in the video memory. The present invention is not limited to any particular pixel truncation algorithm and equation used during the compression and decompression process. Furthermore, multiple pixels (greater than 1) can be truncated at a trade-off with image quality degradation. The following truncation of one pixel per quartet is disclosed as a preferred embodiment of the present invention with the best balance of memory savings and little perceptible impact on image quality.

In the preferred embodiment, the four pixels of the quartet are each named consecutively as P0, P1, P2, or P3. Pixels P1 and P2 are two candidates to be truncated. The algorithm predicts (1) which pixels are more suitable for truncation, and (2) what reconstruction method should be used in the reconstruction to estimate the truncated pixels. There are five possible reconstruction methods for each candidate. That is,
1. Copy the one on the left.
2. Copy the right neighbor.
3. Average the left neighbor and the right neighbor.
4). Add 1/4 of the left neighbor and 3/4 of the right neighbor.
5. Add 3/4 of the left neighbor and 1/4 of the right neighbor.

  Theoretically, truncating P1 and estimating it with a copy of P2 is equivalent to truncating P2 and estimating it with a copy of P1. Thus, for two candidates (ie, P1 and P2), there are only 9 (not 10) possible estimators. Further, after truncating one pixel from the quartet, 21 bits are left to represent the remaining three pixels. In the preferred embodiment, the final compressed data target size for each quartet is 24 bits (25% compression). This means that only 3 bits can be assigned to describe the estimator that is selected, so in practice only 8 estimators can be considered. The estimator omitted from consideration is to reconstruct P2 by 3/4 of the left neighbor and 1/4 of the right neighbor. The reason for omitting this particular estimator is that the statistics of the MPEG picture show that it is least likely to be chosen as the best (four quarter, three quarter estimators). The choice is arbitrary.)

Initially, eight estimators are calculated.
P ⁰ ₁ = P0 (P ^k _j represents the estimated amount of Pi using the k method)
P ⁰ ₁ = P2
P ² ₁ = 0.5P0 + 0.5P2
P ³ ₁ = 0.25P0 + 0.75P2
P ⁴ ₁ = 0.75P0 + 0.25P2
P ¹ ₂ = P3
P ² ₂ = 0.5P1 + 0.5P3
P ³ ₂ = 0.25P1 + 0.75P3

For all estimators, the absolute value of the estimation error is defined as E ^k _i = | P ^k _i −Pi |. The minimum error is min _{i, k} {E ^k _l }. If there is a minimum error greater than 1, the selection is arbitrary. (The decision is left pending for execution). Finally, Pj _imin is truncated according to the minimum error, and a 3-bit reconstruction descriptor (RD) is set to indicate the selected estimator, P ^kmin _imin . The 3-bit RD is concatenated with the remaining three 7-bit pixels and together forms a 24-bit compressed quartet. The articulation method is left pending for execution.

  The decompression of compressed data is simply the reverse of the compression algorithm. The missing 7-bit truncated pixels are: (1) which pixel (ie, P1 or P2) to reconstruct, and (2) which reconstruction method to select for reconstruction. It is reconstructed using the last RD.

  As shown in FIG. 15, the data compressor obtains the reconstruction method provided by 3 bits of RD. Next, the pixel for reconstruction (P1 or P2) is determined and pixel reconstruction is performed according to the inverse of the eight equations described above.

  It should be pointed out that the present invention is not limited to any particular method and equation used in the video data compression stage of (1) error diffusion and (2) pixel truncation. An important feature of the FlexiRam design disclosed as the present invention is the specific sequence of these two data compression / decompression stages. That is, the video data is first compressed using an error diffusion algorithm with a reduced number of bits per pixel. The intermediate compressed video data is then further compressed using a pixel truncation algorithm that truncates one pixel from a particular group of pixels. As discussed previously, the decompression process is just the opposite of the compression process.

  While the invention is described in conjunction with the preferred specific embodiments described above, the description and examples are intended to be illustrative and not limiting the scope of the invention, which is defined by the appended claims. It should be understood that it is specified.

Claims (31)

A method for decoding and displaying a bitstream of data representing an encoded video image, comprising:
Decoding a bitstream of the data to provide reference frame data and bi-directional frame data;
Storing the reference frame data in a first video memory;
Storing the bidirectional frame data in a second video memory;
Retrieving the reference frame data from the first video memory;
Retrieving the bidirectional frame data from the second video memory;
Displaying a video image from the bi-directional frame data and the reference frame data;
A method consisting of: The method of claim 1, wherein
A method in which the storage capacity of the second video memory is smaller than a storage capacity sufficient to store decoded video image information for one complete frame. The method of claim 1, wherein
The method wherein the storage capacity of the first video memory is sufficient to store decoded video image information for two complete frames. The method of claim 1, wherein
The storage capacity of the first video memory is sufficient to store decoded video image information for two complete frames, and the storage capacity of the second video memory is decoded for one complete frame. Less than enough storage capacity to store the recorded video image information. The method of claim 1, wherein
The step of storing the bi-directional frame data in the second video memory further comprises a step of compressing the bi-directional frame data before storing in the second memory, and the bi-directional frame data from the second video memory. Extracting the compressed bi-directional frame data further comprises the step of: A video decoding and display system,
A video memory partitioned into a first number of memory segments;
A display picture partitioned into a second number of display segments, each display segment corresponding to an entry in the display segment list, wherein the second number is a display picture greater than the first number;
A memory manager that maintains a logical sliding window, the logical sliding window comprising a third number of display segment list entries, wherein the third number of display segment list entries in the logical sliding window is a video Each display segment entry in the logical sliding window refers to a memory segment having video data that has been written but not yet displayed, and is maintained below a first number of memory segments in memory. A memory manager;
A system consisting of The system of claim 6, wherein
The system in which the display picture is a B picture. The system of claim 6, wherein
The system in which the display picture is an I picture. The system of claim 6, wherein
The system in which the display picture is a P picture. The system of claim 6, wherein
The memory manager releases a display segment entry from a logical sliding window after a corresponding memory segment is read from the video memory. The system of claim 6, wherein
The memory manager adds a display segment entry to a logical sliding window after a corresponding memory segment is written. The system of claim 6, wherein
The memory manager releases the memory segment from the logical sliding window after the memory segment is read from the video memory, and adds the memory segment to the logical sliding window after the memory segment is written. The system of claim 6, wherein
The logical sliding window comprises a logical top window corresponding to a top field of an interlaced picture and a logical bottom window corresponding to a bottom field of the interlaced picture. The system of claim 6, wherein
The video memory manager is a system that handles both field pictures and frame pictures. A video decoding and display system,
Video memory divided into a number of memory segments;
A memory segment list having a number of entries, each entry of the memory segment list corresponding to a memory segment in the video memory and whether the corresponding memory segment is written but not read A memory segment list consisting of busy indicators indicating
A display picture divided into a number of display segments;
A display segment list having a number of entries, each entry of the display segment list comprising an index corresponding to a display segment in a display picture and pointing to an entry in the memory segment list, the display segment list comprising: A display segment list comprising a portion and a bottom portion, each of the top and bottom portions comprising half of a number of entries in the display segment list;
A read pointer pointing to an entry in the display segment list, wherein the memory segment is referenced by an entry in the display segment list pointed to by a read pointer storing video data to be displayed next When,
A first write pointer and a second write pointer pointing to two different entries of the display segment list, wherein the display picture is in a field picture format, and the first write pointer points to an entry in the top portion of the display segment list On the other hand, the second write pointer points to an entry in the bottom portion of the display segment list, and if the display picture is a frame picture format, the first write pointer and the second write pointer are 1 fixed interval therebetween. A first write pointer and a second write pointer,
A system consisting of A system for displaying a video image,
Video memory,
A memory manager for receiving a bitstream of video data representing the video image;
A display subsystem coupled to the memory manager for displaying the video image;
A data compressor coupled to the memory manager and video memory for compressing the video data to be stored in the video memory;
And a data decompressor coupled to the memory manager and a video memory, for restoring the compressed video data read from the video memory for the memory manager. The system of claim 16, wherein
The data compressor is a lossy system. The system of claim 16, wherein
The data compressor is a lossless system. The system of claim 16, wherein
The data compressor includes an error diffusion mechanism and a pixel truncation mechanism for compressing the video data. The system of claim 19, wherein
The data decompressor comprises a pixel reconstruction mechanism and a bit joining mechanism for restoring the compressed video data stored in the video memory. The system of claim 16, wherein
The data compressor includes an error diffusion mechanism and a pixel truncation mechanism for compressing the video data, and the data decompressor reconstructs the compressed video data stored in the video memory. And a system consisting of a bit joining mechanism. The system of claim 21, wherein
The error diffusion mechanism is a 1-bit error diffusion mechanism, the pixel truncation mechanism is a 1-pixel truncation mechanism per quartet, the pixel reconstruction mechanism is a 1-pixel reconstruction mechanism per quartet, and the bit junction mechanism is a zero junction A system that is a mechanism. A method of decoding and displaying a video image,
Decoding a bitstream of encoded video data representing the video image;
Providing the decoded video data to a memory manager;
Compressing the decoded video data;
Storing the compressed video data in a video memory;
Reading the compressed video data from a video memory;
Decompressing compressed video data for a display subsystem displaying the video image;
A method consisting of: 24. The method of claim 23.
The method of compressing the decoded video data is lossy. 24. The method of claim 23.
The method of compressing the decoded video data is lossless. 24. The method of claim 23.
The method of compressing the decoded video data comprises an error diffusion stage and a pixel truncation stage, and the step of restoring the compressed video data comprises a pixel reconstruction stage and a bit joining stage. A system for decoding and displaying a bitstream of data representing an encoded video image,
A decoder for decoding a bitstream of the data, wherein the decoded data comprises reference frame data and bidirectional frame data;
A first video memory manager coupled to the decoder and handling the reference frame data;
A first video memory coupled to the first video memory manager for storing the reference frame data;
A second video memory manager coupled to the decoder and handling the bidirectional frame data;
A second video memory coupled to the second video memory manager for storing the bi-directional frame data;
A display subsystem coupled to the first video memory manager and the second video memory manager for displaying the video image;
A system consisting of 28. The system of claim 27.
A system in which the storage capacity of the second video memory is smaller than a storage capacity sufficient to store decoded video image information for one complete frame. 28. The system of claim 27.
A system wherein the storage capacity of the first video memory is sufficient to store decoded video image information for two complete frames. 28. The system of claim 27.
The storage capacity of the first video memory is sufficient to store decoded video image information for two complete frames, and the storage capacity of the second video memory is decoded for one complete frame. System smaller than sufficient storage capacity to store the recorded video image information. 28. The system of claim 27.
A data compressor coupled to the second video memory manager and the second video memory for compressing the bi-directional frame data to be stored in the second video memory;
A data decompressor coupled to the second video memory manager and the second video memory, for restoring compressed bi-directional frame data read from the second video memory;
A system that further consists of.

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