JP2009176077A - Setup time generation method, device, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively utilize a hardware synthesis system even concerning an object with a large number of variables when allowing a part of processing embodied by software to be hardware by using the hardware synthesis system. <P>SOLUTION: When the setup time of a variable to be exchanged between processing for leaving in the software and processing for making into the hardware, a description part to be made into the hardware in the software is designated, and a variable list where the variables to be referred to in the description part are listed is generated. When an address by tracking a machine language instruction string with the software compiled therein coincides with the address of the variable list, the setup time of the tracking is recorded and updated in the variable of address. Then, the variable list with the setup times of each variable recorded and updated therein is output. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a setup time generation method, apparatus, and program for realizing a part of the processing of a system that is realized by software description such as C language.

Conventionally, when a part of the processing is implemented as hardware with respect to what is specified by the software description, the following procedure is used (for example, see Non-Patent Document 1).
(1) Software language description: A software description that mimics the operation of the system (software code, sometimes referred to as “program”) is created.
(2) Selection of locations for hardware: In the above program, the general hardware design (architecture creation) should be designed with consideration given to processing by dedicated hardware instead of existing processors. Do.
(3) Description change in software language: Decide the procedure for transferring information between the software processing to be performed by the processor and the processing to be performed by the dedicated hardware, and rewrite the program description.
(4) Use of a software compiler: A program is compiled into a machine language and stored in a system that simulates a processor or an instruction memory of an actual processor.
(5) Hardware synthesis (behavioral synthesis): Creates a mechanism for executing a processing procedure using an architecture and a mechanism for executing a procedure for transferring information between processing performed by software.
(6) Combined verification: Machine language instruction sequences generated by compiling a program are stored in a system that simulates a processor, or in an instruction memory of an actual processor, and the hardware obtained from a hardware synthesis system. Simulate the connection or actually connect to confirm the desired operation and performance.

With the above procedure, it is possible to design dedicated hardware for processing a part of the software processing, and to check the function and evaluate the performance in combination with the software.
Kurosaka et al., “System Level Design Flow and Design Language”, Information Processing, Vol. 45, No. 5, 456-463, May 2004 (especially FIG. 8 on page 462)

  However, in the above procedure, the following problems occurred in the process. In other words, when the processing to be implemented in hardware is large, scheduling (hardware fetches or rewrites register values) when the variables to be processed by hardware (the number of registers handled as hardware synthesis systems) become very large. In other words, the time required for wasteful synthesis candidates increases in the processing of the hardware synthesis system.

  Therefore, the designer has given up on the hardware synthesis system to perform the process to be implemented in hardware, and the designer analyzes and designs it. However, there is an increased risk of making mistakes and specifying the location to be verified. Was. In particular, the mechanism for passing information to and from the software in the processing object of the hardware synthesis system is mostly due to manual work and the ingenuity of the designer, and the risks and labor described above are large.

  In this way, in a situation where the number of independent variables and registers is very large in the mechanism of information exchange with the software in the processing target of the hardware synthesis system, the hardware can use the variable (see The analysis result of the time information could not be provided to the hardware synthesis system.

  An object of the present invention is to generate a setup time for variables passed between a process to be left in software and a process to be converted into hardware when a part of the process embodied in software is converted into hardware. Thus, it is to provide a setup time generation method, apparatus, and program that can effectively use a hardware synthesis system even for an object having a large number of variables.

In order to achieve the above object, a setup time generation method according to the first aspect of the present invention provides a method for implementing a part of processing embodied in software by using a hardware synthesis system. A setup time generation method for generating a setup time of a variable passed between a process to be stored in a hardware and a process to be hardwareized, wherein the description part to be hardwareized is specified in the software, and the description Generating a variable list that enumerates the variables referenced in the part, and when the address of the trace of the machine language instruction sequence that compiled the software matches the address of the variable list, set up the trace to the variable at the address It is a feature that records and updates the time and outputs a variable list that records and updates the setup time of each variable. To.
According to a second aspect of the present invention, in the setup time generation method according to the first aspect, the setup time of each variable is output in a format suitable for the hardware implementation.
According to a third aspect of the present invention, in the setup time generation method according to the first or second aspect, when there is a conditional branch in the software, the setup time when the condition is satisfied and the setup time when the condition is not satisfied are recorded and updated. It is characterized by generating a list.
According to a fourth aspect of the present invention, when a part of the processing embodied in software is hardwareized by using a hardware synthesis system, the setup time generating device is hardwareized. A setup time generation device for generating a setup time of a variable passed between processes, a compiler for converting the software into a machine language to generate a machine language instruction sequence, and the software in the software A variable list generation unit that generates a variable list that enumerates variables referred to in a description part of processing to be implemented in hardware; a machine language instruction tracking unit that tracks instruction words in the machine language instruction sequence; and the machine A time variable management unit that updates the time each time the word instruction tracking unit advances the tracking of the instruction word by one step, and the variable list generated by the variable list generation unit Storing and receiving current time information from the time variable management unit and a notification with the address value of the variable from the machine language instruction tracking unit, and when there is an entry having the address value in the variable list, And a variable list management unit that records and updates the setup time of the variable list using the time information as the setup time of the variable.
According to a fifth aspect of the present invention, in the setup time generating device according to the fourth aspect, the setup time of each variable of the variable list management unit is determined relative to the setup time of the variable whose value is determined earliest. An output management unit that converts the data into a format and outputs the data is provided.
The invention according to claim 6 is the setup time generation device according to claim 4 or 5, wherein when the machine language instruction tracking unit detects a conditional branch during tracking of the instruction word, the conditional branch is established. A recursive processing management unit that returns a variable setup time to the machine language instruction tracking unit as a return value, the machine language instruction tracking unit receives the return value from the recursive processing management unit, and the condition branch is satisfied A notification with the address value of the variable including the identifier is sent to the variable list management unit, and a notification with the address value of the variable when the conditional branch is not established is sent to the variable list management unit. Is characterized in that the variable is recorded and updated in the variable list with respect to variables when both the conditions are met and when the conditions are not met.
According to the seventh aspect of the present invention, when a part of the processing embodied in software is made into hardware by using a hardware synthesis system, processing to be left in software and processing to be made into hardware are A program for generating a setup time of variables passed between, a step of designating a description part to be implemented in hardware in the software, and a variable list listing variables referred to in the description part Generating an instruction word of a machine language instruction sequence in which the software is compiled, and when the address by the tracking coincides with an address of the variable list, the tracking time is set in a variable of the address. A step to record and update the setup time and a variable list that records the setup time of each variable are displayed. Characterized in that it comprises the steps of, a.

  ADVANTAGE OF THE INVENTION According to this invention, when making a part of process embodied by software into hardware, the setup time of the variable passed between the process left in software and the process made into hardware can be generated. Therefore, since the setup time can be used as a known condition in the process of planning the order in which registers are used in hardware synthesis, even for a large target with 1000 or more variables. There is an advantage that the hardware synthesis system can be used effectively.

  In the present invention, the processing order sequentially performed by software is analyzed and provided to the hardware synthesis system. Specifically, the setup time of each variable is derived from the software description (variables used by the hardware) and the execution order of machine language instructions optimized / synthesized by the compiler, and this is used as the hardware synthesis system. provide. For the convenience of terminology, the effect of this method on the hardware synthesis system will be described first.

  The following is a process generally performed by a hardware synthesis system. First, storage elements (registers) are assigned to variables. Next, the usage order of the arithmetic units and registers is planned. At that time, the constraint conditions such as the type and number of arithmetic units and the number of registers are satisfied. Next, a hardware description is output in a predetermined description language.

Here, as an example, the case where the calculation of “x + y + z” is processed by hardware for variables x, y, and z will be described with reference to FIG. If the setup time remains unknown, one register is used for storing variables, one each for storing variables x, y, and z, and one for storing operation results. Therefore, a total of four registers R1 to R4 are used. Synthesize it as necessary, and the calculation procedure also
(X + y) + z
(X + z) + y
(Y + z) + x
The hardware is a synthesis candidate for the following three operations. FIG. 1 (a) shows these three candidates. 0000, 0001, 0002, 0003, etc. are the addresses of the registers R1 to R4. The comparative evaluation for these candidates is performed in the design process.

  In this example, there is no particular advantage in all three candidates, and it is obvious that any one may be selected. However, since general synthesis targets are larger and control of execution order is involved, in general, the larger the number of variables, the larger the number of candidates, and the hardware synthesis system can process. Disappear. Moreover, even if the processing can be performed to some extent, the time and effort for the subsequent performance evaluation are increased to an extent that cannot be actually realized.

  In order to avoid this, it is only necessary to avoid generating unnecessary hardware candidates that are not worth considering. To that end, existing hardware synthesis systems take into account various constraints and known external conditions. You can use that you can enter.

  However, in order to give this condition, it is said that the hardware must be determined in detail in advance (architecture design of Non-Patent Document 1: Fig. 8). After determining the variables that the hardware and hardware exchange, and after determining the API (Application Program Interface) from the software side, the design on the hardware side was studied. At this time, how to prepare the registers and in what order the prepared registers are used for processing has been determined based on the experience of the designer.

  On the other hand, the present invention can provide that the setup times of the variables x, y, and z are 1, 2, and 3, respectively. However, the hardware synthesis system uses this as a constraint for the plan. As shown in FIG. 1 (b), a total of three registers R4 to R6 are used, one each for variables x and y and one for calculation results. At this time, the variable z is also used as a register for the variable x or y. The calculation procedure is to calculate “x + y” and temporarily store the result in the calculation result register R6, and then add the variable z to the calculation result. In this way, only one type of hardware can be generated. In this way, according to the method of FIG. 1B, hardware can be generated with a fraction of the labor compared to the method of FIG.

  The number of combinations found in the above example generally increases drastically as the number of types of variables increases. For example, as an analogy to the above, if the number of variables is four, it becomes 6: 1, and if it is five, it becomes 60: 1. The method according to FIG. 1 (b) is the number according to FIG. 1 (a). You can see that it is much less. In FIG. 2, (a) shows a synthesis method without considering the variable setup time, and (b) shows a synthesis method with the variable setup time taken into account. The case of 3 is shown.

<Variable setup time>
It is software processing that creates the value of a variable used for processing by hardware, but there is a time when the value of the variable is not changed after a certain point. A variable is stored as a bit value in a register, which is hardware, in accordance with a mechanism and procedure for transfer to a variable register provided in advance. This storage time is referred to as a variable setup time. When the setup time is generalized, it becomes a variable with some logical conditions, but it is expressed here as the setup time, including the generalized case.

<Transfer variable to register>
Transfer of variables to registers is generally performed by the following method. The guest hardware register is connected to the host processor bus, and when the host processor writes a variable to a certain address, it configures a mechanism that can write the variable to the guest hardware register. Keep it. When writing variables by program processing, write them explicitly in the address area of the guest hardware register.

<Outline of processing to synthesize part of software by hardware>
FIG. 3 shows a flowchart of the entire process. First, as indicated by the preprocessing block 100, a part of a program to be hardware is determined in the original program, and preprocessing is performed so that a variable to be referred to or updated can be identified by hardware. The methods include (1) explicitly describing in the program in advance, and (2) adding identification information to variables to be referenced and updated in the part where the program is analyzed and converted into hardware. For example, in the example of (2), the description part of the process to be converted into hardware is specified in the software described in C language or the like. This specification uses the grammatical structure of a comment, which is an explanatory text that does not affect execution (for example, in C language, the comment part is enclosed by / * and * /), and the conventional compiler prepares the present technology (preprocessing 100). ) Can be used as it is. This is processed by a software compiler, and a function for listing the variables with the above identification is added to the compiler. Then, based on the obtained list and machine language instruction sequence, next, as shown in this processing block 200, a setup time analysis process is performed to obtain a setup time for each variable, and a variable list is generated. Thereafter, as shown by the post-processing block 300, hardware synthesis is performed with the setup time as a constraint.

<Setup time analysis process (Example 1)>
FIG. 4 shows an apparatus configuration for performing the setup time analysis process 200 of the present invention. The compiler 211 takes in “software” written in the C language or the like and subjected to the above-described preprocessing 100, converts it into machine language instructions, and stores them in a “machine language instruction sequence” in the memory.

  When “software” is supplied, the variable list generation unit 212 detects the description portion of the portion to be hardwareized and generates a “variable list” listing the variables referred to in the description. The structure of the “variable list” has a memory address (for example, 0xc0000000) and a variable name (for example, buff [0]) for storing the value of the variable as a pair, as shown in a block 221 in FIG. A database with a record having a field that stores the setup time for the variable. When the variable list generation unit 212 completes the generation of the “variable list”, an instruction of “initial generation completion” is sent to the time variable management unit 213, and the time variable management unit 213 sets the value of the time variable t to t = 0.

  The variable list management unit 214 stores the generated “variable list” and receives the current “time information” from the time variable management unit 213 and the “variable write detection notification” from the machine language instruction tracking unit 215. A function of recording and updating the setup time of the “variable list”, and a function of sending a “variable list” recording the setup time to the output management unit 216 as a “response” to the “inquiry” from the output management unit 216 Have When the variable list management unit 214 receives a “variable write detection notification” with a variable address value from the machine language instruction tracking unit 215, the variable list management unit 214 determines whether there is an entry having the corresponding address value in the “variable list”. If there is, the “time information” from the time variable management unit 3 is recorded and updated as the value of the setup time field of the variable of the address value in the “variable list”.

  The machine language instruction tracking unit 215 traces the instruction word in the “machine language instruction sequence”, detects the instruction that is writing to the memory area, and generates a “variable write detection notification” with the address value. The data is sent to the variable list management unit 214. In the machine language instruction tracking unit 215, by executing the instruction in a pseudo manner, each time the instruction tracking is advanced by one step, the time variable is increased by “time update” to the time variable management unit 213. Send the command. Also, from the description of “machine language instruction sequence” and “software”, the address where the instruction to call the process of hardware synthesis is stored is prepared in advance, the instruction tracking has progressed and the address has been reached In the case where it is reached, a “completion notice” of the process is sent to the output management unit 216.

  As a modification, the “variable list” may be previously referred to from the machine language instruction tracking unit 215, and the translation from the address value to the variable name may be performed by the machine language instruction tracking unit 215. In this case, the machine language instruction tracking unit 215 detects an instruction that writes to a memory area corresponding to a variable registered in the “variable list”. If detected, the machine language instruction tracking unit 215 performs a “variable write detection notification” with a variable name, and the variable list management unit 214 updates the setup time field.

  Further, the machine language instruction tracking unit 215 can shorten the processing time by setting a part of the “machine language instruction string” as a processing target instead of the entire “machine language instruction string”. The processing method is prepared in advance with the address where the instruction for calling the process to be implemented in hardware is stored, so the execution of the instruction is reversed from that address, and all the variables in the “variable list” are The process ends when it finds the writing of, or ends when it reaches the limit address designated in advance from the outside. As will be described later, there may be an implementation example in which a plurality of setup time fields are provided depending on the conditions that are satisfied.

  When the output management unit 216 receives the “completion notification” from the machine language instruction tracking unit 215, the output management unit 216 records a record paired with the setup time for the variables registered in the “variable list” in the variable list management unit 214. Based on the setup time based on the set-up time in a style that matches all the specifications of the hardware synthesis system, such as “giving time constraints that other variables are determined relative to the fastest variable”. Embed a predetermined numerical value and output. At that time, in the above-described series of processing, the variables for which the setup time has never been given are not the same as those for the hardware synthesis system, that is, the variables having the fastest setup time. Is fixed, it is embedded in the constraint style. In the above-described manner, “no setup restrictions” means that 0 is given as the setup time.

  FIG. 5 shows a flowchart of processing when the apparatus configuration of FIG. 4 is realized by a computer and a program. This program can be recorded on a recording medium or provided through a network. Software after the preprocessing 100 is taken in (S1), compiled by the compiler 211 and converted into a “machine language instruction sequence” (S2), and a “variable list” is generated by the variable list generation unit 212. (S3). This “variable list” is, for example, the contents shown in block 221 of FIG. When the generation of the “variable list” is completed, the time as the base point is initialized to t = 0 in the time variable management unit 213 (S4). Thereafter, execution tracking of the machine language instruction sequence is started by the machine language instruction tracking unit 215 (S5), and the setup time of the “variable list” is recorded and updated. Here, the setup time of the “variable list” is recorded and updated in accordance with the current “time information” from the time variable management unit 213 and “variable write detection notification” from the machine language instruction tracking unit 215 ( S6, S7, S8). Block 222 in FIG. 6 shows the start of writing of the “variable list”, and block 223 shows the contents of completion of writing of the setup time in all of the “variable list”. For example, in block 223, “0xc0000000: buff [0]: c1” is a variable with a variable name “buff [0]” whose value is stored at the address “0xc0000000” in the memory, and the value is the machine Since it is determined in the cycle “c1”, the variable setup time is “c1”. Then, when the tracking by the machine language instruction tracking unit 215 reaches the address at which the instruction for calling the hardware synthesis is stored (S9), a “completion notification” is notified to the output management unit 216. Therefore, the output management unit 216 Are embedded in the variables registered in the “variable list” of the variable list management unit 214 in a format suitable for the hardware synthesis system, and output from the output management unit 216. Block 224 in FIG. 6 illustrates the constraints imposed by hardware synthesis in accordance with an example format.

  The block 224 in FIG. 6 is an example of a mode in the case where a constraint is given by an integer value in machine cycle units, and the setup time (the setup time with the smallest value) of the variable whose value is determined earliest is c1. Other setup time is given as a relative value from that value. That is, constraints are given by integer values in machine cycle units such as c1 → 0 (because c1−c1 = 0), c2 → c2−c1, c3 → c3−c1,. As described above, as a method for constraining hardware synthesis, a time constraint in which other variables are determined is given by a time relative to a variable whose value is determined earliest.

  As described above, in the setup time analysis process (part 1) described here, a “variable list” referred to in the hardware synthesis process is prepared, and a certain time (for example, a time for setting a value to a certain variable) is prepared. ) Is used as a base point to record the time to set a value for some variable in a certain unit, for example, how many machine cycles it takes, and the software starts executing the hardware synthesis process (the software shown in FIG. 3). In the example of wear, this is repeated until the call to func_B) is reached, and the constraints based on the setup times of the respective variables obtained as a result are passed to the hardware synthesis system.

<Setup time analysis process (Example 2)>
When analyzing the setup time, even if there is a change due to some condition with respect to the number of machine cycles for writing a value to a variable, the method of the setup analysis process (Example 1) can be used as it is. In this case, the machine cycle number at which the value of the variable is determined most slowly among the changing conditions is obtained as the setup time.

  On the other hand, in the setup time analysis process (Example 2), it is analyzed that the setup time does not change depending on the conditions, and in particular, depending on the conditions that are satisfied, some setup times become early (smaller). It is also possible to pass it to the hardware synthesis system.

  When a conditional branch is included, the branch destination process also affects the setup time of variables set up after the process. The processing shown in FIGS. 4 and 5 is also performed on the processing at the branch destination, and an intermediate result is obtained and is added conditionally. In addition, since there may be a variable that determines the setup time in the process when the branch is not performed, the process is recursive in order to save the number of steps that is not affected by the number of steps at the branch destination.

  FIG. 7 shows an apparatus configuration for performing the setup time analysis process (Example 2). This is an example in which handling for conditional branching is added to the apparatus configuration described in FIG. If you do not go through a branch that causes fluctuations in the number of machine cycles in the middle of tracking, all the descriptions in the list are constant, but may go through a branch that changes in the number of machine cycles in the middle of tracking. Therefore, when the branch passes through the machine cycle number fluctuating, the integration of the machine cycle number is sequentially formulated each time the branch is made using the branch condition as a driving variable.

  The apparatus configuration of FIG. 7 differs from the apparatus configuration of FIG. 4 in that the machine language instruction tracking unit 215 detects a “conditional branch” instruction, and if a “conditional branch” is detected, the branch condition is The calculation of the setup time when established is recursively executed in parallel with the calculation of the setup time when the branch condition is not established.

  When the machine language instruction tracking unit 215 detects a “conditional branch”, the recursive processing management unit 217 creates a copy of the “variable list” and tracks the instruction address being tracked by the machine language instruction tracking unit 215. Duplicate the state and process it recursively. This recursive process ends when the end point of the branch destination process is reached when the condition is met, and the “variable list” at this point with the updated setup time is obtained as the “return value” (output). .

  When the machine language instruction tracking unit 215 obtains the “return value”, the machine language instruction tracking unit 215 restores it based on the tracking state such as the address being tracked, and the “return value” is a variable as “variable write detection notification” together with the identifier of the establishment condition. The data is passed to the list management unit 214.

  The variable list management unit 214 generates a field based on the condition satisfaction identifier in each record, and copies the value of the current setup field. Then, the content of the “return value” is added to the value of the field with the condition identifier.

  As described above, since the setup time is obtained when the condition is satisfied, the machine language instruction tracking unit 215 further executes the tracking of the instruction corresponding to the case where the condition is not satisfied, so that the condition is satisfied. Both of the setup times when not established are stored in the “variable list” field. FIG. 8 shows a flowchart of processing when the apparatus configuration of FIG. 7 is realized by a computer and a program. Steps S10 to S13 are added to the flowchart of FIG. This program can be recorded on a recording medium or provided through a network.

  An example of the setup time when there is a branch condition is shown in FIG. There are four variable names, Buff [k], Buff [i], Buff [s], and Buff [t], and each variable when “Condition 1” is met and when it is not met. Shown what the setup time of will be. For example, for Buff [k], the setup is “2” (given the value of machine cycle 2) when “condition 1” is not satisfied, and “8” when it is satisfied. As for Buff [i], when “condition 1” is satisfied, the setup is “17”, but even when the condition is not satisfied, substitution of the default value to the variable is given at “113”. For Buff [s], no value is assigned (the value does not change) when “condition 1” is satisfied, and “150” is given when it is not satisfied. For Buff [t], if not established, no value is assigned (the value does not change). If established, “37” is given. As described above, when the setup time changes (can be reduced) depending on the specific “condition 1”, the setup time of each variable can be obtained according to the “condition 1” that is satisfied.

  Thus, the setup time analysis process 200 is completed. Up to this point, we know which and when are set up for the variables (registers) of the part to be synthesized. In other words, it was possible to list which variable was passed to the hardware synthesis system and which was set up when.

<Hardware synthesis>
The hardware synthesis system is based on a completely sequential description (program) of the procedure for achieving the calculation process on the premise of a certain number of memory element parts (registers) and arithmetic element parts (calculators). In this way, it is possible to perform part of the subsequent execution simultaneously by finding the dependency relationship of the partial procedures that constitute the process and rearranging the partial procedures so that the results are the same (for example, Tsukamoto et al. "Trends in behavioral synthesis technology," Information Processing, Vol. 45, No. 5, 471-476, May 2004).

  The hardware synthesis system estimates the hardware structure candidates by analyzing the program, and the procedure of when and what processing is to be performed in that structure (when to register which register and computing unit = scheduling) Candidates are generated, it is determined whether or not these candidates satisfy given constraints, and if they are satisfied, the structure and procedure are output.

  In addition to the description (program) in which the processing to be synthesized is written in sequential processing, the hardware synthesis system handles as input some constraints such as the type and quantity of registers and arithmetic units For example, there are restrictions on the time from start to end.

  There are some examples of products and research results in the hardware synthesis system, but in common, all of them have analysis results called data flow graphs or data flow control graphs, and what processing is performed when. When performing scheduling, the result of processing is the same as the original sequential processing (program) by protecting the dependency of what other processing can be started after the processing is completed. Yes.

  The input part to be synthesized with hardware is generally composed of a plurality of registers. The hardware synthesis system has been used so far, assuming that the value held by the register is ready (set up) for processing, and it is impossible to know which is first and after. It was.

  However, based on the data flow graph that the hardware synthesis system originally has as the analysis result of the program, if only some values in a large number of registers are determined in advance, which processing is performed from It is a function that can be realized almost as it is in the past.

  As described above, the present invention provides the setting completion time (setup time) of the register value individually (for each register) to the hardware synthesis system in which such a modification is performed.

<Summary>
As described above, according to the present invention, the hardware can use the variable even in the situation where the number of independent variables and registers is very large in the mechanism of information exchange with the software in the processing target of the hardware synthesis system. There is an advantage that the analysis result (setup time) about the temporal information to be provided can be provided to the hardware synthesis system.

  This makes it possible to use the setup time of variables when the hardware synthesis system plans to use registers, reducing the number of useless combinations, and abandoning the use of the hardware synthesis system until now. In addition, a large-scale processing target in which software processing and many variables of about 1000 or more are sequentially exchanged can be implemented by the hardware synthesis system.

  In the past, since the use of hardware synthesis systems was abandoned, the creation of the mechanism for exchanging information with software, which had been done individually by the designer's ingenuity and idea, can now be standardized as a procedure. The risk of entering is reduced, and the verification location can be clearly determined.

  Furthermore, in the conventional design method, it takes a lot of time and effort to recreate the mechanism for transferring information between software and hardware in a language that describes the hardware, and to repeatedly estimate the performance combined with the software processing. However, if the method of the present invention is used, the hardware synthesis system is generated by reflecting the time (setup time) at which the software determines the variable, so the performance can be calculated as it is. , Can save time.

It is explanatory drawing of a hardware synthesis | combination. It is explanatory drawing of a hardware synthesis | combination. It is a block diagram of an example of the process for carrying out the hardware synthesis | combination of a part of software. It is a block diagram of the apparatus structure of a setup time analysis process (Example 1). It is a flowchart of a setup time analysis process (Example 1). It is explanatory drawing of the transition of the variable list | wrist in a setup time analysis process (Example 1). It is a block diagram of the apparatus structure of a setup time analysis process (Example 2). It is a flowchart of a setup time analysis process (Example 2). It is explanatory drawing of the setup time by a setup time analysis process (Example 2).

Claims (7)

When a part of the processing embodied in software is made into hardware using a hardware synthesis system, the setup time of variables passed between the processing left in the software and the processing made into hardware is reduced. A setup time generation method for generating,
A description part to be hardwareized is specified in the software, a variable list enumerating variables referred to in the description part is generated, and an address obtained by tracking a machine language instruction sequence in which the software is compiled is A setup time generation method characterized in that when it matches an address of the variable list, the tracking setup time is recorded and updated in the variable of the address, and a variable list in which the setup time of each variable is recorded and updated is output. In the setup time generation method according to claim 1,
A setup time generation method, wherein the setup time of each variable is output in a format suitable for the hardware implementation. In the setup time generation method according to claim 1 or 2,
When there is a conditional branch in the software, a setup time generating method is characterized in that a variable list is generated by recording and updating a setup time when the condition is satisfied and a setup time when the condition is not satisfied. When a part of the processing embodied in software is made into hardware using a hardware synthesis system, the setup time of variables passed between the processing left in the software and the processing made into hardware is reduced. A setup time generation device for generating,
A compiler that converts the software into machine language to generate a machine language instruction sequence;
A variable list generation unit that generates a variable list that enumerates variables referred to in the description part of the process to be hardwareized in the software;
A machine language instruction tracking unit that tracks instruction words in the machine language instruction sequence;
A time variable management unit that updates the time each time the machine language instruction tracking unit advances the tracking of the instruction word by one step;
Storing the variable list generated by the variable list generation unit, receiving current time information from the time variable management unit and a notification with the address value of the variable from the machine language instruction tracking unit; When there is an entry having the address value in the variable list management unit for recording and updating the setup time of the variable list, using the time information as the setup time of the variable,
A setup time generation device comprising: In the setup time generation device according to claim 4,
A setup time generation comprising: an output management unit that converts a setup time of each variable of the variable list management unit into a format determined by a relative time with a setup time of a variable whose value is determined earliest. apparatus. In the setup time generation device according to claim 4 or 5,
When the machine language instruction tracking unit detects a conditional branch while tracking the instruction word, the machine language instruction tracking unit includes a recursive processing management unit that returns a variable setup time when the conditional branch is established to the machine language instruction tracking unit as a return value ,
The machine language instruction tracking unit receives the return value from the recursive processing management unit, sends a notification with an address value of a variable including an identifier of the condition for establishing the conditional branch to the variable list management unit, and Send a notification with the address value of the variable when the branch is not established to the variable list management unit,
The variable list management unit records and updates the setup time of both the case where the condition is satisfied and the case where the condition is not satisfied about the variable in the variable list,
A setup time generation device characterized by the above. When a part of the processing embodied in software is made into hardware using a hardware synthesis system, the setup time of variables passed between the processing left in the software and the processing made into hardware is reduced. A program to generate,
Designating the hardware description part of the software;
Generating a variable list enumerating variables referred to in the description part;
Tracing an instruction word of a machine language instruction sequence in which the software is compiled;
When the tracking address matches the address of the variable list, the tracking time is recorded and updated as a setup time in the variable of the address; and
Outputting a variable list that records the setup time of each variable;
A program comprising:

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