JP2009170659A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an arrangement design to suppress a Yupin effect, and to miniaturize and highly integrate a memory cell. <P>SOLUTION: In this nonvolatile semiconductor storage device, stripe-like element formation regions 11 are arranged in parallel to one another, and a plurality of nonvolatile memory cells having charge storage layers 12 and control gates 13 are arranged on each element formation region 11. The charge storage layers 12 of the regions adjacent to each other, out of the element formation regions 11 different from each other, are arranged by being shifted in the stripe direction. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device in which nonvolatile memory cells having a charge storage layer are two-dimensionally arranged, and more particularly to a nonvolatile semiconductor memory device having an improved arrangement of charge storage layers in a NAND flash memory or the like.

  In recent years, with the increase in capacity of flash memory, memory cells have been increasingly miniaturized, and charge storage layers such as floating gates (FG) and SiN films of adjacent cells have come close to each other. For this reason, there is a problem of the so-called YUPIN effect that causes a reading error by changing the threshold value of the corresponding cell due to a leakage electric field caused by charges accumulated in the charge accumulation layer of the adjacent memory cell.

  One effective method for reducing the cost of a NAND flash memory in which memory cells are connected in series is to increase the number of memory bits by increasing the number of cells per unit area by miniaturization. However, if the memory cell that accumulates charges in the floating gate is simply reduced, the distance between the element formation regions and between the floating gates is shortened, and the YUPIN effect is increased as it is.

On the other hand, in MONOS, MNOS, and the like, since the charge is uniformly distributed in the charge storage layer, the charge center can be regarded as being in the center of the charge storage layer. In this case, the distance between the charge centers in the adjacent cells can be increased by an amount corresponding to half the width of the element formation region or the floating gate. However, as memory cells are further miniaturized, MONOS and MNOS face the same problem as described above.
JP 2005-530362 A JP 2007-501531 A

  The present invention has been made in view of the above circumstances, and the object of the present invention is to suppress an increase in the YUPIN effect accompanying the miniaturization of the memory cell, and to miniaturize and increase the integration of the memory cell. An object of the present invention is to provide a non-volatile semiconductor memory device that can be measured.

  In order to solve the above problems, the present invention adopts the following configuration.

  That is, one embodiment of the present invention is a nonvolatile semiconductor memory device in which stripe-shaped element formation regions are arranged in parallel and each element formation region includes a plurality of nonvolatile memory cells each having a charge storage layer and a control gate. In the charge storage layer, adjacent ones of the element formation regions different from each other are arranged so as to be shifted in a stripe direction of the element formation region.

  According to the present invention, the YUPIN effect can be reduced by disposing adjacent charge storage layers in a shifted manner. Accordingly, an increase in the YUPIN effect accompanying the miniaturization of the memory cell can be suppressed, and the miniaturization and high integration of the memory cell can be achieved.

  The details of the present invention will be described below with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a plan view showing a pattern layout of element formation regions and floating gates in a NAND flash memory according to the first embodiment of the present invention.

  In the figure, reference numeral 11 denotes a stripe-shaped element formation region (AA), and a plurality of element formation regions 11 are arranged in parallel. In each element formation region 11, a plurality of floating gates 12 (FG) are arranged to form NAND cells in which memory cells are connected in series. Here, in the present embodiment, the arrangement of the floating gate 12 is different from the conventional one.

  Specifically, in each element formation region 11, the floating gates 12 are arranged at a constant pitch with respect to the stripe direction (Y direction) of the element formation region 11. The floating gates 12 adjacent to each other in the direction orthogonal to the Y direction (X direction), that is, the floating gates 12 adjacent to each other between the different element formation regions 11 are shifted in the Y direction. That is, the floating gates 12 are arranged in a staggered manner.

  In FIG. 1, the planar shape of the floating gate 12 is rectangular for simplicity of explanation, but it becomes a parallelogram depending on how the floating gate is processed, as will be described later. That is, the end portion in the X direction of the floating gate 12 is processed simultaneously with the element formation region 11, but the end portion in the Y direction of the floating gate 12 is processed simultaneously with the control gate. For this reason, if the control gate is parallel to the X direction, the floating gate 12 is rectangular. If the control gate is inclined with respect to the X direction, the floating gate is a parallelogram.

  As described above, when the element forming regions 11 and the floating gates 12 are brought close to each other by miniaturization, the floating gates 12 are not arranged next to each other, but are alternately arranged in a staggered manner. Further, the distance between the floating gates 12 can be increased, and a large number of floating gates 12 can be provided in the same area. That is, the YUPIN effect can be weakened with respect to the bit density.

  FIG. 2 is a plan view showing a configuration in which control gates are arranged with respect to the staggered floating gates as shown in FIG.

  The control gate 13 (CG) is disposed obliquely without being orthogonal to the stripe direction of the element formation region 11 so as to connect the staggered floating gates 12. At this time, since the floating gate 12 is processed simultaneously with the control gate 13, the planar shape of the floating gate 12 is not a rectangle but a parallelogram. That is, the staggered arrangement structure of the floating gate 12 and the element forming region 11 can be realized by self-alignment by CG-FG batch processing from the design of the control gate 13 and the element forming region 11.

  Further, due to the staggered arrangement of the floating gates 12, the overall planar shape of the NAND cell portion is not a general rectangle but a parallelogram. For this reason, peripheral circuit portions 14 such as sense amplifiers and decoders arranged on the end side of the element forming region 11 are also inclined on the NAND cell portion side.

  Here, the effect obtained by staggering the floating gates 12 will be described.

  As shown in FIG. 3A, in the normal NAND cell, the floating gates 12 adjacent to each other in the X direction are arranged without being shifted. In this case, the length of the side closest to and opposite to one floating gate 12 and the other floating gate 12 is L1 which is the same as the length of the floating gate 12 in the Y direction. On the other hand, as shown in FIG. 3B, in the NAND cell of this embodiment, the floating gates 12 adjacent to each other in the X direction are shifted from each other in the Y direction. In this case, the length of the side closest to and opposite to one floating gate 12 and the other floating gate 12 is L2, which is shorter than L1. Therefore, the degree of influence by the charge accumulated in the adjacent floating gate 12 is reduced, and the YUPIN effect can be reduced.

  Further, by rounding the corner portion of the floating gate 12 by oxidation treatment or the like, it is possible to further reduce the influence of the electric charge accumulated in the adjacent floating gate 12.

FIG. 4 is a plan view in the case of rounding the corners of the floating gate 12 of this embodiment, and shows four floating gates 12 (FG ₁₁ , FG ₁₂ , FG ₂₁ , FG ₂₂ ). When the corner portion of the floating gate 12 is rounded, the length of the closest and opposite side between the floating gates FG ₁₁ and FG ₂₁ adjacent in the X direction decreases from L2 to L5.

Here, the planar shape of the floating gate 12 is not a rectangle but a parallelogram, and in the case of a parallelogram, the rounded state differs between an acute angle portion and an obtuse angle portion. In general, since the oxidation treatment is easier to proceed in the acute angle portion than in the obtuse angle portion, the rounding amount is larger in the acute angle portion than in the obtuse angle portion. As is clear from FIG. 4, the reduction in the length of the sides of FG ₁₁ and FG ₂₁ that are closest to each other is due to the rounding of the sharp corners, so the corners of the parallelogram floating gate are rounded off. The effect of processing is greater than that of rounding corners of a normal rectangular floating gate.

Further, attention is paid to the distance between the corners of adjacent floating gates 12. Relates floating gate 12 prior to rounding, paying attention to the distance L7 between the upper right of the lower left and FG ₁₂ distance L6, FG ₂₁ and the lower left of the lower right of the FG ₁₁ and the FG _21. Although both the corners L6 and L7 are shortened by the rounding process at the corners, since the rounding amount at the obtuse corners is small, the decrease in the length of L7 is smaller than that when the floating gate 12 is rectangular. However, since L7 is longer than L6 unless the tilt angle of the control gate 13 is extremely increased, there is almost no problem even if the decrease in L7 is reduced. Since L6 is affected by both the obtuse angle and the acute angle, it is almost the same as the decrease when the floating gate 12 is rectangular. That is, even if the floating gate 12 is a parallelogram, the effect of increasing the distance between the corners is almost the same as that of the rectangular shape.

  Next, a manufacturing method of the NAND flash memory according to the present embodiment will be described with reference to FIGS. In each figure, (a) is a longitudinal sectional view taken along the bit line (a sectional view in the gate length direction, and (b) is a longitudinal sectional view taken along the word line (in the gate width direction). Sectional view).

  First, as shown in FIGS. 5A and 5B, a silicon oxynitride (SiON) film 22 serving as a tunnel insulating film is formed on a semiconductor substrate 21 doped with a predetermined impurity by a thermal oxidation method and a thermal nitridation method. After forming about 10 nm, a polysilicon layer 23 doped with phosphorus (P) and a mask material 24 to be a floating gate are sequentially deposited by a CVD (Chemical Vapor Deposition) method. In this case, the polysilicon layer 23 may be doped with various other impurities such as arsenic (As) instead of phosphorus.

  Subsequently, the mask material 24, the polysilicon layer 23, and the silicon oxynitride film 22 are sequentially patterned by lithography and RIE (Reactive Ion Etching). Further, by etching the semiconductor substrate 21 using the mask material 24 as a mask, an element isolation groove 25 having a depth of about 100 nm from the surface of the semiconductor substrate 21 is formed. The region isolated by the element isolation groove 25 is the element formation region 11 shown in FIG. 1, and a configuration in which the stripe-shaped element formation regions 11 are arranged in parallel is obtained.

  Next, as shown in FIGS. 6A and 6B, a silicon oxide film 26 is deposited on the entire surface of the semiconductor substrate 21 and the mask material 24 so as to fill the element isolation trench 25. Subsequently, the silicon oxide film 26 is polished by a CMP (Chemical Mechanical Polishing) method to planarize the surface, thereby forming a silicon oxide film 26 to be an element isolation insulating film.

  Next, as shown in FIGS. 7A and 7B, a predetermined amount is removed by etching the surface portion of the silicon oxide film 26 using a diluted hydrofluoric acid solution, so that the side surface of the polysilicon layer 23 is about 50 nm. After the exposure, the mask material 24 is removed by selectively etching the exposed mask material 24. Further, the natural oxide film formed on the surface of the polysilicon layer 23 is removed using dilute hydrofluoric acid. At this time, the uppermost surface of the polysilicon layer 23 is above the uppermost surface of the silicon oxide film 26.

Subsequently, the semiconductor substrate 21 is carried into a batch-type deposition apparatus. In this apparatus, alumina (Al ₂ O) serving as an interelectrode insulating film at a temperature of 400 ° C. is formed on the entire surface of the silicon oxide film 26 and the polysilicon layer 23. ₃ ) Deposit film 27. Here, the deposition apparatus is provided with an exhaust mechanism and a gas supply source so that a desired atmosphere can be formed.

In this case, an alumina (Al ₂ O ₃ ) film 27 is deposited as an interelectrode insulating film. For example, hafnia (HfO ₂ ), zirconia (ZrO ₂ ), hafnium silicate (ZrSiO), zirconium silicate (ZrSiO), etc. Various other high dielectric constant films having a relative dielectric constant of 4 or more, such as an oxide film or an oxide film doped with impurities in the oxide film, may be deposited.

  Next, as shown in FIGS. 8A and 8B, a conductive layer 28 having a two-layer structure including, for example, a polysilicon layer and a tungsten (W) silicide layer, which will later become a control gate, is deposited by a CVD method to about 100 nm. Thereafter, a mask material 29 is further deposited.

  Subsequently, the mask material 29, the conductive layer 28, the alumina film 27, the polysilicon layer 23, and the silicon oxynitride film 22 are sequentially patterned by lithography and RIE to form the slit portion 30, thereby forming the polysilicon layer 23. And the control gate 13 made of the conductive layer 28 is formed. By tilting the patterning at this time from a direction orthogonal to the stripes of the element formation region 11, the control gates 12 are arranged in an oblique stripe as shown in FIG.

  Next, as shown in FIGS. 9A and 9B, the exposed surface of the semiconductor substrate 21, the silicon oxynitride film 22, the polysilicon layer 23, the alumina film 27, the conductive layer 28, and the mask material 29 is exposed. Then, a silicon oxide film 31 to be an electrode sidewall insulating film is formed by a thermal oxidation method. By this thermal oxidation, as shown in FIG. 4, the corners of the polysilicon layer 23 that becomes the floating gate 12 are rounded.

  Subsequently, a source region 33a and a drain region 33b are formed by ion implantation, and an interlayer insulating film 32 is formed on the entire surface of the silicon oxide film 31 by CVD. Then, a memory cell transistor of the NAND flash memory is manufactured by forming a wiring layer (not shown).

  FIG. 10A shows a longitudinal sectional view of a NAND flash memory in which the memory cell transistors MC manufactured by the above method are two-dimensionally cut along the bit line BL, and FIG. ) Shows a circuit diagram of the NAND flash memory corresponding to the longitudinal sectional view shown in FIG.

  As shown in FIGS. 10A and 10B, in the NAND flash memory, a source region and a drain region of a plurality of memory cell transistors MC are connected in series between two selection transistors (not shown) to select one of them. The transistor is connected to the bit line BL, and the other selection transistor is connected to a source line (not shown). A word line WL is connected as a wiring layer to the control gate formed of the conductive layer of each memory cell transistor MC.

  In this case, a NAND flash memory is manufactured as the flash memory, but various other flash memories having a structure in which a floating gate and a control gate are stacked, such as a NOR type and an AND type, may be manufactured. . Furthermore, a structure in which an insulating film and a gate electrode are stacked and three or more layers including the insulating film and the gate electrode are formed may be used.

  As described above, according to the present embodiment, by arranging the floating gates 12 (polysilicon layers 23) in a staggered manner, the influence of the accumulated charges of the floating gates 12 adjacent to each other in the bit line direction can be suppressed. The accompanying YUPIN effect can be reduced. Therefore, the NAND cell portion can be miniaturized and highly integrated.

(Second Embodiment)
FIG. 11 is a plan view showing a pattern layout of the NAND flash memory according to the second embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The arrangement of the element formation region 11 and the floating gate 12 is the same as that of the first embodiment, but the control gate 43 is not linear but is zigzag with respect to the direction perpendicular to the stripe direction of the element formation region 11. Yes. That is, the control gate 43 is bent in the opposite direction on the left side surface of each region 11 for each element formation region 11.

  The control gate 43 does not need to be bent for each element formation region, but may be for every two element formation regions as shown in FIG. 12, or for more element formation regions. It may be. Furthermore, the position where the control gate 43 is bent may be on the floating gate 12 as shown in FIG.

  Even with such a configuration, as in the first embodiment described above, the length of the closest and opposite sides of the floating gate 12 adjacent in the bit line direction can be shortened. For this reason, it is possible to suppress the influence of the accumulated charges of the floating gate 12 adjacent in the bit line direction, and the same effect as in the first embodiment can be obtained. In addition, since the NAND cell can be finally stored in a rectangle which is a standard shape of a chip or a device, the NAND cell portion side of the peripheral circuit portion does not need to be inclined, and a general shape can be obtained. There are also advantages that can be made.

(Third embodiment)
FIG. 14 is a plan view showing a pattern layout of a NAND flash memory according to the third embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted. 15A is a cross-sectional view taken along the line AA ′ in FIG. 14, and FIG. 15B is a cross-sectional view taken along the line BB ′ in FIG. In addition, the same code | symbol is attached | subjected to the same part as FIG.

  The floating gates 12 adjacent in the X direction are arranged so as to be shifted by one in the Y direction. The floating gates 12 adjacent to each other in the Y direction are arranged alternately so as to be separated by one or three of the width of the floating gate 12, not at a constant interval. The control gate 53 has a width about twice as large as the Y-direction width of the floating gate 12, and the stripe direction (Y direction) of the element formation region 11 so as to cover each of the floating gates 12 in each element formation region. It is arrange | positioned along the X direction orthogonal to.

  Here, as can be seen from the fact that the width of the floating gate 12 (polysilicon layer 23) in the Y direction is different from the width of the control gate 53 (conductive layer 28), the floating gate 12 is not processed together with the control gate 53. The control gate 53 is processed before processing.

  Even with such a configuration, it is possible to suppress the influence of the accumulated charges of the floating gates adjacent in the bit line direction, and the same effect as in the first embodiment can be obtained. Further, the processing of the control gate 53 becomes relatively simple, and the consistency with the current design is high. Furthermore, since the floating gate 12 and the control gate 43 cannot be collectively processed, separate processing of the floating gate and the control gate and the matching accuracy are required, but when the shape of the floating gate 12 is viewed from above, a circular shape or a hexagonal shape is required. Therefore, the distance between adjacent floating gates 12 can be further increased.

(Fourth embodiment)
FIG. 16 is a plan view showing a pattern layout of a NAND flash memory according to the fourth embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the present embodiment, an arrangement method that is effective for increasing the density of the cells with the floating gate 62 having the greatest mutual distance is realized. That is, the floating gate 62 is processed into a circular shape instead of a parallelogram.

  In order to process the floating gate 62 into a circular shape, a polysilicon film to be the floating gate 62 may be formed and then processed by lithography using a mask. Although it is troublesome in terms of processing to process the floating gate 62 separately from the control gate 13, the floating gate 62 can be arranged so as to obtain a close-packed arrangement.

  In order to place the floating gates 62 in the finest form and the distance between the floating gates 62 is increased, the line / space pitch of the element formation region 11 is 1: 1, and the line / space pitch of the control gate 13 is also 1: Assuming that 1, the floating gate 62 is optimally provided in a staggered manner at an angle of 60 degrees. At this time, it is desirable that the floating gate 62 be processed into a circular shape or a shape close to a regular hexagon. As a result, the floating gates 62 can be separated as much as possible, and the YUPIN effect can be minimized.

(Fifth embodiment)
17 and 18 are cross-sectional views showing the manufacturing process of the flash memory according to the fifth embodiment of the present invention. In this embodiment, a MONOS type memory cell using an insulating film as an electric storage layer is used instead of a memory cell having a two-layer gate structure using a floating gate as a charge storage layer.

  The planar pattern of the gate may be any of the first to fourth embodiments, but here the gate pattern is formed in an oblique direction without being orthogonal to the stripe direction of the element formation region as in FIG. 2 of the first embodiment. It shall be arranged.

First, as shown in FIG. 17A, a silicon oxide film (SiO ₂ ) 72 serving as a tunnel insulating film is formed on a semiconductor substrate 71 doped with a predetermined impurity by a thermal oxidation method to a thickness of about 10 nm. A silicon nitride film (SiN) 73 is formed to a thickness of about 10 nm as a charge storage layer, and an Al ₂ O ₃ film (Al ₂ O ₃ ) 74 is formed to a thickness of about 20 nm as a block layer.

  Next, as shown in FIG. 17B, a tantalum nitride film (TaN) 75 is formed as a first electrode layer on the alumina film 74, and a mask material 76 is formed thereon by lithography. The mask material 76 corresponds to the element formation region pattern.

  Next, as shown in FIG. 17C, the tantalum nitride film 75, the alumina film 74, the silicon nitride film 73, and the silicon oxide film 72 are selectively etched by RIE using a mask material 76, and further, the semiconductor substrate 71 is formed. By etching, an element isolation groove 77 having a depth from the surface of the semiconductor substrate 71 of about 100 nm was formed. The region isolated by the element isolation groove 77 is the element formation region 11 shown in FIG. 1, and a configuration in which the stripe-shaped element formation regions 11 are arranged in parallel is obtained.

Next, as shown in FIG. 18D, a silicon oxide film (SiO ₂ ) 78 is deposited on the entire surface of the semiconductor substrate 71 and the mask material 76 so as to fill the element isolation trench 77. Subsequently, the silicon oxide film 78 is polished by CMP to planarize the surface, thereby forming an element isolation insulating film made of the silicon oxide film 78 and exposing the surface of the mask material 76.

  Next, as shown in FIG. 18E, the mask material 76 is removed by selectively etching the exposed mask material 76. Further, the natural oxide film formed on the surface of the tantalum nitride film 75 is removed using dilute hydrofluoric acid.

  Next, as shown in FIG. 18F, a conductive layer 79 as a second electrode layer was formed by a CVD method. The conductive layer 79 has a two-layer structure including tungsten (W) and a W silicide layer, and is deposited to a thickness of about 100 nm, for example.

  Although not shown in the drawings, the conductive layer 79, silicon oxide film 78, tantalum nitride film 75, alumina film 74, silicon nitride film 73, and silicon oxide film 72 are sequentially patterned by lithography and RIE to form slit portions. As a result, a gate portion is formed. The patterning at this time is tilted from a direction orthogonal to the stripes of the element formation region 11, so that the gates 12 are arranged in an oblique stripe as shown in FIG.

  Thereafter, as in the first embodiment, the exposed surface of the semiconductor substrate 71, silicon oxide film 72, silicon nitride film 73, alumina film 74, conductive layer 75, and conductive layer 79 is exposed. A silicon oxide film to be an electrode sidewall insulating film is formed by a thermal oxidation method. By this thermal oxidation, as shown in FIG. 4, the corner portion of the tantalum nitride film 75 that becomes the gate portion is rounded.

  Subsequently, a source region and a drain region are formed by ion implantation, and an interlayer insulating film is formed on the entire surface of the silicon oxide film by CVD. Then, a MONOS type memory cell transistor is manufactured by forming a wiring layer or the like.

  Even with such a method, the same effects as those of the first embodiment can be obtained, and the memory cell portion can be miniaturized and highly integrated. Further, the pattern of the gate part is not necessarily limited to the same pattern as that of the first embodiment, and may be the same as that of the second to fourth embodiments. Furthermore, MNOS can be used instead of MONOS as the configuration of the memory cell portion.

(Modification)
The present invention is not limited to the above-described embodiments. In the embodiment, the example in which the floating gate is used as the charge storage layer and the example in which the insulating film is used have been described. However, the conditions such as the material and thickness of the charge storage layer can be appropriately changed according to the specification. Furthermore, the L / S pitch of the element formation region and the L / S pitch of the control gate can be appropriately changed according to the specifications.

  Further, the method of manufacturing the nonvolatile semiconductor memory device of the present invention is not limited to the method described in the first embodiment, and it is needless to say that the method can be changed as appropriate. In addition, various modifications can be made without departing from the scope of the present invention.

FIG. 3 is a plan view showing a pattern layout of element formation regions and floating gates in the NAND flash memory according to the first embodiment. 1 is a plan view showing a pattern layout of a NAND flash memory according to a first embodiment. The schematic diagram for demonstrating the effect by shifting arrangement | positioning of a floating gate. The schematic diagram for demonstrating the effect by performing a rounding process to a floating gate. Sectional drawing which shows the manufacturing process of the NAND flash memory of 1st Embodiment. Sectional drawing which shows the manufacturing process of the NAND flash memory of 1st Embodiment. Sectional drawing which shows the manufacturing process of the NAND flash memory of 1st Embodiment. Sectional drawing which shows the manufacturing process of the NAND flash memory of 1st Embodiment. Sectional drawing which shows the manufacturing process of the NAND flash memory of 1st Embodiment. FIG. 3 is a diagram showing a cross section and a circuit configuration when cut along the bit line direction of the NAND flash memory according to the first embodiment. FIG. 5 is a plan view showing a pattern layout of a NAND flash memory according to a second embodiment. The top view which shows the modification of 2nd Embodiment. The top view which shows the modification of 2nd Embodiment. FIG. 6 is a plan view showing a pattern layout of a NAND flash memory according to a third embodiment. FIG. 15 is a sectional view taken along the line A-A ′ and a sectional view taken along the line B-B ′ in FIG. 14. FIG. 9 is a plan view showing a pattern layout of a NAND flash memory according to a fourth embodiment. Sectional drawing which shows the manufacturing process of the flash memory concerning 5th Embodiment. Sectional drawing which shows the manufacturing process of the flash memory concerning 5th Embodiment.

Explanation of symbols

11, 21 ... Semiconductor substrate 12, 62 ... Floating gate (charge storage layer)
13,43,53 ... control gate 14 ... peripheral circuit portion 22 ... silicon oxynitride (SiON) film 23 ... polysilicon layer 24 ... mask material 25 ... isolation trench 26 ... silicon oxide film 27 ... alumina (Al ₂ O ₃₎ Film 28 ... Conductive layer 29 ... Mask material 30 ... Slit 31 ... Silicon oxide film 32 ... Correlation insulating film

Claims (5)

A non-volatile semiconductor memory device in which stripe-shaped element formation regions are arranged in parallel, and each element formation region includes a plurality of non-volatile memory cells each having a charge storage layer and a control gate,
2. The nonvolatile semiconductor memory device according to claim 1, wherein the charge storage layers adjacent to each other between the different element formation regions are arranged shifted in a stripe direction of the element formation region.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the wiring of the control gate is disposed obliquely with respect to a direction orthogonal to the stripe direction in accordance with the arrangement of the charge storage layer.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the wiring of the control gate is arranged in a zigzag manner in a direction orthogonal to the stripe direction in accordance with the arrangement of the charge storage layer.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the planar shape of the charge storage layer is a parallelogram, and the corners of the charge storage layer are round.   The memory cell has a two-layer gate configuration having a floating gate as the charge storage layer and the control gate, or a configuration using an insulating film as the charge storage layer, and is connected in series in the stripe direction of the element formation region. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a NAND cell is configured.

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