JP2009170535A - Semiconductor light emitting element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical semiconductor element small in an occupation area, easily manufacturable, and provided with an electrostatic breakdown prevention means. <P>SOLUTION: This optical semiconductor element has electrostatic breakdown prevention element 111a and 111b electrically connected in parallel to a light emitting part formed on a semiconductor substrate 101 and including an active layer 104, and is characterized in that the electrostatic breakdown prevention elements 111a and 111b are provided with a plurality of pin type diodes stacked in a direction vertical to the semiconductor substrate 101, and electrically connected in the same direction, and a tunnel junction is formed on each interface between the pin type diodes adjacent to each other. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an optical semiconductor element used in the field of optical communication.

  Since optical communication is capable of long-distance and large-capacity transmission, long-distance communication has been widely used practically from early on. In general, a semiconductor laser is used as a light source in an optical communication transmitter.

  A semiconductor device may receive static electricity accumulated in an apparatus or a person during a manufacturing process or at the time of mounting, and initial characteristics or reliability may be reduced. In order to avoid such electrostatic breakdown, an electrostatic breakdown prevention circuit and a capacitor are added to the device. In particular, it is said that a diode such as a semiconductor laser is more damaged when static electricity is applied in the reverse direction than in the forward direction. As a means for avoiding this, a structure in which another diode is attached in parallel and in the opposite direction is often used.

  On the other hand, the forward direction has not been emphasized so far, but forward electrostatic breakdown is also becoming a problem as the speed of the laser diode (LD) increases. First, it is effective to reduce the area of the active layer in order to increase the speed of the LD. However, the smaller the active layer area, the higher the current density flowing through the active layer when static electricity is applied. . Second, to increase the speed, it is necessary to reduce the parasitic capacitance. In that case, the current flowing through the parasitic capacitance decreases when static electricity is applied, and most of the current flows through the active layer. is there.

  A countermeasure against forward electrostatic breakdown is one using a Zener diode. This is one in which a zener diode is connected in parallel with the laser and in the opposite direction, and is described in Patent Document 1, for example. The breakdown voltage of the Zener diode is set higher than the operating voltage of the laser and normally does not flow to the Zener diode side, but when a high voltage is applied, the Zener diode is turned on and current flows to the LD side. Can be prevented. In addition, since the Zener diode functions as a normal diode in the forward direction, the structure in which the Zener diode is connected to the LD in the reverse direction has the advantage of being effective in preventing both forward and reverse electrostatic breakdown with respect to the LD. is there.

As another countermeasure, there is a method using a diode array in which diodes are connected in series. When this diode string is connected in parallel to the device to be protected, a current flows through the diode string when a high voltage is applied in the forward direction, so that the current flowing through the device can be suppressed. In addition, since the electric capacitance is connected in series with the capacitance of each diode, it can be made relatively small, and the influence on the modulation speed can be kept small. This structure is used for protecting a gate of a field effect transistor (FET), and an example thereof is given in Patent Document 2. In the case of an FET, it is possible to form a diode array by forming a plurality of diodes on the same surface of a semiconductor layer stacked on a substrate and connecting them in series with wiring.
JP 2005-353647 A JP 2001-332567 A

  However, in the method of Patent Document 1, since the Zener diode generally has a large capacity, the operating speed of the LD is reduced. Therefore, this structure cannot be applied to the high-speed modulation LD.

  On the other hand, in the method of Patent Document 2, since a plurality of diodes are formed in the plane, the area occupied by the entire device increases. Moreover, in order to connect each diode in series, it is necessary to isolate | separate p side and n side. Therefore, it is necessary to form it on a semi-insulating substrate or an undoped layer. In this case, since it becomes impossible to flow an electric current by providing an electrode on the substrate side, both electrodes can be drawn from the surface side. Necessary. Therefore, pads for both electrodes are required, and this area is also required.

  If a plurality of diodes are formed not in the same plane but in a direction perpendicular to the substrate and connected in series, the area can be kept small. In this case, however, a plurality of steps are required to form electrodes on each diode. This causes a decrease in yield and an increase in cost.

  The present invention has been made under such a background, and an object of the present invention is to provide an optical semiconductor device having an electrostatic breakdown preventing means that has a small occupation area and is easy to manufacture. .

The optical semiconductor element according to the present invention is
An electrostatic breakdown preventing element formed on a semiconductor substrate and electrically connected in parallel with a light emitting unit including an active layer,
The electrostatic breakdown preventing element includes a plurality of pin-type diodes stacked in a direction perpendicular to the semiconductor substrate and electrically connected in the same direction,
A tunnel junction is formed at the interface between adjacent pin-type diodes.

In addition, another optical semiconductor element according to the present invention is
An electrostatic breakdown preventing element formed on a semiconductor substrate and electrically connected in parallel with a light receiving portion including an absorption layer,
The electrostatic breakdown preventing element includes a plurality of pin-type diodes stacked in a direction perpendicular to the semiconductor substrate and electrically connected in the same direction,
A tunnel junction is formed at the interface between adjacent pin-type diodes.

  ADVANTAGE OF THE INVENTION According to this invention, the optical semiconductor element provided with the electrostatic breakdown prevention means with a small occupation area and easy manufacture can be provided.

[First Embodiment]
Next, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a cross-sectional view of an optical semiconductor device according to the first embodiment of the present invention. Mesa 112 and 114 are formed on both sides of the mesa 113 on which the surface emitting laser is formed. In the mesas 112 and 114, diode rows 111a and 111b for preventing electrostatic breakdown composed of three pin type diodes are respectively formed. A tunnel junction is formed at the junction interface between the pin-type diodes in the diode array, so that they are electrically connected in series. Each of the two diode arrays is connected in parallel with the surface emitting laser. Here, the diode array of the mesa 114 is electrically connected to the surface emitting laser in the forward direction, and the diode array of the mesa 112 is connected in the reverse direction. An equivalent circuit of this structure is shown in FIG.

In the optical semiconductor device according to the first embodiment, as shown in FIG. 1, an n-type DBR layer 102, an n-type cladding layer 103, an active layer 104, a p-type cladding layer 105, A current confinement oxide layer 106, a p-type semiconductor layer 107, a p-type DBR layer 108, and a p ⁺ -type contact layer 109 are stacked.

Further, an etch stop layer 110 is formed on the left and right mesas 112 and 114. The etch stop layer 110 is not an essential component for operation, but this facilitates manufacture. On this etch stop layer 110, diode row layers 111 a and 111 b are formed by stacking a plurality of n ⁺ type semiconductor layers, undoped (i-type) semiconductor layers, and p ⁺ type semiconductor layers as a set. Yes. Here, the n-type semiconductor layer between the n ⁺ -type semiconductor layer and the undoped semiconductor layer, insert a p-type semiconductor layer between the p ⁺ -type semiconductor layer and the undoped semiconductor layer, 4-layer pair or 5 layers One set may be used. Each mesa reaches from the surface to the surface of the n-type DBR 102. In the diode array layers 111a and 111b, the interface between adjacent pin diodes, that is, the interface between the p ⁺ type semiconductor layer and the n ⁺ type semiconductor layer forms a tunnel junction.

Further, the current-voltage characteristics of the surface emitting laser formed on the mesa 113, the diode array 111a, and the diode array formed on the mesa 114 are as shown in FIG. The rising voltage V 114 of the diode array (shown as 114 in FIG. 3) of the mesa ₁₁₄ is higher than the operating voltage V ₁₁₃ of the surface emitting laser (shown as 113 in FIG. 3) of the mesa 113. The series resistance of the diode array of the mesa 114 is lower than the series resistance of the surface emitting laser of the mesa 113. Therefore, almost no current flows through the diode array of the mesa 114 during the operation of the normal surface emitting laser.

  In this case, since the diode array 111a is reverse-biased, almost no current flows here. When an excessive voltage is applied to the surface-emitting laser in the forward direction due to static electricity or the like and the rising voltage of the surface-emitting laser of the mesa 113 is sufficiently exceeded, a current flows through the diode of the mesa 114. However, since the series resistance of the diode array of the mesa 114 is smaller than the series resistance of the surface emitting laser, as shown in FIG. 3, when the voltage is high, the current flowing through the diode array of the mesa 114 is higher than that of the surface emitting laser. Will be more. Therefore, this structure can prevent an overcurrent from flowing in the surface emitting laser even when an excessive voltage is applied.

  In addition, when an excessive voltage is applied in the reverse direction, a current flows through the diode array 111a, so that a large reverse current can be prevented from flowing through the surface emitting laser. Those connected in the forward direction need to have a rising voltage higher than the operating voltage of the surface emitting laser. Therefore, it is necessary to be a diode array in which a plurality of diodes are connected in series. On the other hand, a single diode may be connected in the reverse direction, and it is not necessarily required to be a diode array. Here, an example in which a diode array is used in the reverse direction is shown, but this structure has the following advantages.

  In general, as one of the quality selection items of a laser diode, there is current measurement when a reverse voltage is applied. In principle, if the diode is below the breakdown voltage, almost no current flows when voltage is applied in the reverse direction. However, this reverse current increases when there is a defect such as a crystal defect. Therefore, it is often a good condition that the magnitude of the current flowing when a certain amount of reverse voltage is applied is below a certain level.

  However, when a diode is connected in parallel to the laser diode in the reverse direction for countermeasures against reverse electrostatic breakdown, when a voltage is applied to the laser diode in the reverse direction, a current flows through the diode for electrostatic breakdown countermeasures. Therefore, the above discrimination method cannot be used. Here, if the applied voltage is lowered to be equal to or lower than the rising voltage of the diode, a certain degree of discrimination can be made, but the judgment accuracy of selection is lowered. On the other hand, when a diode string in which diodes are connected in series is used as a countermeasure against reverse electrostatic breakdown, the rising voltage becomes high, so that a current flowing through the diode string is small even when a relatively high voltage is applied. For this reason, it becomes possible to suppress the fall of the determination precision of the above sorting methods small.

Next, the manufacturing method of the first embodiment will be described with reference to FIG.
First, on the n-type semiconductor substrate 101, an n-type DBR layer 102, an n-type cladding layer 103, an active layer 104, a p-type cladding layer 105, and a high Al content layer 106a, p for forming an oxide layer for current confinement. The semiconductor layer 107, the p-type DBR layer 108, the p ⁺ -type contact layer 109, the etch stop layer 110, and the n ⁺ -type semiconductor layer, the undoped semiconductor layer, and the p ⁺ -type semiconductor layer are set as one set, and three sets are stacked. The diode array layer 111 is sequentially stacked by metal organic chemical vapor deposition (MOCVD) method (FIG. 4A).

  Next, the diode array layer 111 in a region other than the diode array formation region on the wafer is removed by photolithography and etching (FIG. 4B).

  Next, a mask is formed by a photolithography technique, and portions other than the mask are removed to the surface of the n-type DBR layer 102 by etching, thereby preventing surface breakdown laser mesa 113 and electrostatic breakdown located on both sides thereof. The diode array mesas 112 and 114 are formed (FIG. 4C). At this time, one diode row mesa 114 has a larger area than the laser mesa 113, and the other diode row mesa 112 has a smaller area than the laser mesa 113. The diode array mesa 114 having a large area serves to prevent forward electrostatic breakdown, and the diode array mesa 112 having a small area serves to prevent reverse electrostatic breakdown. Further, the surface emitting laser mesa 113 is formed at a place where the diode array layer 111 is removed first.

  Next, the n-side electrode 115 is formed on the n-type DBR layer 102 exposed by the mesa etching. Subsequently, the high Al content layer 106a is oxidized using water vapor or the like (FIG. 4D). As a result, the high Al content layer 106a in the mesa including the active layer 104 is oxidized except for a part, and the oxide layer 106 for current confinement is formed. Here, the high Al content layer 106a in the three mesas 112 to 114 is also oxidized simultaneously, but the area of the non-oxidized region of the diode array mesa 114 having a large area is equal to that of the non-oxidized region of the surface emitting laser mesa 113. It becomes larger than the area. On the other hand, the area of the diode array mesa 112 having a small area is designed such that the entire surface is oxidized. As a result, the upper side of the diode array mesa 112 having a smaller area than the oxide layer 106 is electrically insulated from the substrate side.

  Subsequently, p-side electrodes 116 to 119 are formed. Here, a circular p-side electrode 116 and a ring-shaped p-side electrode 117 are formed on the mesa 112, a p-side electrode 118 having a shape is formed on the mesa 113, and a circular p-side electrode 119 is formed on the mesa 114 (FIG. 4E). ).

  Subsequently, a polyimide layer 120 is formed on the wafer, and the polyimide on the n-side electrode 115 and the mesas 112 to 114 formed in the previous step is removed by photolithography. Furthermore, metal wirings connecting the electrodes of the diode array for preventing electrostatic breakdown and the diode array for preventing reverse electrostatic breakdown of the surface emitting laser are also formed simultaneously (FIG. 4F). Thereby, the structure shown in FIG. 1 is completed.

  In the present embodiment, adjacent pin-type diodes are electrically connected by tunnel junctions, so that a step of forming an electrode on each pin-type diode is not necessary. Therefore, there are obtained advantages that the yield is high and the cost can be reduced.

  In this embodiment, the diode array for preventing electrostatic breakdown is formed on the same layer structure as that of the surface emitting laser. For this reason, it is only necessary to perform the growth once, and after forming the mesa for the surface emitting laser, it is not necessary to lay a layer necessary for the diode array for preventing electrostatic breakdown on the substrate by regrowth. For this reason, it is advantageous in terms of cost. Further, a pin type diode having the same layer structure as that of the underlying surface emitting laser is also connected to the forward diode array. As a result, the number of forward diode arrays is increased to four, and the difference between the rising voltage of the diode array and the operating voltage of the laser diode, that is, the margin is increased.

  In the first embodiment, the diode array 111b for preventing forward electrostatic breakdown and the diode array 111a for preventing reverse electrostatic breakdown are formed, but even if only one of the diode arrays is formed, good.

  In the first embodiment, the diode array layer 111 above the surface emitting laser mesa 113 is removed. However, as shown in FIG. 5, it may be left as it is without being removed. However, in this case, it is necessary to appropriately adjust the refractive index and the layer thickness of each layer in the diode array so that the reflection in the diode array above the surface emitting laser and its uppermost surface does not adversely affect the laser characteristics.

[Second Embodiment]
When only the diode array for preventing reverse electrostatic breakdown is formed, the layer structure can be changed from that of the above embodiment. That is, as shown in FIG. 6 as the second embodiment, the diode array layer 211 in the mesa 212 is an n ⁺ type layer, and this is connected to the p ⁺ type contact layer 209 above the surface emitting laser mesa 213. ing. Further, the p ⁺ -type contact layer 209 and the n-type DBR layer 202 may be short-circuited in the mesa 212 including the reverse electrostatic breakdown preventing diode array 211. In the first embodiment, the reverse breakdown preventing diode row 111 a is insulated by the oxide layer 106. On the other hand, in the second embodiment, the insulating layer 206 is not necessarily insulated. Details of the configuration and manufacturing method of the optical semiconductor device according to the second embodiment will be described in Example 2.

[Third Embodiment]
Furthermore, as shown in FIG. 9, the present invention may be used not only for a surface emitting laser but also for an edge emitter type. Details of the configuration and the manufacturing method of the optical semiconductor device according to the third embodiment will be described in Example 3.

[Fourth Embodiment]
Further, the present invention may be applied to a light receiving element as shown in FIG. As shown in FIG. 11, two columnar mesas 412 and 413 are provided. The right mesa 413 functions as a light receiving element, and the left mesa 412 has an electrostatic breakdown preventing function.

Specifically, as shown in FIG. 11, a light receiving element including an n-type semiconductor layer 403, an undoped semiconductor layer 404, and a p-type semiconductor layer 405 is formed on an n-type semiconductor substrate 401. A p ⁺ type contact layer 409 is stacked thereon.

Further, on the left mesa 412, a diode row 411 is formed by stacking three sets of a p ⁺ type semiconductor layer, an undoped (i type) semiconductor layer, and an n ⁺ type semiconductor layer. Each mesa reaches from the surface to the surface of the n-type semiconductor substrate 401. In the diode column layer 411, adjacent p ⁺ type semiconductor layers and n ⁺ type semiconductor layers form a tunnel junction.

  In the fourth embodiment, a diode array is formed in the direction opposite to the light receiving element. Since the light receiving element is normally used with a reverse bias applied, a forward bias is applied to the diode array. However, since a plurality of diodes are connected in series, no current flows under normal bias conditions. When an excessive reverse bias is applied to the light receiving element due to static electricity, the diode array is turned on, and a current flows to protect the light receiving element from electrostatic breakdown.

  In the present invention, not only when formed on the same substrate, but also those formed on different substrates may be cut out and electrically connected by means such as wire bonding.

Next, the structure and manufacturing method of the first embodiment will be described using specific examples.
Here, an example in which the present invention is applied to an oxidized confined surface emitting laser having an oscillation wavelength of 1.3 μm formed on an n-type GaAs substrate will be described. The structure of the first embodiment has three columnar mesas 112 to 114 as shown in FIG. The radius of the left mesa 112 is the smallest, and the radius of the right mesa 114 is the largest. The central mesa 113 functions as a laser. These are formed on an n-type semiconductor substrate 101 made of GaAs.

On the n-type semiconductor substrate 101, an n-type DBR layer 102 in which a plurality of layers of an n-type GaAs layer and an n-type Al _0.9 Ga _0.1 As layer are stacked as a basic unit, Al _0.3 Ga _0. the n-type cladding layer 103 made of ₇ as, undoped GaInNAs active layer ₁₀₄ made of quantum wells and GaAs barrier _layer, Al 0.3 _{Ga 0.7} p-type cladding layer 105 made of as, oxide layer 106 for current confinement, Al _0.9 Ga0 _{. A} p-type semiconductor layer 107 made of ₁ As, a p-type DBR layer 108 in which a pair of a p-type GaAs layer and a p-type Al _0.9 Ga _0.1 As layer is used as a basic unit, and a p ^{+ made of} GaAs. A mold contact layer 109 is laminated.

Further, an etch stop layer 110 made of n ⁺ type InGaP is formed on the left and right mesas 112 and 114. On this etch stop layer 110, a diode array layer 111 is formed by stacking three pairs of an n ⁺ -type GaAs layer, an undoped GaAs (i-type GaAs) layer, and a p ⁺ -type GaAs layer. Yes. Each mesa reaches from the surface to the surface of the n-type DBR 102. In the diode array layer 111, adjacent p ⁺ -type GaAs layers and n ⁺ -type GaAs layers each form a tunnel junction.

Next, a method for manufacturing the above structure will be described with reference to FIG.
First, an n-type DBR layer 102, an n-type Al _0.3 Ga _0.7 As cladding layer 103, an active layer 104 composed of a non-doped GaInNAs quantum well and a GaAs barrier layer, p-type Al _0. A pair of ₃ Ga _0.7 As cladding layer 105, p-type AlAs layer 106a, p-type Al _0.9 Ga _0.1 As layer 107, p-type GaAs layer and p-type Al _0.9 Ga _0.1 As layer As a basic unit, a p-type DBR layer 108, a p ⁺ -type GaAs layer 109, an etch stop layer 110 made of n ⁺ -type InGaP, an n ⁺ -type GaAs layer, an undoped GaAs (i-type GaAs) layer, Three p ⁺ -type GaAs layers are formed as one set, and the diode array layer 111 formed by stacking the three sets is formed by metal organic chemical vapor deposition (MOCVD: Metal Organic Chemical Vapor Depositio). n) Sequentially stacked by the method (step 1, FIG. 4A).

  Next, the diode array layer 111 is removed from a part of the wafer by photolithography and etching (Step 2, FIG. 4B).

Next, a SiO ₂ film (not shown) is formed by thermal CVD, a circular resist pattern is formed thereon by photolithography, and then the SiO ₂ film is etched using this resist pattern as a mask ( Step 3). Thereby, a circular SiO ₂ film pattern is formed.

Next, etching is performed from the surface to the surface of the n-type DBR layer 102 using this SiO ₂ film pattern as a mask to form mesas 112 to 114 (step 4, FIG. 4C). At this time, the diameters of the mesas 112, 113, and 114 are 15 μm, 20 μm, and 25 μm, respectively. Further, the mesa 113 is formed at the place where the diode array layer 111 is removed in step 2. In the mesa 112, the diode array layer 111 is removed 3 μm from the end of the outer periphery in Step 2, and the diode array layer 111 remains in the center of the mesa 112 having a diameter of 9 μm. On the other hand, the diode row 111 remains on the entire mesa 114. However, actually, the diode array layer 111 at the outer peripheral portion can be removed by the displacement of the etching mask formed in the steps 2 and 4, but there is no particular problem. Thereafter, the SiO ₂ film is removed.

  Next, an electrode is formed on the exposed n-type DBR layer 102 around the mesa as follows. First, after applying a photoresist on the entire surface of the wafer, the photoresist is removed only at a portion where an electrode is to be formed by lithography. After depositing AuGe / AuNi / Ti / Pt / Au, the photoresist is removed and the metal on the photoresist is lifted off to form an electrode 115 on a part of the first DBR layer 102 (process) 5).

  Next, heating is performed at a temperature of about 400 ° C. for about 10 minutes in a furnace in a steam atmosphere. As a result, only the p-type AlAs layer 106a whose side surface is exposed in step 3 is selectively oxidized at the same time to form an oxide layer 106 (step 6, FIG. 4D).

  Subsequently, the p-side electrodes 116 to 119 are formed as follows. First, a photoresist is applied on the wafer, patterned by mask exposure, Ti / Pt / Au is deposited, the photoresist is removed, and Ti / Pt / Au on the photoresist is lifted off. As shown in FIG. 2, a p-side electrode is formed. Here, a circular p-side electrode 116 and a ring electrode 117 are formed on the mesa 112, a ring-shaped p-side electrode 118 is formed on the mesa 113, and a circular p-side electrode 119 is formed on the mesa 114 (step 7).

  Next, after filling the mesa with the polyimide layer 120, the polyimide layer 120 on the n-side electrode 115 formed in the mesa 112 to 114 and step 5 is removed by lithography (step 8).

  Next, pad electrodes 121 and 122 are formed on the polyimide layer 120 (step 9). At this time, the wiring connecting the pad electrode 121 and the n-side electrode 115 formed in Step 5 and the p-side electrode 116 formed in Step 7 and the wiring connecting the pad electrode 122 and the electrodes 117, 118 and 119 formed in Step 7 are simultaneously provided. It is formed.

  Finally, after the back side of the n-type GaAs substrate 101 is polished to a thickness of 150 μm, a back electrode 123 made of AuGe / AuNi / Ti / Au is formed by vapor deposition (step 10). This metal can be used to fuse the element to a heat sink or the like with solder. Thus, the device of FIG. 1 is completed (FIG. 4F).

  Next, the structure and manufacturing method of the second embodiment will be described. Here, as in the first embodiment, an example in which the present invention is applied to an oxidized confined surface emitting laser having an oscillation wavelength of 1.3 μm formed on an n-type GaAs substrate will be described. The structure of the second embodiment has two columnar mesas 212 and 213 as shown in FIG. The right mesa 213 functions as a laser, and the left mesa 212 has an electrostatic breakdown preventing function. These are formed on an n-type semiconductor substrate 101 made of GaAs.

On an n-type semiconductor substrate 201, a pair of an n-type GaAs layer and an n-type Al _0.9 Ga _0.1 As layer is used as a basic unit, and a plurality of these n-type DBR layers 202, Al _0.3 Ga _{0. 7} n-type cladding layer 203 made of As, active layer 204 made of non-doped GaInNAs quantum well and GaAs barrier layer, p-type cladding layer 205 made of Al _0.3 Ga _0.7 As, oxide layer 206 for current confinement, Al _0.9 Ga0 _{. A} p-type semiconductor layer 207 made of ₁ As, a p-type GaAs layer and a p-type Al _0.9 Ga _0.1 As layer as a basic unit, a p-type DBR layer 208 in which a plurality of layers are stacked, and p ^{+ made of} GaAs A mold contact layer 209 is laminated.

Furthermore, an etch stop layer 210 made of n ⁺ -type InGaP is formed on the left mesa 212. On top of this, a p ⁺ type GaAs layer, an undoped GaAs (i type GaAs) layer, and an n ⁺ type GaAs layer are formed as one set, and a diode array 211 is formed by stacking three sets of these. Each mesa reaches from the surface to the surface of the n-type DBR 202. In the diode array layer 211, the adjacent p ⁺ type GaAs layer and n ⁺ type GaAs layer form a tunnel junction.

Next, a method for manufacturing the above structure will be described with reference to FIG. First, an n-type DBR layer 202, an n-type Al _0.3 Ga _0.7 As clad layer 203, an active layer 204 comprising a non-doped GaInNAs quantum well and a GaAs barrier layer on a n-type GaAs substrate 201, a p-type Al _0.3 Ga _0.7 As cladding layer 205, p-type AlAs layer 206a, p-type Al _0.9 Ga0 _{. 1} As layer 207, p-type GaAs layer and p-type Al _0.9 Ga _0.1 As layer as a basic unit, a plurality of p-type DBR layer 208, p ⁺ -type GaAs layer 209, and n ⁺ -type stacked. InGaP layer 210, further, ^{p +} -type GaAs layer, an undoped GaAs (i-type GaAs) layer, ^{n +} -type GaAs layer 3 layer as a pair, a metal organic chemical vapor deposition a diode array layer 211 which has a laminate 3 groups The layers are sequentially stacked by the (MOCVD) method (Step 1. FIG. 7A).

  Next, the diode array layer 211 is removed from a part of the wafer by photolithography and etching (step 2. FIG. 7B).

Next, a SiO ₂ film (not shown) is formed by thermal CVD, a circular resist pattern is formed thereon by photolithography, and then the SiO ₂ film is etched using this resist pattern as a mask ( Step 3). Thereby, a circular SiO ₂ film pattern is formed.

Next, etching is performed from the surface to the surface of the n-type DBR layer 202 using this SiO ₂ film pattern as a mask to form mesas 212 and 213 (step 4, FIG. 7C). Here, the diameters of the mesas 212 and 213 are both 20 μm. In addition, the mesa 213 is formed at the place where the diode array layer 211 is removed in Step 2. On the other hand, the diode array layer 211 is removed from the outer peripheral portion 5 μm of the mesa 212 in step 2, and the diode array 211 layer remains in the central diameter of 15 μm. Thereafter, the SiO2 film is removed.

  Next, an electrode is formed on the exposed n-type DBR layer 202 around the mesa as follows. First, a photoresist is applied to the entire surface of the wafer, and then the photoresist is removed only at a portion where an electrode is to be formed by lithography. After depositing AuGe / AuNi / Ti / Pt / Au, the photoresist is removed and the metal on the photoresist is lifted off to form an electrode 215 on part of the n-type DBR layer 202 (step 5). ).

  Next, heating is performed at a temperature of about 400 ° C. for about 10 minutes in a furnace in a steam atmosphere. As a result, only the p-type AlAs layer 206a whose side surface is exposed in step 3 is selectively oxidized at the same time to form an oxide layer 206 (step 6, FIG. 7D).

  Subsequently, the p-side electrode is formed as follows. First, after applying a photoresist on the wafer and patterning by mask exposure, Ti / Pt / Au is deposited, the photoresist is removed, and Ti / Pt / Au on the photoresist is lifted off to p side. An electrode is formed. Here, a circular p-side electrode 216 and a ring electrode 217 are formed on the mesa 212, and a ring-shaped p-side electrode 218 is formed on the mesa 213 (step 7, FIG. 7E).

Next, after forming the SiO ₂ film 224, the mesa is filled with the polyimide layer 220, and the SiO ₂ film 224 and the polyimide layer 220 on the electrode 215 formed in the step 5 are removed by lithography (step 8). .

  Next, pad electrodes 221 and 222 are formed on the polyimide layer 220 (step 9). At this time, a wiring connecting the pad electrode 221 and the electrode 215 formed in the step 5 and the ring electrode 217 formed in the step 7, and a wiring connecting the pad electrode 222 and the p-side electrode 218 and the p-side electrode 216 formed in the step 7. Are formed simultaneously.

  Finally, after polishing the back side of the n-type GaAs substrate 201 to a thickness of 150 μm, a back electrode 223 made of AuGe / AuNi / Ti / Au is formed by vapor deposition (step 10). This metal can be used to fuse the element to a heat sink or the like with solder. Thus, the element of FIG. 6 is completed (FIG. 7F).

  The diode array layer 211 of Example 2 has a function of preventing reverse electrostatic breakdown. In Example 1, the entire surface of the oxide layer 106 was oxidized in the mesa 112 for preventing reverse electrostatic breakdown, and the upper and lower sides were electrically insulated. This is to prevent current from flowing from the electrode 117 to the electrode 115 in the mesa 112 during the operation of the laser. On the other hand, in the second embodiment, the mesas 212 and 213 have the same diameter. For this reason, the oxidized layer 206 in the mesa 212 also has an unoxidized portion having the same diameter as that of the laser mesa 213, and the upper and lower portions thereof are not electrically insulated. However, in the second embodiment, the electrical connection between the diode array constituted by the diode array layer 211 and the laser is in the opposite direction to that of the first embodiment, and the equivalent circuit is as shown in FIG. That is, since the electrode 215 and the ring electrode 217 are short-circuited, it is not necessary to be insulated by the oxide layer 206.

  Next, the structure and manufacturing method of the third embodiment will be described. Here, an example in which the present invention is applied to an edge-emitting laser having an oscillation wavelength of 1.3 μm formed on an n-type InP substrate will be described. The structure of the third embodiment has three stripe structures as shown in FIG.

The left stripe 312 is formed in the reverse direction and the right mesa 314 is formed to prevent electrostatic breakdown in the forward direction, and the central mesa 313 functions as a laser. These are formed on an n-type semiconductor substrate 301 made of InP, an n-type semiconductor layer 302 made of InP, an n-type clad layer 303 made of InGaAsP, an active layer 304 made of a non-doped InGaAsP quantum well and an InGaAsP barrier layer, p Type InGaAsP cladding layer 305, p-type semiconductor layer 306 made of InP, p ⁺ type contact layer 309 made of InGaAs, a current block made up of a Fe-doped semi-insulating InP layer 307 and an n-type InP layer 308 It has a structure.

Furthermore, the left and right mesas are formed as a set of three layers, an etch stop layer 310 made of p ⁺ type InGaAs, an n ⁺ type InP layer, an undoped InP (i type InP) layer, and a p ⁺ type InP layer. Three sets of diode array layers 311 are stacked. The grooves separating the stripes reach from the surface to the surface of the n-type semiconductor substrate 301, respectively. In the diode column layer 311, adjacent p ⁺ type InP layers and n ⁺ type InP layers form tunnel junctions. Further, the n ⁺ -type InP layers at the lowermost layers of the etch stop layer 310 and the diode array layer 311 each form a tunnel junction.

Next, a method for manufacturing the above structure will be described with reference to FIG. First, an n-type InP layer 302 on the n-type InP substrate 301, n-type _In 0.83 _Ga 0.27 _{As 0.36} P _0.64 cladding layer 303, an undoped _In 0.8 _Ga 0.2 _{As 0.} Active layer 304 composed of ₆₄ P _0.36 quantum well and In _0.83 Ga _0.27 As _0.36 P _0.64 barrier layer, p-type In _0.83 Ga _0.27 As _0.36 P _0.64 The cladding layer 305 and the p-type InP layer 306a are sequentially stacked by metal organic chemical vapor deposition (MOCVD) (step 1).

Then, SiO ₂ is deposited film on the wafer, to form the SiO ₂ stripe mask (not shown) by photolithography and etching (step 2).

  Next, the portion not masked by wet etching is etched down to the n-type InP substrate 301 (step 3, FIG. 10A).

Subsequently, an Fe-doped InP layer 307 and an n-type InP layer 308 are stacked again by MOCVD (step 4, FIG. 10B). These layers are selectively stacked on the portion without the SiO ₂ mask.

Next, the SiO ₂ mask is removed, and a p-type InP layer 306b, a p ⁺ -type InGaAs contact layer 309, an etch stop layer 310 made of p ⁺ -type InGaAs, an n ⁺ -type InP layer, an undoped InP (i-type InP) A diode array layer 311 in which three layers, i.e., three layers of p ⁺ type InP layers, are stacked is stacked by MOCVD (step 5, FIG. 10C). An integrated p-type InP layer 306 is formed from the p-type InP layer 306a formed in step 1 and the p-type InP layer 306b formed in step 5.

  Next, a part of the diode row layer 311 is removed by photolithography and etching (step 6, FIG. 10D).

  Subsequently, a groove reaching the n-type InP substrate 301 is formed again by photolithography and mesa etching, thereby forming three stripes 312, 313, and 314 (step 7, FIG. 10E). The stripe 312 has a diode row 311 a, and below that is a current blocking layer composed of an Fe-doped InP layer 307 and an n-type InP layer 308. The stripe 312 is used for preventing reverse electrostatic breakdown. The stripe 313 includes an active layer 304 and a current blocking layer including an Fe-doped InP layer 307 and an n-type InP layer 308, and functions as a laser. The stripe 314 has a diode array 311b, and has a diode structure including an active layer 304 thereunder. The stripe 314 is used for preventing forward electrostatic breakdown.

Next, after forming the SiO ₂ film 324 on the wafer, a part of the SiO ₂ film 324 on each stripe and on the n-type InP substrate 301 is removed by photolithography and etching (step 8).

Next, an electrode is formed in the portion where the SiO ₂ film 324 is removed. First, after applying a resist, the resist on the portion where the SiO ₂ film on the n-type InP substrate 301 is removed is removed by photolithography. Next, after depositing AuGe / AuNi / Ti / Pt / Au, the metal on the resist is removed by lift-off (step 9). Thereby, an electrode 315 is formed on the n-type InP substrate 301. After applying the resist again, the resist on the portion where the SiO ₂ film on the mesa is removed is removed by photolithography.

Next, after depositing Cr / Au, the metal on the resist is removed by lift-off (step 10). Thus, the electrode 316 on the diode row 311a stripes 312, the electrode 317 is formed on the ^{p +} -type InGaAs contact layer 309 of the stripe 312. An electrode 318 is formed on the p ⁺ type InGaAs contact layer 309 of the stripe 313. Further, an electrode 319 is formed on the diode row 311 b of the stripe 314. At the same time, a wiring connecting the pad electrode 322 and the electrodes 319, 318, and 317 and a wiring connecting the electrodes 315 and 316 are formed.

  Finally, after polishing the back surface side of the n-type InP substrate 301 to a thickness of 150 μm, AuGe / AuNi / Ti / Au is evaporated to form the back electrode 323 (step 11, FIG. 10F).

  As mentioned above, although the Example of this invention was described, the implementation method of this invention is not limited to above-mentioned various forms, A various deformation | transformation is possible in the range which does not deviate from the summary. Regarding the wavelength and material of the semiconductor light emitting device, those other than those listed in the examples can be selected.

Sectional drawing which shows the structure of the optical semiconductor element which concerns on 1st Embodiment. The equivalent circuit of the optical semiconductor element of FIG. The graph which shows the current-voltage characteristic of each part of the optical semiconductor element which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 1st Embodiment. Sectional drawing which shows the structure of the other optical semiconductor element which concerns on 1st Embodiment. Sectional drawing which shows the structure of the optical semiconductor element which concerns on 2nd Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 2nd Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 2nd Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 2nd Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 2nd Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 2nd Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 2nd Embodiment. The equivalent circuit of the optical semiconductor element of FIG. Sectional drawing which shows the structure of the optical semiconductor element which concerns on 3rd Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 3rd Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 3rd Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 3rd Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 3rd Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 3rd Embodiment. Sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 3rd Embodiment. Sectional drawing which shows the structure of the optical semiconductor element which concerns on 4th Embodiment.

Explanation of symbols

101, 201, 301, 401 n-type semiconductor substrate 102, 202 n-type DBR layer 302 n-type semiconductor layer 103, 203, 303 n-type cladding layer 104, 204, 304 active layer 105, 205, 305 p-type cladding layer 106, 206 oxide layer 106a, 206a high Al-containing layer 107 and 207 p-type semiconductor layer 108, 208 p-type DBR layer 109,209,309,409 p ⁺ -type contact layer 110, 210, 310 etch stop layer 111, 211, 311, 411 Diode array layer 112, 113, 114 Mesa 115, 116, 117, 118, 119 Electrode 120, 220, 420 Polyimide layer 121, 122, 221, 222, 322 Pad electrode 123, 223, 323 Back electrode 212, 213 Mesa 215 216, 217, 218 electrodes 24,324 SiO ₂ film 306 p-type semiconductor layer 307 Fe-doped semi-insulating InP layer 308 n-type InP layer 312, 313, 314 mesa 315,316,317,318,319 electrode 403 n-type semiconductor layer 404 an undoped semiconductor layer 405 p-type semiconductor layers 412, 413 mesas 415, 416, 417, 418 electrodes

Claims (8)

An electrostatic breakdown preventing element formed on a semiconductor substrate and electrically connected in parallel with a light emitting unit including an active layer,
The electrostatic breakdown preventing element includes a plurality of pin-type diodes stacked in a direction perpendicular to the semiconductor substrate and electrically connected in the same direction,
An optical semiconductor element, wherein a tunnel junction is formed at an interface between adjacent pin-type diodes.   2. The optical semiconductor element according to claim 1, wherein the active layer and the antistatic element are formed on the same semiconductor substrate.   The optical semiconductor element according to claim 1, wherein a series resistance of the electrostatic breakdown preventing element is lower than a series resistance of the active layer.   The optical semiconductor element according to claim 1, wherein the electrostatic breakdown preventing element is formed in an upper layer than a semiconductor layer constituting the active layer. An electrostatic breakdown preventing element formed on a semiconductor substrate and electrically connected in parallel with a light receiving portion including an absorption layer,
The electrostatic breakdown preventing element includes a plurality of pin-type diodes stacked in a direction perpendicular to the semiconductor substrate and electrically connected in the same direction,
An optical semiconductor element, wherein a tunnel junction is formed at an interface between adjacent pin-type diodes.   6. The optical semiconductor element according to claim 5, wherein the absorption layer and the antistatic element are formed on the same semiconductor substrate.   The optical semiconductor element according to claim 5, wherein a series resistance of the electrostatic breakdown preventing element is lower than a series resistance of the absorption layer.   The optical semiconductor element according to claim 5, wherein the electrostatic breakdown preventing element is formed in an upper layer than a semiconductor layer constituting the absorbing layer.

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