JP2009163874A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which breakdown strength of transistors is excellent. <P>SOLUTION: In a semiconductor integrated circuit device, a selecting circuit 371 selects a potential VPP from a pump circuit 11 for normal operation when a selecting signal SELP is an "H" level, the circuit selects an external potential VEX when the selecting signal SELP is an "L" level, and outputs the selected potential as VP. An inverter 372 reverses a logic level of the selecting signal SELP, also converts a voltage level from a level of an external power source potential EXVDD to a level of a potential VPP, and outputs it. A level converting circuit includes P channel MOS transistors 382, 384 of which both the gate electrodes receive an output potential of the inverter 372, and of which the sources are connected respectively to output nodes N131, N132. Therefore, the breakdown strength of the P channel MOS transistors 381, 383 is improved. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a charge pump circuit, a clock driver, and a level conversion circuit.

  In a flash memory that is a non-volatile memory that can be electrically erased and rewritten, a word line and a bit line are set to different potentials depending on each operation mode. For example, the word line is set to 5.5V at the time of reading, 9.7V at the time of program operation, and -9.2V at the time of data erasing. The bit line is set to 0.7V at the time of reading and to 5.1V at the time of program operation. The well potential is set to 0V at the time of reading and -0.9V at the time of program operation. Therefore, various pump circuits are provided in order to generate a necessary voltage in each operation mode from a single external power supply voltage (for example, 1.8 V).

  A conventional pump circuit that generates a negative voltage has been proposed that resets the potential of the gate electrode of a P-channel MOS transistor constituting the pump circuit when the pump circuit is inactivated. In this case, the negative voltage generation speed does not decrease even in the second and subsequent pump operations (see, for example, Patent Document 1).

  A conventional pump circuit that shares a pump module that operates during a standby cycle and an active cycle has also been proposed. In this case, it is not necessary to separately provide a circuit for a standby cycle and a circuit for an active cycle, so that the area occupied by the circuit is reduced (see, for example, Patent Document 2).

JP 2002-32987 A JP 7-1111093 A

  In recent years, further reduction in area of semiconductor devices has been demanded. However, in the conventional semiconductor device, the reduction of the area occupied by the pump circuit is not sufficiently achieved. There is also a problem in the operating characteristics of the pump circuit and the breakdown voltage characteristics of the transistors.

  Therefore, a main object of the present invention is to provide a semiconductor device with good breakdown voltage characteristics of a transistor.

  Another object of the present invention is to provide a semiconductor device having good operating characteristics.

  The semiconductor device according to the present invention is a semiconductor device including a level conversion circuit, and when the first switching signal is at the first level, the first potential is applied to the power supply node, and the first switching signal is the first switching signal. A selection circuit that applies a second potential lower than the first potential to the power supply node when the level is 2, and a second potential that is applied to the predetermined node when the first switching signal is the first level; And a switching circuit for applying a third potential lower than the second potential to a predetermined node when the first switching signal is at the second level. Here, in the level conversion circuit, the first and second conductivity types in which the gate electrodes are both connected to a predetermined node, and the first electrodes are connected to the first and second output nodes, respectively. The second transistors and their first electrodes are both connected to the power supply node, their second electrodes are respectively connected to the second electrodes of the first and second transistors, and their gate electrodes are respectively The third and fourth transistors of the first conductivity type connected to the second and first output nodes, and their first electrodes are both connected to the reference potential line, and the second electrodes are A second conductive type connected to the first and second output nodes, respectively, each of which has a gate electrode receiving a second switching signal having a first or second level and an inverted signal thereof; 5 and a sixth transistor.

  Another semiconductor device according to the present invention is a semiconductor device including a level conversion circuit, and when the first switching signal is at the first level, the first potential is applied to the power supply node, When the switching signal is at the second level, a selection circuit that applies a second potential lower than the first potential to the power supply node; and when the switching signal is at the first level, the second potential is set to a predetermined level. And a switching circuit that applies a third potential lower than the second potential to the predetermined node when the first switching signal is at the second level. Here, in the level conversion circuit, the first and second conductivity types in which the gate electrodes are both connected to a predetermined node, and the first electrodes are connected to the first and second output nodes, respectively. The second transistors and their first electrodes are both connected to the reference potential line, their second electrodes are connected to the second electrodes of the first and second transistors, respectively, and their gate electrodes Are connected to the power supply node together with the third and fourth transistors of the first conductivity type that receive the second switching signal having the first or second level and the inverted signal thereof, respectively. The second conductivity type of which the second electrodes are connected to the first and second output nodes, respectively, and the gate electrodes are connected to the second and first output nodes, respectively. 5 and a sixth transistor.

  Still another semiconductor device according to the present invention is a semiconductor device including a level conversion circuit, and when the first switching signal is at the first level, the first potential is applied to the power supply node. When the first switching signal is at the second level, a selection circuit that applies a second potential lower than the first potential to the power supply node, and when the first switching signal is at the first level, the second potential is set to a predetermined level. And a switching circuit that applies a third potential lower than the second potential to the predetermined node when the first switching signal is at the second level. Here, in the level conversion circuit, the first and second conductivity types in which the gate electrodes are both connected to a predetermined node, and the first electrodes are connected to the first and second output nodes, respectively. The second transistors and their first electrodes are both connected to the power supply node, their second electrodes are respectively connected to the second electrodes of the first and second transistors, and their gate electrodes are respectively The third and fourth transistors of the first conductivity type connected to the second and first output nodes and their gate electrodes are both connected to a predetermined node, and each of the first electrodes is connected to the first node. The fifth and sixth transistors of the second conductivity type connected to the second output node and their first electrodes are both connected to the reference potential line, and their second current Are connected to the second electrodes of the fifth and sixth transistors, respectively, and the gate electrodes of the second conductive type receive the second switching signal having the first or second level and the inverted signal thereof, respectively. And seventh and eighth transistors.

  Still another semiconductor device according to the present invention is a semiconductor device that includes a clock driver that transmits a clock signal and that corresponds to different power supply potential specifications, and the clock driver has a power supply potential at a first level. A clock signal is transmitted in the case of specification, and includes a first transistor of a first conductivity type and a second transistor of a second conductivity type connected in series between a power supply potential node and a reference potential node A clock signal is transmitted when the power supply potential is a second level specification lower than the first level and the first clock driver circuit having the first inverter, and between the power supply potential node and the reference potential node A third transistor of the first conductivity type connected in series and having a gate insulating film thinner than the gate insulating films of the first and second transistors, respectively. And a second clock driver circuit having a second inverter including a fourth transistor of the second conductivity type. Here, when the power supply potential is at the first level, the gate electrode and the drain electrode of each of the third and fourth transistors are connected to the source electrode, and when the power supply potential is at the second level, the third and fourth transistors are connected. The gate electrode of the fourth transistor is commonly connected to the input node of the second inverter, and the drain electrodes of the third and fourth transistors are commonly connected to the output node of the second inverter.

  Preferably, both the first and third transistors are formed in a common first well region of the second conductivity type, and both the second and fourth transistors are common second of the first conductivity type. Formed in the well region.

  The semiconductor device according to the present invention is a semiconductor device including a level conversion circuit, and when the first switching signal is at the first level, the first potential is applied to the power supply node, and the first switching signal is the first switching signal. A selection circuit that applies a second potential lower than the first potential to the power supply node when the level is 2, and a second potential that is applied to the predetermined node when the first switching signal is the first level; When the first switching signal is at the second level, a switching circuit is provided for applying a third potential lower than the second potential to a predetermined node. Here, in the level conversion circuit, the first and second conductivity types in which the gate electrodes are both connected to a predetermined node, and the first electrodes are connected to the first and second output nodes, respectively. The second transistors and their first electrodes are both connected to the power supply node, their second electrodes are respectively connected to the second electrodes of the first and second transistors, and their gate electrodes are respectively The third and fourth transistors of the first conductivity type connected to the second and first output nodes, and their first electrodes are both connected to the reference potential line, and the second electrodes are A second conductive type connected to the first and second output nodes, respectively, each of which has a gate electrode receiving a second switching signal having a first or second level and an inverted signal thereof; And fifth and sixth transistors are provided. Therefore, with the configuration in which the gate electrodes of the first and second transistors receive the output potential of the switching circuit, the breakdown voltage characteristics of the third and fourth transistors are improved.

  Another semiconductor device according to the present invention is a semiconductor device including a level conversion circuit, and when the first switching signal is at the first level, the first potential is applied to the power supply node, When the switching signal is at the second level, a selection circuit that applies a second potential lower than the first potential to the power supply node; and when the switching signal is at the first level, the second potential is set to a predetermined level. There is provided a switching circuit that applies to the node and applies a third potential lower than the second potential to the predetermined node when the first switching signal is at the second level. Here, in the level conversion circuit, the first and second conductivity types in which the gate electrodes are both connected to a predetermined node, and the first electrodes are connected to the first and second output nodes, respectively. The second transistors and their first electrodes are both connected to the reference potential line, their second electrodes are connected to the second electrodes of the first and second transistors, respectively, and their gate electrodes Are connected to the power supply node together with the third and fourth transistors of the first conductivity type that receive the second switching signal having the first or second level and the inverted signal thereof, respectively. The second conductivity type of which the second electrodes are connected to the first and second output nodes, respectively, and the gate electrodes are connected to the second and first output nodes, respectively. 5 and a sixth transistor. Therefore, by setting the gate electrodes of the first and second transistors to receive the output potential of the switching circuit, the breakdown voltage characteristics of the fifth and sixth transistors are improved.

  Still another semiconductor device according to the present invention is a semiconductor device including a level conversion circuit, and when the first switching signal is at the first level, the first potential is applied to the power supply node. When the first switching signal is at the second level, a selection circuit that applies a second potential lower than the first potential to the power supply node, and when the first switching signal is at the first level, the second potential is set to a predetermined level. And a switching circuit that applies a third potential lower than the second potential to the predetermined node when the first switching signal is at the second level. Here, in the level conversion circuit, the first and second conductivity types in which the gate electrodes are both connected to a predetermined node, and the first electrodes are connected to the first and second output nodes, respectively. The second transistors and their first electrodes are both connected to the power supply node, their second electrodes are respectively connected to the second electrodes of the first and second transistors, and their gate electrodes are respectively The third and fourth transistors of the first conductivity type connected to the second and first output nodes and their gate electrodes are both connected to a predetermined node, and each of the first electrodes is connected to the first node. The fifth and sixth transistors of the second conductivity type connected to the second output node and their first electrodes are both connected to the reference potential line, and their second current Are connected to the second electrodes of the fifth and sixth transistors, respectively, and the gate electrodes of the second conductive type receive the second switching signal having the first or second level and the inverted signal thereof, respectively. Seventh and eighth transistors are provided. Therefore, the breakdown voltage characteristics of the third, fourth, seventh and eighth transistors are improved by adopting a configuration in which the gate electrodes of the first, second, fifth and sixth transistors receive the output potential of the switching circuit. To do.

Still another semiconductor device according to the present invention is a semiconductor device provided with a clock driver, which transmits a clock signal when the power supply potential is a first level specification, and includes a power supply potential node and a reference potential node. A first clock driver circuit having a first inverter including a first transistor of a first conductivity type and a second transistor of a second conductivity type connected in series with each other; The clock signal is transmitted in the case of the specification of the second level lower than the level of 1, and is connected in series between the power supply potential node and the reference potential node, and the gate insulating films thereof are the first and second levels, respectively. A second inverter having a second inverter including a third transistor of the first conductivity type and a fourth transistor of the second conductivity type which are thinner than the gate insulating film of the transistor; And lock the driver circuit is provided. Here, when the power supply potential is at the first level, the gate electrode and the drain electrode of each of the third and fourth transistors are connected to the source electrode, and when the power supply potential is at the second level, the third and fourth transistors are connected. The gate electrode of the fourth transistor is commonly connected to the input node of the second inverter, and the drain electrodes of the third and fourth transistors are commonly connected to the output node of the second inverter. Therefore, since the first and third transistors can be formed in the same well region, the area of the semiconductor device is reduced.

1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. It is a block diagram which shows the structure of the frequency divider shown in FIG. 1 and the positive pump circuits 12 and 13 for internal operation. FIG. 3 is a circuit diagram showing a configuration of a detection circuit 52 shown in FIG. 2. FIG. 3 is a circuit diagram showing in detail a configuration of a unit circuit of the clock driver 53 shown in FIG. 2. 5 is a circuit diagram showing in more detail the configuration of a P-channel MOS transistor group 87 and an N-channel MOS transistor group 88 shown in FIG. FIG. 9 is a layout diagram for explaining the arrangement of P channel MOS transistor groups 85 and 87 and N channel MOS transistor groups 86 and 88 shown in FIG. 4. FIG. 3 is a circuit diagram illustrating a configuration of a charge pump 65 illustrated in FIG. 2. FIG. 8 is a circuit diagram showing a configuration for resetting the potentials of nodes N31 to N40 of charge pump 65 shown in FIG. It is a time chart for demonstrating operation | movement of the charge pump 65 shown in FIG. 3 is a time chart showing potential changes of a bit line BL and a word line WL of the memory unit shown in FIG. FIG. 2 is a block diagram showing a configuration of a normal operation positive pump circuit shown in FIG. 1. It is a circuit diagram which shows the structure of the charge pump shown in FIG. 12 is a time chart for explaining the operation of the normal operation positive pump circuit shown in FIG. FIG. 13 is a schematic cross-sectional view illustrating a configuration of a capacitor 175 illustrated in FIG. 12. It is a schematic sectional drawing which shows the structure of the capacitor 211 shown in FIG. FIG. 2 is a circuit diagram showing a configuration of a charge pump of the internal operation negative pump circuit 15 shown in FIG. 1. FIG. 2 is a circuit diagram showing a configuration of a charge pump of the internal operation negative pump circuit 16 shown in FIG. 1. FIG. 2 is a circuit diagram showing a configuration of an external application selection circuit 25 shown in FIG. 1. FIG. 19 is a simplified circuit block diagram corresponding to the external application selection circuit shown in FIG. 18. 20 is a time chart for explaining the operation of the circuit shown in FIG. 19. It is a time chart for demonstrating operation | movement of the external application selection circuit shown in FIG. It is a figure which shows the example 1 of a change of embodiment of this invention. It is a figure which shows the example 2 of a change of embodiment of this invention. It is a figure which shows the example 3 of a change of embodiment of this invention. It is a figure which shows the example 4 of a change of embodiment of this invention.

  FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. 1, this semiconductor integrated circuit device includes a clock generation circuit 1, reference potential generation circuits 2 and 4, a frequency dividing circuit unit 3, a normal operation positive pump circuit 11, internal operation positive pump circuits 12 and 13, and a drive circuit. Positive pump circuit 14, negative pump circuits 15 to 17 for internal operation, input terminals 21 and 22, external application selection circuits 23 to 28, reset circuits 29 to 33, selection circuits 34 to 37, write circuit 38, word line driver 39 A well driver 40, a source driver 41, and a memory unit 42.

  The normal operation positive pump circuit 11, the internal operation positive pump circuits 12, 13, and the drive positive pump circuit 14 are driven by a single external power supply potential EXVDD (for example, 1.8 V). The internal operation negative pump circuits 15 to 17 are driven by the potential VPC (for example, 2.4 V) from the drive positive pump circuit 14.

  The clock generation circuit 1 generates a clock signal CLK necessary for each pump circuit. The reference potential generation circuit 2 generates a reference potential VREF necessary for each pump circuit. The frequency dividing circuit unit 3 divides the clock signal CLK from the clock generating circuit 1 and outputs the clock signal CLKD. The reference potential generation circuit 4 generates a reference potential VREFS necessary for the normal operation positive pump circuit 11.

  The normal operation positive pump circuit 11 receives the reference potential VREFS and generates a positive potential VPP (for example, 5.5 V) necessary for the word line during a normal operation such as a read operation. The internal operation positive pump circuit 12 receives the clock signal CLKD and the reference potential VREF, and generates a positive potential VPB (for example, 5.1 V) necessary for the bit line during an internal operation such as a program operation. The internal operation positive pump circuit 13 receives the clock signal CLK and the reference potential VREF, and generates a positive potential VPW (eg, 9.7 V) necessary for the word line during an internal operation such as a program operation.

The driving positive pump circuit 14 receives the clock signal CLK and the reference potential VREF, generates a positive potential VPD (for example, 2.4 V), and supplies it to the negative pump circuits 15 to 17 for internal operation. The internal operation negative pump circuit 15 receives the clock signal CLK and the reference potential VREF, and generates a negative potential VNA (for example, −9.2 V) necessary for the word line during an internal operation such as an erase operation. Internal operation negative pump circuit 16 receives clock signal CLK and reference potential VREF, and generates negative potential VNB (for example, −0.5 V) necessary for word line driver 39 during an internal operation such as a program operation. Internal operation negative pump circuit 17 receives clock signal CLK and reference potential VREF, and generates a negative potential VNC (for example, −0.9 V) necessary for a well during an internal operation such as a program operation.

  An external potential VEX is applied to the input terminals 21 and 22. The external application selection circuit 23 selects and outputs either the external potential VEX from the input terminal 21 or the potential VPP from the normal operation positive pump circuit 11. The external application selection circuit 24 selects and outputs either the external potential VEX from the input terminal 21 or the potential VPB from the internal operation positive pump circuit 12. The external application selection circuit 25 selects and outputs either the external potential VEX from the input terminal 21 or the potential VPW from the internal operation positive pump circuit 13. The external application selection circuit 26 selects and outputs either the external potential VEX from the input terminal 22 or the potential VNA from the internal operation negative pump circuit 15. The external application selection circuit 27 selects and outputs either the external potential VEX from the input terminal 22 or the potential VNB from the negative pump circuit 16 for internal operation. The external application selection circuit 28 selects and outputs either the external potential VEX from the input terminal 22 or the potential VNC from the internal operation negative pump circuit 17.

  The reset circuit 29 performs a reset operation for applying the output potential of the external application selection circuit 23 to the output node of the external application selection circuit 24 when the internal operation positive pump circuit 12 is inactive. The reset circuit 30 performs a reset operation for applying the output potential of the external application selection circuit 23 to the output node of the external application selection circuit 25 when the internal operation positive pump circuit 13 is inactive. The reset circuit 31 performs a reset operation for setting the output node of the external application selection circuit 26 to the ground potential (0 V) when the internal operation negative pump circuit 15 is inactive. The reset circuit 32 performs a reset operation for setting the output node of the external application selection circuit 27 to the ground potential (0 V) when the internal operation negative pump circuit 16 is inactive. The reset circuit 33 performs a reset operation for setting the output node of the external application selection circuit 28 to the ground potential (0 V) when the internal operation negative pump circuit 17 is inactive.

  The selection circuit 34 selects one of the output potentials of the external application selection circuits 23 and 25 and the ground potential (0 V) and supplies the selected one to the word line driver 39. The selection circuit 35 selects one of the output potentials of the external application selection circuits 23 and 25 and the ground potential (0 V) and supplies the selected one to the well driver 40 and the source driver 41. The selection circuit 36 selects one of the output potentials of the external application selection circuits 26 and 27 and the ground potential (0 V) and supplies the selected one to the word line driver 39. The selection circuit 37 selects one of the output potentials of the external application selection circuits 26 and 28 and the ground potential (0 V) and supplies the selected one to the well driver 40 and the source driver 41.

  The write circuit 38 receives the output potential of the external application selection circuit 24 and applies a predetermined potential corresponding to the operation mode to the bit line BL of the memory unit 42. The word line driver 39 receives the output potentials of the selection circuits 34 and 36 and applies a predetermined potential corresponding to the operation mode to the word lines WL of the memory unit 42. The well driver 40 receives the output potentials of the selection circuits 35 and 37 and applies a predetermined potential to the well of the memory unit 42 according to the operation mode. The source driver 41 receives the output potentials of the selection circuits 35 and 37 and applies a predetermined potential corresponding to the operation mode to the source line SL of the memory unit 42. The memory unit 42 includes a plurality of memory cells for storing data.

For example, during a read operation, the potential VPP (for example, 5.5 V) from the normal operation positive pump circuit 11 is applied to the word of the memory unit 42 via the external application selection circuit 23, the selection circuit 34, and the word line driver 39. Is applied to the line WL. A ground potential (0 V) from the selection circuit 37 is applied to the well of the memory unit 42 via the well driver 40. The ground potential (0 V) from the selection circuit 37 is applied to the source line SL of the memory unit 42 via the source driver 41.

  During the program operation, the potential VPW (eg, 9.7 V) from the internal operation positive pump circuit 13 is applied to the word line WL of the memory unit 42 via the external application selection circuit 25, the selection circuit 34, and the word line driver 39. Given. The potential VPB (for example, 5.1 V) from the internal operation positive pump circuit 12 is applied to the bit line BL of the memory unit 42 via the external application selection circuit 24 and the write circuit 38. Further, the potential VNC (for example, −0.9 V) from the internal operation negative pump circuit 17 is applied to the well of the memory unit 42 via the external application selection circuit 28, the selection circuit 37 and the well driver 40. Further, the ground potential (0 V) from the selection circuit 35 is applied to the source line SL of the memory unit 42.

  In the erase operation, the potential VNA (for example, −9.2 V) from the internal operation negative pump circuit 15 is supplied to the word line WL of the memory unit 42 via the external application selection circuit 26, the selection circuit 36, and the word line driver 39. Given to. A potential VPW (for example, 7.5 V) from the internal operation positive pump circuit 13 is applied to the well of the memory unit 42 via the external application selection circuit 25, the selection circuit 35, and the well driver 40. Further, the potential VPW (for example, 7.5 V) from the internal operation positive pump circuit 13 is applied to the source line SL of the memory unit 42 via the external application selection circuit 25, the selection circuit 35, and the source driver 41. Note that the level of the output potential VPW of the internal operation positive pump circuit 13 is switched according to the operating state (for example, it is set to 9.7 V during the program operation and 7.5 V during the erase operation).

  FIG. 2 is a block diagram showing the configuration of the frequency divider 3 and the internal operation positive pump circuits 12 and 13 shown in FIG. In FIG. 2, the frequency dividing circuit unit 3 includes a frequency dividing circuit 59 and a selection circuit 60. The internal operation positive pump circuit 12 includes an inverter 51, a detection circuit 52, clock drivers 53 and 54, charge pumps 55 and 56, and AND circuits 57 and 58. The internal operation positive pump circuit 13 includes an inverter 61, a detection circuit 62, clock drivers 63 and 64, charge pumps 65 and 66, and AND circuits 67 and 68.

  When the activation signal EN1 is at the “H” level, which is the activation level, the frequency dividing circuit 59 divides the frequency of the clock signal CLK from the clock generation circuit 1 (decreases the frequency) and generates the clock signal CLK1. On the other hand, when the activation signal EN1 is at the “L” level of the inactivation level, the clock signal CLK from the clock generation circuit 1 is output as it is as the clock signal CLK2. When the activation signal EN1 is at the “H” level, which is the activation level, the selection circuit 60 selects the clock signal CLK1 from the frequency dividing circuit 59 and outputs it as the clock signal CLKD. On the other hand, when the activation signal EN1 is at the “L” level of the inactivation level, the clock signal CLK2 from the frequency dividing circuit 59 is selected and output as the clock signal CLKD. Inverter 51 inverts and outputs the logic level of clock signal CLKD. The inverter 61 inverts the logic level of the clock signal CLK and outputs it.

  FIG. 3 is a circuit diagram showing a configuration of the detection circuit 52. In FIG. 3, the detection circuit 52 includes resistance elements 71 and 72, a comparison circuit 73, and a constant current source 74. The potential VPB from the output node N1 is divided by the resistance elements 71 and 72 and applied to the negative input terminal of the comparison circuit 73 as the divided potential VPBD. A reference potential VREF that is a potential corresponding to the target level of the potential VPB is applied to the positive input terminal of the comparison circuit 73. A constant current source 74 is connected between the ground terminal of the comparison circuit 83 and the ground potential GND line.

The comparison circuit 73 compares the divided potential VPBD with the reference potential VREF. When the divided potential VPBD is lower than the reference potential VREF, the output detection signal PEB is set to the “H” level, and the divided potential VPBD is greater than the reference potential VREF. Is higher, the output detection signal PEB is set to the “L” level. With such a configuration, the detection circuit 52 outputs the detection signal PEB to the AND circuits 57 and 58 based on the reference potential VREF from the reference potential generation circuit 2 and the potential VPB from the output node N1.

  Returning to FIG. 2, the configuration and operation of the detection circuit 62 are the same as those of the detection circuit 52 shown in FIG. 3, and based on the reference potential VREF from the reference potential generation circuit 2 and the potential VPW from the output node N2. The detection signal PEW is output to the AND circuits 67 and 68.

  AND circuits 57 and 58 receive activation signal EN2 from the outside and detection signal PEB from detection circuit 52. The output signal of the AND circuit 57 is supplied to the clock driver 53, and the output signal of the AND circuit 58 is supplied to the clock driver 54. AND circuit 67 receives activation signal EN3 from the outside and detection signal PEW from detection circuit 62. An output signal of the AND circuit 67 is given to the clock driver 63. AND circuit 68 receives external activation signal EN4 and detection signal PEW from detection circuit 62. An output signal of the AND circuit 68 is given to the clock driver 64.

  The clock driver 53 is activated when the output signal of the AND circuit 57 is at “H” level, and current-amplifies the clock signal CLKD from the frequency dividing circuit unit 3 to generate four-phase clock signals φA1 to φA4 and charge them. Feed to pump 55. On the other hand, when the output signal of AND circuit 57 is at “L” level, it is inactivated and clock signal CLKD from frequency divider circuit section 3 is not transmitted.

  FIG. 4 is a circuit diagram showing in detail the configuration of the unit circuit of the clock driver 53. 4, the unit circuit of clock driver 53 includes switch circuits 81 to 84, P channel MOS transistor groups 85 and 87, and N channel MOS transistor groups 86 and 88.

  The switch circuits 81 to 84 are controlled by an external selection signal SEL. Selection signal SEL is set to “L” level when external power supply potential EXVDD is low (eg, 1.8 V), and is set to “H” level when external power supply potential EXVDD is high (eg, 3.0 V). Switch circuit 81 connects the ground potential GND line and node N12 when selection signal SEL is at "L" level. On the other hand, when the selection signal SEL is at “H” level, the node N11 and the node N12 are connected. Switch circuit 82 disconnects output node N14 and output node N18 when selection signal SEL is at "L" level. On the other hand, when the selection signal SEL is at “H” level, the output node N14 and the output node N18 are connected. The switch circuit 83 connects the node N11 and the node N15 when the selection signal SEL is at the “L” level. On the other hand, when selection signal SEL is at “H” level, ground potential GND line and node N15 are connected. Switch circuit 84 connects output node N17 and output node N18 when selection signal SEL is at "L" level. On the other hand, when selection signal SEL is at "H" level, output node N17 and output node N18 are disconnected.

  P channel MOS transistor group 85 includes P channel MOS transistors 91 and 92 and a plurality of P channel MOS transistors 101. N channel MOS transistor group 86 includes N channel MOS transistors 93 and 94 and a plurality of N channel MOS transistors 102. The number of P-channel MOS transistors 101 and N-channel MOS transistors 102 is the same.

P channel MOS transistors 91 and 92 are connected between a line of external power supply potential EXVDD and node N13, respectively. N channel MOS transistors 93 and 94 are connected in series between node N13 and a line of ground potential GND. The gates of P channel MOS transistor 91 and N channel MOS transistor 94 are both connected to node N12. The gates of P channel MOS transistor 92 and N channel MOS transistor 93 both receive the output signal of AND circuit 57. P channel MOS transistor 101 and N channel MOS transistor 102 are connected in series between an external power supply potential EXVDD line and a ground potential GND line. A plurality of sets of P-channel MOS transistor 101 and N-channel MOS transistor 102 each constitute an inverter. The plurality of inverters are connected in series between the node N13 and the output node N14.

  P channel MOS transistor group 87 includes P channel MOS transistors 95 and 96 and a plurality of P channel MOS transistors 103. N channel MOS transistor group 88 includes N channel MOS transistors 97 and 98 and a plurality of N channel MOS transistors 104. The number of P-channel MOS transistors 103 and N-channel MOS transistors 104 is the same.

  P channel MOS transistors 95 and 96 are connected between a line of external power supply potential EXVDD and node N16, respectively. N channel MOS transistors 97 and 98 are connected in series between node N16 and a line of ground potential GND. The gates of P channel MOS transistor 95 and N channel MOS transistor 98 are both connected to node N15. The gates of P channel MOS transistor 96 and N channel MOS transistor 97 both receive the output signal of AND circuit 57. P-channel MOS transistor 103 and N-channel MOS transistor 104 are connected in series between the line of external power supply potential EXVDD and the line of ground potential GND. A plurality of sets of P-channel MOS transistor 103 and N-channel MOS transistor 104 each constitute an inverter. The plurality of inverters are connected in series between the node N16 and the output node N17.

  P channel MOS transistors 91, 92, 101 and N channel MOS transistors 93, 94, 102 are suitable when the oxide film is thick and external power supply potential EXVDD is high (eg, 3V). P-channel MOS transistors 95, 96, and 103 and N-channel MOS transistors 97, 98, and 104 are suitable when the oxide film is thin and external power supply potential EXVDD is low (for example, 1.8 V). Thus, transistor groups 85 and 86 composed of transistors with thick oxide films and transistor groups 87 and 88 composed of transistors with thin oxide films are provided, and the transistor groups are selected according to the level of the external power supply potential EXVDD. Use it.

  That is, when external power supply potential EXVDD is high (for example, 3 V), selection signal SEL is set to “H” level, and clock signal CLKD has a plurality of stages composed of P channel MOS transistor group 85 and N channel MOS transistor group 86. Is output from the output node N18 as the clock signal φA1. On the other hand, when external power supply potential EXVDD is low (for example, 1.8 V), selection signal SEL is set to “L” level, and clock signal CLKD is formed of P channel MOS transistor group 87 and N channel MOS transistor group 88. The clock signal φA1 is output from the output node N18 through a plurality of stages of inverters.

FIG. 5 is a circuit diagram showing in more detail the configuration of P channel MOS transistor group 87 and N channel MOS transistor group 88 shown in FIG. Referring to FIG. 5, switch circuits 105, 107, 112 are provided at the gates of P-channel MOS transistors 95, 96, 103. Switch circuits 106, 108 and 113 are provided at the drains of P-channel MOS transistors 95, 96 and 103. Switch circuits 109 and 114 are provided at the drains of N-channel MOS transistors 97 and 104, respectively. Switch circuits 110, 111, and 115 are provided at the gates of N-channel MOS transistors 97, 98, and 104, respectively. The switch circuits 105 to 115 are controlled by a selection signal SEL.

  When selection signal SEL is at “L” level (when external power supply potential EXVDD is low), switch circuit 105 connects node N15 and the gate of P-channel MOS transistor 95. Switch circuit 106 connects the drain of P-channel MOS transistor 95 and node N16. Switch circuit 107 connects the output node of AND circuit 57 and the gate of P-channel MOS transistor 96. Switch circuit 108 connects the drain of P-channel MOS transistor 96 and node N16. Switch circuit 109 connects node N16 and the drain of N-channel MOS transistor 97. Switch circuit 110 connects the output node of AND circuit 57 and the gate of N channel MOS transistor 97. Switch circuit 111 connects node N15 and the gate of N-channel MOS transistor 98. Therefore, when the output signal of AND circuit 57 is at “H” level, P channel MOS transistor 96 is turned off and N channel MOS transistor 97 is turned on, so that the clock signal transmitted to node N15 has a logic level. Inverted and applied to node N16. When the output signal of AND circuit 57 is at “L” level, P-channel MOS transistor 96 is conductive and N-channel MOS transistor 97 is non-conductive, so that node N16 is fixed at “H” level, and node N15 The transmitted clock signal is not transmitted to node N16.

  On the other hand, when selection signal SEL is at “H” level (when external power supply potential EXVDD is high), switch circuit 105 connects the line of external power supply potential EXVDD and the gate of P channel MOS transistor 95. Switch circuit 106 connects the drain of P-channel MOS transistor 95 and the line of external power supply potential EXVDD. Switch circuit 107 connects the line of external power supply potential EXVDD and the gate of P channel MOS transistor 96. Switch circuit 108 connects the drain of P channel MOS transistor 96 and the line of external power supply potential EXVDD. Switch circuit 109 connects the ground potential GND line and the drain of N-channel MOS transistor 97. Switch circuit 110 connects the ground potential GND line and the gate of N-channel MOS transistor 97. Switch circuit 111 connects the ground potential GND line and the gate of N-channel MOS transistor 98.

  Thus, the sources, drains and gates of P channel MOS transistors 95 and 96 are all connected to the line of external power supply potential EXVDD. Further, the drain and gate of N channel MOS transistor 97 and the source and gate of N channel MOS transistor 98 are both connected to the line of ground potential GND. Therefore, P channel MOS transistors 95 and 96 and N channel MOS transistors 97 and 98 are rendered non-conductive, and the MOS transistor is prevented from being deteriorated by high external power supply potential EXVDD.

  When selection signal SEL is at “L” level (when external power supply potential EXVDD is low), switch circuit 112 connects node N16 and the gate of P-channel MOS transistor 103. Switch circuit 113 connects the drain of P-channel MOS transistor 103 and node N21. Switch circuit 114 connects node N21 and the drain of N-channel MOS transistor 104. Switch circuit 115 connects node N16 and the gate of N-channel MOS transistor 104. Therefore, the logic level of the clock signal transmitted to node N16 is inverted and applied to node N21.

  On the other hand, when selection signal SEL is at “H” level (when external power supply potential EXVDD is high), switch circuit 112 connects the line of external power supply potential EXVDD and the gate of P channel MOS transistor 103. Switch circuit 113 connects the drain of N-channel MOS transistor 103 and the line of external power supply potential EXVDD. Switch circuit 114 connects the ground potential GND line and the drain of N-channel MOS transistor 104. Switch circuit 115 connects the ground potential GND line and the gate of N-channel MOS transistor 104.

  Thus, the source, drain and gate of P channel MOS transistor 103 are all connected to the line of external power supply potential EXVDD. The source, drain and gate of N channel MOS transistor 104 are all connected to the ground potential GND line. Therefore, P channel MOS transistor 103 and N channel MOS transistor 104 are rendered non-conductive, and deterioration of the MOS transistor due to high external power supply potential EXVDD is prevented.

  With the above configuration, the MOS transistors included in P-channel MOS transistor group 87 and N-channel MOS transistor group 88 are switched so that external power supply potential EXVDD is not applied to the MOS transistors when external power supply potential EXVDD is high. This prevents the MOS transistor from deteriorating.

  Here, the case where the switch circuits 81 to 84 and 105 to 115 are switch circuits that are switched by the selection signal SEL has been described. However, the switch circuits 81 to 84 and 105 to 115 can change the AL (aluminum) by changing the mask. It may be a switching circuit for switching the wiring path.

  FIG. 6 is a layout diagram for explaining the arrangement of P channel MOS transistor groups 85 and 87 and N channel MOS transistor groups 86 and 88 shown in FIG. In FIG. 6, N well region 121 is connected to a line of external power supply potential EXVDD, and P well region 122 is connected to a line of ground potential GND.

  In the N well region 121, PMOS regions 123 and 124 are arranged. In PMOS region 123, P channel MOS transistors 91 and 92 and a plurality of P channel MOS transistors 101 shown in FIG. 4 are arranged. In PMOS region 124, P channel MOS transistors 95 and 96 and a plurality of P channel MOS transistors 103 shown in FIG. 4 are arranged.

  NMOS regions 125 and 126 are arranged on P well region 122. In NMOS region 125, N channel MOS transistors 93 and 94 and a plurality of N channel MOS transistors 102 shown in FIG. 4 are arranged. N channel MOS transistors 97 and 98 and a plurality of N channel MOS transistors 104 shown in FIG. 4 are arranged in NMOS region 126.

In the conventional clock driver, the N well region 121 is separated into two, and the PMOS region 123 and the PMOS region 124 are arranged on separate N well regions. This is because the switch circuits 105 to 115 are not provided in the P channel MOS transistor group 87 and the N channel MOS transistor group 88. In this case, when external power supply potential EXVDD is high, node N15 is set to “L” level, and P channel MOS transistor 95 is rendered conductive. Thus, since P-channel MOS transistor 95 having a thin oxide film receives high external power supply potential EXVDD, the transistor may be deteriorated. Therefore, the N well region in which the PMOS region 123 is disposed and the N well region in which the PMOS region 124 is disposed.
The well region was separated. Thereby, a high external power supply potential EXVDDH can be applied to the N well region where the PMOS region 123 is disposed, and a low internal power supply potential EXVDDL can be applied to the N well region where the PMOS region 124 is disposed. However, in such a configuration, a space is required at the boundary between the two N-well regions, so that the layout area of the clock driver is large.

  Therefore, in this embodiment, switch circuits 105 to 115 are provided in P channel MOS transistor group 87 and N channel MOS transistor group 88, and PMOS regions 123 and 124 are arranged on one N well region 121. Therefore, the layout area of the clock driver is reduced.

  The layout diagram shown in FIG. 6 is a diagram showing the arrangement of the transistors of the unit circuit of the clock driver 53 shown in FIG. 4, and the clock driver 53 is provided with a plurality of unit circuits. For example, when the charge pump 55 has a 10-stage configuration, this unit circuit is provided twice the number of stages of the pump unit, that is, 20 units. Therefore, in this embodiment, the layout area for each unit circuit of the clock driver is reduced, so that the layout area of the entire clock driver is greatly reduced.

  Returning to FIG. 2, the configuration and operation of the clock drivers 54, 63 and 64 are the same as those of the clock driver 53. The clock driver 54 is activated when the output signal of the AND circuit 58 is at “H” level, current-amplifies the output clock signal of the inverter 51, and generates the four-phase clock signals / φA1 to / φA4 to generate the charge pump 56. To give. On the other hand, when the output signal of AND circuit 58 is at “L” level, it is deactivated and the output clock signal of inverter 51 is not transmitted. The clock driver 63 is activated when the output signal of the AND circuit 67 is at “H” level. The clock driver 63 amplifies the clock signal CLK from the clock generation circuit 1 to generate the four-phase clock signals φB1 to / φB4 to be charged. Feed to pump 65. On the other hand, when the output signal of AND circuit 67 is at “L” level, it is deactivated and clock signal CLK from clock generation circuit 1 is not transmitted. The clock driver 64 is activated when the output signal of the AND circuit 68 is at “H” level, current-amplifies the output clock signal of the inverter 61, generates the four-phase clock signals / φB1 to / φB4, and generates the charge pump 66. To give. On the other hand, when the output signal of AND circuit 68 is at “L” level, it is deactivated and the output clock signal of inverter 61 is not transmitted.

  Charge pump 55 is driven by clock signals φA1 to φA4 from clock driver 53 to generate potential VPB and supply it to output node N1. Charge pump 56 is driven by clock signals / φA1 to / φA4 from clock driver 54 to generate potential VPB and supply it to output node N1. Charge pump 65 is driven by clock signals φB1 to φB4 from clock driver 63 to generate potential VPW and supply it to output node N2. Charge pump 66 is driven by clock signals / φB1 to / φB4 from clock driver 64 to generate potential VPW and supply it to output node N2.

  Here, the configuration and operation of the charge pump 65 will be described in detail. FIG. 7 is a circuit diagram showing a configuration of the charge pump 65. In FIG. 7, charge pump 65 includes N channel MOS transistors 131-151 and capacitors 161-180.

N channel MOS transistors 131-140 are connected in series between a line of external power supply potential EXVDD and node N51. N channel MOS transistors 131-140 have their gates connected to nodes N31-N40, respectively. N channel MOS transistors 141-150 are connected between nodes N41-N50 and nodes N31-N40, respectively. The gates of N channel MOS transistors 141-150 are connected to node N4, respectively.
2 to N51. N channel MOS transistor 151 has its drain and gate connected to node N51 to form a diode. Potential VPW is output from the source of N channel MOS transistor 151.

  Odd-numbered capacitors 161-169 have one electrode receiving clock signal φB2 from clock driver 63 and the other electrode connected to odd-numbered nodes N31-N39. Even-numbered capacitors 162 to 170 have one electrode receiving clock signal φB4 from clock driver 63 and the other electrode connected to even-numbered nodes N32 to N40. Odd-numbered capacitors 171 to 179 have one electrode receiving clock signal φB3 from clock driver 63 and the other electrode connected to even-numbered nodes N42 to N50. Even-numbered capacitors 172 to 180 have one electrode receiving clock signal φB1 from clock driver 63 and the other electrode connected to odd-numbered nodes N43 to N51. Thus, the charge pump 65 has a 10-stage pump configuration.

  FIG. 8 is a circuit diagram showing a configuration for resetting the potentials of nodes N31 to N40 of charge pump 65 shown in FIG. 8, charge pump 65 further includes an inverter 181, P channel MOS transistors 182 and 183, and N channel MOS transistors 184, 185 and 191 to 200.

  P-channel MOS transistor 182 and N-channel MOS transistor 184 are connected in series between a potential VPP (output potential of normal operation positive pump circuit 11) line and a ground potential GND line. P channel MOS transistor 182 has its gate connected to output node N62. The gate of N channel MOS transistor 184 receives an external reset signal RS via inverter 181. P-channel MOS transistor 183 and N-channel MOS transistor 185 are connected in series between a potential VPP (output potential of normal operation positive pump circuit 11) line and a ground potential GND line. P channel MOS transistor 183 has its gate connected to node N61. N channel MOS transistor 185 has its gate receiving external reset signal RS.

  N channel MOS transistors 191 to 200 are connected between nodes N31 to N40 shown in FIG. 7 and the line of external power supply potential EXVDD, respectively. The gates of N channel MOS transistors 191 to 200 are commonly connected to output node N61.

  FIG. 9 is a time chart for explaining the operation of the charge pump 65. In FIG. 9, clock signals φB <b> 1 to φB <b> 4 are signals given from the clock driver 63.

Here, the operation of the pump unit at the 10th stage in FIG. 7 will be described using this time chart. In the period from time t0 to time t1, clock signals φB1 and φB2 are set to “H” level, the charge of node N49 is transferred to node N50, and node N50 is charged to a high potential. At time t1, in response to clock signal φB2 falling to "L" level, N channel MOS transistor 139 is rendered non-conductive, and node N49 and node N50 are electrically disconnected. Next, at time t2, the potential of node N50 rises in response to clock signal φB3 being raised to “H” level. At this time, since N channel MOS transistor 150 is conductive in response to clock signal φB1 being at “H” level, the charge of node N50 is transferred to node N40, and node N40 is charged to a high potential. . At time t3, in response to the fall of clock signal φB1 to “L” level, N channel MOS transistor 150 is rendered non-conductive, and node N50 and node N40 are electrically disconnected. Next, at time t4, N channel MOS transistor 140 responds in response to clock signal φB4 reaching the “H” level.
Is conducted. At this time, since the potential of the node N40 charged to a high potential further increases, the transfer capability of the N-channel MOS transistor 140 increases, and the node N40 is not affected by the threshold voltage of the N-channel MOS transistor 140. The charge of N50 is transferred to the node N51. The operation of the pump unit from the first stage to the ninth stage is the same, and the potentials of the nodes N41 to N51 rise in order.

Assuming that the threshold voltage of the N-channel MOS transistor 151 constituting the diode is Vth, the potential of the node N51, that is, the output potential of the 10th stage pump unit is (VPW + Vth). Therefore, when the output potential of the i-th pump unit is Vi, the following equation is established.
Vi = EXVDD + i (VPW + Vth−EXVDD) / 10 (1)
The nodes N31 to N40 of the pump units in each stage are set to a higher potential than the output potential Vi of the pump unit of each stage. Here, consider a case where the pump operation of the internal operation positive pump circuit 13 is once stopped and then restarted. That is, referring to FIG. 1, external application circuit 23 selectively outputs output potential VPP (for example, 5.5 V) of normal operation positive pump circuit 11, and external application circuit 25 outputs internal operation positive pump circuit 13. While the output potential VPW (for example, 9.7 V) is selectively output, the pump operation of the internal operation positive pump circuit 13 is stopped and the reset circuit 30 selects the external application to the output node of the external application selection circuit 24. An output potential VPP (for example, 5.5 V) of circuit 23 is applied. Thereafter, the operation of the internal operation positive pump circuit 13 is resumed, and the potential VPW (for example, 9.7 V) is generated again from the internal operation positive pump circuit 13.

  Referring to FIG. 7, in this case, the output potential of charge pump 65 is reset from VPW (for example, 9.7 V) to VPP (for example, 5.5 V). At this time, the node N51 is at a high potential (for example, 5.5 V + Vth). Since a high potential remains at node N40, N channel MOS transistor 140 is rendered conductive, and node N50 is set to the same high potential (eg, 5.5 V + Vth) as node N51. N-channel MOS transistor 150 has its gate rendered conductive by receiving the high potential of node N51. Therefore, when the output potential of charge pump 65 is reset from VPW (for example, 9.7 V) to VPP (for example, 5.5 V), the potential of node N40 decreases due to coupling, but node N40 has an external potential. A high potential equal to or higher than the power supply potential EXVDD (for example, 1.8 V) remains. The ninth-stage pump unit is the same as the tenth-stage pump unit. Node N49 is set to the same high potential as node N50, and node 39 has a high potential equal to or higher than external power supply potential EXVDD (eg, 1.8 V). Will remain. Since a high potential is not originally applied to the first-stage pump unit, when the output potential of the charge pump 65 is reset from VPW (for example, 9.7 V) to VPP (for example, 5.5 V), the nodes N31 and N32 ,... Are lowered by coupling, and the potentials of nodes N31, N32,... Are lower than external power supply potential EXVDD (for example, 1.8 V).

  In this state, when the operation of the internal operation positive pump circuit 13 is restarted and the positive potential VPW (for example, 9.7 V) is generated again from the internal operation positive pump circuit 13, the ninth and tenth stages Since the potential higher than the external power supply potential EXVDD (for example, 1.8 V) remains at the nodes N39 and N40 of the pump section, the N-channel MOS transistors 139 and 140 are conductive and have no rectifying action. That is, since the pump unit on the rear stage side cannot perform the pump operation, the pumping capacity of the charge pump 65 is reduced. In order to prevent such a problem, a circuit shown in FIG. 8 is provided.

Referring to FIG. 8, reset signal RS is a signal that is set to “H” level when internal operation positive pump circuit 13 is operating, and is set to “L” level when it is stopped. When reset signal RS is at “H” level, N channel MOS transistor 184 is turned off and N channel MOS transistor 185 is turned on. In response, output node N62 is set to “L” level, and P channel MOS transistor 182 is rendered conductive. Therefore, node N61 is set to “H” level, and P channel MOS transistor 183 is rendered non-conductive. At this time, N channel MOS transistors 191 to 200 are rendered non-conductive in response to output node N62 being set to "L" level.

  On the other hand, when reset signal RS is at “L” level, N-channel MOS transistor 184 is turned on and N-channel MOS transistor 185 is turned off. In response, node N61 is set to “L” level, and P channel MOS transistor 183 is rendered conductive. Therefore, output node N62 is set to “H” level, and P channel MOS transistor 182 is rendered non-conductive. At this time, N channel MOS transistors 191 to 200 are rendered conductive in response to output node N62 being set to "H" level. Therefore, the potentials of nodes N31 to N40 are reset to external power supply potential EXVDD (for example, 1.8 V). Therefore, when the operation of the internal operation positive pump circuit 13 is restarted and the positive potential VPW (eg, 9.7 V) is generated again from the internal operation positive pump circuit 13, the ninth and tenth stages Since the potential higher than the external power supply potential EXVDD (for example, 1.8 V) does not remain at the nodes N39 and N40 of the pump unit, the rectifying action of the N channel MOS transistors 139 and 140 is recovered. That is, the problem that the pump unit of the rear stage side does not perform the pump operation is solved, and the pumping capacity of the charge pump 65 is prevented from being lowered.

  Next, returning to FIG. 1, an operation in which the potentials of the bit line BL and the word line WL of the memory unit 42 are controlled by the internal operation positive pump circuits 12 and 13 will be described. FIG. 10 is a time chart showing potential changes of the bit line BL and the word line WL of the memory unit 42. In FIG. 10, the normal operation period is a period during which a normal operation such as a read operation is performed, the internal operation period is a period during which an internal operation such as a program operation is performed, and the preparation period is a preparation for transition from the normal operation state to the internal operation state. It is a period to perform.

  Referring to FIGS. 1, 2, and 10, normal operation positive pump circuit 11 generates positive potential VPP (for example, 5.5 V) in the normal operation period up to time t10. The external application selection circuit 23 selectively outputs the potential VPP from the normal operation positive pump circuit 11. The selection circuit 34 selects the output potential VPP of the external application selection circuit 23 and supplies it to the word line driver 39. The potential of the word line WL in the memory unit 42 is set to VPP by the word line driver 39. Further, the internal operation positive pump circuits 12 and 13 are inactivated. The reset circuit 29 applies a potential (VPP−Vth) that is lower than the output potential VPP of the external application selection circuit 23 by the threshold voltage Vth of the transistor to the output node of the external application selection circuit 24. The potential of the bit line BL of the memory unit 42 is set to (VPP−Vth) by the write circuit 38.

At time t10, activation signals EN1 to EN4 are set to the “H” level of the activation level. In response to the activation signal EN1 being set to the activation level “H” level, the frequency dividing circuit unit 3 divides the clock signal CLK from the clock generation circuit 1 and outputs the clock signal CLKD. The internal operation positive pump circuits 12 and 13 are activated in response to the activation signals EN2 to EN4 being set to the “H” level of the activation level. The external application selection circuit 24 selectively outputs the output potential of the internal operation positive pump circuit 12. The external application selection circuit 25 selects the output potential of the internal operation positive pump circuit 13 and outputs it to the writing circuit 38. The reset circuits 29 and 30 do not perform the reset operation because the internal operation positive pump circuits 12 and 13 are activated. The selection circuit 34 selects the output potential of the external application selection circuit 25 and supplies it to the word line driver 39. The output potential of the internal operation positive pump circuit 13 is applied to the word line WL of the memory unit 42. Further, the output potential of the internal operation positive pump circuit 12 is applied to the bit line BL of the memory unit 42. The period from time t10 to time t11 is a preparation period for transition from the normal operation period to the internal operation period.

  At time t11, the potential of the word line WL is set to a predetermined potential VPW (for example, 9.7 V) by the internal operation positive pump circuit 13, and the potential of the bit line BL is set to the predetermined potential VPB by the internal operation positive pump circuit 12. (For example, 5.1V). Further, at time t11, the activation signals EN1 and EN4 are set to the “L” level of the inactivation level. In response to the activation signal EN1 being set to the inactivation level “L” level, the frequency dividing circuit unit 3 outputs the clock signal CLKD from the clock generation circuit 1 as the clock signal CLKD without frequency dividing. To do. For this reason, the driving capability of the positive pump circuit 12 for internal operation is increased. Further, the clock driver 64 of the internal operation positive pump circuit 13 is deactivated in response to the activation signal EN4 being set to the “L” level of the deactivation level. For this reason, the driving capability of the internal operation positive pump circuit 13 is halved.

  At time t12, activation signals EN2 and EN3 are set to the “L” level of the inactivation level. In response to this, the internal operation positive pump circuits 12, 13 are deactivated. The selection circuit 34 selects the output potential VPP of the external application selection circuit 23 and supplies it to the word line driver 39. The potential of the word line WL in the memory unit 42 is set to VPP by the word line driver 39. The reset circuit 29 applies a potential (VPP−Vth) that is lower than the output potential VPP of the external application selection circuit 23 by the threshold voltage Vth of the transistor to the output node of the external application selection circuit 24. The potential of the bit line BL of the memory unit 42 is set to (VPP−Vth) by the write circuit 38.

  In this way, the driving capabilities of the internal operation positive pump circuits 12 and 13 are switched at time t11. After word line WL is raised to a predetermined potential VPW (for example, 9.7 V), current consumption is reduced. Therefore, the clock drivers 63 and 64 and the charge pumps 65 and 66 of the internal operation positive pump circuit 1 are activated until time t11, and only the clock driver 63 and the charge pump 65 are activated after time t11. Bit line BL requires a large write current after being raised to a predetermined potential VPB (for example, 5.1 V). For this reason, the clock signal CLK is frequency-divided by the frequency dividing circuit unit 3 until time t11, and the potential of the bit line BL is gradually reduced to a predetermined potential VPB (for example, 5.5 V) by the low-frequency clock signal CLKD. Established. Here, by reducing the frequency of the clock signal CLKD, the potential of the bit line BL is prevented from becoming higher than the predetermined potential VPB. After time t11, since the clock signal CLK is not divided, the potential of the bit line BL is maintained at VPB by the clock signal CLKD having a high frequency. Therefore, the pump operation is appropriately controlled according to the state, and the ripple of the potential of the word line WL is suppressed. In addition, the peak value of the write current of the bit line BL is suppressed.

  Referring to FIG. 2, the reason why the inverter 51 is provided in the internal operation positive pump circuit 12 is to provide clock drivers 53 and 54 with mutually complementary clock signals. As a result, the two charge pumps 55 and 56 alternately and continuously generate voltages. Similarly, the internal operation positive pump circuit 13 is also provided with an inverter 61, and the two charge pumps 65 and 66 generate voltages alternately and continuously. For this reason, ripples of the output potentials VPB and VPW of the internal operation pump circuits 12 and 13 are suppressed.

  Although the case where the internal operation positive pump circuits 12 and 13 are provided with two sets of clock drivers and charge pumps has been described here, the number of sets of clock drivers and charge pumps may be arbitrarily plural. By changing these numbers, the driving capability of the pump circuit can be changed.

FIG. 11 is a block diagram showing a configuration of the normal operation positive pump circuit 11 shown in FIG.
In FIG. 11, the normal operation positive pump circuit 11 includes an active detection circuit 201, a standby detection circuit 202, a clock generation circuit 203, a clock driver 204, and a charge pump 205.

  The configurations and operations of the active detection circuit 201 and the standby detection circuit 202 are the same as those of the detection circuit 52 shown in FIG. However, the switch signal / SW is applied to the active detection circuit 201. The switching signal / SW is set to the “L” level of the activation level in the active state where the current consumption is large (operation state where the internal circuit operates), and in the standby state where the current consumption is small (standby state where the internal circuit does not operate). Is set to the “H” level which is an inactivation level.

  When the switching signal / SW is at the “L” level of the activation level, the active detection circuit 201 sends the clock generation circuit 203 to the clock generation circuit 203 based on the reference potential VREFS from the reference potential generation circuit 4 and the potential VPP from the output node N71. The detection signal PEAC is output. That is, the potential VPP divided by the internal resistance element is compared with the reference potential VREFS. When the potential VPP is lower than the target level, the output detection signal PEAC is set to the “H” level. When voltage VPP is higher than the target level, output detection signal PEAC is set to “L” level. Further, when the switching signal / SW is at the “H” level of the inactivation level, the output detection signal PEAC is set to the “L” level.

  Standby detection circuit 202 outputs detection signal PEST to clock generation circuit 203 based on reference potential VREFS from reference potential generation circuit 4 and potential VPP from output node N71. That is, the potential VPP is compared with the potential divided by the internal resistance element and the reference potential VREFS. When the potential VPP is lower than the target level, the output detection signal PEST is set to the “H” level. When the potential VPP is higher than the target level, the output detection signal PEST is set to the “L” level.

  Based on detection signals PEAC and PEST from active detection circuit 201 and standby detection circuit 202, clock generation circuit 203 generates active clock signal CLKAC, standby clock signal CLKST and shared clock signal CLKAS. When switching signal / SW is at "L" level, in response to detection signal PEAC from active detection circuit 201, active clock signal CLKAC and shared clock signal CLKAS are generated. On the other hand, when switching signal / SW is at “H” level, standby clock signal CLKST and shared clock signal CLKAS are generated in response to detection signal PEST from standby detection circuit 202.

  The configuration and operation of the clock driver 204 are the same as those of the clock drivers 53, 54, 63, and 64 shown in FIG. Clock driver 204 generates four-phase clock signals φAC1 to φAC4 and φAS1 to φAS4 in response to clock signals CLKAC and CLKAS from clock generation circuit 203 when switching signal / SW is at “L” level. On the other hand, when switching signal / SW is at “H” level, four-phase clock signals φST4, φAS1 to φAS4 are generated in response to clock signals CLKST, CLKAS from clock generation circuit 203.

  FIG. 12 is a circuit diagram illustrating the configuration of the charge pump 205, and is a diagram to be compared with FIG. Referring to charge pump 205 in FIG. 12, the difference from charge pump 65 in FIG. 7 is that the number of pump units is reduced from 10 to 7, and capacitors 171 to 174 are replaced by capacitors 211 to 214. In addition, N-channel MOS transistors 215 and 216 and a capacitor 217 are added, and clock signals φB1 to φB4 are replaced with clock signals φAC1 to φAC4, φAS1 to φAS4, and φST4.

  N channel MOS transistor 215 is connected between a line of external power supply potential EXVDD and node N44. N channel MOS transistor 215 has its gate connected to node N81. N channel MOS transistor 216 is connected between a line of external power supply potential EXVDD and node N81. N channel MOS transistor 216 has its gate connected to node N44. Capacitor 217 has one electrode receiving clock signal φST4 from clock driver 204 and the other electrode connected to node N81.

  One electrodes of capacitors 161 and 163 both receive clock signal φAC4. One electrode of capacitor 162 receives clock signal φAC2. One electrode of capacitor 211 receives clock signal φAC1. One electrode of capacitor 212 receives clock signal φAC3.

  One electrodes of capacitors 164 and 166 both receive clock signal φAS2. One electrodes of capacitors 165 and 167 both receive clock signal φAS4. One electrodes of capacitors 213 and 175 both receive clock signal φAS1. One electrode of capacitors 214 and 176 receives clock signal φAS3. The potential VPP is output from the source of the N channel MOS transistor 137.

  FIG. 13 is a time chart for explaining the operation of the normal operation positive pump circuit 11. In FIG. 13, the active state is switched to the standby state at time t20.

  In the period up to time t20, switching signal / SW is set to the “L” level of the activation level. In response to this, clock generation circuit 203 generates active clock signal CLKAC and shared clock signal CLKAS in response to “H” level detection signal PEAC from active detection circuit 201. Clock driver 204 generates clock signals φAC1 to φAC4 and φAS1 to φAS4 in response to clock signals CLKAC and CLKAS. At this time, the clock signal φST4 is set to the “L” level.

  The charge pump 205 is driven by clock signals φAC1 to φAC4, φAS1 to φAS4, and performs a pump operation by a seven-stage pump unit to generate a potential VPP. This pump operation is the same as the operation of the charge pump 65 shown in FIG.

  At time t20, switching signal / SW is raised to the inactivation level “H” level. In response to this, clock generation circuit 203 generates standby clock signal CLKST and shared clock signal CLKAS in response to “H” level detection signal PEST from standby detection circuit 202. Clock driver 204 generates clock signals φST4, φAS1 to φAS4 in response to clock signals CLKST, CLKAS. At this time, clock signals φAC1 to φAC4 are set to the “L” level.

  The charge pump 205 is driven by clock signals φST4, φAS1 to φAS4, and performs a pump operation by a five-stage pump unit to generate a potential VPP. Thus, the pump operation is performed by the seven-stage pump unit in the active state, and the pump operation is performed by the five-stage pump unit in the standby state. The current consumption of the pump circuit in the standby state is reduced by making the number of stages of the pump unit that performs the pump operation in the standby state smaller than the number of stages of the pump unit that performs the pump operation in the active state.

Conventionally, an active charge pump and a standby charge pump are separately provided. For this reason, the layout area of the charge pump occupying most of the area of the semiconductor integrated circuit device has been increased. However, in this embodiment, a part of the pump part of the charge pump (the pump part of the four stages from the rear stage) is shared as the active and standby pump parts, and the pump operation is performed in the active state and the standby state. Change the number of pump stages to be performed. Therefore, the layout area of the charge pump is reduced.

  FIG. 14 is a schematic cross-sectional view showing the configuration of capacitor 175 shown in FIG. In FIG. 14, the capacitor 175 includes a P substrate 221, an N well 222, N + type regions 223 and 224, and a gate (G) 225.

  An N well 222 is formed on the surface of the P substrate 221. N + -type regions 223 and 224 are formed on N well 222. A gate 225 made of the second polysilicon PS2 is formed on the N well 222. N + type regions 223 and 224 receive potential VSD, and gate 225 receives potential VG.

  The capacitor 175 having such a configuration is suitable when the oxide film formed between the N well 222 and the gate 225 is thick and applied potentials VSD and VG are high. The capacitor 175 has a small capacity per unit area. Capacitor 176 has the same configuration as capacitor 175. Thus, since a high potential is applied to the capacitors 175 and 176 corresponding to the fifth-stage and sixth-stage pump units, the high-voltage capacitors 175 and 176 having a thick oxide film are used.

  FIG. 15 is a schematic cross-sectional view showing a configuration of capacitor 211 shown in FIG. In FIG. 15, the capacitor 211 includes a P substrate 231, an N well 232, N + type regions 233 and 234, a floating gate (FG) 235 and a control gate (CG) 236.

  An N well 232 is formed on the surface of the P substrate 231. N + -type regions 233 and 234 are formed on N well 232. A floating gate 235 made of the first polysilicon PS1 is formed on the N well 232. A control gate 236 made of second polysilicon is formed on the floating gate 235. N + type regions 233 and 234 and control gate 236 receive potential VCG, and floating gate 235 receives potential VFG.

  The capacitor 211 having such a configuration is suitable when the oxide film formed between the N well 232 and the floating gate 235 is thin and the applied potential VCG is low. The capacitor 211 has a large capacity per unit area. The capacitors 212 to 214 have the same configuration as the capacitor 211. As described above, since a high potential is not applied to the capacitors 211 to 214 corresponding to the first to fourth pump units, it is not necessary to use a high-voltage capacitor with a thick oxide film, and a capacitor with a thin oxide film. 211-214 are used. For this reason, the layout area of the pump circuit is reduced as compared with the conventional case where only the high voltage capacitor is used.

  Returning to FIG. 1, the drive positive pump circuit 14 has the same configuration as the internal operation positive pump circuits 12 and 13, and the clock signal CLK from the clock generation circuit 1 and the reference potential from the reference potential generation circuit 2. Driven by VREF to generate a positive potential VPC (eg, 2.4V).

Similarly to the internal operation positive pump circuits 12 and 13 shown in FIG. 2, the internal operation negative pump circuits 15 to 17 include a detection circuit, a clock driver, and a charge pump. The configuration and operation of the detection circuit and clock driver of the internal operation negative pump circuit 15 are the same as those of the detection circuit and clock driver of the internal operation positive pump circuits 12 and 13 shown in FIG. However, the configuration and operation of the charge pump of the internal operation negative pump circuit 15 are different from the charge pumps of the internal operation positive pump circuits 12 and 13 shown in FIG.

  FIG. 16 is a circuit diagram showing the configuration of the charge pump of the internal operation negative pump circuit 15 shown in FIG. In FIG. 16, the charge pump of the negative pump circuit 15 for internal operation includes a level shifter 241, diodes 251 to 260, and capacitors 261 to 270.

  Based on the clock signal CLK from the clock generation circuit 1, the clock driver of the internal operation negative pump circuit 15 generates complementary clock signals φNA and / φNA. The level shifter 241 is driven by a potential VPC (for example, 2.4 V) from the driving positive pump circuit 14. Level shifter 241 converts the voltage level of clock signals φNA, / φNA from the level of external power supply potential EXVDD (for example, 1.8 V) to the level of potential VPC (for example, 2.4 V), and outputs it.

  Diodes 251 to 260 are connected in series between output node N91 and a line of ground potential GND. Odd-numbered capacitors 261 to 269 have one electrode connected to odd-numbered nodes N91 to N99 and the other electrode receiving clock signal / φNA from level shifter 241. Even-numbered capacitors 262-270 have one electrode connected to even-numbered nodes N 92 -N 100 and the other electrode receiving clock signal φNA from level shifter 241. Output node N91 outputs potential VNA (for example, -9.2 V). Here, the threshold voltage of the diode is Vdio.

  When clock signal φNA is set to “H” level (VPC), diode 260 is turned on, and the potential of node N100 becomes potential Vdio that is higher than ground potential (0 V) by threshold voltage Vdio of diode 260. Next, when the clock signal φNA is set to the “L” level (0 V), the potential of the node N100 decreases to (Vdio−VPC). At this time, since the clock signal / φNA is at the “H” level (VPC), the diode 259 is turned on, and the potential of the node N99 is higher than the potential of the node N100 by the threshold voltage Vdio of the diode 259 ( 2Vdio-VPC). Next, when the clock signal / φNA is set to the “L” level (0 V), the potential of the node N99 is lowered to 2 (Vdio−VPC).

  Thus, the potentials of the nodes N100 to N91 are lowered by (Vdio−VPC), and the potential VNA of the output node N91 is 10 (Vdio−VPC). For example, when the threshold voltage Vdio of the diode is 1.5V and the potential VPC from the driving positive pump circuit 14 is 2.4V, the potential VNA = 10 (1.5−2.4) = − 9V.

  In the conventional semiconductor integrated circuit device, since the driving positive pump circuit 14 is not provided, the internal operation negative pump circuit 15 is driven by the external power supply potential EXVDD (for example, 1.8 V). In this case, since the voltage level of clock signals φNA, / φNA is the level of external power supply potential EXVDD (for example, 1.4 V), generated potential VNA is 10 (Vdio−EXVDD). For example, when the threshold voltage Vdio of the diode is 1.5V and the external power supply potential EXVDD is 1.8V, the potential VNA = 10 (1.5−1.8) = − 3V. Therefore, in order to generate the potential VNA of −9 V, the number of diodes must be tripled to 30, which increases the layout area of the pump circuit.

  However, in this embodiment, the driving positive pump circuit 14 is provided, and the internal operation negative pump circuit 15 is driven at the potential VPC (for example, 2.4 V). As a result, the number of pump stages is reduced, and the area of the negative pump circuit 15 for internal operation is reduced.

The normal operation positive pump circuit 11 and the internal operation positive pump circuits 12 and 13 use an N-channel MOS transistor as the charge pump, but the internal operation negative pump circuit 15 uses a polysilicon diode. In the case of an N-channel MOS transistor, the back gate can be separated by a triple N well configuration, so that the back gate potential can be arbitrarily set. However, in the case of a P-channel MOS transistor, the back gate is fixed to the potential of the P substrate (ground potential GND) by the manufacturing process. Therefore, when a deep negative potential VNA (for example, −9.2 V) is generated, the potential difference between the source, drain, and P substrate of the P-channel MOS transistor exceeds the junction breakdown voltage (back gate effect). Therefore, a polysilicon diode is used as a rectifying element instead of the P-channel MOS transistor.

  FIG. 17 is a circuit diagram showing the configuration of the charge pump of the internal operation negative pump circuit 16 shown in FIG. In FIG. 17, the charge pump of negative pump circuit 16 for internal operation includes level shifter 271, P channel MOS transistors 281 to 285, and capacitors 291 to 294.

  The clock driver of the internal operation negative pump circuit 16 generates the four-phase clock signals φNB1 to φNB4 based on the clock signal CLK from the clock generation circuit 1. The level shifter 271 is driven by the potential VPC (for example, 2.4 V) from the driving positive pump circuit 14. Level shifter 271 converts the voltage levels of clock signals φNB2 and φNB4 from the level of external power supply potential EXVDD (for example, 1.8 V) to the level of potential VPC (for example, 2.4 V) and outputs the result.

  P channel MOS transistors 281 and 282 are connected in series between a line of ground potential GND and node N105. The gates of P channel MOS transistors 281 and 282 are connected to nodes N101 and N102, respectively. P-channel MOS transistors 283 and 284 are connected between nodes N103 and N104 and nodes N101 and N102, respectively. P channel MOS transistors 283 and 284 have their gates connected to nodes N104 and N105, respectively. P channel MOS transistor 285 has its drain and gate connected to node N105 to form a diode. The back gates of P-channel MOS transistors 281 to 285 are connected to the ground potential GND line, respectively. A potential VNB (−0.5 V) is output from the source of the P-channel MOS transistor 285.

  Capacitor 291 has one electrode receiving clock signal φNB2 from level shifter 271 and the other electrode connected to node N101. Capacitor 292 has one electrode receiving clock signal φNB4 from level shifter 271 and the other electrode connected to node N102. Capacitor 293 has one electrode receiving clock signal φNB3 from the clock driver and the other electrode connected to node N104. Capacitor 294 has one electrode receiving clock signal φNB1 from the clock driver and the other electrode connected to node N105.

  The pump operation of the internal operation negative pump circuit 16 is the same as the operation of the charge pump 65 of the internal operation positive pump circuit 13 shown in FIG. However, a P-channel MOS transistor is used in place of the N-channel MOS transistor, and the node N103 is connected to the ground potential GND line. Therefore, the potentials of the nodes N104 and N105 are lower than 0V. As a result, a negative potential VNB (for example, −0.5 V) is generated by the pump operation. In this case, the number of pump stages can be reduced as compared with the conventional case where the positive pump circuit 14 for driving is not provided, and the area of the negative pump circuit 16 for internal operation is reduced.

Returning to FIG. 1, the configuration and operation of the charge pump of the internal operation negative pump circuit 17 are the same as the charge pump of the internal operation negative pump circuit 16. Since the program operation is defined to have a shorter period than the erase operation, the negative pump circuit 17 for internal operation that generates the negative potential VNC (for example, −0.9 V) necessary for the well during the program operation is driven greatly. Ability is required. Since the polysilicon diode has a small current driving capability per unit area, when generating a shallow negative potential VNC (for example, −0.9 V) that does not cause a problem with the junction breakdown voltage, a P-channel MOS transistor is used as a rectifying element. When used, the layout area of the pump circuit can be reduced. Since the potential of the P substrate of the P channel MOS transistor is at the level of the ground potential GND, the threshold voltage of the P channel MOS transistor slightly increases due to the back gate effect. However, in this embodiment, the driving positive pump circuit 14 is provided, and the internal operation negative pump circuit 17 is driven by the potential VPC (for example, 2.4 V) from the driving positive pump circuit 14, whereby the P channel Even if the threshold voltage of the MOS transistor is slightly increased, there is no problem in operation.

  Further, the provision of the drive positive pump circuit 14 increases the area of the drive positive pump circuit 14, but the ratio of the area reduction of the internal operation negative pump circuits 15 to 17 is larger. The area of the entire semiconductor integrated circuit device is reduced. Since the negative pump circuits for internal operation 15 to 17 do not operate at the same time, one positive pump circuit for driving 14 can be shared.

  FIG. 18 is a circuit diagram showing a configuration of the external application selection circuit 25 shown in FIG. In FIG. 18, external application selection circuit 25 includes inverters 331, 333-336, buffer circuit 332, P channel MOS transistors 341-348, 351-359, and N channel MOS transistors 361-367.

  P-channel MOS transistors 341 and 342 and N-channel MOS transistor 361 are connected in series between input terminal 21 and the ground potential GND line. P channel MOS transistor 341 has its gate connected to node N122, and P channel MOS transistor 342 has its gate receiving potential VPP (for example, 5.5 V). N channel MOS transistor 361 has its gate receiving selection signal SELR via inverter 331. P-channel MOS transistors 343 and 344 and N-channel MOS transistor 362 are connected in series between input terminal 21 and the ground potential GND line. P channel MOS transistor 343 has its gate connected to node N121, and P channel MOS transistor 344 has its gate receiving potential VPP (for example, 5.5 V). The gate of N channel MOS transistor 362 receives selection signal SELR via inverters 333 and 331. P-channel MOS transistors 345 and 346 and N-channel MOS transistor 363 are connected in series between input terminal 21 and the ground potential GND line. The gates of P channel MOS transistor 345 and N channel MOS transistor 363 are connected to node N121. P channel MOS transistor 346 has its gate receiving potential VPP (for example, 5.5V). P-channel MOS transistors 347 and 348 and N-channel MOS transistor 364 are connected in series between input terminal 21 and the ground potential GND line. P channel MOS transistor 347 has its gate connected to node N123, and P channel MOS transistor 348 has its gate receiving potential VPP (for example, 5.5 V). N channel MOS transistor 364 has its gate receiving selection signal SELR through inverter 334.

Buffer circuit 332 is driven at potential VPP (for example, 5.5 V), and the voltage level of selection signal SELR is changed from the level of external power supply potential EXVDD (for example, 1.8 V) to the level of potential VPP (for example, 5.5 V). The signal SELS converted into is output. Inverter 336 is driven by the potential of output node N128, its input terminal receives selection signal SELR via inverter 331, and its output terminal is connected to the gate of P-channel MOS transistor 359. P channel MOS transistor 359 is connected between the output node of internal operation positive pump circuit 13 and output node N128.

  P channel MOS transistors 351 and 352 are connected in series between output node N128 and node N124. The gate of P channel MOS transistor 351 is connected to node N 125, and the gate of P channel MOS transistor 352 receives output signal SELS of buffer circuit 332. P channel MOS transistors 353 and 354 and N channel MOS transistor 365 are connected in series between output node N128 and a line of ground potential GND. The gates of P channel MOS transistor 353 and N channel MOS transistor 365 are connected to node N127. The gate of P channel MOS transistor 354 receives output signal SELS of buffer circuit 332. P-channel MOS transistors 355 and 356 and N-channel MOS transistor 366 are connected in series between output node N128 and the ground potential GND line. P channel MOS transistor 355 has its gate connected to node N 127, and P channel MOS transistor 356 has its gate receiving output signal SELS of buffer circuit 332. N channel MOS transistor 366 has its gate receiving selection signal SELR through inverters 335 and 331. P-channel MOS transistors 357 and 358 and N-channel MOS transistor 367 are connected in series between output node N128 and a line of ground potential GND. P channel MOS transistor 357 has its gate connected to node N 126, and P channel MOS transistor 358 has its gate receiving output signal SELS of buffer circuit 332. The gate of N channel MOS transistor 367 receives selection signal SELR via inverter 331.

  FIG. 19 is a simplified circuit block diagram corresponding to the external application selection circuit 25 shown in FIG. An application of the circuit configuration of FIG. 19 is the external application selection circuit 25 shown in FIG. In FIG. 19, selection signals SELP and SELQ are signals having a potential amplitude from 0V to an external power supply potential EXVDD (for example, 1.8V). When the selection signal SELP is at “H” level, the selection circuit 371 selects the potential VPP (for example, 5.5 V) from the normal operation positive pump circuit 11 received via the reset circuit 30, and the selection signal SELP is “ In the case of “L” level, external potential VEX (for example, 10 V) from input terminal 21 is selected, and the selected potential is output as VP. Inverter 372 is driven by potential VPP (for example, 5.5 V) from normal operation positive pump circuit 11. Inverter 372 inverts the logic level of selection signal SELP, converts the voltage level from the level of external power supply potential EXVDD (for example, 1.8 V) to the level of potential VPP (for example, 5.5 V), and outputs it.

  P channel MOS transistors 381 and 382 are connected in series between the output node of selection circuit 371 and node N131. P channel MOS transistor 381 has its gate connected to output node N132. P channel MOS transistor 382 has its gate connected to the output node of inverter 372. P channel MOS transistors 383 and 384 are connected in series between the output node of selection circuit 371 and node N132. P channel MOS transistor 383 has its gate connected to node N131. P channel MOS transistor 384 has its gate connected to the output node of inverter 372. P-channel MOS transistors 382 and 384 are provided to reduce the potential difference between the source and drain of P-channel MOS transistors 381 and 383 and to prevent deterioration of P-channel MOS transistors 381 and 383.

  N channel MOS transistor 385 is connected between node N131 and a line of ground potential GND. N channel MOS transistor 385 has its gate receiving selection signal SELQ. N channel MOS transistor 386 is connected between output node N132 and a line of ground potential GND. N channel MOS transistor 386 has its gate receiving selection signal SELQ via inverter 373.

  FIG. 20 is a time chart for explaining the operation of the circuit shown in FIG. At time t30, the selection circuit 371 selects and outputs the potential VPP according to the “H” level selection signal SELP. Further, in response to selection signal SELQ being raised to “H” level, N channel MOS transistor 385 is turned on and N channel MOS transistor 386 is turned off. In response, node N131 is set to “L” level and P channel MOS transistor 383 is rendered conductive. Inverter 372 receives “H” level selection signal SELP and outputs an “L” level (0 V) signal. P-channel MOS transistors 382 and 384 are turned on in response to an “L” level signal from inverter 372. At this time, node NA is set to potential Vth which is higher than gate voltage level (0 V) of P channel MOS transistor 382 by threshold voltage Vth of P channel MOS transistor 382, and output node N132 is at “H” level (VPP). To be. P channel MOS transistor 381 is rendered non-conductive.

  At time t31, selection signal SELQ falls to “L” level. In response, N channel MOS transistor 385 is turned off and N channel MOS transistor 386 is turned on. Therefore, output node N132 falls to “L” level (0 V), and P-channel MOS transistor 381 is rendered conductive. In response, nodes NA and N131 are raised to “H” level (VPP). P channel MOS transistor 383 is rendered non-conductive.

  At time t32, selection signal SELP falls to "L" level. In response to this, the selection circuit 371 selects and outputs the potential VEX. For this reason, the potential of the node NA rises to VEX.

  At time t33, selection signal SELQ is raised to “H” level. In response, N channel MOS transistor 385 is turned on and N channel MOS transistor 386 is turned off. Therefore, node N131 falls to “L” level, and P channel MOS transistor 383 is rendered conductive. At this time, P channel MOS transistor 384 is rendered conductive because its gate receives potential VPP (for example, 5.5 V) and its drain receives potential VEX (for example, 10 V). In response, output node N132 is raised to “H” level (VEX). Therefore, P channel MOS transistor 381 becomes non-conductive, and the potential of node NA is higher than the potential of “H” level (VPP) from inverter 372 by threshold voltage Vth of P channel MOS transistor 382. (VPP + Vth).

  At time t34, selection signal SELQ falls to "L" level. In response, N channel MOS transistor 385 is turned off and N channel MOS transistor 386 is turned on. Therefore, output node N132 falls to “L” level (0 V), and P-channel MOS transistor 381 is rendered conductive. In response, node NA is raised to “H” level (VEX). At this time, P channel MOS transistor 382 is rendered conductive because its gate receives potential VPP (for example, 5.5 V) and its drain receives potential VEX (for example, 10 V). Therefore, node N131 is set to “H” level, and P channel MOS transistor 383 is rendered non-conductive.

In the conventional external application selection circuit, the inverter 372 is not provided, and the gates of the P-channel MOS transistors 382 and 384 receive the external power supply potential EXVDD (for example, 1.8 V). In this case, the potential difference between the source (output node of the selection circuit 371) and the drain (node NA) of the P-channel MOS transistor 381 was large immediately before the P-channel MOS transistor 381 was turned on at time t34. In other words, N channel MOS transistor 385 is turned on and N channel MOS transistor 386 is turned off in response to selection signal SELQ being raised to “H” level at time t33. Therefore, node N131 falls to “L” level, and P channel MOS transistor 383 is rendered conductive. At this time, P channel MOS transistor 384 is rendered conductive because its gate receives potential EXVDD (for example, 1.8 V) and its drain receives potential VEX (for example, 10 V). In response, output node N132 is raised to “H” level (VEX). Therefore, P channel MOS transistor 381 is rendered non-conductive, and the potential at node NA is higher by the threshold voltage Vth of P channel MOS transistor 382 than the gate voltage level (EXVDD) of P channel MOS transistor 382 (EXVDD + Vth). ). At time t34, in response to selection signal SELQ falling to "L" level, N channel MOS transistor 386 is turned on and N channel MOS transistor 385 is turned off. Therefore, output node N132 falls to “L” level, and P channel MOS transistor 381 is rendered conductive.

  Therefore, the potential difference between the source (output node of selection circuit 371) and the drain (node NA) of P channel MOS transistor 381 at the time immediately before P channel MOS transistor 381 becomes conductive at time t34 is VEX− (EXVDD + Vth). It becomes. For example, when external power supply potential EXVDD is 1.8V and external potential VEX is 10V, the potential difference between the source (output node of selection circuit 371) and drain (node NA) of P-channel MOS transistor 381 is (8.2- Vth). Thus, at the time immediately before the P-channel MOS transistor 381 becomes conductive, the potential difference between the source (output node of the selection circuit 371) and the drain (node NA) of the P-channel MOS transistor 381 exceeds the withstand voltage level. The P channel MOS transistor sometimes deteriorated.

  However, in this embodiment, the gates of P-channel MOS transistors 382 and 384 receive the output signal of inverter 372 driven at potential VPP (for example, 5.5 V). As a result, as shown in FIG. 20, at the time immediately before the P-channel MOS transistor 381 becomes conductive at time t34, the source (output node of the selection circuit 371) and the drain (node NA) of the P-channel MOS transistor 381 are not connected. Is VEX− (VPP + Vth). For example, when the potential VPP is 5.5 V and the external potential VEX is 10 V, the potential difference between the source (output node of the selection circuit 371) and the drain (node NA) of the P-channel MOS transistor 381 is (4.5−Vth). It is. Therefore, the potential difference between the source (output node of selection circuit 371) and the drain (node NA) of P channel MOS transistor 381 is reduced at a time immediately before P channel MOS transistor 381 becomes conductive. As described above, by preventing the potential difference between the source and drain of the P channel MOS transistor from exceeding the withstand voltage level at the time immediately before the P channel MOS transistor is turned on, the P channel MOS transistor is prevented from being deteriorated. Is done.

  Returning to FIG. 18, the operation of the external application selection circuit 25 will be described next. FIG. 21 is a time chart for explaining the operation of the external application selection circuit 25. In FIG. 21, the operation of the main part 321 of the external application selection circuit 25 will be described in particular. The output potential of the external application selection circuit 25 is not directly switched from the potential VPW (from the internal operation positive pump circuit 13) to the external potential VEX (from the input terminal 21), but once to the potential VPP (for normal operation) From the positive pump circuit 11). This is because the reset circuit 30 applies the output potential (VPP) of the external application selection circuit 23 to the output node of the external application selection circuit 25 when the internal operation positive pump circuit 13 becomes inactive. Here, an operation in which the output potential of the external application selection circuit 25 is switched between the potential VPP and the external potential VEX will be described.

  In the period up to time t40, N channel MOS transistor 366 is turned off and N channel MOS transistor 367 is turned on in response to selection signal SELR at the “L” level (0 V). Therefore, node N127 is set to “L” level, and P channel MOS transistor 355 is rendered conductive. The buffer circuit 332 outputs an “L” level signal SELS in response to the “L” level selection signal SELR. P channel MOS transistor 356 is turned on in response to signal SELS at the “L” level. Therefore, node N126 is set to “H” level, and P channel MOS transistor 357 is rendered non-conductive. At this time, potential VPP (for example, 5.5 V) from reset circuit 30 is transmitted to node NB via P-channel MOS transistor 355, and the potential of node NB is set to VPP. At this time, external potential VEX from input terminal 21 is not transmitted to output node N128, and output node N128 receives potential VPP from reset circuit 30.

  At time t40, selection signal SELR is raised to “H” level (EXVDD). In response, N channel MOS transistor 366 is turned on and N channel MOS transistor 367 is turned off. Therefore, node N126 is set to “L” level, and P channel MOS transistor 357 is rendered conductive. The buffer circuit 332 outputs an “H” level (VPP) signal SELS in response to the “H” level (EXVDD) selection signal SELR. At this time, P channel MOS transistor 358 is rendered conductive because its gate receives potential VPP (for example, 5.5 V) and its drain receives potential VEX (for example, 10 V). Therefore, node N127 is set to “H” level, and P channel MOS transistor 355 is rendered non-conductive. At this time, the potential of node NB is set to a potential (VPB + Vth) that is higher by threshold voltage Vth of P channel MOS transistor 356 than potential VPP (for example, 5.5 V) received at the gate of P channel MOS transistor 356. At this time, output node N128 receives external potential VEX from input terminal 21.

  At time t41, the selection signal SELR is lowered to the “L” level (0 V). In response, N channel MOS transistor 367 is turned on and N channel MOS transistor 366 is turned off. Therefore, node N127 is set to “L” level, and P channel MOS transistor 355 is rendered conductive. The buffer circuit 332 outputs the “L” level (0 V) selection signal SELS in response to the “L” level (0 V) selection signal SELR. At this time, P channel MOS transistor 356 is rendered conductive because its gate receives selection signal SELS of “L” level (0 V) and its drain receives potential (VPP + Vth). Therefore, node N126 is set to “H” level, and P channel MOS transistor 357 is rendered non-conductive. At this time, the potential of the node NB is set to VPP. At this time, external potential VEX from input terminal 21 is not transmitted to output node N128, and output node N128 receives potential VPP from reset circuit 30.

  Conventionally, the gates of P-channel MOS transistors 342, 344, 346, 348, 352, 354, 356, and 358 are connected to a line of external power supply potential EXVDD (for example, 1.8 V). In this case, during the period from time t40 to time t41, the potential of node NB is higher than threshold voltage Vth of P channel MOS transistor 356 than potential EXVDD (eg, 1.8 V) received at the gate of P channel MOS transistor 356. Is set to a higher potential (EXVDD + Vth).

  At time t41, the selection signal SELR is lowered to the “L” level (0 V). In response, N channel MOS transistor 367 is turned on and N channel MOS transistor 366 is turned off. Therefore, node N127 is set to “L” level, and P channel MOS transistor 355 is rendered conductive.

Therefore, the potential difference between the source (output node N128) and drain (node NB) of P channel MOS transistor 355 is VEX− (EXVDD + Vth) immediately before P channel MOS transistor 355 becomes conductive at time t41. For example, when external power supply potential EXVDD is 1.8 V and potential VEX is 10 V, the potential difference between the source (output node N128) and drain (node NB) of P-channel MOS transistor 355 is (8.2-Vth). . Thus, at the time immediately before P channel MOS transistor 355 is turned on, the potential difference between the source (output node N128) and drain (node NB) of P channel MOS transistor 355 exceeds the withstand voltage level. The transistor sometimes deteriorated. This is affected by the lowering of the external power supply voltage EXVDD.

  In this embodiment, therefore, the gates of P-channel MOS transistors 342, 344, 346, and 348 receive potential VPP (for example, 5.5 V) from normal operation positive pump circuit 11, and P-channel MOS transistors 352 and 354 are supplied. , 356, 358 receive the output signal of the buffer circuit 332 driven at the potential VPP (for example, 5.5V). Thus, the potential VPP (for example, 5.5 V) that is higher than the external power supply potential EXVDD (for example, 1.8 V) and is always generated from the normal operation positive pump circuit 11 is used. However, when the potential of output node N128 is set to VPP, the gate potentials of P-channel MOS transistors 352, 354, 356, and 358 need to be lower than VPP. Therefore, the voltage level of the output signal of the buffer circuit 332 is switched by the selection signal SELR.

  Therefore, as shown in FIG. 21, the potential difference between the source (output node N128) and the drain (node NB) of the P channel MOS transistor 355 at the time immediately before the P channel MOS transistor 355 becomes conductive at time t41 is VEX- (VPP + Vth). For example, when potential VPP is 5.5V and external potential VEX is 10V, the potential difference between the source and drain of P-channel MOS transistor 355 is (4.5−Vth). Therefore, the potential difference between the source (output node N128) and the drain (node NB) of P channel MOS transistor 355 is reduced at the time immediately before P channel MOS transistor 355 is turned on. As described above, by preventing the potential difference between the source and drain of the P channel MOS transistor from exceeding the withstand voltage level at the time immediately before the P channel MOS transistor is turned on, the P channel MOS transistor is prevented from being deteriorated. Is done.

  Returning to FIG. 1, the configuration and operation of the external application selection circuits 23, 24, 26 to 28 are the same as those of the external application selection circuit 25. Therefore, the same effect can be obtained for the external application selection circuits 23, 24, and 26 to 28.

  Hereinafter, modified examples 1 to 4 of the embodiment will be described. In FIG. 22 showing the first modification, the inverter 372 in FIG. 19 is replaced with an inverter 391. In FIG. 22, an inverter 391 has its power supply terminal receiving potential VPP (for example, 5.5V) and its ground terminal receiving potential EXVDD (for example, 1.8V). The inverter 391 outputs a signal of “L” level (EXVDD) when the selection signal SELP is “H” level (EXVDD), and “H” level (when the selection signal SELP is “L” level (0V) ( VPP) signal is output.

  The operation of the circuit shown in FIG. 22 is the same as the operation of the circuit shown in FIG. 19, but the potential of the node NA is changed during the period from time t30 to time t31 with reference to the time chart shown in FIG. The difference is (EXVDD + Vth).

Therefore, in the first modification, the potential difference between the source (output node of selection circuit 371) and the drain (node NA) of P channel MOS transistor 381 is reduced immediately before P channel MOS transistor 381 is turned on. . As described above, by preventing the potential difference between the source and drain of the P channel MOS transistor from exceeding the withstand voltage level at the time immediately before the P channel MOS transistor is turned on, the P channel MOS transistor is prevented from being deteriorated. Is done.

  Note that by applying the circuit configuration shown in FIG. 22 to the external application selection circuits 23 to 28 shown in FIG. 1, the P channel MOS transistors of the external application selection circuits 23 to 28 are prevented from deteriorating.

  In FIG. 23 showing the second modification, the P-channel MOS transistors 382 and 384 in FIG. 22 are deleted, and N-channel MOS transistors 401 and 402 are added. Referring to FIG. 22, N channel MOS transistor 401 is connected between node NA and the drain of N channel MOS transistor 385. N channel MOS transistor 402 is connected between output node 132 and the drain of N channel MOS transistor 386. The gates of N channel MOS transistors 401 and 402 receive the output signal of inverter 391.

  Therefore, in the second modification, the potential difference between the source and drain of N channel MOS transistors 385 and 386 is reduced immediately before N channel MOS transistors 385 and 386 become conductive. As described above, by preventing the potential difference between the source and the drain of the N channel MOS transistor from exceeding the withstand voltage level at the time immediately before the N channel MOS transistor is turned on, the N channel MOS transistor is prevented from being deteriorated. Is done.

  In addition, by applying the circuit configuration shown in FIG. 23 to the external application selection circuits 23 to 28 shown in FIG. 1, the N channel MOS transistors of the external application selection circuits 23 to 28 are prevented from deteriorating.

  In FIG. 24 showing the third modification, the inverter 391 and the N-channel MOS transistors 401 and 402 shown in FIG. 23 are added to the circuit shown in FIG. Therefore, in Modification 3, the potential difference between the sources and drains of P channel MOS transistors 381 and 383 is reduced immediately before P channel MOS transistors 381 and 383 are turned on. As described above, by preventing the potential difference between the source and drain of the P channel MOS transistor from exceeding the withstand voltage level at the time immediately before the P channel MOS transistor is turned on, the P channel MOS transistor is prevented from being deteriorated. Is done.

  Furthermore, the potential difference between the source and drain of N channel MOS transistors 385 and 386 is reduced just before N channel MOS transistors 385 and 386 become conductive. As described above, by preventing the potential difference between the source and the drain of the N channel MOS transistor from exceeding the withstand voltage level at the time immediately before the N channel MOS transistor is turned on, the N channel MOS transistor is prevented from being deteriorated. Is done.

  Note that, by applying the circuit configuration shown in FIG. 23 to the external application selection circuits 23 to 28 shown in FIG. 1, the P channel MOS transistors and the N channel MOS transistors of the external application selection circuits 23 to 28 deteriorate. Is prevented.

  In FIG. 25 which shows the example 4 of a change, the inverter 371 of FIG. 24 is deleted. Referring to FIG. 25, the gates of P channel MOS transistors 382 and 384 and N channel MOS transistors 401 and 402 both receive the output signal of inverter 391.

  Therefore, in the fourth modification, the potential difference between the source and drain of P channel MOS transistors 381 and 383 is reduced immediately before P channel MOS transistors 381 and 383 become conductive. As described above, by preventing the potential difference between the source and drain of the P channel MOS transistor from exceeding the withstand voltage level at the time immediately before the P channel MOS transistor is turned on, the P channel MOS transistor is prevented from being deteriorated. Is done.

  Furthermore, the potential difference between the source and drain of N channel MOS transistors 385 and 386 is reduced just before N channel MOS transistors 385 and 386 become conductive. As described above, by preventing the potential difference between the source and the drain of the N channel MOS transistor from exceeding the withstand voltage level at the time immediately before the N channel MOS transistor is turned on, the N channel MOS transistor is prevented from being deteriorated. Is done.

  Note that, by applying the circuit configuration shown in FIG. 23 to the external application selection circuits 23 to 28 shown in FIG. 1, the P channel MOS transistors and the N channel MOS transistors of the external application selection circuits 23 to 28 deteriorate. Is prevented.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1,203 clock generation circuit, 2,4 reference potential generation circuit, 3 frequency dividing circuit section, 11 normal operation positive pump circuit, 12, 13 internal operation positive pump circuit, 14 drive positive pump circuit, 15-17 internal Negative pump circuit for operation, 21, 22 input terminal, 23 to 28, external application selection circuit, 29 to 33 reset circuit, 34 to 37, 60, 371 selection circuit, 38
Write circuit, 39 word line driver, 40 well driver, 41 source driver, 42 memory section, 51, 61, 181, 331, 333-336, 372, 373, 391 inverter, 52, 62 detection circuit, 53, 54, 63, 64, 204 clock driver, 55, 56, 65, 66, 205 charge pump, 57, 58, 67, 68 AND circuit, 59 frequency divider circuit, 71, 72 resistance element, 73 comparison circuit, 74 constant current source, 81 to 84, 105 to 115 switch circuit, 85, 87 P channel MOS transistor group, 86, 88 N channel MOS transistor group, 91, 92, 95, 96, 101, 103, 182, 183, 281 to 285, 341 348, 351-359, 381-384 P-channel MOS transistors, 93, 9 97, 98, 102, 104, 131-151, 184, 185, 191-200, 215, 216, 361-367, 385, 386, 401, 402 N-channel MOS transistor, 121 N-well region, 122 P-well region Upper, 123, 124 PMOS region, 125, 126 NMOS region, 161-180, 211-214, 217, 261-270, 291-294 capacitor, 201 detection circuit for active, 202 detection circuit for standby, 221, 231 P substrate 222, 232 N well, 223, 224, 233, 234 N + type region, 225 gate, 235 floating gate, 236 control gate, 241, 271 level shifter, 251 to 260 diode, 332 buffer circuit.

Claims (3)

A semiconductor device including a level conversion circuit,
When the first switching signal is at the first level, a first potential is applied to the power supply node, and when the first switching signal is at the second level, a second potential lower than the first potential is applied. A selection circuit applied to the power supply node; and when the first switching signal is at the first level, the second potential is applied to a predetermined node, and the first switching signal is at the second level. Comprises a switching circuit for applying a third potential lower than the second potential to the predetermined node;
The level conversion circuit includes:
First and second transistors of a first conductivity type, both of which have their gate electrodes connected to the predetermined node and whose first electrodes are connected to first and second output nodes, respectively;
The first electrodes are both connected to the power supply node, the second electrodes are connected to the second electrodes of the first and second transistors, respectively, and the gate electrodes are respectively connected to the second and second electrodes. The third and fourth transistors of the first conductivity type connected to the first output node, and the first electrodes thereof are both connected to a reference potential line, and the second electrodes are respectively connected to the reference potential line. Fifth and sixth fifth conductive types connected to the first and second output nodes and whose gate electrodes receive the second switching signal having the first or second level and its inverted signal, respectively. A semiconductor device including a transistor. A semiconductor device including a level conversion circuit,
When the first switching signal is at the first level, a first potential is applied to the power supply node, and when the first switching signal is at the second level, a second potential lower than the first potential is applied. A selection circuit applied to the power supply node; and when the first switching signal is at the first level, the second potential is applied to a predetermined node, and the first switching signal is at the second level. Comprises a switching circuit for applying a third potential lower than the second potential to the predetermined node;
The level conversion circuit includes:
First and second transistors of a first conductivity type, both of which have their gate electrodes connected to the predetermined node and whose first electrodes are connected to first and second output nodes, respectively;
Both of the first electrodes are connected to a reference potential line, their second electrodes are connected to the second electrodes of the first and second transistors, respectively, and their gate electrodes are connected to the first electrode, respectively. Or the third and fourth transistors of the first conductivity type that receive the second switching signal having the second level and its inverted signal, and the first electrodes thereof are both connected to the power supply node, Second electrodes of the second conductivity type are connected to the first and second output nodes, respectively, and their gate electrodes are connected to the second and first output nodes, respectively. A semiconductor device including a transistor. A semiconductor device including a level conversion circuit,
When the first switching signal is at the first level, a first potential is applied to the power supply node, and when the first switching signal is at the second level, a second potential lower than the first potential is applied. A selection circuit applied to the power supply node; and when the first switching signal is at the first level, the second potential is applied to a predetermined node, and the first switching signal is at the second level. Comprises a switching circuit for applying a third potential lower than the second potential to the predetermined node;
The level conversion circuit includes:
First and second transistors of a first conductivity type, both of which have their gate electrodes connected to the predetermined node and whose first electrodes are connected to first and second output nodes, respectively;
The first electrodes are both connected to the power supply node, the second electrodes are connected to the second electrodes of the first and second transistors, respectively, and the gate electrodes are respectively connected to the second and second electrodes. Third and fourth transistors of the first conductivity type connected to the first output node;
Fifth and sixth transistors of the second conductivity type, both having their gate electrodes connected to the predetermined node and having their first electrodes connected to the first and second output nodes, respectively; The first electrodes are both connected to a reference potential line, the second electrodes are respectively connected to the second electrodes of the fifth and sixth transistors, and the gate electrodes are respectively connected to the first electrodes. Alternatively, a semiconductor device including seventh and eighth transistors of the second conductivity type that receive the second switching signal having the second level and its inverted signal.

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