JP2009158710A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device including a transistor which is formed in an SOI layer of an SOI substrate and has excellent transistor characteristics even when the SOI layer is isolated by an element isolation region. <P>SOLUTION: A polysilicon gate 11g, which is formed even on a silicon oxide film 9 and subjected to planarization processing and patterning processing, is silicide-processed from its surface to obtain a silicide region 18g. The silicide region 18g is formed extending from the surface of the polysilicon gate 11g along the depth, so the polysilicon gate 11g is all the silicide region 18g on the silicon oxide film 9. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device including a transistor formed over an SOI substrate.

  71 to 85 are cross-sectional views showing a conventional manufacturing method of a semiconductor device including a MOS transistor formed on an SOI substrate. Hereinafter, a conventional method for manufacturing a semiconductor device will be described with reference to these drawings.

  First, as shown in FIG. 71, a silicon oxide film 104 and a silicon nitride film 105 are sequentially formed on an SOI layer 103 of an SOI substrate including a silicon support substrate 101, a buried oxide film 102, and an SOI layer 103. Thereafter, a resist film is applied over the entire surface, and a resist pattern 106 for forming a trench is formed by photolithography (photolithography).

  Next, as shown in FIG. 72, the silicon nitride film 105, the silicon oxide film 104, and the SOI layer 103 are etched by using a resist pattern 106 for trench formation (not shown in FIG. 72) as a mask to perform trench opening 107. Form. At this time, the remaining SOI layer 103a which is a part of the SOI layer 103 is left below the bottom surface of the trench opening 107 (partial trench isolation).

  Thereafter, as shown in FIG. 73, the inner wall of the trench is oxidized (film thickness: 50 nm or less) to form an oxide film 108 on the side surface of the SOI layer 103 in the trench opening 107 and on the surface of the remaining SOI layer 103a. Thereafter, if necessary, a photographic process and an etching process are added, and the oxide film 108 as the inner wall oxide film and the remaining SOI layer 103a are etched until the buried oxide film 102 is reached, thereby forming an opening for a complete separation portion. You may do it.

  Subsequently, as shown in FIG. 74, a silicon oxide film 109 is formed on the entire surface, and baking is performed by annealing at 500 ° C. to 1300 ° C. This annealing may be omitted.

  Then, as a pretreatment for planarization, a resist film is applied on the entire surface, an etching resist pattern is formed by photolithography, and etching is performed. This pre-processing is performed to selectively pre-etch only a large area portion (difficult to perform CMP (Chemical Mechanical Polishing)) where the pattern of the silicon oxide film 109 is formed relatively large.

  Thereafter, as shown in FIG. 75, the silicon oxide film 109 is subjected to a CMP process using the silicon nitride film 105 as a stopper, and the silicon oxide film 109 is planarized.

  Next, as shown in FIG. 76, after removing the silicon nitride film 105, impurity implantation for channel region formation is performed on the SOI layer 103, and then the silicon oxide film 104 is removed.

  Subsequently, as shown in FIG. 77, a gate insulating film 110 is formed on the SOI layer 103, and a polysilicon film 111 for a gate electrode is formed on the entire surface.

  Then, a resist pattern (not shown) for etching is formed by photolithography, and as shown in FIG. 78, patterning is performed by etching using the resist pattern as a mask to obtain a polysilicon gate 111g. As shown in 79, the gate insulating film 110 is patterned to obtain a gate insulating film 110g.

  Thereafter, as shown in FIG. 80, a silicon oxide film spacer 112 is formed on the side surface of the polysilicon gate 111g. Subsequently, using the polysilicon gate 111g and the silicon oxide film 112 as a mask, the Ext portion impurity 113 and the pocket impurity 114 are sequentially implanted and diffused into the SOI layer 3 to diffuse the Ext portion (extension region) and the Pck portion (pocket region). )

  Next, as shown in FIG. 81, a sidewall silicon oxide film 115 and a sidewall silicon nitride film 116 are sequentially formed on the side surface of the silicon oxide film 112. A sidewall portion is constituted by the sidewall silicon oxide film 115 and the sidewall silicon nitride film 116. Subsequently, using the polysilicon gate 111g, the silicon oxide film 112, and the sidewall portion as a mask, an S / D portion impurity 117 is implanted and diffused to obtain an S / D portion (source / drain region). At this time, the Ext part and the Pck part are also determined. For the convenience of explanation, illustration of accurate formation positions in the SOI layer 3 of the S / D portion, the Ext portion, and the Pck portion is omitted. The same applies to the subsequent figures.

  Thereafter, as shown in FIG. 82, silicide regions 118s and silicide regions are formed in and on the surface of the S / D portion and on the surface and on the surface of the polysilicon gate 11g in order to reduce resistance after annealing. 118g is formed.

  Subsequently, as shown in FIG. 83, a liner nitride film 119 and an interlayer insulating film 120 are formed on the entire surface, and the interlayer insulating film 120 is planarized by CMP treatment.

  Then, an etching resist pattern (not shown) is formed by photolithography, and after contact holes are formed by etching, contact plugs 121 are formed in the contact holes as shown in FIG.

  Finally, a metal layer is formed on the entire surface, an etching resist pattern (not shown) is formed by photolithography, and then the metal wiring 122 is patterned using the resist pattern as a mask, as shown in FIG.

  For example, Patent Document 1 discloses a method for manufacturing a semiconductor device in which a MOS transistor is formed while element isolation is performed on an SOI substrate.

JP 2003-115592 A

  As described above, a semiconductor device having a MOS transistor on an SOI substrate is manufactured by a conventional method for manufacturing a semiconductor device.

  86 to 88 are explanatory views for explaining problems caused by a conventional method for manufacturing a semiconductor device. As shown in FIG. 86, the silicon oxide film 109, which is an isolation oxide film, is formed so as to protrude from the surface of the SOI layer 103 by a step of st19. Therefore, in the polysilicon film 111, on the silicon oxide film 109 and the SOI layer 103. As a result of the formation of the step st11 (the protruding height of the silicon oxide film 109 from the surface of the SOI layer 103) between the gate insulating film 110 and the gate insulating film 110, the polysilicon film 111 has a recess on the gate insulating film 110. Will have.

  As described above, when an organic BARC having a low viscosity is applied as an antireflection film on the polysilicon film 111 having the recess due to the step st11 (st19), the organic BARC region 123 is accumulated in the recess of the polysilicon film 111. That is, the organic BARC region 123 exists locally.

  Therefore, when the resist 124 is patterned, the size and shape of the resist 124 vary due to the influence of the organic BARC region 123. Therefore, the pattern accuracy of the polysilicon gate 111g patterned using the resist 124 as a mask is degraded. There was a problem.

  In addition, when the polysilicon film 111 is patterned with the resist 124, the second problem that the patterning accuracy for the polysilicon film 111 deteriorates and the shape of the polysilicon gate 111g varies due to the organic BARC region 123 on the upper side. There was a point.

  Also, as shown in FIGS. 87 and 88, when the level difference st11 is high when the polysilicon film 111 is formed, the film thickness tb of the polysilicon film 111 in the isolation edge gate region 125 is larger than the film thickness ta in other regions. Become thicker. In addition, the CC cross section of FIG. 87 becomes FIG. As a result, after the etching for obtaining the polysilicon gate 111g, the gate size of the isolation edge gate region 125 becomes thicker than that at the time of design, resulting in a third problem that the operating characteristics of the MOS transistor are deteriorated.

  The present invention has been made to solve the above first to third problems. Even if the SOI layer in the SOI substrate is separated by the element isolation region, the transistor characteristics are excellent as a transistor formed in the SOI layer. An object is to obtain a method for manufacturing a semiconductor device including a transistor having the transistor.

  According to one embodiment of the present invention, the CMP process is performed from the surface of the polysilicon film formed as the gate material to flatten the surface of the polysilicon film. Then, the polysilicon film is patterned to obtain a polysilicon gate partly existing on the silicon oxide film constituting the partial isolation region. Thereafter, the polysilicon gate is silicided from the surface to form a silicide region. At this time, the silicide region is formed in the entire region of the polysilicon gate on the silicon oxide film.

  According to this embodiment, all the polysilicon gates on the silicon oxide film are formed by the silicide region, so that the good body potential can be fixed through the remaining SOI layer below the silicon oxide film. However, there is an effect that a good transistor can be obtained.

<Embodiment 1>
(General manufacturing process)
1 to 15 are sectional views showing a method for manufacturing a semiconductor device including a MOS transistor formed on an SOI substrate according to the first embodiment of the present invention. Hereinafter, the manufacturing process contents of the embodiment will be described with reference to these drawings.

  First, as shown in FIG. 1, a silicon oxide film 4 and a silicon nitride film 5 are sequentially formed on an SOI layer 3 of an SOI substrate including a silicon support substrate 1, a buried oxide film 2, and an SOI layer 3. Thereafter, a resist film is applied to the entire surface, and a resist pattern 6 for forming a trench is formed by photolithography.

  Next, as shown in FIG. 2, the silicon nitride film 5, the silicon oxide film 4 and the SOI layer 3 are etched using the resist pattern 6 for trench formation as a mask to form a trench opening 7. At this time, the remaining SOI layer 3a which is a part of the SOI layer 3 is left below the bottom surface of the trench opening 7 (partial trench isolation).

  Thereafter, as shown in FIG. 3, the inner wall of the trench is oxidized (film thickness: 50 nm or less), and an oxide film 8 is formed on the side surface of the SOI layer 3 in the trench opening 7 and on the surface of the remaining SOI layer 3a. Thereafter, if necessary, a photographic process and an etching process may be added, and the oxide film 8 as the inner wall oxide film and the remaining SOI layer 3a may be etched until the buried oxide film 2 is reached to form a complete separation portion. .

  Subsequently, as shown in FIG. 4, a silicon oxide film 9 is formed on the entire surface, and baking is performed by annealing at 500 ° C. to 1300 ° C. This annealing may be omitted.

  Then, as a pretreatment for planarization, a resist film is applied on the entire surface, an etching resist pattern is formed by photolithography, and etching is performed. This pretreatment is performed in order to selectively pre-etch only a large area portion (which is difficult to undergo CMP treatment) where the pattern of the silicon oxide film 9 is formed relatively large.

  Thereafter, as shown in FIG. 5, the silicon oxide film 9 is subjected to a CMP process using the silicon nitride film 5 as a stopper, and the silicon oxide film 9 is planarized. As a result, the remaining silicon oxide film 9 (oxide film 8) becomes a partial insulating film. Then, a partial isolation region for element isolation is formed by the remaining SOI layer 3a under the silicon oxide film 9 and the silicon oxide film 9.

  Next, as shown in FIG. 6, the silicon nitride film 5 is removed, and then an impurity implantation for forming a channel region is performed on the SOI layer 3, and then the silicon oxide film 4 is removed. As shown in FIG. 6, the silicon oxide film 9 is formed to protrude from the surface of the SOI layer 3 by a step st9 (predetermined step).

  Subsequently, as shown in FIG. 7, a gate insulating film 10 such as a silicon oxide film is formed on the SOI layer 3, and a polysilicon film 11 for a gate electrode is formed on the entire surface. At this time, the polysilicon film 11 is formed flat without any step on the surface between the SOI layer 3 and the silicon oxide film 9 by a planarization process on the polysilicon film 11 described in detail later.

  Then, a resist pattern (not shown) for etching is formed by photolithography, and patterning is performed by etching using the resist pattern as a mask to obtain a polysilicon gate 11g, as shown in FIG. As shown in FIG. 9, the gate insulating film 10 is patterned to obtain a gate insulating film 10g.

  Thereafter, as shown in FIG. 10, a silicon oxide film spacer 12 is formed on the side surface of the polysilicon gate 11g. Subsequently, using the polysilicon gate 11g and the silicon oxide film 12 as a mask, the Ext portion impurity 13 and the pocket impurity 14 are sequentially implanted and diffused into the SOI layer 3 to obtain an Ext portion and a Pck portion.

  Next, as shown in FIG. 11, a sidewall silicon oxide film 15 and a sidewall silicon nitride film 16 are sequentially formed on the side surface of the silicon oxide film 12. A sidewall portion is constituted by the sidewall silicon oxide film 15 and the sidewall silicon nitride film 16. Subsequently, using the polysilicon gate 11g, the silicon oxide film 12 and the sidewall portion as a mask, an S / D portion impurity 17 is implanted and diffused to obtain an S / D portion (source / drain region). At this time, the Ext part and the Pck part are also determined. For the convenience of explanation, illustration of accurate formation positions in the SOI layer 3 of the S / D portion, the Ext portion, and the Pck portion is omitted. The same applies to the subsequent figures.

  Thereafter, as shown in FIG. 12, silicide regions 18s and silicide regions are formed in and on the surface of the S / D portion and in the surface and on the surface of the polysilicon gate 1g in order to reduce the resistance after annealing. 18 g is formed. The silicide region 18g and the silicide region 18s are formed by silicidation from the surface to the inside of the polysilicon film 11 and the S / D part.

  As a result, a MOS transistor having the S / D portion (silicide region 18s), the Ext portion, the gate insulating film 10g, and the polysilicon gate 11g (silicide region 18g) as main parts is completed. This MOS transistor is isolated by a partial isolation region composed of a silicon oxide film 9 (oxide film 8) and a remaining SOI layer 3a below the silicon oxide film 9.

  The silicide region 18g is formed on the silicon oxide film 9 at a depth reaching the silicon oxide film 9, as will be described later. As a result, the silicide region 18g is formed in the entire region of the polysilicon gate 11g on the silicon oxide film 9.

  Subsequently, as shown in FIG. 13, a liner nitride film 19 and an interlayer insulating film 20 are sequentially formed on the entire surface, and the interlayer insulating film 20 is planarized by CMP processing.

  Then, an etching resist pattern (not shown) is formed by photolithography, and after contact holes are formed by etching, contact plugs 21 are formed in the contact holes as shown in FIG.

  Finally, a metal layer is formed on the entire surface, an etching resist pattern (not shown) is formed by photolithography, and then the metal wiring 22 is patterned using the resist pattern as a mask as shown in FIG.

(Planarization process for the polysilicon film 11)
16 to 20 are cross-sectional views showing a manufacturing process of planarization processing for the polysilicon film 11 according to the first embodiment (hereinafter sometimes abbreviated as “polysilicon planarization processing”). These drawings correspond to the steps shown in FIGS. 7 to 9 in the general steps shown in FIGS. The details of the polysilicon planarization process according to the first embodiment will be described below with reference to FIGS.

  First, as shown in FIG. 16, a polysilicon film 11 ((first) gate electrode material layer) is formed on the entire surface with a step st9 of the silicon oxide film 9 and a thickness larger than the target thickness. At this time, a step st1 is formed between the SOI layer 3 and the silicon oxide film 9 reflecting the step st9 of the silicon oxide film 9.

  Then, as shown in FIG. 17, the polysilicon film 11 is subjected to a CMP process for a predetermined time, thereby planarizing the surface of the polysilicon film 11 and eliminating the step st1.

  At this time, the polysilicon film 11 on the silicon oxide film 9 is not completely removed, and the predetermined time is set as the time for setting the polysilicon film 11 as the target film thickness. A polysilicon film 11 can be obtained.

  Note that it is desirable to confirm whether or not the polysilicon film 11 has reached the target film thickness by measuring the film thicknesses of the polysilicon film 11 on the gate insulating film 10 and the silicon oxide film 9 after the CMP process. .

  Next, as shown in FIG. 18, an impurity 31 for gate injection is implanted into the polysilicon film 11 to make the polysilicon film 11 have a predetermined conductivity type. Note that the gate implantation impurity 31 is appropriately determined depending on the MOS type (PMOS, NMOS).

  Next, as shown in FIG. 19, a resist 32 is applied on the polysilicon film 11 whose surface is flattened and patterned.

  Then, as shown in FIG. 20, using the patterned resist 32 (not shown in FIG. 20) as a mask, the polysilicon film 11 and the gate insulating film 10 are sequentially etched to form the polysilicon gate 11g and the gate insulating film 10g. obtain.

  FIG. 21 is a plan view showing a planar configuration of a semiconductor device manufactured by the semiconductor device manufacturing method of the first embodiment. As shown in the figure, the silicon oxide film 9 is formed across the figure at predetermined intervals, thereby isolating the SOI layer 3 between the silicon oxide films 9 and 9 from the outside. In practice, the silicon oxide film 9 is vertically formed in the drawing at predetermined intervals in the same manner, but the illustration is omitted for convenience of explanation.

  On the other hand, the silicon oxide film 9 and the SOI layer 3 are vertically cut in the drawing to form a polysilicon gate 11g. The AA cross section of FIG. 21 becomes FIG. Moreover, the BB cross section of FIG. 21 becomes FIG. FIG. 9 shows the case where the silicon oxide film 9 exists on the extended line of the BB cross section in FIG.

  Thus, the surface of the polysilicon film 11 can be planarized by the polysilicon planarization process according to the first embodiment. Therefore, since the foreign matter such as organic BARC which becomes an antireflection film does not accumulate in the recess, the first and second problems described above do not occur, so that the resist for forming the polysilicon gate (resist 32 in FIG. 19). Equivalent) The pattern accuracy of the polysilicon gate 11g can be improved without causing variations in dimensions and shape during patterning.

  Further, since the polysilicon film 11 in the isolation edge gate region is not thicker than other regions and the above third problem does not occur, the isolation edge after gate etching using the resist is not caused. It is possible to reduce the size variation and shape variation (see FIGS. 87 and 88) of the polysilicon gate 11g including the thickness of the portion.

  Thus, a MOS transistor having good transistor characteristics can be obtained by the polysilicon planarization process according to the first embodiment.

  FIG. 22 is a plan view schematically showing the planar shape of the polysilicon gate 11g after obtaining the polysilicon gate 11g. As shown in the figure, as a result of planarizing the polysilicon film 11 by the above-described polysilicon planarization process, the thickness of the polysilicon film 11 on the silicon oxide film 9 becomes thinner than other regions. The gate vicinity region 30 is not etched quickly and tends to have a tapered planar shape.

(Process for forming silicide region 18g)
FIG. 23 is a cross-sectional view showing another cross-section showing the formation process of the silicide region shown in FIG. 12 in the general processing shown in FIGS. This section corresponds to the section AA in FIG.

  As shown in the figure, the silicide region 18g is formed extending in the depth direction from the surface of the polysilicon gate 11g, and the entire surface of the silicon oxide film 9 becomes the silicide region 18g.

  FIG. 24 is a sectional view showing a sectional structure including the body potential fixing portion. As shown in the figure, a body fixing region 3b is provided adjacent to the remaining SOI layer 3a formed under the silicon oxide film 9 which is a partial insulating film. Body contact region 3c is formed in the upper layer portion of body fixing region 3b. By applying a predetermined body potential to body contact region 3c, the body potential of the body region which is SOI layer 3 under polysilicon gate 11g can be set via body fixing region 3b and remaining SOI layer 3a. it can.

  Thus, the remaining SOI layer 3a constituting the partial isolation region plays an important role as an electrical connection means for setting the body potential. However, when a gate voltage is applied to the polysilicon gate 11g and depletion occurs in the remaining SOI layer 3a, the resistance is increased and the body potential setting is hindered.

Therefore, it is desirable that the voltage VS applied to the partial insulating film (silicon oxide film 9) under the polysilicon gate 11g is small. Generally, the voltage VB applied to the partial insulating film is determined by the following formula (1), where the gate voltage is VG and the flat band voltage is VFB.
VB = VG + VFB (1)

  On the other hand, in the flat band voltage VFB, when the isolation region is entirely the silicide region 18g as in the first embodiment (first flat band voltage VFB1), polysilicon remains in a part of the isolation region. (Second flat band voltage VFB2).

  Since the work function of silicide is near the mid gap (0.46 eV) and smaller than polysilicon, the first flat band voltage VFB1 is smaller than the second flat band voltage VFB2. Therefore, as apparent from the equation (1), by suppressing the voltage VB applied to the partial insulating film, the depletion layer width of the remaining SOI layer 3a is reduced, and the increase in resistance of the remaining SOI layer 3a is effectively suppressed. There is an effect that can.

  As a result, by forming the polysilicon gate 11g on the silicon oxide film 9 which is a partial insulating film by the silicide region 18g by the method for manufacturing the semiconductor device of the first embodiment, it is possible to achieve good body potential fixation. There is an effect that a MOS transistor having good transistor characteristics can be obtained.

  FIG. 25 is a plan view showing a planar structure after obtaining the silicide regions 18s and 18g. As shown in the figure, a silicide region 18s is formed in the surface of the SOI layer 3, and a silicide region 18g is formed in the surface of the polysilicon gate 11g. Then, a silicon oxide film 12 is formed around the silicide region 18g (polysilicon gate 11g), and a sidewall silicon nitride film 16 (sidewall silicon oxide film 15) is formed around the silicon oxide film 12.

<Embodiment 2>
(Polysilicon planarization)
26 to 30 are cross-sectional views showing a polysilicon planarization process in the method of manufacturing a semiconductor device according to the second embodiment. These drawings correspond to the steps shown in FIGS. 7 to 9 in the general steps shown in the first embodiment. The contents of the polysilicon planarization process according to the second embodiment will be described below with reference to FIGS.

  First, as shown in FIG. 26, a polysilicon film 11 is formed on the entire surface. At this time, a step st2 is formed between the SOI layer 3 and the silicon oxide film 9 reflecting the step st9. The polysilicon film 11 is formed with a thickness larger than the step st9 of the silicon oxide film 9.

  Then, as shown in FIG. 27, the time-determined CMP process for the polysilicon film 11 is performed for a predetermined time, thereby flattening the surface of the polysilicon film 11 and eliminating the step st2. The predetermined time is set to a time during which all the polysilicon film 11 on the silicon oxide film 9 is not removed.

  Next, as shown in FIG. 28, an additional polysilicon layer 23 (second gate electrode material layer) is further deposited on the polysilicon film 11. The film thickness of the additional polysilicon layer 23 is set to a film thickness that makes the target film thickness the sum of the film thicknesses of the polysilicon film 11 and the additional polysilicon layer 23. Thereafter, an impurity 31 for gate implantation is implanted to make the polysilicon film 11 and the additional polysilicon layer 23 have a predetermined conductivity type.

  Before forming the additional polysilicon layer 23 after the CMP process, the film thicknesses of the polysilicon films 11 on the gate insulating film 10 and the silicon oxide film 9 are measured, and the measurement result is achieved to achieve the target film thickness. It is desirable to determine the thickness of the additional polysilicon layer 23 based on the above.

  Next, as shown in FIG. 29, a resist 32 is applied on the additional polysilicon layer 23 and patterned.

  Then, as shown in FIG. 30, the polysilicon film 11, the additional polysilicon layer 23, and the gate insulating film 10 are etched using the patterned resist 32 (not shown in FIG. 30) as a mask, so that the polysilicon gate 11g and A gate insulating film 10g is obtained.

  The cross-sectional structures shown in FIGS. 26 to 30 correspond to the AA cross section of FIG. 21 shown in the first embodiment.

(effect)
As described above, by planarizing the surface of the polysilicon film 11 by the polysilicon planarization process according to the second embodiment, a MOS transistor having good transistor characteristics can be obtained as in the first embodiment.

  Further, since the additional polysilicon layer 23 is deposited after the CMP process on the polysilicon film 11, a desired target film thickness can be achieved while compensating for the decrease in the film thickness of the polysilicon film 11 due to the CMP process. At this time, by measuring the film thickness of the polysilicon film 11 after the CMP process, the film thickness of the additional polysilicon layer 23 that satisfies the target film thickness can be accurately recognized.

  In the method of manufacturing the semiconductor device according to the second embodiment, the silicide region 18g is formed on the silicon oxide film 9 without the polysilicon region, as in the first embodiment. Therefore, by the method for manufacturing the semiconductor device of the second embodiment, a good body potential can be fixed as in the first embodiment, so that a MOS transistor having good transistor characteristics can be obtained.

  Further, the polysilicon film 11 manufactured by the method for manufacturing a semiconductor device of the second embodiment tends to have a tapered planar shape in the gate region 30 near the isolation region (see FIG. 22).

<Embodiment 3>
(Polysilicon planarization)
31 to 35 are cross-sectional views showing a polysilicon planarization process in the semiconductor device manufacturing method of the third embodiment. These drawings correspond to the steps shown in FIGS. 7 to 9 in the general steps shown in the first embodiment. The details of the polysilicon planarization process according to the third embodiment will be described below with reference to FIGS.

  First, as shown in FIG. 31, a polysilicon film 11 is formed on the entire surface. At this time, a step st2 is formed between the SOI layer 3 and the silicon oxide film 9 reflecting the step st9. The polysilicon film 11 is formed with a thickness larger than the step st9 of the silicon oxide film 9.

  Then, as shown in FIG. 32, the CMP process for the polysilicon film 11 is performed using the silicon oxide film 9 as a stopper (the termination is detected by the silicon oxide film 9), so that the surface of the polysilicon film 11 is covered with the silicon oxide film 9. The level difference st2 is eliminated by flattening at the formation height.

  Next, as shown in FIG. 33, an additional polysilicon layer 23 is further deposited on the polysilicon film 11. The film thickness of the additional polysilicon layer 23 is set to a film thickness at which the sum of the film thicknesses of the polysilicon film 11 and the additional polysilicon layer 23 becomes a target film thickness. Thereafter, an impurity 31 for gate implantation is implanted to make the polysilicon film 11 and the additional polysilicon layer 23 have a predetermined conductivity type.

  Before forming the additional polysilicon layer 23 after the CMP process, the thickness of the polysilicon film 11 on the gate insulating film 10 is measured, and the thickness of the additional polysilicon layer 23 is determined based on the measurement result. desirable.

  Next, as shown in FIG. 34, a resist 32 is applied on the additional polysilicon layer 23 and patterned.

  Then, as shown in FIG. 35, the polysilicon film 11, the additional polysilicon layer 23, and the gate insulating film 10 are etched using the patterned resist 32 (not shown in FIG. 35) as a mask, so that the polysilicon gate 11g and A gate insulating film 10g is obtained.

  The cross-sectional structure shown in FIGS. 31 to 35 corresponds to the AA cross section of FIG. 21 shown in the first embodiment.

(effect)
As described above, by planarizing the surface of the polysilicon film 11 by the polysilicon planarization process according to the third embodiment, a MOS transistor having good transistor characteristics can be obtained as in the first embodiment.

  Furthermore, in the method of manufacturing the semiconductor device according to the third embodiment, since the polysilicon film 11 is planarized by the stopper CMP process using the silicon oxide film 9 as a stopper, the amount of cutting during the CMP process is performed with good controllability. Can do. As a result, since the additional polysilicon layer 23 can be deposited with good film thickness controllability, the resultant film thickness of the finally obtained polysilicon film 11 and additional polysilicon layer 23 can be easily controlled. .

  In the method of manufacturing the semiconductor device according to the third embodiment, the silicide region 18g is formed on the silicon oxide film 9 without the polysilicon region as in the first embodiment. Therefore, by the method for manufacturing the semiconductor device of the third embodiment, a good body potential can be fixed as in the first embodiment, so that a MOS transistor having good transistor characteristics can be obtained.

  Further, the polysilicon film 11 manufactured by the method for manufacturing a semiconductor device of the third embodiment tends to have a tapered planar shape in the gate region 30 near the isolation region (see FIG. 22).

<Embodiment 4>
(Polysilicon planarization)
36 to 40 are cross-sectional views showing a polysilicon planarization process in the semiconductor device manufacturing method of the fourth embodiment. These drawings correspond to the steps shown in FIGS. 7 to 9 in the general steps shown in the first embodiment. The details of the polysilicon planarization process according to the fourth embodiment will be described below with reference to FIGS.

  First, as shown in FIG. 36, a polysilicon film 11 made of polysilicon (first material) is formed on the entire surface. At this time, a step st3 is formed between the SOI layer 3 and the silicon oxide film 9 reflecting the step st9. The polysilicon film 11 is formed thicker than the step st9 of the silicon oxide film 9.

  Then, as shown in FIG. 37, the concave portion of the polysilicon film 11 caused by the step st3 is embedded with a resist 27 (embedded region). The resist 27 has a material (second material) that a general resist material has. Note that organic BARC may be used as the resist 27.

  Next, as shown in FIG. 38, a region having a depth corresponding to the thickness of the resist 27 from the surface of the polysilicon film 11 is set as a removal target polysilicon region 11r. Then, the resist 27 and the removal target polysilicon region 11r are removed from the surface to the depth direction by dry etching.

  As the dry etching, the resist 27 and the removal target polysilicon region 11r are simultaneously removed at the same depth by performing etching with a small selection ratio between the resist 27 and the removal target polysilicon region 11r, such as using a sputtering method. be able to. As a result, the surface of the remaining polysilicon film 11 can be planarized.

  The polysilicon film 11 reached the target film thickness by measuring the thickness of the polysilicon film 11 on the gate insulating film 10 and the silicon oxide film 9 after the removal of the resist 27 and the target polysilicon region 11r. It is desirable to check whether or not.

  Next, as shown in FIG. 39, a gate implantation impurity 31 is implanted into the polysilicon film 11 after the removal of the resist 27 and the removal target polysilicon region 11r, so that the polysilicon film 11 has a predetermined conductivity type. .

  Next, as shown in FIG. 40, the polysilicon film 11 and the gate insulating film 10 are etched using a patterned resist (not shown in FIG. 40) as a mask to obtain a polysilicon gate 11g and a gate insulating film 10g. .

  The cross-sectional structure shown in FIGS. 36 to 40 corresponds to the AA cross section of FIG. 21 shown in the first embodiment.

(effect)
As described above, by planarizing the surface of the polysilicon film 11 by the polysilicon planarization process according to the fourth embodiment, a MOS transistor having good transistor characteristics can be obtained as in the first embodiment.

  In the method of manufacturing the semiconductor device according to the fourth embodiment, the silicide region 18g is formed on the silicon oxide film 9 without the polysilicon region, as in the first embodiment. Therefore, by the method for manufacturing a semiconductor device of the fourth embodiment, a good body potential can be fixed as in the first embodiment, so that a MOS transistor having good transistor characteristics can be obtained.

  Further, the polysilicon film 11 manufactured by the method for manufacturing a semiconductor device of the fourth embodiment tends to have a tapered planar shape in the gate region 30 near the isolation region (see FIG. 22).

<Embodiment 5>
(Polysilicon planarization)
41 to 45 are cross-sectional views showing a polysilicon planarization process in the semiconductor device manufacturing method of the fifth embodiment. These drawings correspond to the steps shown in FIGS. 7 to 9 in the general steps shown in the first embodiment. The details of the polysilicon planarization process according to the fifth embodiment will be described below with reference to FIGS.

  First, as shown in FIG. 41, a polysilicon film 11 made of polysilicon (first material) is formed on the entire surface. At this time, a step st3 is formed between the SOI layer 3 and the silicon oxide film 9 reflecting the step st9. Note that the polysilicon film 11 is formed to be thicker than the step st9.

  Then, as shown in FIG. 42, the recess of the polysilicon film 11 caused by the step st3 is filled with a resist 27. The resist 27 has a material (second material) that a general resist material has. Note that organic BARC may be used as the resist 27.

  Next, as shown in FIG. 43, the recess portion of the polysilicon film 11 in the polysilicon film 11, that is, the portion existing at the formation height corresponding to the film thickness of the resist 27 is defined as the amorphization target polysilicon region 11a. . Then, Si or Ge is implanted into the resist 27 and the amorphization target polysilicon region 11a with low energy, and the amorphization target polysilicon region 11a is amorphized (changed to a fourth material).

  Note that the amorphization target polysilicon region 11 a can be formed at the same depth as the bottom surface of the resist 27 by adjusting the implantation energy of Si or the like.

  Next, as shown in FIG. 44, the resist 27 is removed, and the amorphized polysilicon region 11a that has been amorphized by immersing in an alkaline aqueous solution or the like is removed. In the polysilicon film 11, since the amorphous region to be amorphousized 11a and the non-amorphous region are made of different materials and the etching rate with respect to the alkaline aqueous solution is greatly different, only the amorphous region to be amorphous region 11a is selectively selected. Can be removed.

  43 and 44, the formation depth of the amorphization target polysilicon region 11a is set to the same level as the bottom surface of the resist 27, and the resist 27 and the amorphization target polysilicon region 11a are each selectively removed with high accuracy. can do. As a result, the surface of the polysilicon film 11 after removing the resist 27 and the amorphization target polysilicon region 11a can be flattened with high accuracy.

  The polysilicon film 11 reaches the target film thickness by measuring the film thicknesses of the polysilicon film 11 on the gate insulating film 10 and on the silicon oxide film 9 after removing the resist 27 and the amorphization target polysilicon region 11a. It is desirable to confirm whether or not

  Thereafter, an impurity 31 for gate injection is implanted into the polysilicon film 11 after the removal of the resist 27 and the amorphization target polysilicon region 11a, so that the polysilicon film 11 has a predetermined conductivity type.

  Next, as shown in FIG. 45, the polysilicon film 11 and the gate insulating film 10 are etched using a patterned resist (not shown in FIG. 45) as a mask to obtain the polysilicon gate 11g and the gate insulating film 10g. .

  The cross-sectional structure shown in FIGS. 41 to 45 corresponds to the AA cross section of FIG. 21 shown in the first embodiment.

(effect)
In this way, by planarizing the surface of the polysilicon film 11 by the polysilicon planarization process according to the fifth embodiment, a MOS transistor having good transistor characteristics can be obtained as in the first embodiment.

  In the method of manufacturing the semiconductor device according to the fifth embodiment, the silicide region 18g is formed on the silicon oxide film 9 without the polysilicon region, as in the first embodiment. Therefore, by the method for manufacturing the semiconductor device of the fifth embodiment, a good body potential can be fixed as in the first embodiment, so that a MOS transistor having good transistor characteristics can be obtained.

  Further, the polysilicon film 11 manufactured by the semiconductor device manufacturing method of the fifth embodiment tends to have a tapered planar shape in the gate vicinity region 30 on the isolation region (see FIG. 22).

<Embodiment 6>
(Polysilicon planarization)
46 to 50 are cross-sectional views showing a polysilicon planarization process in the semiconductor device manufacturing method of the sixth embodiment. These drawings correspond to the steps shown in FIGS. 7 to 9 in the general steps shown in the first embodiment. The details of the polysilicon planarization process of the fifth embodiment will be described below with reference to FIGS.

  First, as shown in FIG. 46, a polysilicon film 11 is formed on the entire surface. At this time, a step st2 is formed between the SOI layer 3 and the silicon oxide film 9 reflecting the step st9. Note that the polysilicon film 11 is formed to be thicker than the step st9.

  As shown in FIG. 47, the polysilicon film 11 can be subjected to hydrogen annealing at a high temperature of 400 ° C. to 1300 ° C. to flatten the surface of the polysilicon film 11 and reduce the step st2.

  Note that it is possible to confirm whether or not the polysilicon film 11 has reached the target film thickness by measuring the film thicknesses of the polysilicon film 11 on the gate insulating film 10 and the silicon oxide film 9 after the hydrogen annealing treatment. desirable.

  Next, as shown in FIG. 48, an impurity 31 for gate implantation is implanted to make the polysilicon film 11 have a predetermined conductivity type.

  Subsequently, as shown in FIG. 49, a resist 32 is applied on the polysilicon film 11 and patterned.

  Then, as shown in FIG. 50, the polysilicon film 11 and the gate insulating film 10 are etched using the patterned resist 32 (not shown in FIG. 50) as a mask to obtain the polysilicon gate 11g and the gate insulating film 10g. .

  46 to 50 correspond to the AA cross section of FIG. 21 shown in the first embodiment.

(effect)
In this way, by planarizing the surface of the polysilicon film 11 by the polysilicon planarization process according to the sixth embodiment, a MOS transistor having good transistor characteristics can be obtained as in the first embodiment.

  In the method of manufacturing the semiconductor device according to the sixth embodiment, the silicide region 18g is formed on the silicon oxide film 9 without the polysilicon region as in the first embodiment. Therefore, by the method for manufacturing the semiconductor device of the sixth embodiment, a good body potential can be fixed as in the first embodiment, so that a MOS transistor having good transistor characteristics can be obtained.

  Further, the polysilicon film 11 manufactured by the method for manufacturing a semiconductor device of the sixth embodiment tends to have a tapered planar shape in the gate region 30 near the isolation region (see FIG. 22).

<Embodiment 7>
(Polysilicon planarization)
51 to 55 are cross-sectional views showing a polysilicon planarization process in the semiconductor device manufacturing method of the seventh embodiment. These drawings correspond to the steps shown in FIGS. 7 to 9 in the general steps shown in the first embodiment. The details of the polysilicon planarization process according to the seventh embodiment will be described below with reference to FIGS.

  First, as shown in FIG. 51, a polysilicon film 11 is formed on the entire surface. At this time, a step st2 is formed between the SOI layer 3 and the silicon oxide film 9 reflecting the step st9. Note that the polysilicon film 11 is formed to be thicker than the step st9.

  Then, as shown in FIG. 52, Si or Ge is implanted with low energy into the amorphization target polysilicon region 11a, which is the upper layer portion of the polysilicon film 11, to amorphize the amorphization target polysilicon region 11a.

  Thereafter, as shown in FIG. 53, hydrogen annealing is performed at a high temperature of 400 ° C. to 1300 ° C. to flatten the surface of the polysilicon film 11 (11a) and reduce the level difference st2. At this time, the amorphized target polysilicon region 11a is converted into polysilicon again. Thereafter, an impurity 31 for gate implantation is implanted to make the polysilicon film 11 in which the amorphization target polysilicon region 11a is again polysilicon into a predetermined conductivity type.

  Note that it is possible to confirm whether or not the polysilicon film 11 has reached the target film thickness by measuring the film thicknesses of the polysilicon film 11 on the gate insulating film 10 and the silicon oxide film 9 after the hydrogen annealing treatment. desirable.

  Next, as shown in FIG. 54, a resist 32 is applied on the polysilicon film 11 and patterned.

  Then, as shown in FIG. 55, the polysilicon film 11 and the gate insulating film 10 are etched using the patterned resist 32 (not shown in FIG. 55) as a mask to obtain the polysilicon gate 11g and the gate insulating film 10g. .

  The cross-sectional structures shown in FIGS. 51 to 55 correspond to the AA cross section of FIG. 21 shown in the first embodiment.

(effect)
Thus, by planarizing the surface of the polysilicon film 11 by the polysilicon planarization process according to the seventh embodiment, a MOS transistor having good transistor characteristics can be obtained as in the first embodiment.

  Furthermore, in the seventh embodiment, hydrogen annealing is performed after the amorphization target polysilicon region 11a, which is the upper layer portion of the polysilicon film 11, is made amorphous, so that hydrogen annealing is performed in a more unstable state. As a result, the flatness of the surface of the polysilicon film 11 can be increased as compared with the case of the sixth embodiment.

  In the method of manufacturing the semiconductor device according to the seventh embodiment, the silicide region 18g is formed on the silicon oxide film 9 without the polysilicon region as in the first embodiment. Therefore, by the method of manufacturing the semiconductor device of the seventh embodiment, a good body potential can be fixed as in the first embodiment, so that a MOS transistor having good transistor characteristics can be obtained.

  Further, the polysilicon film 11 manufactured by the semiconductor device manufacturing method of the seventh embodiment tends to have a tapered planar shape in the gate region 30 near the isolation region (see FIG. 22).

<Eighth embodiment>
(Polysilicon planarization)
56 to 60 are cross-sectional views showing a polysilicon planarization process in the semiconductor device manufacturing method according to the eighth embodiment. These drawings correspond to the steps shown in FIGS. 7 to 9 in the general steps shown in the first embodiment. The contents of the polysilicon planarization process according to the eighth embodiment will be described below with reference to FIGS.

  First, as shown in FIG. 56, an amorphous silicon layer 24 (amorphized gate electrode material layer) is formed on the entire surface. At this time, a step st2 is formed between the SOI layer 3 and the silicon oxide film 9 reflecting the step st9. Note that the amorphous silicon layer 24 is formed with a thickness greater than that of the step st9.

  Then, as shown in FIG. 57, the amorphous silicon layer 24 is subjected to hydrogen annealing at a high temperature of 400 ° C. to 1300 ° C. to flatten the surface of the polysilicon film 11 (amorphous silicon layer 24) and reduce the level difference st2. To do. At this time, the amorphous silicon layer 24 is turned into polysilicon to form the polysilicon film 11 (crystallized gate electrode material layer).

  Thereafter, as shown in FIG. 58, an impurity 31 for gate implantation is implanted to make the polysilicon film 11 have a predetermined conductivity type.

  Next, as shown in FIG. 59, a resist 32 is applied on the polysilicon film 11 and patterned.

  Then, as shown in FIG. 60, the polysilicon film 11 and the gate insulating film 10 are etched using the patterned resist 32 (not shown in FIG. 60) as a mask to obtain the polysilicon gate 11g and the gate insulating film 10g. .

  The cross-sectional structures shown in FIGS. 56 to 60 correspond to the AA cross section of FIG. 21 shown in the first embodiment.

(effect)
As described above, by planarizing the surface of the polysilicon film 11 by the polysilicon planarization process according to the eighth embodiment, a MOS transistor having good transistor characteristics can be obtained as in the first embodiment.

  Furthermore, in the eighth embodiment, hydrogen annealing is performed on the amorphous silicon layer 24, which is a more unstable layer than the polysilicon film 11, so that the surface of the polysilicon film 11 is flatter than that in the sixth embodiment. The degree can be increased.

  In the semiconductor device manufacturing method according to the eighth embodiment, the silicide region 18g is formed on the silicon oxide film 9 without the polysilicon region, as in the first embodiment. Therefore, by the method for manufacturing the semiconductor device of the eighth embodiment, a good body potential can be fixed as in the first embodiment, so that a MOS transistor having good transistor characteristics can be obtained.

  Further, the polysilicon film 11 manufactured by the method for manufacturing a semiconductor device of the eighth embodiment tends to have a tapered planar shape in the gate region 30 near the isolation region (see FIG. 22).

<Embodiment 9>
(Polysilicon planarization)
61 to 65 are cross-sectional views showing a polysilicon planarization process in the semiconductor device manufacturing method according to the ninth embodiment. These drawings correspond to the steps shown in FIGS. 7 to 9 in the general steps shown in the first embodiment. The details of the polysilicon planarization process according to the ninth embodiment will be described below with reference to FIGS.

  First, as shown in FIG. 61, a polysilicon film 11 made of polysilicon (first material) is formed on the entire surface. At this time, a step st2 is formed between the SOI layer 3 and the silicon oxide film 9 reflecting the step st9. The polysilicon film 11 is formed with a film thickness thicker than the step st9.

  Then, as shown in FIG. 62, polysilazane (SOG (Spin On Glass); second material), which is a liquid oxide film, is applied so that the depressions in the polysilicon film 11 resulting from the step st2 are removed from the polysilazane region 25. Embed with

  Next, as shown in FIG. 63, annealing at 1000 ° C. or lower is performed to oxidize the polysilazane region 25 and change the polysilazane into a silicon oxide film (third material) to obtain a silicon oxide region 25o. On the other hand, the portion of the polysilicon film 11 corresponding to the recess of the polysilicon film 11, that is, the thickness corresponding to the film thickness of the silicon oxide region 25o is defined as the removal target polysilicon region 11r.

  Then, the surface of the remaining polysilicon film 11 is planarized by removing the silicon oxide region 25o and the removal target polysilicon region 11r by dry etching. Since the silicon oxide region 25o and the removal target polysilicon region 11r are common in that Si is used as a material, dry etching without a selection ratio (etching rate) can be easily performed, so that the remaining polysilicon film 11 surfaces can be flattened with high accuracy.

  Next, as shown in FIG. 64, an impurity 31 for gate injection is implanted into the polysilicon film 11 whose surface is flattened to make the polysilicon film 11 have a predetermined conductivity type.

  Next, as shown in FIG. 65, the polysilicon film 11 and the gate insulating film 10 are etched using a patterned resist (not shown in FIG. 65) as a mask to obtain a polysilicon gate 11g and a gate insulating film 10g. .

  The cross-sectional structures shown in FIGS. 61 to 65 correspond to the AA cross section of FIG. 21 shown in the first embodiment.

(effect)
In this way, by planarizing the surface of the polysilicon film 11 by the polysilicon planarization process according to the ninth embodiment, a MOS transistor having good transistor characteristics can be obtained as in the first embodiment.

  In the semiconductor device manufacturing method according to the ninth embodiment, the silicide region 18g is formed on the silicon oxide film 9 without the polysilicon region, as in the first embodiment. Therefore, by the method for manufacturing the semiconductor device of the ninth embodiment, a good body potential can be fixed as in the first embodiment, so that a MOS transistor having good transistor characteristics can be obtained.

  Further, the polysilicon film 11 manufactured by the semiconductor device manufacturing method of the ninth embodiment tends to have a tapered planar shape in the gate region 30 near the isolation region (see FIG. 22).

<Embodiment 10>
(Polysilicon planarization)
66 to 70 are cross-sectional views showing a polysilicon planarization process in the semiconductor device manufacturing method of the tenth embodiment. These drawings correspond to the steps shown in FIGS. 7 to 9 in the general steps shown in the first embodiment. The contents of the polysilicon planarization process according to the tenth embodiment will be described below with reference to FIGS.

  First, as shown in FIG. 66, a polysilicon film 11 is formed on the entire surface. At this time, a step st2 is formed between the SOI layer 3 and the silicon oxide film 9 reflecting the step st9. Note that the polysilicon film 11 is formed to be thicker than the step st9.

  Then, as shown in FIG. 67, by applying liquid Si, the recessed portion of the polysilicon film 11 resulting from the step st2 is embedded in the liquid silicon region 26 (embedded region).

  In addition, about liquid Si, what mixed cyclopentasilane (CPS) and polysilane and dissolved in the organic solvent etc. can be considered. Details of liquid Si can be found in, for example, the document “Solution-Processed Silicon Films and Transistors, Yasuo Matsuki et al., P16-22 JSR TECHNICAL REVIEW No. 114/2007”. It is disclosed.

  Next, as shown in FIG. 68, annealing at 1000 ° C. or lower is performed to convert the liquid silicon region 26 into polysilicon, thereby obtaining a solidified polysiliconized region 26p. As a result, the surface of the synthetic polysilicon film 28 composed of the polysilicon film 11 and the polysiliconized region 26p is flattened with high accuracy. Thereafter, a gate implantation impurity 31 is implanted into the synthetic polysilicon film 28 to make the polysiliconized region 26p and the polysilicon film 11 have a predetermined conductivity type.

  Instead of forming polysilicon, a method may be used in which the liquid silicon region 26 is amorphized (the crystal grain size can be changed by irradiating an excimer laser) to obtain a solidified amorphous region. .

  Thereafter, as shown in FIG. 69, a resist 32 is applied on the synthetic polysilicon film 28 and patterned.

  Next, as shown in FIG. 70, the synthetic polysilicon film 28 and the gate insulating film 10 are etched using the patterned resist (not shown in FIG. 70) as a mask to form the polysilicon gate 11g and the gate insulating film 10g. obtain.

  The cross-sectional structures shown in FIGS. 66 to 70 correspond to the AA cross section of FIG. 21 shown in the first embodiment.

(effect)
In this way, by planarizing the surface of the polysilicon film 11 by the polysilicon planarization process according to the tenth embodiment, a MOS transistor having good transistor characteristics can be obtained as in the first embodiment.

  In the semiconductor device manufacturing method according to the tenth embodiment, the silicide region 18g is formed on the silicon oxide film 9 without the polysilicon region, as in the first embodiment. Therefore, by the method for manufacturing the semiconductor device of the tenth embodiment, a good body potential can be fixed as in the first embodiment, so that a MOS transistor having good transistor characteristics can be obtained.

  Further, the polysilicon film 11 manufactured by the semiconductor device manufacturing method of the tenth embodiment tends to have a tapered planar shape in the gate region 30 near the isolation region (see FIG. 22).

It is sectional drawing which shows the general process of the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 6 is a cross-sectional view showing a general process of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a general process of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a general process of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a general process of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a general process of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a general process of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a general process of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a general process of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a general process of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a general process of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a general process of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a general process of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a general process of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a general process of the method for manufacturing the semiconductor device of the first embodiment. 3 is a cross-sectional view showing a polysilicon planarization process in the first embodiment. FIG. 3 is a cross-sectional view showing a polysilicon planarization process in the first embodiment. FIG. 3 is a cross-sectional view showing a polysilicon planarization process in the first embodiment. FIG. 3 is a cross-sectional view showing a polysilicon planarization process in the first embodiment. FIG. 3 is a cross-sectional view showing a polysilicon planarization process in the first embodiment. FIG. 3 is a plan view showing a planar configuration of the semiconductor device manufactured by the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a plan view schematically showing a planar shape after obtaining a polysilicon gate by the method for manufacturing a semiconductor device of the first embodiment; FIG. FIG. 13 is a cross-sectional view showing another cross-section showing the silicide region forming step shown in FIG. 12. 4 is a cross-sectional view showing a cross-sectional structure including a body potential fixing portion manufactured by the method for manufacturing a semiconductor device of the first embodiment. FIG. FIG. 13 is a plan view showing a planar structure after a silicide region forming step shown in FIG. 12. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the second embodiment. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the second embodiment. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the second embodiment. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the second embodiment. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the second embodiment. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the third embodiment. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the third embodiment. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the third embodiment. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the third embodiment. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the third embodiment. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the fourth embodiment. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the fourth embodiment. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the fourth embodiment. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the fourth embodiment. FIG. 10 is a cross-sectional view showing a polysilicon planarization process in the fourth embodiment. It is sectional drawing which shows the polysilicon planarization process in Embodiment 5. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 5. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 5. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 5. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 5. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 6. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 6. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 6. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 6. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 6. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 7. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 7. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 7. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 7. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 7. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 8. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 8. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 8. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 8. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 8. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 9. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 9. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 9. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 9. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 9. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 10. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 10. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 10. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 10. FIG. It is sectional drawing which shows the polysilicon planarization process in Embodiment 10. FIG. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the general process of the manufacturing method of the conventional semiconductor device. It is explanatory drawing for demonstrating the problem by the manufacturing method of the conventional semiconductor device. It is explanatory drawing for demonstrating the problem by the manufacturing method of the conventional semiconductor device. It is explanatory drawing for demonstrating the problem by the manufacturing method of the conventional semiconductor device.

Explanation of symbols

  1 silicon support substrate, 2 buried oxide film, 3 SOI layer, 4,9 silicon oxide film, 5 silicon nitride film, 6 resist pattern, 7 trench opening, 8 oxide film, 10, 10 g gate insulating film, 11 polysilicon film 11g polysilicon gate, 12 silicon oxide film, 13 ext portion impurity, 14 pocket impurity, 15 side wall silicon oxide film, 16 side wall silicon nitride film, 17 S / D portion impurity, 18g, 18s silicide Region, 19 liner nitride film, 20 interlayer insulation film, 21 contact plug, 22 metal wiring layer, 23 additional polysilicon layer, 24 amorphous silicon layer, 25 polysilazane region, 25o silicon oxide region, 26 liquid silicon region, 26p polysiliconization Area, 27 Regis G. 28 Synthetic polysilicon film.

Claims (13)

A method of manufacturing a semiconductor device including a transistor formed on an SOI substrate including a semiconductor support substrate, a buried insulating film, and an SOI layer,
The transistor is isolated by a partial isolation region, and the partial isolation region includes a partial insulating film provided in an upper layer portion of the SOI layer and a remaining SOI layer that is a part of the SOI layer under the partial insulating film. The partial insulating film is formed to protrude from the surface of the SOI layer by a predetermined step,
The step of forming a gate electrode in the transistor includes
(a) forming a first gate electrode material layer containing silicon on the entire surface including on the partial insulating film with a film thickness equal to or larger than the predetermined step;
(b) performing a CMP process from the surface of the first gate electrode material layer to planarize the surface of the first gate electrode material layer;
(c) patterning the first gate electrode material layer to obtain the gate electrode;
(d) siliciding the gate electrode from the surface to form a silicide region,
The silicide region is formed in the entire region of the gate electrode on the partial insulating film,
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1,
The CMP process executed in step (b) includes a timed CMP process that is performed for a predetermined time.
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1,
The CMP process performed in the step (b) includes a stopper CMP process using the partial insulating film as a stopper.
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 1 to 3,
(e) after the step (b) and before the step (c), further comprising the step of forming a second gate electrode material layer on the first gate electrode material layer,
Step (c)
Patterning the second gate electrode material layer in addition to the first gate electrode material layer to obtain the gate electrode;
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device including a transistor formed on an SOI substrate including a semiconductor support substrate, a buried insulating film, and an SOI layer,
The transistor is isolated by a partial isolation region, and the partial isolation region includes a partial insulating film provided in an upper layer portion of the SOI layer and a remaining SOI layer that is a part of the SOI layer under the partial insulating film. The partial insulating film is formed to protrude from the surface of the SOI layer by a predetermined step,
The step of forming a gate electrode in the transistor includes
(a) The gate electrode material formed on the SOI layer, comprising a step of forming a gate electrode material layer having a first material on the entire surface including the partial insulating film with a film thickness equal to or greater than the predetermined step. The layer has a recess reflecting the predetermined step,
(b) forming a buried region having a second material in the recess of the gate electrode material layer;
(c) removing the buried region and the gate electrode material layer from the surface in the depth direction, leaving only the gate electrode material layer;
(d) patterning the gate electrode material layer to obtain the gate electrode,
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 5,
Step (c)
A process of performing an etching process on the buried region and the gate electrode material layer with a small selectivity between the first and second materials;
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 6,
(e) After the step (b) and before the step (c), the second material of the embedded region is changed to a third material that is partially in common with the first material. Further comprising the step of:
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 5,
(e) After the step (b) and before the step (c), a removal target region existing at a formation height corresponding to the buried region in the gate electrode material layer is defined as the first material. Further comprising a step of changing to a different fourth material,
Step (c)
(c-1) selectively removing the embedded region;
(c-2) selectively removing the region to be removed that has been changed to the third material after the execution of the step (e),
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device including a transistor formed on an SOI substrate including a semiconductor support substrate, a buried insulating film, and an SOI layer,
The transistor is element-isolated by a partial isolation region, and the partial isolation region includes a partial insulating film provided in an upper layer portion of the SOI layer and a remaining SOI layer that is a part of the SOI layer under the partial insulating film. The partial insulating film is formed to protrude from the surface of the SOI layer by a predetermined step,
The step of forming a gate electrode in the transistor includes
(a) forming a gate electrode material layer on the entire surface including on the partial insulating film with a film thickness equal to or greater than the predetermined step;
(b) performing a high temperature annealing process on the gate electrode material layer at 400 ° C. or higher to flatten the surface of the gate electrode material layer;
(c) patterning the gate electrode material layer to obtain the gate electrode,
A method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device according to claim 9, comprising:
(d) After the step (a), before the step (b), further comprising the step of amorphizing the upper layer portion of the gate electrode material layer,
A method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device according to claim 9, comprising:
The gate electrode material layer formed in the step (a) includes an amorphous gate electrode material layer that has been made amorphous.
The gate electrode material layer after the step (b) treatment includes a crystallized gate electrode material layer obtained by crystallizing the amorphous gate electrode material layer,
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device including a transistor formed on an SOI substrate including a semiconductor support substrate, a buried insulating film, and an SOI layer,
The transistor is isolated by a partial isolation region, and the partial isolation region includes a partial insulating film provided in an upper layer portion of the SOI layer and a remaining SOI layer that is a part of the SOI layer under the partial insulating film. The partial insulating film is formed to protrude from the surface of the SOI layer by a predetermined step,
The step of forming a gate electrode in the transistor includes
(a) forming a gate electrode material layer made of polysilicon on the entire surface including on the partial insulating film with a film thickness equal to or larger than the predetermined step, and the gate electrode material layer formed on the SOI layer includes: Reflecting the predetermined step, and having a dent,
(b) forming a buried region made of liquid silicon in the recess of the gate electrode material layer, and planarizing the surface of the gate electrode material layer including the buried region;
(c) heat-treating the buried region to solidify the buried region, and a synthetic polysilicon film is formed by the gate electrode material layer and the buried region,
(d) further comprising the step of patterning the synthetic polysilicon film to obtain the gate electrode;
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 5 to 12,
The gate electrode can be silicided from the surface;
(f) siliciding the gate electrode from the surface to form a silicide region,
The silicide region is formed in the entire region of the gate electrode on the partial insulating film,
A method for manufacturing a semiconductor device.

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