JP2009158539A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a semiconductor device having a (111)-aligned ferroelectric film without a variation in alignment. <P>SOLUTION: Disclosed is the manufacturing method of the semiconductor device including the ferroelectric film, wherein the ferroelectric film is formed through (A) a stage of switching the atmosphere in a treatment container in which a substrate to be treated where the semiconductor device is formed is held from a first atmosphere to a second atmosphere and (B) a stage of forming the ferroelectric film on the substrate to be treated in the second atmosphere by an organic metal vapor-phase deposition method using as a raw material an organic metal compound supplied from a raw material gas supply line. The stage (B) is started by starting supplying the raw material gas to the treatment container after the lapse of a predetermined gas stabilization time after the stage (A), and the predetermined gas stabilization time is set longer than a time (V/L) obtained by dividing the total V of the capacity of an atmospheric gas line and the capacity of a mixing/discharging portion by the flow rate L of a mixed gas in the atmospheric gas line. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention generally relates to semiconductor devices, and more particularly to a method of manufacturing a semiconductor device having a ferroelectric capacitor.

  A ferroelectric memory is a voltage-driven non-volatile semiconductor memory element, which operates at high speed, has low power consumption, and has preferable characteristics that do not lose stored information even when the power is turned off. Ferroelectric memories are already used in IC cards and portable electronic devices.

  FIG. 1 is a cross-sectional view showing the structure of a so-called stack type ferroelectric memory device 10.

  Referring to FIG. 1, a ferroelectric memory device 10 is a so-called 1T1C type device, in which two memory cell transistors are provided in a bit line in an element region 11A defined by an element isolation region 11I on a silicon substrate 11. Is formed by sharing.

  More specifically, an n-type well is formed as the element region 11A in the silicon substrate 11, and a first MOS transistor having a polysilicon gate electrode 13A and polysilicon are formed on the element region 11A. A second MOS transistor having a gate electrode 13B is formed through gate insulating films 12A and 12B, respectively.

The further in the silicon substrate 11, the p in correspondence to respective sidewalls of the gate electrode 13A ^- -type LDD region 11a, and 11b are formed, also in correspondence to respective sidewalls of the gate electrode 13B p ^- -type LDD regions 11c and 11d are formed. Here, since the first and second MOS transistors are formed in common in the element region 11A, the same p ⁻ type diffusion region is shared as the LDD region 11b and the LDD region 11c.

  A silicide layer 14A is formed on the polysilicon gate electrode 13A, and a silicide layer 14B is formed on the polysilicon gate electrode 13B. Further, both side walls of the polysilicon gate electrode 13A and the polysilicon gate are formed. Each side wall insulating film is formed on both side wall surfaces of the electrode 13B.

Further, in the silicon substrate 11, p ⁺ type diffusion regions 11e and 11f are formed outside the respective side wall insulating films of the gate electrode 13A, and each of the side wall insulating films of the gate electrode 13B is formed. On the outside, p ⁺ -type diffusion regions 11g and 11h are formed. However, the diffusion regions 11f and 11g are composed of the same p ⁺ -type diffusion region.

Further, on the silicon substrate 11, the gate electrode 13A including the silicide layer 14A and the sidewall insulating film is covered, and the gate electrode 13B including the silicide layer 14B and the sidewall insulating film is covered. A SiON film 15 is formed, and an interlayer insulating film 16 made of SiO ₂ is formed on the SiON film 15. Further, contact holes 16A, 16B, and 16C are formed in the interlayer insulating film 16 so as to expose the diffusion regions 11e, 11f (and hence the diffusion regions 11g) and 11h, respectively, and are formed in the contact holes 16A, 16B, and 16C. The via plugs 17A, 17B, and 17C made of W (tungsten) are formed through the adhesion layers 17a, 17b, and 17c in which the Ti film and the TiN film are stacked.

  Further, on the interlayer insulating film 16, a first ferroelectric capacitor C1 in which a lower electrode 18A, a polycrystalline ferroelectric film 19A, and an upper electrode 20A are stacked in contact with the tungsten plug 17A is also provided. A second ferroelectric capacitor C2 in which a lower electrode 18C, a polycrystalline ferroelectric film 19C, and an upper electrode 20C are stacked is formed in contact with the plug 17C.

Further, a hydrogen barrier film 21 made of Al ₂ O ₃ is formed on the interlayer insulating film 16 so as to cover the ferroelectric capacitors C 1 and C ₂ , and the next interlayer insulating film 22 is further formed on the hydrogen barrier film 21. Is formed.

  Further, in the interlayer insulating film 22, a contact hole 22A exposing the upper electrode 20A of the ferroelectric capacitor C1, a contact hole 22B exposing the via plug 17B, and an upper electrode 20C of the ferroelectric capacitor C2 are provided. An exposed contact hole 22C is formed, and tungsten plugs 23A, 23B, and 23C are formed in the contact holes 22A to 22C through adhesion layers 23a, 23b, and 23c in which a Ti film and a TiN film are laminated, respectively.

  Further, Al wiring patterns 24A, 24B, and 24C are formed on the interlayer insulating film 22 with a barrier metal film having a Ti / TiN laminated structure corresponding to the tungsten plugs 23A, 23B, and 23C, respectively. .

Conventionally, in the ferroelectric memory, as the polycrystalline ferroelectric films 19A and 19C, lead zirconate titanate (PZT), SrBi ₂ Ta ₂ O ₉ (SBT, Y1) or SrBi ₂ (Ta, Nb) ₂ O is used. ₉ (SBTN, YZ), Bi ₄ Ti ₃ O ₉ , (Bi, La) ₄ Ti ₃ O ₁₂ , BiFeO ₃ and the like are used.

  By the way, in the ferroelectric memory as shown in FIG. 1, the crystal orientation of the polycrystalline ferroelectric films 19A and 19C to be the ferroelectric capacitor insulating film is very important. Ferroelectric materials such as PZT have a tetragonal perovskite structure, and ferroelectric properties are manifested when metal atoms such as Ti and Zr are displaced in the c-axis direction in the perovskite structure. Therefore, in a ferroelectric capacitor having a configuration in which a ferroelectric film is sandwiched between upper and lower electrodes, as in the ferroelectric memory 10 of FIG. 1, the electric field direction is strong so that it is parallel to the c-axis direction of the ferroelectric. Ideally, the dielectric film has a (001) orientation. When the ferroelectric film has a (100) orientation, ferroelectricity does not appear.

However, in the perovskite film, the difference between the c-axis and the a-axis is not so large even though it is tetragonal. Therefore, in the PZT film formed by a normal manufacturing method, the (001) -oriented crystal grains and (100) Considering that almost the same number of oriented crystal grains are generated and those with other orientations are also generated, the proportion of crystals that actually contribute to the operation of the ferroelectric capacitor was small. Under such circumstances, conventionally, in the technical field of ferroelectric memory, the ferroelectric films 19A and 19C are formed as (111) orientation films as a whole, and the orientation direction is aligned in the <111> direction. The switching charge amount _QSW is ensured.

  Under these circumstances, in a ferroelectric memory, a Pt film as a lower electrode of a ferroelectric capacitor is placed on an orientation control film such as a self-orientation Ti film via a conductive oxygen diffusion barrier film such as a TiAlN film (111). A ferroelectric film such as PZT is formed on the (111) orientation. Here, the self-oriented Ti film exhibits a (002) orientation. Further, the TiAlN oxygen diffusion barrier film suppresses oxygen in the ferroelectric film from entering the W plug.

  Conventionally, in the ferroelectric memory, such polycrystalline ferroelectric films 19A and 19C are formed by the sputtering method or the sol-gel method. However, in such a ferroelectric memory, the miniaturization and the integration density are improved. For this reason, attempts have been made to form a ferroelectric film by a metal organic vapor phase deposition method (MOCVD method) excellent in step coverage.

  However, in MOCVD, platinum (Pt) or iridium (Ir) having a strong (111) orientation is used for the lower electrodes 18A and 18C, and a polycrystalline ferroelectric film such as a PZT film is simply formed thereon. However, the desired (111) orientation cannot be obtained in the polycrystalline ferroelectric films 19A and 19C.

  When a ferroelectric film such as PZT is formed by the MOCVD method, it is necessary to heat to a temperature at least higher than the decomposition temperature of the raw material. Therefore, the film is generally formed at a high temperature and is formed accordingly. 1 is crystallized at the same time as the film is formed, but when the Pt film is used for the lower electrodes 18A and 18C in the configuration of FIG. 1, the Pt in the lower electrodes 18A and 18C is heated by the heat in the MOCVD process. In particular, Pb in the PZT films 19A and 19C reacts to deteriorate the morphology of the surfaces of the lower electrodes 18A and 18C, thereby preventing the (111) orientation of the polycrystalline ferroelectric films 19A and 19C.

In the configuration shown in FIG. 1, when the Ir film is used as the lower electrodes 18A and 18C in order to avoid the above-described problem, the lower electrode 18A or 18C and the polycrystalline ferroelectric substance are compared with the case where the Pt film is used. Although the reaction at the interface with the film 19A or 19C is suppressed, since oxygen gas or the like is introduced into the film forming chamber as an oxidant, the surface of the Ir film constituting the lower electrodes 18A and 18C is oxidized, resulting in many The crystal ferroelectric films 19A and 19C cannot inherit the preferential Ir films 19A and 19C (111) orientation. Therefore, in Patent Document 1, when the PZT film is formed by the MOCVD method on the lower electrodes 18A and 18C made of the Ir film using the initial layer (seed layer), a low oxygen partial pressure or oxygen concentration is used. The seed layer is preferentially (111) oriented. After the seed layer is formed, the main parts of the PZT films 19A and 19C take over the (111) orientation of the seed layer and are formed at a high film formation speed under a high oxygen partial pressure.
JP 2003-324101 A

  By the way, when the polycrystalline ferroelectric films 19A and 19C having the (111) orientation are formed by the MOCVD method as described above, the inventors of the present invention have the degree of the (111) orientation, that is, the orientation ratio, as shown in FIG. As shown in Fig. 2, we found a problem that the wafers vary greatly.

  Referring to FIG. 2, the vertical axis represents the X-ray diffraction integrated intensity from the PZT (111) plane of the polycrystalline ferroelectric films 19A and 19B obtained by X-ray diffraction, and the horizontal axis represents the sequentially processed target. Although the numbers of the processed substrates are shown, it can be seen that the value of the integrated intensity of X-ray diffraction of PZT (111) varies by nearly 20%. Such a variation in the PZT (111) integral intensity indicates that there is a large variation in the (111) orientation in the polycrystalline ferroelectric films 19A and 19C.

  According to one aspect, the present invention is a method of manufacturing a semiconductor device including a ferroelectric film, a processing container exhausted by an exhaust device, and a source gas supply line for supplying a source gas into the processing container; Ferroelectricity by metal organic vapor phase deposition performed using an organic metal deposition apparatus provided with an atmosphere gas line for supplying at least first and second atmosphere gases in the form of a mixed gas into the processing container A body film forming step, wherein the processing container is connected to the source gas line and the atmosphere gas line, and the source gas and the mixed gas are mixed to form a processing gas, and the processing gas is processed into the processing gas. A mixing / releasing part for discharging into the container, wherein the atmosphere gas line is supplied from the first and second flow rate control means for supplying the first and second atmosphere gases at respective flow rates; The ferroelectric film is formed by the step (A) of changing the atmosphere in the processing container holding the substrate to be processed on which the semiconductor device is formed from the first atmosphere to the second atmosphere. And (B) a ferroelectric film on the substrate to be processed in the second atmosphere in the processing container, using an organometallic compound supplied from the source gas supply line as a raw material, Forming a film by a metal organic vapor phase deposition method, and the step (B) includes a step of supplying the source gas to the processing container after a predetermined gas stabilization time after the step (A). The predetermined gas stabilization time is determined by calculating the total volume V of the atmosphere gas line and the volume of the mixing / releasing part by the flow rate L of the mixed gas in the atmosphere gas line. Less than the time obtained by dividing (V / L) It is set to provide a method of manufacturing a semiconductor device according to claim.

  According to another aspect, the present invention provides a processing container exhausted by an exhaust device, a source gas supply line for supplying a source gas into the processing container, and at least first and second atmospheres in the processing container. A ferroelectric capacitor including a process for forming a ferroelectric film by a metal organic vapor deposition method performed using an organic metal deposition apparatus having an atmosphere gas line for supplying a gas in the form of a mixed gas; In the method of manufacturing a semiconductor device, the processing container is connected to the source gas line and the atmosphere gas line, and the source gas and the mixed gas are mixed to form a processing gas, and the processing gas is processed into the processing gas. A mixing / releasing unit for discharging into the container, wherein the atmosphere gas line is supplied from the first and second flow rate control means for supplying the first and second atmosphere gases at respective flow rates; / A process extending to the discharge part, and (A) introducing a substrate to be processed in which a lower electrode is formed in the processing container; and (B) after the step (A), the substrate to be processed Increasing the temperature in the first atmosphere in which the flow rate of the first atmospheric gas is set to the first flow rate and the flow rate of the second atmospheric gas is set to the second flow rate including zero; C) After the step (B), the flow rate of the first atmospheric gas is decreased from the first flow rate to the third flow rate, and the flow rate of the second atmospheric gas is changed from the second flow rate to the fourth flow rate. And (D) after the step (C), a ferroelectric film is formed on the lower electrode after the step of switching the first atmosphere to the second atmosphere. Forming a film by supplying the raw material gas into the processing container from The step (D) is started by starting the supply of the raw material gas to the processing container after the elapse of a predetermined gas stabilization time after the step (C), and the predetermined gas stabilization time is The volume V of the atmosphere gas line and the volume V of the mixing / discharge section are set to be equal to or longer than the time (V / L) obtained by dividing the sum V by the flow rate L of the mixture gas in the atmosphere gas line. A method of manufacturing a semiconductor device is provided.

  According to the present invention, the flow rates of the first and second atmospheric gases supplied from the first and second flow rate control means to the processing vessel change, and the atmosphere during the formation of the ferroelectric film is the first. When the atmosphere is switched from the first atmosphere to the second atmosphere, the film formation of the ferroelectric film is started after a predetermined gas stabilization time has elapsed, resulting in non-uniform mixing of the first and second gases. Even when a large number of wafers are used as the substrate to be processed and the ferroelectric films are sequentially formed, the ferroelectric film characteristics for each wafer, especially the crystal orientation, are effectively suppressed. The problem of variability can be solved.

  Further, according to the present invention, after the deposition of one substrate to be processed is completed and the substrate to be processed is taken out, the inside of the processing container is purged before the next substrate to be processed is introduced into the processing container. As a result, component elements having a high vapor pressure among the constituent elements of the ferroelectric film, such as Pb deposited on the side wall surface of the processing container, are deposited on the peripheral portion of the substrate to be processed and formed thereon. The problem of shifting the film quality of the ferroelectric film, particularly the crystal orientation, from the desired (111) orientation is solved.

[First Embodiment]
Hereinafter, referring to FIGS. 3A to 3E, an experiment of manufacturing a ferroelectric capacitor by the MOCVD method performed by the inventor of the present invention will be described, and the manufacturing of the ferroelectric capacitor according to the first embodiment of the present invention will be described. The process will be described.

Referring to FIG. 3A, a Ti film 42 having (002) orientation is formed by sputtering as an orientation control film on a silicon oxide film 41 covering a silicon substrate (not shown). On the surface 42, a TiAlN film 43 is formed as a conductive oxygen diffusion barrier film by a reactive sputtering method. The silicon oxide film 41 may carry an Al ₂ O ₃ film on its surface.

For example, the Ti film 42 has a sputtering power of 2.6 kW at a substrate temperature of 20 ° C. in an Ar atmosphere having a pressure of 0.15 Pa in a DC sputtering apparatus with a distance between the substrate to be processed and the target set to 60 mm. It is formed by supplying for 2 seconds. The TiAlN film 43 uses Ti and Al alloy targets in the same DC sputtering apparatus and supplies Ar gas at a flow rate of 40 sccm and nitrogen gas at a flow rate of 10 sccm in an Ar / N ₂ atmosphere at a pressure of 253.3 Pa. The film is formed to a thickness of 100 nm by supplying a sputtering power of 1.0 kW at a substrate temperature of 400 ° C.

  The Ti film 42 is preferably nitrided once after film formation. By nitriding the Ti film 42 in this way, oxidation of Ti from the side surface of the film can be suppressed during the subsequent recovery heat treatment of the ferroelectric film. For example, the nitriding treatment is performed in a nitrogen atmosphere by a rapid heat treatment at a temperature of 650 ° C. for 60 seconds, whereby the (111) -oriented TiN base conductive film 42N is obtained from the (002) -oriented Ti film 42.

  Next, in the step of FIG. 3B, a lower electrode film 45 made of an Ir film having a thickness of about 100 nm is formed on the TiAlN film 43 at a substrate temperature of 550 ° C. in an Ar atmosphere with a pressure of 0.2 Pa, for example. And formed by a sputtering method in which a sputtering power of 0.5 kW is applied. The Ir lower electrode film 45 thus formed has a (111) orientation.

  Further, the structure of FIG. 3B is subjected to rapid heat treatment at a temperature of 650 ° C. for 60 seconds in an Ar atmosphere to improve the crystallinity of the Ir film 45. Further, the Ir film 45 and the TiAlN film below the Ir film 45 are improved. The adhesion between the two is improved.

  Next, in the step of FIG. 3C, a first PZT film 46 is formed on the lower electrode 45 as a seed layer to a thickness of about 1 to 10 nm, preferably about 5 nm, by MOCVD.

  FIG. 4 shows a schematic configuration of a downflow type metal organic deposition apparatus (MOCVD apparatus) 1 used in the process of FIG.

  Referring to FIG. 4, the MOCVD apparatus 1 includes a processing container 1A exhausted by an exhaust line 2 including an APC (automatic pressure control apparatus) 2A and a vacuum pump 2P, and the processing container 1A includes the processing container 1A shown in FIG. The susceptor 1B is provided to hold the substrate 41 in the state of) as the substrate W to be processed. The susceptor 1B includes a heating unit (not shown) for heating the substrate W to be processed.

  Further, a shower head 1C is provided in the processing vessel 1A so as to face the substrate W to be processed on the susceptor 1B, and a raw material gas containing oxygen gas and each constituent element of PZT is supplied to the shower head 1C through a line 3. The PZT film 46 is formed by discharging the various source gases into the processing container.

Further, in the MOCVD apparatus 1 of FIG. 4, there are provided raw material containers 3A to 3C for holding organometallic raw materials of Pb, Zr, Ti in a liquid state dissolved in an organic solvent and a container 3D for holding only the solvent, Each liquid raw material is pressurized by He gas from the line 3H, and the corresponding mass flow controller 3a and valve 3v, the corresponding mass flow controller 3b and valve 3w,
The nitrogen carrier gas is supplied from the line 4N to the vaporizer 4 via the corresponding mass flow controller (MFC) 3c and the valve 3x, and the corresponding mass flow controller (MFC) 3d and the valve 3y. As a result of vaporizing the liquid material in the vaporizer 4, vapor phase materials of Pb, Zr and Ti are formed in the vaporizer 4.

  The vapor phase raw material thus formed is supplied to the shower head 1C together with the nitrogen carrier gas via the valve 4A and the line 3. Further, in order to stabilize the generation of the vapor phase raw material in the vaporizer 3, the vaporizer 4 is further provided with a valve 4B, and when the vapor phase raw material is not supplied to the processing vessel 1A, the vapor phase raw material is generated. The raw material is discarded from the switching valve 4B to the abatement apparatus (not shown) through the preflow line 4P and the vacuum pump 2P.

More specifically, as a raw material for Pb, the formula Pb (C ₁₁ H ₁₉ O ₂ ) ₂
Pb (DPM) ₂ represented by the formula, Zr (dmhd) ₄ represented by the formula Zr (C ₉ H ₁₅ O ₂ ) ₄ as the Zr raw material, and the formula Ti (O—C ₃ H ₇ as the Ti raw material. ) ₂ (C ₁₁ H ₁₉ O ₂ ) ₂ represented by Ti (O—iPr) ₂ (DPM) ₂ or Ti (O—iPr) ₂ (DMHD) ₂ , and these raw materials are used as butyl acetate or THF (tetrahydrofuran). And the like are dissolved in a concentration of 0.1 to 0.3 mol / l to form liquid raw materials of Pb, Zr, and Ti.

  Further, the liquid raw material thus formed is vaporized in the vaporizer 4 to form vapor phase raw materials of Pb, Zr and Ti, which are supplied from the respective mass flow controllers 5A and 5B via the line 5. The PZT film 46 is formed in an atmosphere defined by the ratio of the Ar gas and the oxygen gas, supplied to the processing vessel 1A through the shower head 1C together with the Ar gas and the oxygen gas supplied in this manner. The

  At this time, in this embodiment, first, the substrate to be processed W, that is, the silicon substrate 41 in the state of FIG. 3B, is introduced into the processing container 1A, and only oxygen gas is flowed at a flow rate of 2000 SCCM under a pressure of 533 Pa. Then, the temperature of the substrate to be processed W is raised to a predetermined film forming temperature, for example, about 620 ° C.

  During this time, the respective vapor phase raw materials are discarded from the valve 4B to the exhaust line 2 via the preflow line 4P. Thereafter, the valve 4A is opened at the same time as the valve 4B is closed. The Pb, Zr, and Ti vapor phase raw materials discarded through the preflow line 4P are supplied to the shower head 1C and introduced into the processing vessel 1A. As a result, the PZT film 46 is formed at a temperature of 620 ° C. under a pressure of 533 Pa on the substrate W to be processed in the processing container 1A.

  At that time, in the process of FIG. 3C, the flow rate of oxygen gas supplied from the line 5 into the processing container 1A is reduced from 2000 SCCM before film formation to 625 SCCM, and at the same time, supplied to the processing container 1A. The Ar gas flow rate is increased from 0 SCCM before film formation to 1375 SCCM, and the PZT film 46 is formed at a low oxygen partial pressure.

  The configuration of the MOCVD apparatus 1 in FIG. 4 is well known, and further description is omitted.

  Next, in the step of FIG. 3D, the second ferroelectric film 47 is formed on the first ferroelectric film 46 by the MOCVD method using the MOCVD apparatus 1 of FIG. The film is formed at a film forming temperature of 620 ° C., except that the flow rate of oxygen gas supplied from the line 5 is increased to 2000 SCCM and the flow rate of Ar gas is decreased to 0. The PZT film 47 inherits the orientation of the underlying seed layer, that is, the PZT film 46, and grows in the same orientation. That is, when the PZT film 46 has a (111) orientation, the PZT film 47 also has a (111) orientation.

  Next, in the step of FIG. 3E, the upper electrode 48 is formed on the PZT film 47 by sputtering using IrOx that forms a good interface with the PZT. In the present embodiment, the use of Pt having catalytic action as the upper electrode 48 is avoided, whereby the reduction of the PZT films 46 and 47 by activated hydrogen is suppressed.

  More specifically, after the step of FIG. 3D, an IrOx film having a thickness of 50 nm is first sputtered on the PZT film 47 by sputtering, for example, at a substrate temperature of 300 ° C. Oxygen gas is supplied at a flow rate of 120 sccm and 80 sccm, respectively, and a sputtering power of 1 to 2 kW is applied to form, for example, a film thickness of 50 nm and in a state already crystallized at the time of film formation.

  Next, the IrOx film thus formed is rapidly crystallized at a temperature of 725 ° C. for 60 seconds while supplying oxygen gas at a flow rate of 20 sccm and Ar gas at a flow rate of 2000 sccm, and is completely crystallized. In addition, this rapid heat treatment compensates oxygen vacancies caused by the formation of the upper electrode 48 in the PZT films 46 and 47.

Next, a second iridium oxide film (IrOy film) is formed on the first iridium oxide film (the IrOx film) thus formed by sputtering in an Ar atmosphere of 0.8 Pa by 1.0 kW. With a sputtering power of 100 to 300 nm, for example, a thickness of 200 nm is formed. The second iridium oxide film thus formed has a composition close to the stoichiometric composition of IrO ₂ (x <y ≦ 2), and a catalyst such as Ir or Pt with respect to hydrogen or water. Even when the multilayer wiring structure is formed on the structure shown in FIG. 3E without causing an effect, the PZT films 46 and 47 are reduced by hydrogen released from the interlayer insulating film containing moisture. Is suppressed, and the hydrogen resistance of the ferroelectric capacitor is improved.

  The upper electrode 48 having such a two-layer structure ensures excellent adhesion between the lower IrOx film and the underlying PZT film 47, and the upper IrOy film provides the above-mentioned description. As described above, the hydrogen resistance of the ferroelectric capacitor is improved.

In the present embodiment, Ir, Ru, Rh, Re, Os, Pd, or an oxide thereof, or a conductive oxide such as SrRuO ₃ can be used as the upper electrode 48 instead of IrOx. Further, the upper electrode 48 may have a laminated structure of these metals or conductive oxide layers.

In this embodiment, an Ir film may be formed on the surface of the upper electrode 48 although not shown. As a result, penetration of H ₂ O into the ferroelectric films 46 and 47 via the upper electrode 48 is suppressed, and contact characteristics with the wiring pattern are improved.

  5 (A) to 5 (C) show the process of FIG. 3 (C) in detail.

  Referring to FIG. 5A, as described above, in this embodiment, first, the substrate to be processed W, that is, the silicon substrate 41 in the state of FIG. Only oxygen gas is introduced at a flow rate of 2000 SCCM under a pressure of 533 Pa, and the temperature of the substrate to be processed W is raised to a predetermined film forming temperature, for example, a temperature of about 620 ° C. As a result, the substrate to be processed W is processed. On the surface of the (111) -oriented Ir lower electrode layer 45, a very thin Ir oxide film 45Ox having a composition expressed by IrOx is formed. The Ir oxide film 45Ox itself is amorphous and has no crystal orientation. In this state, the valve 4A is closed and the valve 4B is opened in the MOCVD apparatus 1 of FIG. 4, and the vapor phase raw material formed by the vaporizer 4 passes through the preflow line 4P and the pump. It is thrown away to an abatement device not shown.

Next, as shown in FIG. 5 (B), the PZT film 46 is formed on the Ir oxide film 45Ox in FIG. 5 (A). As described above with reference to FIG. The flow rate of oxygen gas supplied from the line 5 during 1A is reduced from 2000 SCCM before film formation to 625 SCCM by controlling the MFC 5B, and at the same time, the Ar gas flow rate supplied into the processing vessel 1A is reduced to the MFC 5A. Is controlled to increase from 0 SCCM before film formation to 1375 SCCM, in an Ar / O ₂ mixed gas atmosphere having a low oxygen partial pressure. In this case, as shown in FIG. 5C, oxygen atoms in the IrOx film 45Ox move to the PZT film 46 containing many oxygen vacancies so that the IrOx film 45Ox is integrated with the Ir lower electrode layer 45. The (111) plane is changed to an exposed Ir film, and the PZT film 46 is in contact with the (111) plane of the Ir film. At this time, the orientation of the PZT film 46 matches the (111) orientation of the Ir lower electrode 45, and the PZT film 46 has a desired (111) orientation.

  Thus, in the process of FIG. 3C, it is necessary to first form the Ir oxide film 45Ox on the surface of the Ir lower electrode layer 45 at a high oxygen partial pressure as shown in FIG. As shown in (B), it is necessary to form the PZT film 46 on the Ir oxide film 45Ox with a low oxygen partial pressure.

  Further, in the step of FIG. 3D, the PZT film 47 is formed on the (111) -oriented PZT film 46 formed in this manner, and the oxygen gas supplied from the line 5 as described above. The flow rate is formed by increasing the flow rate of Ar gas to 2000 SCCM by controlling the MFC 5B and decreasing the flow rate of the Ar gas to 0 by controlling the MFC 5A.

  FIG. 6 shows an example of a process recipe corresponding to the steps of FIGS. 5 (A) to 5 (C) and FIG. 3 (D).

  Referring to FIG. 6, in the temperature raising step of FIG. 5A, the flow rate of the oxygen gas supplied from the MFC 5B of the MOCVD apparatus 1 shown in FIG. 4 is set to 2000 SCCM and is supplied from the MFC 5A. The flow rate of Ar gas is set to 0 SCCM, that is, is blocked, and as a result, an Ir oxide film 45Ox is formed on the surface of the Ir lower electrode layer 45 as described above with reference to FIG. 5A. As described above, in this state, in the MOCVD apparatus 1 of FIG. 4, the valve 4A is closed and the valve 4B is opened, and the vapor phase raw material formed in the vaporizer 4 is the preflow line. It is thrown away to the abatement apparatus (not shown) through 4P and the pump.

  In the present embodiment, the formation of the PZT film 46 in the step of FIG. 5 (B) is performed such that the Ar gas flow rate supplied from the MFC 5A is larger than the oxygen gas flow rate supplied from the MFC 5B. For example, the value is set to 1375 SCCM, the flow rate of the oxygen gas supplied from the MFC 5B is set to a value of 625 SCCM, for example, and the raw material gas formed in the vaporizer 4 is opened by opening the valve 4A and the valve 4B. And is supplied to the processing vessel 1A through the raw material line 3 and the shower head 1C.

The inventor of the present invention moves the oxygen atoms in the Ir oxide film 45Ox to the PZT film 46, thereby making the Ir oxide film 45Ox integral with the lower Ir electrode layer 45 (111). In a series of processes for converting to an oriented Ir film and further aligning the orientation of the PZT film 46 in contact with the (111) oriented Ir film thus formed to the desired (111) orientation, the Ar / O ₂ It was found that the stability of the composition of the mixed gas atmosphere is very important.

  Therefore, in the recipe of FIG. 6, the temperature raising step in FIG. 5A (“temperature raising step” in FIG. 6) and the PZT film 46 deposition step in FIG. 5B (“first step in FIG. 6”). A gas stabilization process (“Gas stabilization process 1” in FIG. 6) is provided for a predetermined time during the “film deposition process”), and until the predetermined time elapses in the gas stabilization process 1, the valve The material gas is not supplied from the vaporizer 4 to the processing container 1A by opening 4A.

That is, in the recipe of FIG. 6, after the predetermined time has elapsed and the composition of the Ar / O ₂ mixed gas atmosphere is stabilized in the gas line 5 and the shower head 1C, the valve in the MOCVD apparatus 1 of FIG. Simultaneously with closing 4B, the valve 4A is opened, the supply of the source gas to the line 3 and the shower head 1C is started, and the deposition of the PZT film 46 is started. As will be described later with reference to FIG. 8, by providing such a gas stabilization step 1, variation in the (111) orientation of the PZT film 46 described above with reference to FIG. 2 and the PZT film 47 thereon is provided. The problem can be solved.

  Further, after the step of FIG. 5C, the step of FIG. 3D is executed to form a thick PZT film 47 on the PZT film 46 having the (111) orientation. Film formation is performed by setting the oxygen gas flow rate to 2000 SCCM in the MFC 5B, and further setting the Ar gas flow rate to 0 SCCM in the MFC 5A, in other words, shutting off the Ar gas. A second gas stabilization step (“gas stabilization step 2”) is provided for a predetermined time period between the “first deposition step” and the “second film deposition step” for depositing the PZT film 47. ing.

  That is, in the “gas stabilization process 2”, the valve 4A is closed and the valve 4B is opened in the MOCVD apparatus of FIG. 4 simultaneously with the end of the “first film deposition process”. The made source gas is again discarded through the preflow line and the vacuum pump 2P. Further, in the “gas stabilization step 2”, the Ar gas flow rate setting of the MFC 5A is changed to 0 SCCM, and the oxygen gas flow rate setting of the MFC 5B is changed to 2000 SCCM.

In this state, the “gas stabilization step 2” is continued for a predetermined time, and when the predetermined time has elapsed and the deposition atmosphere of the PZT film 47 has changed from the Ar / O ₂ mixed gas atmosphere to the oxygen atmosphere, In the MOCVD apparatus 1 of FIG. 4, the valve 4B is closed simultaneously with the opening of the valve 4A, and the supply of the source gas to the line 3 and the shower head 1C is started, and the PZT corresponding to the step of FIG. The deposition of the film 47 is started.

  FIG. 7 is a diagram showing an estimate of “predetermined time” required for the stabilization of the atmosphere in “gas stabilization step 1” and “gas stabilization step 2” of FIG. FIG. 7 is a diagram showing a simplified configuration of the MOCVD apparatus 1 of FIG.

Referring to FIG. 7, when the volume of the line 5 from the MFC 5A and the MFC 5B to the shower head 1C is V _1, and further the volume of the shower head 1C is V ₂ , the stabilization of the atmosphere Since the gas in the line 5 and the shower head 1C needs to be exchanged, the “predetermined time” T is:
T = (V ₁ + V ₂ ) / L
Is determined. Here, L is the flow rate of the Ar / O ₂ mixed gas or oxygen gas flowing through the line 5.

  Therefore, by performing the “gas stabilization process 1” and the “gas stabilization process 2” over a period of time T or more, respectively, the PZT film 46 or the PZT film 47 can be formed in a controlled atmosphere. It can be done in the middle. As a result, the orientation of the PZT film 46 is aligned with the (111) orientation. Therefore, the orientation of the PZT film 47 formed thereon can be aligned with the desired (111) orientation.

For example, when the sum of the volume V ₁ and the volume V ₂ is 830 cm ³ and the total flow rate of the gas flowing through the line 5, that is, the Ar / O ₂ mixed gas or oxygen gas is 2000 SCCM, the time T As a result, a value of about 25 seconds (= 830/2000 × 60 sec) is obtained, and each of the “gas stabilization step 1” and the “gas stabilization step 2” is performed for a time of 25 seconds or more. It is possible to stabilize the atmosphere in the “film deposition step” and “second film deposition step”.

  FIG. 8 shows a case where, in the recipe of FIG. 6, the periods of the “gas stabilization step 1” and “gas stabilization step 2” are changed variously as shown in process sequences 1 to 3 shown in Table 1 below. FIG. 3 is a diagram showing a change in (111) diffraction intensity from the PZT film 47 for each wafer in comparison with the result of FIG. 2. However, in FIG. 8, the experiment “A” corresponds to the experiment of FIG. 2, and as shown in the sequence 1 of Table 1, the “gas stabilization process 1” and the “gas stabilization process 2” are both performed for 5 seconds. The case where only it went is shown. On the other hand, in FIG. 8, the experiments “B” and “C” correspond to the above sequences 2 and 3, respectively. In sequence 2, the “gas stabilization step 1” is performed for 30 seconds, and the “gas stabilization step 2” is performed. The sequence is performed for 5 seconds, and in the sequence 3, the “gas stabilization step 1” is performed for 30 seconds, and the “gas stabilization step 2” is also performed for 30 seconds. In any of the above-described sequences 1 to 3, the formation of the PZT films 46 and 47 is described in relation to the recipe of FIG. 6 except for the “gas stabilization step 1” and “gas stabilization step 2”. The same conditions are used. Note that FIG. 2 described above is a result obtained by actually obtaining the PZT films 46 and 47 in a state before patterning them into the individual ferroelectric capacitors C1 and C2.

図８を参照するに、前記「Ａ」の実験では、先にも説明したようにＰＺＴ膜４７からの（１１１）回折ピークの積分強度がウェハ毎に２０％近くもばらつくのに対し、前記「Ｂ」および「Ｃ」の実験では、ばらつきはほとんどなくなり、しかも図２の実験におけるもっとも高い配向率が、再現性よく実現されているのがわかる。また図８の結果から、前記ＰＺＴ膜４６，４７の配向にもっとも影響があるのは、前記「ガス安定工程１」であることがわかる。

Referring to FIG. 8, in the experiment “A”, as described above, the integrated intensity of the (111) diffraction peak from the PZT film 47 varies by nearly 20% from wafer to wafer. In the experiments of “B” and “C”, there is almost no variation, and the highest orientation ratio in the experiment of FIG. 2 is realized with good reproducibility. Further, from the result of FIG. 8, it is understood that the “gas stabilizing process 1” has the most influence on the orientation of the PZT films 46 and 47.

  That is, according to the present embodiment, when the PZT film is formed while switching the atmosphere from one atmosphere to the next atmosphere as shown in FIG. 6, between the one atmosphere and the next atmosphere, respectively. Of the PZT film in the next step by providing a gas stabilization step for a time sufficient for the gas in the mixing chamber of the shower line and the gas line for supplying the atmospheric gas to the MOCVD apparatus to be replaced Can be stably performed, and a high orientation ratio can be realized. Here, the orientation ratio is the X-ray diffraction peak intensity corresponding to the (001) / (100), (101) / (110), and (222) planes of the PZT film 47 by the θ-2θ method of X-ray diffraction. Measured and calculated according to (222) strength / {(001) / (100) strength + (101) / (110) strength + (222) strength} × 100%, and the larger the value, the stronger ( 111) It means that orientation has occurred.

Note that the above description is not limited to the case where the ferroelectric films 46 and 47 are PZT films, and the ferroelectric films 46 and 47 may be formed of a ferroelectric film having an ABO ₃ type perovskite structure. The metal elements that occupy the A seat include Bi, Pb, Ba, Sr, Ca, Na, K, and rare earth elements, and the metal elements that occupy the B seat include Ti, Zr, Nb, Ta, W, It may contain Mn, Fe, Co, Cr or the like.

  The conductive oxygen barrier film 71 is not limited to a TiAlN film, and an Ir film or a Ru film can also be used.

  Further, the orientation control film 70 is not limited to a Ti film or a TiN film, but is composed of a Pt film, an Ir film, a Re film, a Ru film, a Pd film, an Os film, or an alloy of elements constituting these films. It is also possible to do. As the orientation control film 70, a single layer film or a multilayer film made of any of Ti, Al, Ir, Pt, Ru, Pd, Os, Rh, PtOx, IrOx, RuOx, and PdOx can be used. .

Further, the lower electrode layer 45 is not limited to Ir, and may be composed of Ru, Pt, or the like.

[Second Embodiment]
Incidentally, the result of FIG. 8 shows that the ferroelectric capacitor structure including the PZT films 46 and 47 is formed on the silicon wafer having a diameter of 20 cm by the steps of FIGS. 3 (A) to 3 (E). Although the result was obtained for the central portion, the inventor of the present invention investigated the in-plane distribution of the X-ray diffraction peak integrated intensity from the PZT (111) plane in the research that is the basis of the present invention. As a result, as shown in FIG. 9, it has been found that an in-plane distribution in which the intensity of the (111) diffraction peak is reduced occurs in the peripheral portion of the wafer. The results of FIG. 9 show that the PZT film 46 in the semiconductor chip taken from the peripheral portion of the wafer even when the optimized recipe of FIG. 6 is used in the steps shown in FIGS. 3 (A) to 3 (E). , 47 is not necessarily optimized as described in FIG. 8 above.

  The inventor of the present invention conducted an intensive investigation on the cause of the in-plane distribution generated in the crystal orientation of the PZT film as shown in FIG. 9 above, and as shown in FIG. It has been found that the deposition of impurities made of Pb (lead) occurs, and the amount of deposited Pb impurities tends to increase toward the outer periphery of the wafer. In FIG. 10, after the PZT film is formed repeatedly according to the recipe of FIG. 8 in the MOCVD apparatus 1 of FIG. 4, the substrate W to be processed is taken out from the processing container 1A and a new test wafer W is introduced. 8 shows the distribution of Pb impurities deposited on the test wafer when only the “temperature raising step” in FIG. 8 is performed.

The relationship of FIG. 10 is that when depositing a ferroelectric film containing Pb having a high vapor pressure, such as a PZT film, on the substrate W to be processed in the MOCVD apparatus 1 of FIG. In the upper surface of 1B, deposition of Pb occurs in the exposed portion around the substrate to be processed W, and the Pb deposited in such a portion contaminates the peripheral portion of the wafer serving as the substrate to be processed W as the impurity. In addition, as a result of the PZT films 46 and 47 being deposited on such impurities, the orientation is shifted from the desired (111) orientation. It should be noted that Pb has a vapor pressure on the order of 10 ⁻⁴ Torr at a temperature of 550 ° C. used for forming the PZT film.

  Therefore, in the present embodiment, after the processing of one wafer is completed and the wafer is taken out, and before the start of the next wafer processing, a process of purging the inside of the processing container 1A by purging is provided. A semiconductor device manufacturing method is provided in which the next wafer is introduced into the processing container 1A after such a purging step.

  FIG. 11 shows an example of a pressure recipe used in the film forming process of the PZT films 46 and 47 according to the present embodiment including such a purge process, and FIG. 12 shows the MOCVD of FIG. 4 to which the recipe of FIG. 11 is applied. The apparatus 1 is shown including the substrate transfer system. In FIG. 12, the parts described above are denoted by the same reference numerals, and description thereof is omitted.

  First, referring to FIG. 12, in the present embodiment, the processing vessel 1A of the MOCVD apparatus 1 constitutes a part of a single-wafer substrate processing apparatus and is coupled to the vacuum transfer chamber 6 through a gate valve 6G. The vacuum transfer chamber 6 is coupled to a load lock chamber 7 through a gate valve 7G.

Referring to the recipe of FIG. 11, first, in the “wafer introduction, O ₂ gas introduction” step, the substrate W to be processed is introduced into the processing container 1A of the processing apparatus 1 from the vacuum transfer chamber 6, and the pressure is increased to 533 Pa. Then, the “temperature raising step” in FIG. 6 is executed. Further, after the “Ar / O ₂ gas switching + stabilization” step corresponding to the atmosphere switching and “gas stabilization step 1” in FIG. 6, the “first film deposition step”, “gas” in the recipe of FIG. "Deposition process first and second" corresponding to "stabilization process 2" and "" second film deposition process "are executed, and then the valve 4A is closed and closed in the MOCVD apparatus 1 of FIG. 4 or FIG. By opening 4B, the supply of the raw material gas to the processing container 1A is shut off. Further, in the “O ₂ + Ar gas stop, wafer removal” process, the supply of Ar gas and oxygen gas from the MFC 5A and MFC 5B is shut off, the gate valve 6G is opened, and the substrate W to be processed in the processing container 1A is opened. It is taken out into the vacuum transfer chamber 6. The substrate W thus taken out is returned to the load lock chamber 7 from the vacuum transfer chamber 6 by further opening the gate valve 7G, while the next substrate W ′ to be processed waiting in the load lock chamber 7 is transferred. Then, it is introduced into the vacuum transfer chamber 6 through the gate valve 7G and waits.

Furthermore, by performing the steps from the “wafer introduction, O ₂ gas introduction” step to “O ₂ + Ar gas stop, wafer removal” with respect to the next substrate to be processed W ′ on standby, the PZT Films 46 and 47 are formed on the surface of the substrate to be processed W ′.

In the recipe of FIG. 11, in the “O ₂ + Ar gas stop, wafer removal” step, after the substrate W is taken out in this way, the gate valve 6G is closed, and the inside of the processing container 1A is closed. The vacuum pump 2P reduces the pressure to a pressure of, for example, about 10 ⁻¹ Pa, which is lower than the pressure (533 Pa) used for the deposition of the PZT films 46 and 47, and the inside of the processing vessel 1A is, for example, 60 seconds or more. By evacuating, a vacuum purge of the processing container 1A (“processing container purging process”) is performed.

  In FIG. 13, after performing such vacuum purging for 30 seconds, 60 seconds and 120 seconds, the next substrate to be processed W ′ is introduced into the processing container 1A, and the PZT is placed on the next substrate to be processed W ′. The result of having calculated | required the in-plane distribution of the integrated intensity | strength of the X-ray-diffraction peak from a PZT (111) surface at the time of forming film | membrane 46 and 47 similarly is shown. In the figure, “30 sec purge” is the in-plane distribution shown in FIG.

  Referring to FIG. 13, when the “processing vessel purge process” in the recipe of FIG. 11 is performed for 30 seconds, the (111) orientation ratio of the PZT films 46 and 47 greatly decreases in the region where the width of the peripheral portion of the wafer is about 30 mm. In this region, it is considered that Pb deposition as shown in FIG. 14 occurs. However, the in-plane non-uniformity is greatly improved only by performing the “processing vessel purge step” for 60 seconds. It is understood that the in-plane non-uniformity can be substantially completely removed by performing the “processing vessel purge step” for 120 seconds.

  FIG. 14 shows the recipe of FIG. 11 in which the “processing container purging process” is performed for 120 seconds, and then the next substrate to be processed W ′ is introduced into the processing container 1A, and the process up to the “temperature raising process” is performed. FIG. 11 is a diagram showing the distribution of Pb on the surface of the substrate W ′ to be processed in comparison with the distribution described above with reference to FIG. 10. Similar to FIG. 10, FIG. 14 shows the distribution of Pb for the outer peripheral portion having a width of 30 mm.

Referring to FIG. 14, the “control standard” is the distribution shown in FIG. 10, and the “invention” is the case where the “processing vessel purge step” is not performed. The case where the “processing vessel purge step” is performed for 120 seconds at a pressure of 10 ⁻¹ Pa as described above is shown.

  Referring to FIG. 14, by performing such a purging step, it is possible to significantly reduce the proportion of Pb particles that are deposited on the substrate to be processed prior to the formation of the PZT film. Recognize.

  In the recipe of FIG. 11, the “processing vessel purge step” starts from vacuum purging the processing vessel 11, and as shown in FIG. 15, first, the pressure in the processing vessel is changed to the PZT film 46, It is also possible to temporarily increase the pressure at the time of film formation of 47c and then to reduce the pressure as in the recipe of FIG. In the recipe of FIG. 11, since the pressure temporarily increases during the “processing vessel purge step”, the exhaust efficiency by the vacuum pump 2P is improved.

  Alternatively, in the recipe of FIG. 11, as shown in FIG. 16, the temperature of the susceptor 1 </ b> B is changed from the temperature at which the PZT films 46 and 47 are formed, for example, 620 ° C. It is also possible to raise the temperature to a high value, for example, 650 ° C. In this way, by raising the susceptor temperature during the “processing vessel purge step”, vaporization of Pb impurities that accumulate on the susceptor and contaminate the substrate to be processed is promoted, and the purge efficiency is improved.

Alternatively, in the recipe of FIG. 11, as shown in FIG. 17, during the “processing container purge step”, the pressure of the processing container 1 </ b> A is changed during the deposition of the PZT films 46 and 47, as in the recipe of FIG. 11. The pressure may be reduced to 533 Pa or less, for example, 10 ⁻¹ Pa or less, and at the same time, Ar gas may be supplied from the MFC 5A at a flow rate of 1000 SCCM, for example, and the inside of the processing vessel 1A may be purged with Ar gas. According to this configuration, the purge efficiency inside the processing container 1A can be improved.

[Third Embodiment]
Hereinafter, a manufacturing process of the ferroelectric memory according to the third embodiment of the present invention will be described with reference to FIGS.

  Referring to FIG. 18A, an n-type well is formed as an element region 61A in a silicon substrate 61. On the element region 61A, a first MOS transistor having a polysilicon gate electrode 63A and a polysilicon gate are formed. A second MOS transistor having an electrode 63B is formed through gate insulating films 62A and 62B, respectively.

The further in the silicon substrate 61, the p in correspondence to respective sidewalls of the gate electrode 63A ^- -type LDD region 61a, and 61b are formed, also in correspondence to respective sidewalls of the gate electrode 13B p ^- -type LDD regions 61c and 61d are formed. Here, since the first and second MOS transistors are formed in common in the element region 61A, the same p ⁻ type diffusion region is shared as the LDD region 61b and the LDD region 61c.

  A silicide layer 64A is formed on the polysilicon gate electrode 63A, and a silicide layer 64B is formed on the polysilicon gate electrode 63B. Further, both side walls of the polysilicon gate electrode 63A and the polysilicon gate are formed. Each side wall insulating film is formed on both side wall surfaces of the electrode 63B.

Further, in the silicon substrate 61, p ⁺ type diffusion regions 61e and 61f are formed outside the respective side wall insulating films of the gate electrode 63A, and each of the side wall insulating films of the gate electrode 63B is formed. On the outside, p ⁺ -type diffusion regions 61g and 61h are formed. However, the diffusion regions 61f and 61g are composed of the same p ⁺ -type diffusion region.

Further, on the silicon substrate 61, the gate electrode 63A is covered including the silicide layer 64A and the sidewall insulating film, and the gate electrode 63B is covered including the silicide layer 64B and the sidewall insulating film. The SiON film 65 is formed to a thickness of 200 nm, for example, and an interlayer insulating film 66 made of SiO ₂ is formed on the SiON film 65 by a plasma CVD method using TEOS as a material to a thickness of 1000 nm, for example. ing. Further, the interlayer insulating film 66 is planarized by CMP, and contact holes 66A, 66B, 66C are exposed in the interlayer insulating film 66 so as to expose the diffusion regions 61e, 61f (and hence the diffusion regions 61g), 61h, respectively. Is formed. Via plugs 67A, 67B made of W (tungsten) are formed in the contact holes 66A, 66B, 66C via adhesion layers 67a, 67b, 67c in which a Ti film having a thickness of 30 nm and a TiN film having a thickness of 20 nm are laminated. , 67C are formed.

Further, in the structure of FIG. 18A, the next interlayer insulating film 68 made of a silicon oxide film is formed on the interlayer insulating film 66 through another SiON film 67 having a thickness of, for example, 130 nm in the same manner as the interlayer insulating film 66. The film is formed to a thickness of, for example, 300 nm by a plasma CVD method using TEOS as a raw material. Here, instead of the SiON film 67, an SiN film or an Al ₂ O ₃ film can be used.

  Next, in the step of FIG. 18B, via holes 68A and 68C that expose the via plugs 67A and 67C are formed in the interlayer insulating film 68, respectively, and the via holes 68A are made of tungsten so as to be in contact with the via plug 67A. 69A is formed through an adhesion layer 69a in which the same Ti film and TiN film as the adhesion layer 67a are laminated. A via plug 69C is formed in the via hole 68C to be in contact with the via plug 67C through a contact layer 69c formed by laminating a Ti film and a TiN film similar to the contact layer 67c.

Next, in the step of FIG. 18C, the surface of the interlayer insulating film 68 is treated with NH ₃ plasma, NH groups are bonded to oxygen atoms on the surface of the interlayer insulating film 68, and then the Ti film 70 is sputtered to form the interlayer insulating film 68. For example, a thickness of 20 nm is formed on the insulating film 68 so as to cover the via plugs 69A and 69B under the same conditions as those of the Ti film 42 shown in FIG. By treating the surface of the interlayer insulating film 68 with NH ₃ plasma in this way, the oxygen atoms on the surface of the interlayer insulating film 68 are terminated by NH groups, and are preferentially bonded to Ti atoms to have their orientation. Since there is no restriction, the Ti film 70 has an ideal (002) orientation.

  Further, in FIG. 18C, the Ti film 70 is rapidly heat-treated in a nitrogen atmosphere at a temperature of 650 ° C. to convert it into a (111) -oriented TiN film 70.

  Next, in the process of FIG. 18D, a TiAlN film 71 is formed on the TiN film 70 as an oxygen diffusion barrier under the same conditions as the TiAlN film 43 of FIG. 3A, and in the process of FIG. 14E, Similar to the lower electrode 45 of FIG. 3B, an Ir film having a thickness of about 100 nm is laminated on the TiAlN film 71 by sputtering to form a lower electrode layer 73.

  Next, in the step of FIG. 18F, the first PZT film 74A is formed on the Ir lower electrode 73 of FIG. 14E in the same manner as in the steps of FIGS. 3C and 5A to 5C. According to the MOCVD method, the film is deposited to a thickness of 1 to 50 nm according to the recipe of FIG. 6 at a film forming temperature of 620 ° C. under a pressure of 533 Pa.

  Further, in the step of FIG. 18G, the second PZT film 74B is formed on the first PZT film 74A by the MOCVD method at 620 ° C. under the pressure of 533 Pa, similarly to the PZT film 47 of FIG. At a film temperature, the film is formed to a thickness of, for example, 80 nm according to the recipe of FIG.

  As described above, the PZT film 74A formed in this way exhibits a strong (111) orientation. Therefore, the PZT film 74B formed thereon also has a strong (111) orientation of the PZT film 74A. Inherit.

  As described above, the lower electrode layer 73 may be formed of a noble metal such as Pt, Ru, Rh, Re, Os other than Ir. In this case, the first PZT film 74A contains a metal element constituting the lower electrode film 73.

  Next, in the step of FIG. 18H, an upper electrode 76 made of iridium oxide is formed on the PZT film 74B.

  More specifically, first, a first iridium oxide film having a non-stoichiometric composition IrOx film on the PZT film 74B having a thickness of 50 nm is crystallized at the time of film formation by a sputtering method. Form. For example, the first iridium oxide film is formed by sputtering an Ir target at a power of 1 to 2 kW while supplying Ar gas and oxygen gas at a flow rate of 100 SCCM at a film forming temperature of 300 ° C. Is done. By forming the first iridium oxide film in a non-stoichiometric composition, excess Pb in the PZT film 74B under the first iridium oxide film is absorbed in the first iridium oxide film, and the PZT film 74B and the upper electrode 76 are absorbed. The problem of peeling at the interface is eliminated.

  Further, in the process of FIG. 18H, the first iridium oxide film thus obtained is supplied at a temperature of 725 ° C. in an atmosphere in which oxygen gas is supplied at a flow rate of 20 SCCM and Ar gas is supplied at a flow rate of 2000 SCCM. Rapid heat treatment is performed for 60 seconds to recover the plasma damage of the first iridium oxide film. At the same time, oxygen vacancies in the PZT films 74A and 74B are compensated, and at the same time, the PZT films 74A and 74B are completely crystallized.

Further, in the step of FIG. 18H, the second iridium oxide film is formed on the first iridium oxide film having the non-stoichiometric composition thus formed at a power of 1.0 kW under a pressure of 0.8 Pa. By sputtering, it is formed to have a film thickness of 100 to 300 nm and to have a composition closer to the stoichiometric composition than the first iridium oxide film. As a result, the problem that the PZT films 74A and 74B are reduced by hydrogen radicals generated by the catalytic action of Ir is reduced, and the hydrogen resistance of the formed ferroelectric capacitor is improved. The upper electrode 76 may be Ir, Ru, Rh, Re, Os, Pd, or a conductive oxide thereof, or a conductive oxide such as SrRuO ₃ , or a laminate thereof, instead of iridium oxide. Can be used.

  Further, in the upper electrode 76 of FIG. 18H, although not shown, an Ir film as a hydrogen barrier film and a conductivity improving film is formed on the second iridium oxide film by sputtering in an Ar atmosphere under a pressure of 1 Pa. The film is deposited to a thickness of 50 to 100 nm with a power of 1.0 kW. As the hydrogen barrier film, it is possible to use a Ru film, a Rh film, a Pd film, or the like in addition to the Ir film.

  Next, after the step of FIG. 18H, the substrate back surface is cleaned, and in the step of FIG. 18I, the TiAlN film 77 and the silicon oxide film 78 are respectively formed on the upper electrode 76 using the reactive sputtering method and the TEOS raw material. A hard mask layer is formed by plasma CVD.

  Further, in the step of FIG. 18J, the silicon oxide film 78 is patterned to form hard mask patterns 78A and 78C corresponding to desired ferroelectric capacitors C1 and C2.

In the next step of FIG. 18K, the TiAlN film 77, the upper electrode layer 76, the PZT films 74 and 75, the lower electrode layer 73, and the Al ₂ O ₃ film are formed using the hard mask patterns 78A and 78B as a mask. Until the TiAlN film 71 is exposed, patterning is performed by dry etching using HBr, O ₂ , Ar, and C ₄ F ₈ , and a lower portion corresponding to the ferroelectric capacitor C 1 is formed under the hard mask pattern 78 A. The structure in which the electrode layer 73, the PZT films 74A and 74B, the upper electrode layer 76, and the TiAlN mask pattern 77A are stacked corresponds to the ferroelectric capacitor C2 below the hard mask pattern 76C. , PZT films 74A and 74B, an upper electrode layer 76, and a TiAlN mask pattern 77C are stacked. A structure is obtained.

  Next, in the step of FIG. 18L, the hard mask patterns 78A and 78C are removed by dry etching or wet etching, and in the step of FIG. 18M, the TiN on the interlayer insulating film 68 is formed using the ferroelectric capacitors C1 and C2 as a mask. The film 70 and the TiAlN film 71 thereon are removed by dry etching, and a structure in which a TiN pattern 70A and a TiAlN pattern 71A are stacked under the lower electrode layer 73 is formed in each of the capacitors C1 and C2.

Further, in the step of FIG. 18N, the interlayer insulating film 68 exposed in the step of FIG. 18M is very thin and has a film thickness so as to continuously cover the side wall surface and the upper surface of the ferroelectric capacitors C1 and C2. An Al ₂ O ₃ film 79 of 20 nm or less is formed as a hydrogen barrier film by sputtering or ALD, and then heat treatment is performed at 550 to 750 ° C., for example, 650 ° C. in an oxygen atmosphere in the step of FIG. In the PZT films 74A and 74B in the ferroelectric capacitors C1 and C2, damage caused by the dry etching process of FIG. 18M is recovered.

Further, in the step of FIG. 18P, the next Al ₂ O ₃ film 80 is formed on the Al ₂ O ₃ film 79 of FIG. 18O to a film thickness of, for example, 20 nm by the MOCVD method. In the plasma CVD method, an interlayer insulating film 81 made of a silicon oxide film is formed by using a mixed gas of TEOS, oxygen and helium so as to cover the Al ₂ O ₃ hydrogen barrier films 79 and 80 formed in this way. Thus, a film thickness of 1500 nm is formed. In the step of FIG. 18Q, the surface of the interlayer insulating film 81 formed in this way is flattened by the CMP method, and then heat-treated in plasma using N ₂ O or nitrogen gas. Remove moisture. Further, in the step of FIG. 18Q, an Al ₂ O ₃ film 82 is formed as a hydrogen barrier film on the interlayer insulating film 81 to a thickness of 20 to 100 nm by sputtering or MOCVD. In the process of FIG. 18Q, the interlayer insulating film 81 has a film thickness of, for example, 700 nm as a result of the planarization process by the CMP method.

  Next, in the step of FIG. 18R, an interlayer insulating film 83 made of a silicon oxide film is formed on the hydrogen barrier film 82 to a thickness of 300 to 500 nm by the plasma CVD method using a TEOS material. In the step of FIG. A via hole 83A exposing the upper electrode 76A of the ferroelectric capacitor C1 and a via hole 83C exposing the upper electrode 76C of the ferroelectric capacitor C2 are formed in the interlayer insulating film 83.

  Further, in the step of FIG. 18S, heat treatment is performed in an oxidizing atmosphere through the via holes 83A and 83C formed in this way, and the PZT films 74A, 75A, 74C, and 75C are generated along with the via hole forming step. Compensate for oxygen deficiency.

  Next, the bottom and inner wall surfaces of the via holes 83A and 83C are respectively covered with barrier metal films 84a and 84c made of a single layer film of TiN, the via hole 83A is filled with a tungsten plug 84A, and the via hole 83C is filled with a tungsten plug 84C. To do.

  Further, after the formation of the tungsten plugs 84A and 84C, a via hole 83B exposing the via plug 67B is formed in the interlayer insulating film 83, and this is filled with the tungsten via plug 84B. Note that the tungsten via plug 84B is accompanied by an adhesion film 84b having a Ti / TiN laminated structure as usual.

  Further, in the step of FIG. 18T, a wiring pattern 85A made of an AlCu alloy corresponding to the via plug 84A is sandwiched between the adhesion films 85a and 85d of the Ti / TiN laminated structure on the interlayer insulating film 83, A wiring pattern 85B made of an AlCu alloy corresponding to the via plug 84B is sandwiched between the adhesion films 85b and 85e of the Ti / TiN laminated structure, and a wiring pattern 85C made of an AlCu alloy corresponding to the via plug 85C is It is formed so as to be sandwiched between adhesion films 85c and 85f having a Ti / TiN laminated structure.

  Further, a further wiring layer is formed on the structure of FIG. 18T as necessary.

  As described above, the metal element contained in the first PZT film 74A is not limited to Ir, and enters the B-seat of the perovskite structure to make the tetragonal PZT unit cell more cubic. It is also possible to use Ru, Rh, Re, Os, Pd or the like having an ionic radius that approaches.

  At this time, the introduction of these metal elements into the PZT film 74A is not limited to diffusion from the lower electrode. For example, as described in the ion implantation and the modification of the first embodiment, It is also possible to introduce it by simultaneously supplying an Ir raw material during film formation.

  In this embodiment, the ferroelectric films 74A and 74B are PZT films, but may be PLZT films containing La.

Further, the ferroelectric films 74A and 74B are not limited to PZT films, and may be formed of a ferroelectric film having an ABO ₃ type perovskite structure containing Pb, for example, a metal that occupies the A seat. The elements include Bi, Pb, Ba, Sr, Ca, Na, K, and rare earth elements, and the metal elements that occupy the B seat include Ti, Zr, Nb, Ta, W, Mn, Fe, Co, It may contain Cr or the like.

  The conductive oxygen barrier film 71 is not limited to a TiAlN film, and an Ir film or a Ru film can also be used.

  Further, the orientation control film 70 is not limited to a Ti film or a TiN film, but is composed of a Pt film, an Ir film, a Re film, a Ru film, a Pd film, an Os film, or an alloy of elements constituting these films. It is also possible to do. As the orientation control film 70, a single layer film or a multilayer film made of any of Ti, Al, Ir, Pt, Ru, Pd, Os, Rh, PtOx, IrOx, RuOx, and PdOx can be used. .

  Further, when such a ferroelectric memory is manufactured one after another on a large number of silicon wafers using the MOCVD apparatus 1 described with reference to FIGS. 4 and 12, the processing of one silicon wafer is completed. At the time when the silicon wafer is taken out, the processing container of the MOCVD apparatus 1 is purged according to the recipe of FIG. 11 or FIGS. 15 to 17 so that the PZT films 46 and 47 on the silicon wafer to be processed next are , (111) orientation in-plane distribution can be improved.

As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.
(Appendix 1)
A method of manufacturing a semiconductor device including a ferroelectric film,
A processing container exhausted by an exhaust device, a raw material gas supply line for supplying a raw material gas into the processing container, and an atmosphere for supplying at least first and second atmospheric gases into the processing container in the form of a mixed gas A process for forming a ferroelectric film by a metal organic vapor phase deposition method performed using a metal metal deposition apparatus equipped with a gas line,
The processing vessel is connected to the source gas line and the atmosphere gas line, and mixes the source gas and the mixed gas to form a processing gas, and releases the processing gas into the processing vessel. With
The atmosphere gas line extends from the first and second flow rate control means for supplying the first and second atmosphere gases at respective flow rates to the mixing / releasing unit,
The film formation process of the ferroelectric film includes:
(A) switching the atmosphere in the processing container holding the substrate to be processed on which the semiconductor device is formed from a first atmosphere to a second atmosphere;
(B) In the processing container, in the second atmosphere, a ferroelectric film is formed on the substrate to be processed by using an organic metal compound supplied from the source gas supply line as a raw material by a metal organic vapor deposition method. Forming a film, and
The step (B) is started by starting the supply of the source gas to the processing container after a predetermined gas stabilization time after the step (A),
The predetermined gas stabilization time is obtained by dividing the total volume V of the volume of the atmospheric gas line and the volume of the mixing / releasing portion by the flow rate L of the mixed gas in the atmospheric gas line (V / L) A method for manufacturing a semiconductor device, characterized by being set to the above.
(Appendix 2)
A processing container exhausted by an exhaust device, a raw material gas supply line for supplying a raw material gas into the processing container, and an atmosphere for supplying at least first and second atmospheric gases into the processing container in the form of a mixed gas A method of manufacturing a semiconductor device having a ferroelectric capacitor, including a film formation process of a ferroelectric film by a metal organic vapor phase deposition method performed using an organic metal deposition apparatus including a gas line,
The processing vessel is connected to the source gas line and the atmosphere gas line, and mixes the source gas and the mixed gas to form a processing gas, and releases the processing gas into the processing vessel. With
The atmosphere gas line extends from the first and second flow rate control means for supplying the first and second atmosphere gases at respective flow rates to the mixing / releasing unit,
(A) introducing a substrate to be processed in which a lower electrode is formed into the processing container;
(B) After the step (A), the flow rate of the first atmosphere gas is set to the first flow rate and the flow rate of the second atmosphere gas is set to the second flow rate including zero after the step (A). A step of raising the temperature in the set first atmosphere;
(C) After the step (B), the flow rate of the first atmospheric gas is decreased from the first flow rate to the third flow rate, and the flow rate of the second atmospheric gas is changed from the second flow rate to the second flow rate. Changing the first atmosphere to a second atmosphere by increasing the flow rate to 4;
(D) after the step (C), forming a ferroelectric film on the lower electrode by supplying the source gas into the processing vessel from the source gas supply line,
The step (D) is started by starting the supply of the source gas to the processing container after a predetermined gas stabilization time after the step (C),
The predetermined gas stabilization time is obtained by dividing the total volume V of the volume of the atmospheric gas line and the volume of the mixing / releasing portion by the flow rate L of the mixed gas in the atmospheric gas line (V / L) A method for manufacturing a semiconductor device, characterized by being set to the above.
(Appendix 3)
Further, after the step (D), (E) the flow rate of the first atmospheric gas is increased from the third flow rate to the fifth flow rate, and the flow rate of the second atmospheric gas is increased from the fourth flow rate. A step of switching the second atmosphere to a third atmosphere by reducing the flow rate to a sixth flow rate including zero; (F) after the step (E), another ferroelectric on the ferroelectric film; Forming a body film by supplying the source gas into the processing vessel from the source gas supply line, and the step (F) includes the predetermined step after the step (E). 3. The method of manufacturing a semiconductor device according to appendix 2, wherein the method is started by starting the supply of the source gas to the processing container after the gas stabilization time has elapsed.
(Appendix 4)
4. The method of manufacturing a semiconductor device according to claim 1, wherein the first atmosphere gas is an oxygen gas, and the second atmosphere gas is an Ar gas.
(Appendix 5)
Of the supplementary notes 2 to 4, wherein in the step (D) and the step (F), the source gas supply path is switched from the preflow line connected to the exhaust device to the source gas line. A manufacturing method of a semiconductor device given in any 1 paragraph.
(Appendix 6)
6. The method of manufacturing a semiconductor device according to any one of appendices 2 to 5, wherein the mixing / discharging unit is a shower head.
(Appendix 7)
The source gas contains Pb (lead), and after the step (F), (G) a step of taking out the substrate to be processed from the processing vessel, and (H) after the step (G), the processing vessel The method for manufacturing a semiconductor device according to appendix 3, wherein the steps (A) to (F) are repeated after the step of exhausting air and the step (H).
(Appendix 8)
The method of manufacturing a semiconductor device according to appendix 7, wherein the step (H) is performed with a pressure in the processing container set lower than that in the step (F).
(Appendix 9)
The process (H) is performed by setting the pressure in the processing container to be higher than that in the process (F) first and then lower than that in the process (F). The manufacturing method of the semiconductor device of description.
(Appendix 10)
The method of manufacturing a semiconductor device according to claim 9, wherein the step (H) is performed by introducing an inert gas as a purge gas into the processing container.
(Appendix 11)
8. The semiconductor device according to appendix 7, wherein in the step (H), the temperature of a susceptor that holds the substrate to be processed in the processing container is set higher than in the step (F). Manufacturing method.
(Appendix 12)
The processing container is coupled to a vacuum transfer chamber. In the step (A), the substrate to be processed is introduced from the vacuum transfer chamber into the processing container. In the step (G), the substrate to be processed is the processing container. Returning to the said vacuum conveyance chamber, The manufacturing method of the semiconductor device of Claim 3 characterized by the above-mentioned.

It is a figure which shows the structure of the ferroelectric memory by the related technique of this invention. It is a figure which shows the subject of this invention. It is a figure which shows the formation process of the ferroelectric memory by the 1st Embodiment of this invention. It is a figure which shows the structure of the MOCVD apparatus used at the process of FIG. It is a figure explaining the process of FIG.3 (C) in detail. It is a figure which shows the example of the recipe used by 1st Embodiment. It is a figure which shows schematically the MOCVD apparatus of FIG. It is a figure explaining the effect of a 1st embodiment. It is a figure explaining the subject of the 2nd Embodiment of this invention. It is another figure explaining the subject of 2nd Embodiment. It is a figure explaining the example of the recipe used by 2nd Embodiment. It is a figure which shows the MOCVD apparatus of FIG. 4 including a board | substrate conveyance system. It is a figure explaining the effect of 2nd Embodiment. It is another figure explaining the effect of 2nd Embodiment. It is a figure explaining the modification of the recipe used by 2nd Embodiment. It is a figure explaining another modification of the recipe used by 2nd Embodiment. It is a figure explaining another modification of the recipe used by a 2nd embodiment. It is FIG. (1) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (2) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (3) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (4) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (5) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (6) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (7) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (8) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (9) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (10) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (11) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (12) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (13) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (14) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (15) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (16) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (17) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (18) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (19) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (20) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention.

Explanation of symbols

41 Insulating layer 42, 70 Ti film 43, 71 TiAlN film 45, 73 Lower electrode 46, 74A First PZT film 47, 74B Second PZT film 48, 76 Upper electrode 61 Substrate 61A Element region 61I Element isolation structure 61a to 61f Diffusion region 62A, 62B Gate insulating film 63A, 63B Gate electrode 64A, 64B Gate silicide layer 65, 67 SiON film 66, 68, 81, 83 Interlayer insulating film 66A, 66B, 66C, 68A, 68C, 83A, 83B, 83C Via hole 67A to 67C, 69A, 69C, 84A to 84C Via plug 67a, 67b, 67c, 69a, 69c, 84a, 84b, 84c Adhesion film 78 Hard mask film 78A, 78B Hard mask pattern 79, 80 Al ₂ O ₃ hydrogen barrier film 85A, 85B, 85C Pattern - down

Claims (6)

A method of manufacturing a semiconductor device including a ferroelectric film,
A processing container exhausted by an exhaust device, a raw material gas supply line for supplying a raw material gas into the processing container, and an atmosphere for supplying at least first and second atmospheric gases into the processing container in the form of a mixed gas A process for forming a ferroelectric film by a metal organic vapor phase deposition method performed using an organic metal deposition apparatus equipped with a gas line,
The processing vessel is connected to the source gas line and the atmosphere gas line, and mixes the source gas and the mixed gas to form a processing gas, and releases the processing gas into the processing vessel. With
The atmosphere gas line extends from the first and second flow rate control means for supplying the first and second atmosphere gases at respective flow rates to the mixing / releasing unit,
The film formation process of the ferroelectric film includes:
(A) switching the atmosphere in the processing container holding the substrate to be processed on which the semiconductor device is formed from a first atmosphere to a second atmosphere;
(B) In the processing container, in the second atmosphere, a ferroelectric film is formed on the substrate to be processed by using an organic metal compound supplied from the source gas supply line as a raw material by a metal organic vapor deposition method. Forming a film, and
The step (B) is started by starting the supply of the source gas to the processing container after a predetermined gas stabilization time after the step (A),
The predetermined gas stabilization time is obtained by dividing the total volume V of the volume of the atmospheric gas line and the volume of the mixing / releasing portion by the flow rate L of the mixed gas in the atmospheric gas line (V / L) A method for manufacturing a semiconductor device, characterized by being set to the above. A processing container exhausted by an exhaust device, a raw material gas supply line for supplying a raw material gas into the processing container, and an atmosphere for supplying at least first and second atmospheric gases into the processing container in the form of a mixed gas A method of manufacturing a semiconductor device having a ferroelectric capacitor, including a film formation process of a ferroelectric film by a metal organic vapor phase deposition method performed using an organic metal deposition apparatus including a gas line,
The processing vessel is connected to the source gas line and the atmosphere gas line, and mixes the source gas and the mixed gas to form a processing gas, and releases the processing gas into the processing vessel. With
The atmosphere gas line extends from the first and second flow rate control means for supplying the first and second atmosphere gases at respective flow rates to the mixing / releasing unit,
(A) introducing a substrate to be processed in which a lower electrode is formed into the processing container;
(B) After the step (A), the flow rate of the first atmosphere gas is set to the first flow rate and the flow rate of the second atmosphere gas is set to the second flow rate including zero after the step (A). A step of raising the temperature in the set first atmosphere;
(C) After the step (B), the flow rate of the first atmospheric gas is decreased from the first flow rate to the third flow rate, and the flow rate of the second atmospheric gas is changed from the second flow rate to the second flow rate. Changing the first atmosphere to a second atmosphere by increasing the flow rate to 4;
(D) after the step (C), forming a ferroelectric film on the lower electrode by supplying the source gas into the processing vessel from the source gas supply line,
The step (D) is started by starting the supply of the source gas to the processing container after a predetermined gas stabilization time after the step (C),
The predetermined gas stabilization time is obtained by dividing the total volume V of the volume of the atmospheric gas line and the volume of the mixing / releasing portion by the flow rate L of the mixed gas in the atmospheric gas line (V / L) A method for manufacturing a semiconductor device, characterized by being set to the above.   Further, after the step (D), (E) the flow rate of the first atmospheric gas is increased from the third flow rate to the fifth flow rate, and the flow rate of the second atmospheric gas is increased from the fourth flow rate. A step of switching the second atmosphere to a third atmosphere by reducing to a sixth flow rate including zero; (F) after the step (E), another ferroelectric on the ferroelectric film; Forming a body film by supplying the source gas into the processing vessel from the source gas supply line, and the step (F) includes the predetermined step after the step (E). The method of manufacturing a semiconductor device according to claim 2, wherein the method is started by starting supply of the source gas to the processing container after a gas stabilization time has elapsed.   The method of manufacturing a semiconductor device according to claim 1, wherein the first atmospheric gas is an oxygen gas, and the second atmospheric gas is an Ar gas.   In the step (D) and the step (F), the source gas supply path is switched from a preflow line connected to the exhaust device to the source gas line. A method for manufacturing a semiconductor device according to claim 1.   The source gas contains Pb (lead), and after the step (F), (G) a step of taking out the substrate to be processed from the processing vessel, and (H) after the step (G), the processing vessel 4. The method of manufacturing a semiconductor device according to claim 3, wherein the steps (A) to (F) are repeated after the step of exhausting air and the step (H).

Images