JP2009157258A - Display device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the load of a driving circuit when driving a plurality of display members. <P>SOLUTION: A display device 100 includes a first display member 10 having pixels P1 connected to a plurality of data lines 17 respectively and a second display member 20 having pixels P2 connected to a plurality of data lines 27 respectively. A data line driving circuit 44 outputs data signals D[1] to D[n] to the plurality of data lines 17 respectively from the side opposite to the second display member 20, of the plurality of data lines 17, and n unit circuits Q[1] to Q[n] are disposed on the side opposite to the data line driving circuit 44, of the plurality of data lines 17. A unit circuit Q[j] in the j-th stage is interposed between the data line 17 in the j-th row of the first display member 10 and the data line 27 in th j-th row of the second display member and holds a data signal D[j] supplied to the data line 17 and then outputs it to the data line 27. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for displaying images on a plurality of display bodies.

An electronic device having a plurality of display bodies has been conventionally proposed. For example, in an electronic device typified by a mobile phone, a display body that displays an image on the front side and a display body that displays an image on the back side are installed. In Patent Documents 1 and 2, in a display device including a first display body and a second display body, a drive circuit (scanning line drive circuit or data line drive circuit) mounted on the first display body is first described. A technique is disclosed that is used for driving each pixel of one display body and driving each pixel of a second display body.
JP 2003-323164 A JP 2004-117755 A

  However, in the configurations of Patent Document 1 and Patent Document 2, since the wiring (for example, the scanning line and the data line) connected to the drive circuit is continuous over the first display body and the second display body, the drive circuit is one. Compared with the case where only the display body is driven, the load on the drive circuit becomes excessive. In view of the above circumstances, an object of the present invention is to reduce the load on a driving circuit when driving a plurality of display bodies.

  In order to solve the above problems, the display device according to the first aspect of the present invention includes a pixel on each of the plurality of first wirings (for example, the scanning lines 15 and the data lines 17 in FIGS. 1, 4, and 5). A first display body to which a pixel is connected, a second display body in which pixels are connected to each of a plurality of second wirings (for example, scanning lines 25 and data lines 27 in FIGS. 1, 4 and 5), and a plurality of A driving circuit that outputs a driving signal to each of the plurality of first wirings from the side opposite to the second display body with the first wiring interposed therebetween (for example, the data line driving circuit 44 in FIGS. 1 and 4 or the scanning line driving in FIG. 5). Circuit 42) and one of the first display body and the second display body, interposed between each first wiring and each second wiring, and holds a drive signal supplied to the first wiring. And a plurality of unit circuits that output to two wirings. In the above configuration, since the drive circuit is shared by the first display body and the second display body, the display is compared with the configuration in which the drive circuit is individually arranged on each of the first display body and the second display body. The configuration of the apparatus can be simplified. In addition, since the drive signal supplied to the first wiring is held in the unit circuit and then output to the second wiring, the driving circuit is compared with a configuration in which the first wiring and the second wiring are directly connected. The load of is reduced. In addition, the specific example of the display apparatus which concerns on a 1st aspect is later mentioned as 1st Embodiment (FIG. 1) or 2nd Embodiment (FIG. 5).

  In the display device according to the first aspect, each of the plurality of unit circuits includes, for example, a first holding unit (for example, holding a driving signal supplied to the first wiring in a first period of each of the plurality of unit periods. 2 and the first output means for outputting the drive signal held by the first holding means to the second wiring in the second period in each of the plurality of unit periods (for example, the output part 513 in FIG. 2). A second portion for holding the drive signal supplied to the first wiring in the second period of each of the plurality of unit periods (for example, the holding portion 521 in FIG. 2), and a second holding And a second portion including second output means (for example, the output unit 523 in FIG. 2) for outputting the drive signal held by the means to the second wiring in the first period in each of the plurality of unit periods. In the above aspect, since the first output means and the second output means alternately output the drive signal to the second wiring, sufficient time for the first holding means and the second holding means to hold the drive signal is secured. it can.

  The display device according to the second aspect of the present invention includes a first display body in which a pixel is connected to each of the plurality of first wirings, and a second display body in which a pixel is connected to each of the plurality of second wirings. A driving circuit arranged between the plurality of first wirings and the plurality of second wirings in one of the first display body and the second display body and outputting a plurality of driving signals, and each of the plurality of first wirings A plurality of first switches (for example, switch SWa1 and switch SWb1 in FIG. 6) for controlling the availability of each drive signal and a plurality of second switches for controlling the availability of each drive signal to each of the plurality of second wirings. A switch (for example, the switch SWa2 and the switch SWb2 in FIG. 6). In the above configuration, since the drive circuit is shared by the first display body and the second display body, the display is compared with the configuration in which the drive circuit is individually arranged on each of the first display body and the second display body. The configuration of the apparatus can be simplified. In addition, since whether the drive signal can be supplied to each first wiring and whether the drive signal can be supplied to each second wiring is controlled by the first switch and the second switch, for example, each first switch and each second switch. It is possible to reduce the load on the driving circuit by driving each of the pixels by selectively conducting any of the above. A specific example of the display device according to the second aspect will be described later as a third embodiment (FIG. 6).

  The display device according to the third aspect of the present invention includes a first display body in which a pixel is connected to each of the plurality of first wirings, and a second display body in which a pixel is connected to each of the plurality of second wirings. A driving circuit arranged between the plurality of first wirings and the plurality of second wirings in one of the first display body and the second display body and outputting a driving signal to each first wiring and each second wiring; It comprises. In the above configuration, since the drive circuit is shared by the first display body and the second display body, the display is compared with the configuration in which the drive circuit is individually arranged on each of the first display body and the second display body. The configuration of the apparatus can be simplified. A specific example of the display device according to the third aspect will be described later as a fourth embodiment (FIG. 7).

  In the display device according to each of the above embodiments, a data line driving circuit that outputs a data signal corresponding to a gradation specified for each pixel as a driving signal, and a scanning signal that selects a pixel to which the data signal is supplied are provided. A scanning line driving circuit that outputs as a driving signal is preferably employed as the driving circuit.

  In the display device according to each aspect described above, for example, a power supply circuit that generates a potential is provided on the other of the first display body and the second display body, and the drive circuit receives supply of the power supply potential from the power supply circuit. Works. According to the above aspect, the configuration of the first display body is simplified as compared with the configuration in which the power supply circuit is disposed together with the drive circuit on one of the first display body and the second display body.

  In the display device according to each aspect described above, for example, a detection unit (for example, the detection body 81 or the detection body 82 in FIG. 8) that generates a detection signal corresponding to the state of the first display body or the second display body, A signal processing unit disposed on the other of the display body and the second display body and processing a detection signal; and a driving circuit disposed on one of the first display body and the second display body is processed by the signal processing unit. A drive signal is generated based on the subsequent detection signal. According to the above aspect, the configuration of the first display body is simplified as compared with the configuration in which the signal processing means is disposed together with the drive circuit on one of the first display body and the second display body.

<A: First Embodiment>
FIG. 1 is a block diagram showing a configuration of a display device according to the first embodiment of the present invention. As shown in FIG. 1, the display device 100 includes a first display body 10, a second display body 20, and a control circuit 70. Each of the first display body 10 and the second display body 20 is a separate image display for displaying an image. The control circuit 70 controls the operations of the first display body 10 and the second display body 20. For example, the control circuit 70 designates either the first display body 10 or the second display body 20 and displays an image.

  The first display body 10 is a liquid crystal device in which liquid crystal is sealed in a gap between the substrate 11 and the substrate 12. Similarly, the second display body 20 is a liquid crystal device in which liquid crystal is sealed in a gap between the substrate 21 and the substrate 22. The first display body 10 and the second display body 20 are electrically connected via a flexible wiring substrate 75 bonded to the substrate 11 and the substrate 21. Actually, the flexible wiring board 75 is curved so that the second display body 20 is positioned on the back side of the first display body 10, and the gap between the first display body 10 and the second display body 20 is illuminated. An illumination device (not shown) is inserted.

  On the substrate 11 of the first display body 10, m scanning lines 15 extending in the X direction and n data lines 17 extending in the Y direction are formed. A pixel P 1 is arranged at a position corresponding to the intersection of each scanning line 15 and each data line 17. The plurality of pixels P1 are arranged in a matrix within the display area A1. As shown in FIG. 1, each pixel P <b> 1 includes a transistor 32 and an electro-optic element 34. The transistor 32 is interposed between the electro-optic element 34 and the data line 17 and has a gate connected to the scanning line 15.

  Similarly, in the second display body 20, m scanning lines 25 extending in the X direction and n data lines 27 extending in the Y direction are formed on the substrate 21, and each scanning line 25 and each data A pixel P2 is arranged at the intersection with the line 27. The plurality of pixels P2 are arranged in a matrix within the display area A2. The pixel P2 includes a transistor 32 and an electro-optic element 34, like the pixel P1. The transistor 32 is interposed between the electro-optic element 34 and the data line 27 and has a gate connected to the scanning line 25. The electro-optical element 34 in each of the pixel P1 and the pixel P2 is a liquid crystal capacitor in which liquid crystal is interposed between a pixel electrode and a counter electrode (both not shown).

  A scanning line driving circuit 42 and a data line driving circuit 44 are disposed in a region of the substrate 11 of the first display body 10 on the side opposite to the second display body 20 across the display region A1. The scanning line driving circuit 42 and the data line driving circuit 44 are configured by complementary transistors (for example, thin film transistors in which a semiconductor layer is formed of low-temperature polysilicon or amorphous silicon) formed directly on the surface of the substrate 11.

  The scanning line driving circuit 42 is connected to the m scanning lines 15 of the first display body 10 and the m scanning lines 25 of the second display body 20. When the control circuit 70 designates the first display body 10 as an image display destination, the scanning line driving circuit 42 outputs m scanning signals YA [1] to YA [m] to each scanning line 15. Each of the scanning lines 15 is selected sequentially. On the other hand, when the control circuit 70 designates the second display body 20, the scanning line driving circuit 42 outputs the scanning signals YB [1] to YB [m] to each scanning line 25, so that the m scanning lines 25. Are sequentially selected.

  Further, when the first display body 10 is designated, the control circuit 70 outputs gradation data designating the gradation of each pixel P1 to the data line driving circuit 44, and when the second display body 20 is designated. Outputs gradation data designating the gradation of each pixel P 2 to the data line driving circuit 44. The data line driving circuit 44 generates data signals D [1] to D [n] corresponding to the gradation data and outputs them to each of the n data lines 17. The data signal D [j] output to the data line 17 in the j-th column (j = 1 to n) has a voltage value corresponding to the gradation data of any pixel (P1, P2) in the j-th column. Is a set voltage signal. As shown in FIG. 1, the data signals D [1] to D [n] are supplied to the data lines 17 from the end opposite to the second display body 20.

  A signal control unit 52 is disposed on the substrate 11 of the first display body 10 on the second display body 20 side (the side opposite to the data line driving circuit 44) when viewed from the display area A1. The signal control unit 52 converts n unit circuits Q [1] to Q [n] corresponding to the number of data lines 27 of the second display body 20 (or the number of data lines 17 of the first display body 10) to X It is a circuit arranged in the direction. The unit circuit Q [j] in the j-th stage includes the data line 17 in the j-th column of the first display body 10 and the data line 27 in the j-th column of the second display body 20 (more specifically, in the j-th column). And the flexible wiring board 75 connected to the data line 27). The control circuit 70 supplies the signal SEL1 and the signal SEL2 in common to the n unit circuits Q [1] to Q [n].

  FIG. 2 is a circuit diagram of the unit circuit Q [j]. As shown in FIG. 2, the unit circuit Q [j] is divided into a first portion 51 and a second portion 52. The first part 51 includes a holding part 511 and an output part 513, and the second part 52 includes a holding part 521 and an output part 523. Each of the holding unit 511 and the holding unit 521 includes a switch SW1 and a capacitive element C. The switch SW1 is interposed between the j-th column data line 17 and the connection point N in the first display body 10, and controls the electrical connection (conduction / non-conduction) between the two. The capacitive element C is interposed between the connection point N and the ground line (or other constant potential line). On the other hand, each of the output unit 513 and the output unit 523 includes a buffer circuit BF and a switch SW2. The input terminal of the buffer circuit BF is connected to the connection point N. The switch SW2 is interposed between the output terminal of the buffer circuit BF and the data line 27 of the j-th column in the second display body 20, and controls the electrical connection between them. The switch SW1 of the first part 51 and the switch SW2 of the second part 52 are controlled according to the signal SEL1, and the switch SW2 of the first part 51 and the switch SW1 of the second part 52 are controlled according to the signal SEL2. .

  Next, the operation of the display device 100 will be described. When the first display body 10 is designated as the image display destination, the control circuit 70 sets both the signal SEL1 and the signal SEL2 to a low level. Accordingly, in each of the unit circuits Q [1] to Q [n], the switches SW1 and SW2 in both the first portion 51 and the second portion 52 are turned off. That is, the data line 27 of the second display body 20 is electrically disconnected from the data line 17 of the first display body 10. In the above state, the scanning line driving circuit 42 sequentially selects each of the m scanning lines 15 of the first display body 10 by outputting the scanning signals YA [1] to YA [m], while the data The line drive circuit 44 outputs data signals D [1] to D [n] corresponding to the gradation data of each pixel P1 of the first display body 10 to each of the n data lines 17. Therefore, a voltage corresponding to the data signals D [1] to D [n] is applied to the electro-optic element 34 of each pixel P1 of the first display body 10, and the gradation data is displayed in the display area A1 of the first display body 10. An image corresponding to is displayed.

  When the second display body 20 is designated as an image display destination, the control circuit 70 generates the signal SEL1 and the signal SEL2 that change with the unit period TU as a cycle and outputs the signal SEL1 to the signal control unit 52 as shown in FIG. To do. The signal SEL1 and the signal SEL2 have a relationship in which the levels are inverted. That is, the signal SEL1 maintains a high level in the first half period T1 of each unit period TU and maintains a low level in the second half period T2, and the signal SEL2 is in the first half period T1 of each unit period TU. The low level is maintained and the high level is maintained in the second half period T2. On the other hand, the scanning line driving circuit 42 sequentially selects each of the m scanning lines 25 of the second display body 20, and the data line driving circuit 44 responds to the gradation data of each pixel P2 of the second display body 20. The data signals D [1] to D [n] are output to each of the n data lines 17.

  In FIG. 3, the voltage (voltage at the connection point N) held by the capacitive element C in each of the first part 51 and the second part 52 of the unit circuit Q [j] is shown along with the voltage waveform of the data signal D [j]. It is shown in the figure. In the period T1 of the unit period TU, the signal SEL1 is set to the high level, so that the switch SW1 of the first portion 51 in each of the unit circuits Q [1] to Q [n] is controlled to be in the on state. Therefore, the data signal D [j] supplied to the data line 17 in the jth column is held in the capacitive element C of the first portion 51 in the unit circuit Q [j]. As shown in FIG. 3, the data signal D [j] held in the capacitive element C is maintained even during the period T2 of the unit period TU in which the switch SW1 is turned off by the signal SEL1 transitioning to the low level. . In the period T2, the signal SEL2 is set to a high level, so that the switch SW2 of the first portion 51 in each unit circuit Q [j] is controlled to be in an on state. Therefore, the data signal D [j] held in the capacitive element C in the immediately preceding period T1 is subjected to waveform shaping by the buffer circuit BF and then the data line in the jth column of the second display body 20 via the switch SW2. 27 is output.

  On the other hand, in the second portion 52 of the unit circuit Q [j], the data signal D [j] has a capacitance when the switch SW1 is turned on in the period T2 of the unit period TU in which the signal SEL2 is set to the high level. It is held by element C. Then, since the signal SEL1 is set to the high level in the immediately following period T1, the switch SW2 is turned on, so that the data signal D [j] held in the capacitor C as shown in FIG. Is output to the data line 27 of the j-th column of the second display body 20. That is, the first portion 51 of the unit circuit Q [j] holds the data signal D [j] of the data line 17 and the second portion 52 outputs the data signal D [j] of the capacitive element C to the data line 27. In operation, the first portion 51 of the unit circuit Q [j] outputs the data D [j] of the capacitive element C to the data line 27 and the second portion 52 holds the data signal D [j] of the data line 17. The operation is sequentially repeated with a half time length of the unit period TU as a period.

  As described above, each of the m scanning lines 25 of the second display body 20 in parallel with the operation of outputting the data signals D [1] to D [n] to the n data lines 27 of the second display body 20. Are sequentially selected by the scanning line driving circuit 42, a voltage corresponding to the data signals D [1] to D [n] is applied to the electro-optic element 34 of each pixel P2 of the second display body 20, and the second display. In the display area A2 of the body 20, an image corresponding to the gradation data is displayed. As can be understood from the above description, the data signal D [j] supplied to the second display body 20 is half the unit period TU compared to the data signal D [j] in the first display body 10. The signal is delayed by the length of time. Accordingly, the scanning line driving circuit 42 generates the scanning signals YB [1] to YB [m] so as to match the phase of the data signal D [j] supplied to the second display body 20.

  As described above, in this embodiment, since the data line driving circuit 44 is shared by the first display body 10 and the second display body 20, each of the first display body 10 and the second display body 20 is separately provided. It is not necessary to arrange the data line driving circuit 44 of the first data line. Therefore, it is possible to reduce the power consumed by the display device 100 and the cost required for manufacturing the display device 100. The data line driving circuit 44 requires a complementary transistor. In this embodiment, the data line driving circuit 44 does not need to be disposed on the second display body 20, and thus the substrate 21 of the second display body 20. Only one of the n-channel type and the p-channel type is sufficient as the conductivity type of the transistor (for example, the transistor of the pixel P2) formed in (1). Therefore, it is possible to simplify the manufacture of the second display body 20 as compared with the case where a complementary transistor is formed on the substrate 21 of the second display body 20.

  Further, when an image is displayed on the second display body 20, the data signal D [j] output from the data line driving circuit 44 to the data line 17 of the first display body 10 is held in the unit circuit Q [j]. Then, the data is output to the data line 27 of the second display body 20. Therefore, there is an advantage that the load on the data line driving circuit 44 is reduced as compared with the configuration in which the data line 17 and the data line 27 are directly connected. Further, in this embodiment, in the period T2 in which the first portion 51 of the unit circuit Q [j] outputs the data signal D [j] to the data line 27, the second portion 52 outputs the data signal D [j] to the data line 17. The first portion 51 captures the data signal D [j] from the data line 17 in the period T1 during which the second portion 52 outputs the data signal D [j] to the data line 27. According to the above configuration, there is an advantage that a sufficient time can be secured for holding the data signal D [j] in the capacitive element C. Therefore, even when the driving capability of the buffer circuit BF is low (for example, when the buffer circuit BF is configured by a thin film transistor formed directly on the substrate 11 of the first display body 10), the data signal D [j] is surely obtained. Can be output to the data line 27.

  In the above configuration, each scanning line 15 of the first display body 10 and each scanning line 25 of the second display body 20 are driven by the scanning line drive circuit 42 on the first display body 10, but are shown in FIG. As described above, the scanning line driving circuit 42A for selecting each scanning line 15 is arranged on the first display body 10 and the scanning line driving circuit 42B for selecting each scanning line 25 is also arranged on the second display body 20. Adopted.

<B: Second Embodiment>
Next, a second embodiment of the present invention will be described. In the first embodiment, unit circuits Q [1] to Q [n] (signal control unit 52) are interposed between the data line 17 and the data line 27. In the present embodiment, the same configuration is adopted for the scanning lines 15 of the first display body 10 and the scanning lines 25 of the second display body 20. In addition, about the element in which an effect | action and a function are equivalent to 1st Embodiment in each following form, the same code | symbol as the above is attached | subjected and each detailed description is abbreviate | omitted suitably.

  FIG. 5 is a block diagram showing the relationship between each scanning line 15 of the first display body 10 and each scanning line 25 of the second display body 20 and the scanning line driving circuit 42. Since the relationship between each data line 17 or each data line 27 and the data line drive circuit 44 and the signal control unit 52 is the same as that in the first embodiment, the illustration is omitted in FIG. As shown in FIG. 5, a signal control unit 54 is disposed on the periphery of the substrate 11 of the first display body 10 on the second display body 20 side (the side opposite to the scanning line driving circuit 42). The signal control unit 54 supplies m unit circuits R [1] to R [m] corresponding to the total number of scanning lines 25 of the second display body 20 (total number of scanning lines 15 of the first display body 10) in the X direction. It is a circuit arranged in. Each of the unit circuits R [1] to R [m] is composed of a first portion 51 and a second portion 52 as in the unit circuit Q [j] illustrated in FIG. Control is performed according to the signals SEL1 and SEL2. But you may control each of the signal control part 52 and the signal control part 54 with the signal of another system | strain.

  The unit circuit R [i] of the i-th stage (i = 1 to m) in the signal control unit 54 includes the i-th scanning line 15 in the first display body 10 and the i-th row in the second display body 20. Between the scanning line 25 and the scanning line 25. Scan signals Y [1] to Y [m] generated and output by the scan line driving circuit 42 are supplied to each of the m scan lines 15 of the first display body 10 and m signals of the signal control unit 54. It is also supplied to each of the unit circuits R [1] to R [m].

  The first portion 51 of the unit circuit R [i] holds the scanning signal Y [i] supplied to the scanning line 15 in the capacitive element C during the period T1 of the unit period TU, and the buffer circuit BF and the buffer circuit BF during the period T2. The signal is output from the switch SW2 to the scanning line 25. The second portion 52 of the unit circuit R [i] holds the scanning signal Y [i] supplied to the scanning line 15 in the capacitive element C in the period T2 of the unit period TU, and the buffer circuit in the immediately following period T1. The signal is output from BF to the scanning line 25 via the switch SW2. That is, after the scanning signals Y [1] to Y [m] supplied to the scanning lines 15 of the first display body 10 are delayed by the signal controller 54 by a time length that is half the unit period TU, the second display is performed. It is supplied to each scanning line 25 of the body 20. Since the data line driving circuit 44 and the signal control unit 52 operate in the same manner as in the first embodiment, in this embodiment, images equivalent to the display area A1 of the first display body 10 and the display area A2 of the second display body 20 are displayed. Are displayed in parallel.

  As described above, in this embodiment, the scanning signal Y [i] output to the scanning line 15 of the first display body 10 is held in the unit circuit R [i] and then the second display body 20 is scanned. Output on line 25. Therefore, for example, there is an advantage that the load on the scanning line driving circuit 42 is reduced as compared with a configuration in which the scanning lines 15 and 25 are directly connected. Furthermore, since the first portion 51 and the second portion 52 in the unit circuit R [i] alternately output the scanning signal Y [i], a sufficient time is allowed for the capacitive element C to hold the scanning signal Y [i]. Can be secured. Therefore, even when the driving capability of the buffer circuit BF in the unit circuit R [i] is low (for example, when the buffer circuit BF is configured by a thin film transistor formed directly on the substrate 11 of the first display body 10), it is reliable. In addition, the scanning signal Y [i] can be output to the scanning line 25.

<C: Third Embodiment>
FIG. 6 is a block diagram showing the configuration of the display device 100 according to the third embodiment of the present invention. As shown in FIG. 6, the scanning line driving circuit 42 and the second display body 20 side of the surface of the substrate 11 of the first display body 10 as viewed from the display area A1 (that is, the gap between the display area A1 and the display area A2) A data line driving circuit 44 is arranged. In the substrate 11, n switches SWa 1 are arranged in the X direction in the gap between the data line driving circuit 44 and the display area A 1. The j-th stage switch SWa1 is interposed between the output end of the data signal D [j] in the data line driving circuit 44 and the j-th column data line 17 of the first display body 10, and electrically The correct connection. In the area of the substrate 11 opposite to the display area A1 across the data line driving circuit 44, n switches SWa2 are arranged in the X direction. The j-th stage switch SWa2 is interposed between the output terminal of the data signal D [j] in the data line driving circuit 44 and the j-th column data line 27 of the second display body 20, and electrically The correct connection.

  In the gap between the scanning line driving circuit 42 and the display area A1 in the substrate 11, m switches SWb1 are arranged in the X direction. The i-th stage switch SWb1 is interposed between the output terminal of the scanning signal Y [i] in the scanning line driving circuit 42 and the i-th scanning line 15 of the first display body 10, and electrically The correct connection. In the area of the substrate 11 opposite to the display area A1 across the scanning line driving circuit 42, m switches SWb2 are arranged in the X direction. The i-th stage switch SWb2 is interposed between the output terminal of the scanning signal Y [i] in the scanning line driving circuit 42 and the i-th scanning line 25 of the second display body 20, and electrically The correct connection. Each switch (SWa1, SWa2, SWb1, SWb2) is, for example, a thin film transistor formed directly on the surface of the substrate 11.

  Each switch SWa1 and each switch SWb1 operate according to the signal SEL1, and each switch SWa2 and each switch SWb2 operate according to the signal SEL2. When the first display body 10 is designated as an image display destination, the control circuit 70 sets the signal SEL1 so that each switch SWa1 and each switch SWb1 is turned on, and each switch SWa2 and each switch SWb2 is turned off. The signal SEL2 is set so that In the above state, the scanning signals Y [1] to Y [m] output from the scanning line driving circuit 42 are supplied to the scanning lines 15 of the first display body 10, and the data output from the data line driving circuit 44 is output. Signals D [1] to D [n] are supplied to the data lines 17 of the first display body 10. Accordingly, an image is displayed in the display area A1 of the first display body 10. Since the scanning signals Y [1] to Y [m] and the data signals D [1] to D [n] are not supplied to the second display body 20, no image is displayed on the display area A2 of the second display body 20.

  On the other hand, when the second display body 20 is designated as the image display destination, the control circuit 70 sets the signal SEL2 so that each switch SWa2 and each switch SWb2 is turned on, and each switch SWa1 and each switch SWb1 is set. The signal SEL1 is set so as to be turned off. Accordingly, the scanning signals Y [1] to Y [m] are supplied only to the scanning lines 25, and the data signals D [1] to D [n] are supplied only to the data lines 27. Therefore, the image is displayed only in the display area A2 of the second display body 20.

  As described above, in this embodiment, since the scanning signals Y [1] to Y [m] are supplied to only one of the scanning lines 15 and the scanning lines 25, for example, the scanning lines 15 and 25 Compared with the configuration in which the scanning signal Y [i] is output to both the scanning line 15 and the scanning line 25, the load on the scanning line driving circuit 42 is reduced. Similarly, since data signals D [1] to D [n] are supplied to only one of each data line 17 and each data line 27, the data line 17 and the data line 27 are connected (data signal D). Compared with a configuration in which [j] is output to both the data line 17 and the data line 27), the load on the data line driving circuit 44 is reduced. In addition, in this embodiment, it is not necessary to arrange the signal control unit 52 of the first embodiment and the signal control unit 54 of the second embodiment. Further, since the scanning line driving circuit 42 is disposed between each scanning line 15 and each scanning line 25 and the data line driving circuit 44 is disposed between each data line 17 and each data line 27, There is an advantage that the load on the scanning line driving circuit 42 and the data line driving circuit 44 is equalized when the first display body 10 is driven and when the second display body 20 is driven.

<D: Fourth Embodiment>
FIG. 7 is a block diagram of a display device 100 according to the fourth embodiment of the present invention. As shown in FIG. 7, the first display body 10 and the second display body 20 are arranged in the X direction and are electrically connected via a flexible wiring board 75. A data line driving circuit 44A is disposed on the substrate 11 of the first display body 10. The data line driving circuit 44A outputs data signals DA [1] to DA [n] to each of the n data lines 17 of the first display body 10. Similarly, a data line driving circuit 44B that outputs data signals DB [1] to DB [n] to each of the n data lines 27 of the second display body 20 is disposed on the substrate 21 of the second display body 20. Is done.

  A scanning line driving circuit 42 is disposed on the second display body 20 side of the substrate 11 of the first display body 10 as viewed from the display area A1. The scanning line driving circuit 42 generates and outputs m systems of scanning signals Y [1] to Y [m] as in the third embodiment. Both the i-th scanning line 15 of the first display body 10 and the i-th scanning line 25 of the second display body 20 are electrically connected to the output terminal of the scanning signal Y [i] in the scanning line driving circuit 42. Connected. Accordingly, the common scanning signal Y [i] is supplied to the i-th scanning line 15 and the i-th scanning line 25.

  When the control circuit 70 designates the first display body 10 as an image display destination, the data line driving circuit 44A outputs data signals DA [1] to DA [n] to the data lines 17. Since the data line driving circuit 44B stops its operation, an image is displayed only in the display area A1 of the first display body 10. On the other hand, when the second display body 20 is designated, only the data line driving circuit 44B outputs the data signals DB [1] to DB [n] to the respective data lines 27, whereby the display area A2 of the second display body 20 is displayed. An image is displayed. When the control circuit 70 designates both the first display body 10 and the second display body 20, both the display area A1 and the display area A2 are operated by operating both the data line driving circuit 44A and the data line driving circuit 44B. An image is displayed.

  As described above, in the present embodiment, since the first display body 10 and the second display body 20 share the scanning line driving circuit 42, each of the first display body 10 and the second display body 20 is separately provided. It is not necessary to arrange the scanning line driving circuit 42. Therefore, it is possible to reduce the power consumed by the display device 100 and the cost required for manufacturing the display device 100. In addition, since the scanning line driving circuit 42 requires a complementary transistor, in this embodiment, since the scanning line driving circuit 42 does not need to be disposed on the second display body 20, the substrate 21 of the second display body 20. The conductivity type of the transistor formed in the transistor can be either n-channel or p-channel. Therefore, it is possible to simplify the manufacture of the second display body 20 as compared with the case where a complementary transistor is formed on the substrate 21 of the second display body 20.

<E: Fifth Embodiment>
FIG. 8 is a block diagram of a display device 100 according to the fifth embodiment of the present invention. As shown in FIG. 8, the display device 100 of this embodiment has a configuration in which a detection body 81, a detection body 82, a signal processing unit 84, and a power supply circuit 87 are added to the display device 100 of the third embodiment. The detection body 81 is disposed on the surface of the substrate 11 of the first display body 10, and the detection body 82, the signal processing unit 84, and the power supply circuit 87 are disposed on the surface of the substrate 21 of the second display body 20. The signal processing unit 84 and the power supply circuit 87 are composed of thin film transistors formed directly on the surface of the substrate 21, for example.

  The detection body 81 is a sensor that generates a detection signal corresponding to the surrounding state (the state of the first display body 10). Similarly, the detection body 82 is a sensor that generates a detection signal corresponding to the surrounding state (the state of the second display body 20). For example, a temperature sensor that detects the ambient temperature and an illuminance sensor that detects the amount of ambient light are suitably employed as the detection body 81 and the detection body 82. Only one of the detection body 81 and the detection body 82 may be installed.

  The signal processing unit 84 is a circuit that processes detection signals generated by the detection body 81 and the detection body 82. For example, an A / D converter that converts a detection signal into digital data and an amplifier that amplifies the detection signal are employed as the signal processing unit 84. A detection signal processed by the signal processing unit 84 is output to the control circuit 70. The control circuit 70 controls the operation of the scanning line driving circuit 42 and the data line driving circuit 44 based on the detection signal supplied from the signal processing unit 84. For example, when the level of the detection signal is high (for example, when the temperature of the first display body 10 or the second display body 20 is high or when the amount of light around the first display body 10 or the second display body 20 is large), each data For example, the voltage values of the signals D [1] to D [n] are increased or decreased. However, the content of the control according to the detection result by the detection body 81 or the detection body 82 is arbitrary.

  The power supply circuit 87 in FIG. 8 is a circuit (for example, a charge pump circuit) that generates various potentials (power supply potentials) used in the display device 100. The potential generated by the power supply circuit 87 is supplied to the scanning line driving circuit 42 and the data line driving circuit 44 of the first display body 10 via wiring on the flexible wiring board 75. The scanning line driving circuit 42 and the data line driving circuit 44 operate using the power supply potential supplied from the power supply circuit 87. The power supply circuit 87 generates a predetermined reference potential and supplies it to the counter electrode (common electrode) of the first display body 10 and the second display body 20.

  As described above, in the present embodiment, since the signal processing unit 84 and the power supply circuit 87 are shared by the first display body 10 and the second display body 20, the first display body 10 and the second display body 20. Compared with a configuration in which the signal processing unit 84 and the power supply circuit 87 are arranged, the power consumed by the display device 100 and the cost necessary for manufacturing the display device 100 can be reduced. In addition, although the form based on 3rd Embodiment was demonstrated in FIG. 8, the structure which shares the signal processing part 84 and the power supply circuit 87 with the 1st display body 10 and the 2nd display body 20 is 1st Embodiment. The same applies to the embodiment, the second embodiment, and the fourth embodiment.

<F: Modification>
Various modifications can be made to the above embodiments. Specific modifications are exemplified below. Two or more aspects may be arbitrarily selected from the following examples and combined.

(1) Modification 1
The number of data lines 17 of the first display body 10 may be different from the number of data lines 27 of the second display body 20. Similarly, the number of scanning lines 15 of the first display body 10 may be different from the number of scanning lines 25 of the second display body 20. A configuration in which the size (for example, the size of the display area or the substrate) is different between the first display body 10 and the second display body 20 is also adopted. A configuration in which the scanning line driving circuit 42 and the data line driving circuit 44 are arranged on a small display body of the first display body 10 and the second display body 20 is preferable.

(2) Modification 2
The signal control unit 52 in the first embodiment and the second embodiment and the signal control unit 54 in the second embodiment may be installed in the second display body 20. Similarly, each switch (SWa1, SWa2, SWb1, SWb2) in the third embodiment is arranged in the second display body 20, and the signal processing unit 84 or the power supply circuit 87 in the fifth embodiment is the first display body 10. A configuration arranged in the above is also suitable.

(3) Modification 3
A configuration in which the first display body 10 and the second display body 20 are integrated (for example, a configuration in which the display area A1 and the display area A2 are defined on the surface of one substrate) is also employed. Further, the scanning line driving circuit 42 (42A, 42B) and the data line driving circuit 44 (44A, 44B) may be mounted in the form of an integrated circuit or may be externally attached to the display device 100.

(4) Modification 4
The liquid crystal capacitance is merely an example of an electro-optic element. The electro-optic element applied to the present invention is distinguished from a self-light-emitting type that emits light itself and a non-light-emitting type that changes the transmittance of external light, a current-driven type that is driven by current supply, and an electric field (voltage) There is no distinction from the voltage driven type driven by the application of. For example, an organic EL (Electroluminescence) element, an inorganic EL element, a field electron emission element (FE (Field-Emission) element), a surface conduction electron emission element (SE (Surface conduction Electron emitter) element), a ballistic electron emission element (BS) The present invention is applied to display devices using various electro-optical elements such as (Ballistic electron Emitting) elements, LED (Light Emitting Diode) elements, electrophoretic elements, and electrochromic elements.

<G: Application example>
Next, an electronic apparatus using the display device according to the present invention will be described. FIGS. 9 to 11 show forms of electronic devices using the display device 100 according to any one of the forms described above.

  FIG. 9 is a perspective view illustrating a configuration of a mobile personal computer that employs the display device 100. The personal computer 2000 includes the display device 100 and a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed. When the display device 100 is opened with respect to the main body 2010, the user visually recognizes the display area A1 of the first display body 10 as shown in FIG. 9, and when the display device 100 is closed with respect to the main body 2010. The user visually recognizes the display area A2 of the second display body 20.

  FIG. 10 is a perspective view illustrating a configuration of a mobile phone using the display device 100. A cellular phone 3000 includes a plurality of operation buttons 3001 and scroll buttons 3002, and the display device 100 according to each of the above modes. In the state where the display device 100 is opened with respect to the operation button 3001, the display area A1 of the first display body 10 is visually recognized by the user as shown in FIG. 10, and in the state where the display device 100 is closed to the operation button 3001 side. The display area A2 of the second display body 20 is visually recognized by the user.

  FIG. 11 is a perspective view showing a configuration of a personal digital assistant (PDA) using the display device 100. The portable information terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the display device 100 according to each of the above forms. The first display body 10 (display area A1) is arranged on the front side of the portable information terminal 4000 (the arrangement side of the operation buttons 4001), and the second display body 20 is arranged on the back side. When the power switch 4002 is operated, various information such as an address book and a schedule book are displayed on the display device 100.

  Note that examples of the electronic apparatus to which the display device according to the present invention is applied include the digital still camera, the television, the video camera, the car navigation apparatus, the pager, the electronic notebook, the electronic paper, in addition to the apparatuses illustrated in FIGS. Examples include calculators, word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with touch panels, and the like.

1 is a block diagram of a display device according to a first embodiment of the present invention. It is a circuit diagram of a unit circuit. It is a timing chart which shows operation | movement of a display apparatus. It is a block diagram of the display apparatus concerning the modification of a 1st embodiment. It is a block diagram which shows the partial structure of the display apparatus which concerns on 2nd Embodiment. It is a block diagram which shows the structure of the display apparatus which concerns on 3rd Embodiment. It is a block diagram which shows the structure of the display apparatus which concerns on 4th Embodiment. It is a block diagram which shows the structure of the display apparatus which concerns on 5th Embodiment. It is a perspective view which shows the form (personal computer) of an electronic device. It is a perspective view which shows the form (cellular phone) of an electronic device. It is a perspective view which shows the form (mobile information terminal) of an electronic device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Display apparatus, 10 ... 1st display body, 20 ... 2nd display body, 15, 25 ... Scanning line, 17, 27 ... Data line, A1, A2 ... Display area, P1, P2 ... ... Pixel, 42, 42A, 42B ... Scanning line drive circuit, 44, 44A, 44B ... Data line drive circuit, 52, 54 ... Signal control unit, 51 ... First part, 52 ... Second part, 511, 521 ... holding unit, 513, 523 ... output unit, SW1, SW2, SWa1, SWa2, SWb1, SWb2 ... switch, 70 ... control circuit.

Claims (9)

A first display body in which a pixel is connected to each of the plurality of first wirings;
A second display body in which a pixel is connected to each of the plurality of second wirings;
A drive circuit for outputting a drive signal to each of the plurality of first wirings from the opposite side of the second display body across the plurality of first wirings;
The first display body and the second display body are disposed between the first wirings and the second wirings and hold a drive signal supplied to the first wirings. And a plurality of unit circuits that output to the second wiring. Each of the plurality of unit circuits is
First holding means for holding the drive signal supplied to the first wiring in a first period of each of a plurality of unit periods; and a drive signal held by the first holding means in each of the plurality of unit periods A first portion including first output means for outputting to the second wiring in a second period;
A second holding means for holding the drive signal supplied to the first wiring in the second period in each of the plurality of unit periods; and a drive signal held by the second holding means for the plurality of unit periods. 2. The display device according to claim 1, further comprising: a second portion including second output means for outputting to the second wiring in the first period in each. A first display body in which a pixel is connected to each of the plurality of first wirings;
A second display body in which a pixel is connected to each of the plurality of second wirings;
A driving circuit arranged between the plurality of first wirings and the plurality of second wirings in one of the first display body and the second display body to output a plurality of driving signals;
A plurality of first switches for controlling whether or not each of the drive signals can be supplied to each of the plurality of first wirings;
A display device comprising: a plurality of second switches that control whether or not the drive signals can be supplied to each of the plurality of second wirings. A first display body in which a pixel is connected to each of the plurality of first wirings;
A second display body in which a pixel is connected to each of the plurality of second wirings;
One of the first display body and the second display body is disposed between the plurality of first wirings and the plurality of second wirings and sends a drive signal to each of the first wirings and each of the second wirings. A display device comprising: a drive circuit for outputting. 5. The display device according to claim 1, wherein the drive circuit is a data line drive circuit that outputs a data signal corresponding to a gradation specified for each pixel as the drive signal. 5. The display device according to claim 1, wherein the driving circuit is a scanning line driving circuit that outputs a scanning signal for selecting a pixel to which a data signal is supplied as the driving signal. A power supply circuit that is disposed on the other of the first display body and the second display body and generates a power supply potential;
The display device according to claim 1, wherein the drive circuit operates by receiving supply of a power supply potential from the power supply circuit. Detection means for generating a detection signal according to a state of the first display body or the second display body;
Signal processing means disposed on the other of the first display body and the second display body for processing the detection signal;
8. The drive circuit disposed on one of the first display body and the second display body generates the drive signal based on a detection signal after processing by the signal processing means. Display device. An electronic apparatus comprising the display device according to claim 1.

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