JP2009152459A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device using a tungsten film for its gate, source, or drain electrode, which can reduce an nMOS-pMOS resistance difference. <P>SOLUTION: The method of manufacturing a semiconductor device comprises the steps of: forming nMOS and pMOS containing gate electrodes (14a, 14b) and source/drain diffusion layers (16a, 16b) on a silicon substrate 10; forming a tungsten film 17 selectively on the gate electrodes (14a, 14b) and the source/drain diffusion layers (16a, 16b); forming insulating films (etching stopping silicon oxide film 18 and silicon nitride film 19) to cover the tungsten film 17; removing the insulating film of the pMOS region 12b; and forming a tungsten film 20 selectively on the tungsten film 17 of the pMOS region 12b. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a tungsten (W) film for a gate electrode, a source electrode, or a drain electrode.

  As a technique for reducing the resistance of a gate electrode, a source electrode, or a drain electrode, a so-called salicide (Self-Aligned Silicide) process is known in which a metal silicide film is formed on a surface in a self-aligned manner. Cobalt (Co), titanium (Ti), nickel (Ni), or the like is used as a metal material to be reacted with silicon (Si) in the salicide process.

In the salicide process, the metal material erodes the source / drain diffusion layer in order to react with the underlying silicon. For this reason, when the source / drain diffusion layer becomes thinner with the miniaturization of the semiconductor device, there is a concern of increasing junction leakage. Further, when nickel silicide (NiSi) is formed, there is a problem in that a spike-like nickel disilicide (NiSi ₂ ) phase is formed with a high resistance and junction leakage current further increases.

By the way, as an alternative to the salicide process, a process of selectively forming a tungsten film on the gate electrode and the source / drain diffusion layer is known (for example, see Non-Patent Document 1). Unlike nickel and the like, tungsten can be grown on the source / drain diffusion layer without eroding silicon. That is, there is a merit that the source / drain diffusion layer can be maintained as it is, and it is particularly suitable when the source / drain diffusion layer is thin, and has attracted attention.
EK Broadbent et al., J. Electrochem. Soc., Vol. 131, No. 6, pp. 1427 (1984)

However, when a tungsten film is used for a CMOSFET (Complementary Metallic Oxide Semiconductor Field Effect Transistor), there are the following problems.
FIG. 18 is a cross-sectional view showing each step when a tungsten film is formed on the CMOSFET.

  First, as shown in FIG. 18A, an STI (Shallow Trench Isolation) 81 filled with an insulating film is formed on a silicon substrate 80, an n-channel MOSFET (hereinafter abbreviated as nMOS) region 82a and a p-channel MOSFET. After defining regions 82b (hereinafter abbreviated as pMOS), gate insulating films 83a and 83b, gate electrodes 84a and 84b, and sidewall insulating films 85a and 85b are formed in the respective regions. Thereafter, ion implantation is performed alternately on the nMOS region 82a and the pMOS region 82b to form source / drain diffusion layers 86a and 86b.

  Next, as shown in FIG. 18B, a tungsten film 87 is selectively formed on the gate electrodes 84a and 84b and the source / drain diffusion layers 86a and 86b simultaneously by using CVD (Chemical Vapor Deposition). . At this time, the film formation rate of the tungsten film 87 is different between the nMOS region 82a and the pMOS region 82b, and the pMOS region 82b is thinner than the nMOS region 82a.

As a result, there is a problem that the pMOS side has a higher resistance than the nMOS side.
In order to reduce the resistance of the tungsten film 87 on the pMOS side, if the film thickness of the tungsten film 87 is increased, the tungsten film 87 on the gate electrode 84a is now on the source / drain diffusion layer 86a on the nMOS side. There was a problem of contact.

  Accordingly, the present inventors have aimed to provide a semiconductor device manufacturing method capable of reducing a resistance difference between an nMOS and a pMOS in a semiconductor device using a tungsten film as a gate electrode, a source electrode or a drain electrode. To do.

  In order to achieve the above object, a semiconductor device manufacturing method including the following steps is provided. The method for manufacturing a semiconductor device includes a step of forming an n-channel MOSFET and a p-channel MOSFET having a gate electrode and a source / drain diffusion layer on a semiconductor substrate, and the gate electrode and the source / drain diffusion layer. A step of selectively forming a first tungsten film; a step of forming an insulating film so as to cover the first tungsten film; and removing the insulating film in the formation region of the p-channel MOSFET. And a step of selectively forming a second tungsten film on the first tungsten film in the formation region of the p-channel MOSFET.

  In order to achieve the above object, a method of manufacturing a semiconductor device having the following steps is provided. The method for manufacturing a semiconductor device includes a step of forming an n-channel MOSFET and a p-channel MOSFET having a gate electrode and a source / drain diffusion layer on a semiconductor substrate, and the gate electrode and the source / drain diffusion layer. A step of selectively forming a first tungsten film; a step of forming an insulating film so as to cover the first tungsten film; and removing the insulating film in a formation region of the n-channel MOSFET. A step of removing the first tungsten film in the formation region of the n-channel MOSFET, and selecting a second tungsten film on the gate electrode and the source / drain diffusion layer of the n-channel MOSFET. Forming the same.

  In order to achieve the above object, a method of manufacturing a semiconductor device having the following steps is provided. The method for manufacturing a semiconductor device includes a step of forming an n-channel MOSFET and a p-channel MOSFET having a gate electrode and a source / drain diffusion layer on a semiconductor substrate, and the gate electrode and the source / drain diffusion layer. A step of selectively forming a tungsten film, a step of forming an insulating film so as to cover the tungsten film, a step of removing the insulating film in the formation region of the p-channel MOSFET, and the p-channel Removing the tungsten film in the formation region of the MOSFET, and forming a silicide film on the gate electrode and the source / drain diffusion layer in the formation region of the p-channel MOSFET.

  In a semiconductor device using a tungsten film for a gate electrode, a source electrode, or a drain electrode, a resistance difference between an nMOS and a pMOS can be reduced.

Hereinafter, the present embodiment will be described in detail with reference to the drawings.
1 to 3 are cross-sectional views in each step of the semiconductor device manufacturing method according to the first embodiment.

  First, an nMOS and a pMOS having a gate electrode and source / drain diffusion layers are formed on a semiconductor substrate. For example, as shown in FIG. 1A, an STI 11 filled with, for example, a silicon oxide film is formed as an element isolation region on a silicon substrate 10 on which a well (not shown) of a predetermined conductivity type is formed. The nMOS region 12a and the pMOS region 12b are defined. Thereafter, gate insulating films 13a and 13b, gate electrodes 14a and 14b, and sidewall insulating films 15a and 15b are formed in each region. Thereafter, ion implantation is alternately performed on the nMOS region 12a and the pMOS region 12b to form source / drain diffusion layers 16a and 16b.

The material of the gate insulating films 13a and 13b is not particularly limited. For example, a silicon oxide film of about 2 nm is formed by, for example, a thermal oxidation method.
The gate electrodes 14a and 14b are formed by using a polysilicon film or an amorphous silicon film with a film thickness of about 100 nm by, for example, a CVD method, and then dopant impurities are formed on the polysilicon film or the amorphous silicon film by an ion implantation method. Use the introduced one. When forming the nMOS gate electrode 14a, for example, phosphorus (P) is used as an n-type dopant impurity, and ion implantation is performed with an acceleration voltage of 5 keV and a dose of 1 × 10 ¹⁶ cm ⁻² , for example. When the pMOS gate electrode 14b is formed, for example, boron (B) is used as a p-type dopant impurity, and the ion implantation is performed with an acceleration voltage of 0.5 keV and a dose of 5 × 10 ¹⁵ cm ⁻² , for example. To do. Thereafter, patterning is performed by photolithography and dry etching.

Of the source / drain diffusion layers 16a and 16b, extension regions which are shallow impurity diffusion regions are formed after patterning of the gate electrodes 14a and 14b. The gate electrodes 14a and 14b are used as masks, for example, by implanting dopant impurities into the silicon substrate 10 on both sides of the gate electrodes 14a and 14b by ion implantation. When forming an nMOS, for example, arsenic (As) is used as an n-type dopant impurity, and, for example, ions are implanted with an acceleration voltage of 1 keV and a dose of 1 × 10 ¹⁵ cm ⁻² . When forming a pMOS, for example, boron is used as a p-type dopant impurity, and, for example, ion implantation is performed with an acceleration voltage of 0.5 keV and a dose of 1 × 10 ¹⁵ cm ⁻² .

  The sidewall insulating films 15a and 15b are formed, for example, by forming a silicon oxide film with a thickness of 100 nm by the CVD method on the entire surface of the silicon substrate 10 after the extension region is formed. It is formed by etching. The sidewall insulating films 15a and 15b are not limited to silicon oxide films, and other insulating films may be used.

Of the source / drain diffusion layers 16a and 16b, deep impurity diffusion layers are formed on the silicon on both sides of the sidewall insulating films 15a and 15b by, for example, ion implantation using the gate electrodes 14a and 14b and the sidewall insulating films 15a and 15b as masks. It is formed by implanting dopant impurities into the substrate 10. When forming an nMOS, for example, phosphorus is used as an n-type dopant impurity, and ion implantation is performed with an acceleration voltage of 8 keV and a dose of 1 × 10 ¹⁶ cm ⁻² . In the case of forming a pMOS, for example, boron is used as a p-type dopant impurity, and ion implantation is performed with an acceleration voltage of 5 keV and a dose of 5 × 10 ¹⁵ cm ⁻² . Thereafter, the dopant impurity introduced into the impurity diffusion region is activated by performing heat treatment at a predetermined temperature.

Subsequently, natural oxide films (not shown) formed on the surfaces of the gate electrodes 14a and 14b and the surfaces of the source / drain diffusion layers 16a and 16b by, for example, plasma treatment with hydrogen or ammonia or dilute hydrofluoric acid treatment. Remove. Then, a tungsten film 17 is selectively formed on the gate electrodes 14a and 14b and the source / drain diffusion layers 16a and 16b. The tungsten film 17 is formed by using a CVD method, for example, with a source gas of tungsten hexafluoride (WF ₆ ) and silane (SiH ₄ ) at a film forming temperature of 200 to 400 ° C. and a pressure of 0.1 to 10 Pa. The film is formed with a film thickness of about 40 nm. At this time, the pMOS region 12b is thinner than the nMOS region 12a due to the difference in film formation rate.

  Further, an etching stop silicon oxide film 18 and a silicon nitride film 19 having a tensile stress are sequentially stacked on the nMOS region 12a and the pMOS region 12b so as to cover the tungsten film 17. For example, using the CVD method, the etching stop silicon oxide film 18 is formed to a thickness of about 1 to 20 nm, and the silicon nitride film 19 is formed to a thickness of about 10 to 100 nm.

  Next, by masking the nMOS region 12a with a photoresist mask (not shown) and dry etching, the silicon nitride film 19 and the etching stop silicon oxide film in the pMOS region 12b as shown in FIG. 18 is removed.

  Thereafter, for example, a natural oxide film (not shown) formed on the surface of the gate electrode 14b and the surface of the source / drain diffusion layer 16b of the pMOS region 12b by plasma treatment such as hydrogen or ammonia or dilute hydrofluoric acid treatment. Remove.

  Then, as shown in FIG. 1C, a tungsten film 20 is selectively formed on the gate electrode 14b in the pMOS region 12b and the tungsten film 17 on the source / drain diffusion layer 16b. The tungsten film 20 is formed by CVD using, for example, a source gas of tungsten hexafluoride and silane with a film formation temperature of 200 to 400 ° C. and a pressure of 0.1 to 10 Pa, and a film thickness of about 5 to 40 nm. .

  By such a process, the tungsten film 20 is not formed in the nMOS region 12a that is still covered with the silicon nitride film 19, and the tungsten film 20 having a desired thickness is formed only on the tungsten film 17 in the pMOS region 12b. Can be formed. That is, the film thickness of the tungsten film 17 in the nMOS region 12a can be made equal to the film thickness of the tungsten films 17 and 20 in the pMOS region 12b.

  Subsequently, as shown in FIGS. 2A and 2B, an etching stop silicon oxide film 21 and a compression film are formed on the silicon nitride film 19 and the pMOS region 12b in the nMOS region 12a so as to cover the tungsten film 20. A silicon nitride film 22 having stress is laminated in order. For example, the CVD method is used to form the etching stop silicon oxide film 21 with a thickness of about 1 to 20 nm and the silicon nitride film 22 with a thickness of about 20 to 100 nm.

  Then, the pMOS region 12b is masked with a photoresist mask (not shown) and dry-etched to remove the silicon nitride film 22 and the etching stop silicon oxide film 21 in the nMOS region 12a as shown in FIG. .

  By covering the nMOS with the silicon nitride film 19 having a tensile stress, a tensile strain is applied to the channel region, a high electron mobility can be realized, and the operation speed of the nMOS can be improved. By covering the pMOS with the silicon nitride film 22 having a compressive stress, a compressive strain is applied to the channel region, a high hole mobility can be realized, and the operating speed of the pMOS can be improved.

The result of measuring the sheet resistance of the tungsten film in the semiconductor device manufactured by the above process is shown below.
First, as a comparative example, the sheet resistance of the tungsten film 87 formed in the step shown in FIG. 18 is shown.

4A and 4B are diagrams showing the sheet resistance of the tungsten film formed in the process of FIG. 18, where FIG. 4A shows the sheet resistance of nMOS, and FIG. 4B shows the sheet resistance of pMOS.
The horizontal axis represents the sheet resistance [ohm / sq. The vertical axis represents the cumulative probability [%]. The tungsten film 87 having a length (L) of 100 μm and a width (W) of 0.14 μm was measured under the condition that a film was deposited on a blanket n-type silicon substrate at a thickness of 20 nm.

  As shown in FIG. 4A, the sheet resistance in the nMOS is 20 [ohm / sq. As described above, the sheet resistance in the pMOS is 150 [ohm / sq. As shown in FIG. 4B, the sheet resistance of the pMOS has reached about 7.5 times that of the nMOS.

5A and 5B are diagrams showing the sheet resistance of the tungsten film formed in the process of the present embodiment, where FIG. 5A shows the sheet resistance of nMOS, and FIG. 5B shows the sheet resistance of pMOS.
The horizontal axis represents the sheet resistance [ohm / sq. The vertical axis represents the cumulative probability [%]. Tungsten films 17 and 20 having a length (L) of 100 μm and a width (W) of 0.11 μm were measured by depositing both tungsten films 17 and 20 on a blanket n-type silicon substrate under a condition of 30 nm.

  As shown in FIG. 5A, the sheet resistance in the nMOS is 4 [ohm / sq. As described above, as shown in FIG. 5B, the sheet resistance in the pMOS is 5 [ohm / sq. That is all. That is, the sheet resistance of the pMOS is 1.25 times that of the nMOS, and according to the method of manufacturing the semiconductor device of the present embodiment, the resistance of the tungsten films 17 and 20 can be lowered in the pMOS. It has been found that the resistance difference between the pMOSs can be greatly reduced.

  As a result of STEM (Scanning Transmission Electron Microscope) measurement, the film thickness of the tungsten film formed under the conditions shown in FIG. 4 is 26.1 nm for nMOS and 11.8 nm for pMOS. On the other hand, the nMOS was about 2.2 times thicker. On the other hand, the film thickness of the tungsten film of the semiconductor device of this embodiment formed under the conditions of FIG. 5 is 41.4 nm for nMOS, and 31.4 nm for pMOS. The nMOS was about 1.25 times thicker than the pMOS. Generally, the allowable range of the film thickness difference between the pMOS and the nMOS is about 1.5 times or less, so 1.25 times is within the allowable range.

Next, a method for manufacturing the semiconductor device according to the second embodiment will be described.
The method of manufacturing the semiconductor device of the second embodiment is an example in which silicon germanium (SiGe) is used for the source / drain diffusion layer and gate electrode of the pMOS, and the others are the methods of manufacturing the semiconductor device of the first embodiment. It is almost the same as the method.

6 to 9 are cross-sectional views in each step of the method of manufacturing the semiconductor device according to the second embodiment.
First, nMOS and pMOS regions are formed on a semiconductor substrate by the same process as that of the semiconductor device manufacturing method of the first embodiment. For example, as shown in FIG. 6A, an STI 31 filled with, for example, a silicon oxide film is formed on a silicon substrate 30 as an element isolation region, thereby defining an nMOS region 32a and a pMOS region 32b. Thereafter, gate insulating films 33a and 33b, gate electrodes 34a and 34b, and sidewall insulating films 35a and 35b are formed in each region. Thereafter, ion implantation is alternately performed on the nMOS region 32a and the pMOS region 32b to form source / drain diffusion layers 36a and 36b. The manufacturing conditions and the like in the above steps are the same as those in the method for manufacturing the semiconductor device of the first embodiment, and thus description thereof is omitted.

  Thereafter, a silicon oxide film 37 having a thickness of about 40 nm is formed on the entire surface of the nMOS region 32a and the pMOS region 32b by, for example, the CVD method. Subsequently, as shown in FIG. 6B, the silicon oxide film 37 is patterned by photolithography and dry etching to leave the nMOS region 32a and remove the pMOS region 32b. Then, using the patterned silicon oxide film 37 as a mask, the silicon substrate 30 is etched with a high selectivity with respect to the silicon oxide film 37 by, for example, the RIE method. Thereby, for example, recesses having a depth of 50 μm are formed in the source / drain diffusion layers 36b on both sides of the sidewall insulating film 35b of the pMOS region 32b. At this time, the upper portion of the gate electrode 34b made of a polysilicon film or an amorphous silicon film is also slightly removed by etching.

Next, the surface of the silicon substrate 30 in which the recesses are formed is cleaned using, for example, dilute hydrofluoric acid (for example, HF: H ₂ O = 5: 100) for 5 seconds. Thereafter, as shown in FIG. 6C, dopant impurities are introduced into the recesses above the gate electrode 34b and the source / drain diffusion layer 36b by, for example, CVD using the silicon oxide film 37 as a mask. The formed silicon germanium film (Si _1-x Ge _x film) 38 is selectively epitaxially grown. For example, boron is used as the dopant impurity. The composition ratio x of germanium can be appropriately set within the range of 0 <x <1.

  Since the lattice constant of silicon germanium is larger than that of silicon, compressive strain is applied to the channel region of the pMOS. As a result, high hole mobility is realized, and the operating speed of the pMOS can be improved.

  Next, after the silicon oxide film 37 formed in the nMOS region 32a is removed by etching, the surfaces of the gate electrodes 34a and 34b and the source / drain diffusion layers are formed by, for example, plasma treatment such as hydrogen or ammonia or dilute hydrofluoric acid treatment. The natural oxide films (not shown) formed on the surfaces of 36a and 36b are removed. Then, as shown in FIG. 7A, the tungsten film 39 is formed by using a CVD method, for example, using tungsten hexafluoride and silane as the source gas, and a film forming temperature of 200 to 400 ° C. and a pressure of 0.1 to 10 Pa. Then, a film having a thickness of about 5 to 40 nm is selectively formed on the gate electrodes 34a and 34b and the source / drain diffusion layers 36a and 36b.

  At this time, the film formation rate is different between the nMOS region 32a and the pMOS region 32b, and the pMOS region 32b is thinner than the nMOS region 32a. Here, the film thickness of the tungsten film 39 in the nMOS region 32a is formed so as to be an optimum value (for example, a film thickness value that achieves a target sheet resistance).

  Further, as shown in FIG. 7B, an etching stop silicon oxide film 40 and a silicon nitride film 41 having a tensile stress are sequentially stacked on the nMOS region 32a and the pMOS region 32b so as to cover the tungsten film 39. For example, the CVD method is used to form the etching stop silicon oxide film 40 with a thickness of about 1 to 20 nm and the silicon nitride film 41 with a thickness of about 20 to 100 nm.

  Next, the nMOS region 32a is masked with a photoresist mask (not shown) and dry-etched, so that the silicon nitride film 41 and the etching stop silicon oxide film in the pMOS region 32b are formed as shown in FIG. 7C. 40 is removed.

  Thereafter, for example, a natural oxide film (not shown) formed on the surface of the gate electrode 34b and the surface of the source / drain diffusion layer 36b of the pMOS region 32b by plasma treatment such as hydrogen or ammonia or dilute hydrofluoric acid treatment. Remove.

  Then, as shown in FIG. 8A, the tungsten film 42 is selectively formed on the tungsten film 39 on the gate electrode 34b and the source / drain diffusion layer 36b in the pMOS region 32b. The tungsten film 42 is formed with a film thickness of about 5 to 40 nm at a film forming temperature of 200 to 400 ° C. and a pressure of 0.1 to 10 Pa using, for example, a source gas of tungsten hexafluoride and silane by using the CVD method. .

  Through such a process, the tungsten film 42 is not formed in the nMOS region 32a that is still covered with the silicon nitride film 41, and the tungsten film 42 having a desired thickness is formed only on the tungsten film 39 in the pMOS region 32b. Can be additionally deposited. As a result, the film thickness of the tungsten film 39 in the nMOS region 32a can be set to the optimum value.

  Thereafter, as shown in FIG. 8B, an etching stop silicon oxide film 43 and a silicon nitride film having a compressive stress are formed on the silicon nitride film 41 and the pMOS region 32b in the nMOS region 32a so as to cover the tungsten film. 44 are sequentially laminated. For example, the CVD method is used to form the etching stop silicon oxide film 43 with a thickness of about 1 to 20 nm and the silicon nitride film 44 with a thickness of about 20 to 100 nm.

  Then, as shown in FIG. 9, the pMOS region 32b is masked with a photoresist mask (not shown), and the nMOS region 32a is dry-etched to thereby etch the silicon nitride film 44 and the etching stop silicon oxide film 43 in the nMOS region 32a. Remove.

  By covering the nMOS with the silicon nitride film 41 having a tensile stress, tensile strain is applied to the channel region, high electron mobility can be realized, and the operation speed of the nMOS can be improved. By covering the pMOS with the silicon nitride film 44 having a compressive stress, a compressive strain is applied to the channel region, a high hole mobility can be realized, and the operating speed of the pMOS can be improved.

  As described above, in the method of manufacturing the semiconductor device of the second embodiment, the tungsten film 42 is selected on the tungsten film 39 in the pMOS region 32b, as in the method of manufacturing the semiconductor device of the first embodiment. Therefore, the resistance difference between the nMOS and the pMOS can be reduced.

Next, a method for manufacturing the semiconductor device of the third embodiment will be described.
In the semiconductor device manufacturing methods of the first and second embodiments described above, a tungsten film in the pMOS region that is formed thinner than the nMOS region is additionally deposited. In contrast, in the method of manufacturing the semiconductor device according to the third embodiment, when the tungsten film is simultaneously formed in the nMOS region and the pMOS region, the tungsten film in the pMOS region is formed to have a target thickness. The tungsten film in the nMOS region that is too thick is removed, and a tungsten film is formed again in the target film thickness only in the nMOS region.

10 to 13 are cross-sectional views in each step of the semiconductor device manufacturing method according to the third embodiment.
First, nMOS and pMOS regions are formed on a semiconductor substrate in the same process as the method of manufacturing the semiconductor device of the second embodiment. For example, as shown in FIG. 10A, an STI 51 filled with, for example, a silicon oxide film is formed on a silicon substrate 50 as an element isolation region, thereby defining an nMOS region 52a and a pMOS region 52b. Thereafter, gate insulating films 53a and 53b, gate electrodes 54a and 54b, and sidewall insulating films 55a and 55b are formed in the respective regions. Thereafter, ion implantation is performed alternately on the nMOS region 52a and the pMOS region 52b to form source / drain diffusion layers 56a and 56b. Thereafter, a silicon germanium film 57 is formed on the gate electrode 54b and the source / drain diffusion layer 56b in the pMOS region 52b. The manufacturing conditions in the above steps are the same as those in the method for manufacturing the semiconductor device of the second embodiment, and a description thereof will be omitted.

  Thereafter, for example, natural oxide films (not shown) formed on the surfaces of the gate electrodes 54a and 54b and the surfaces of the source / drain diffusion layers 56a and 56b by plasma treatment with hydrogen or ammonia or dilute hydrofluoric acid treatment, for example. Remove. Then, as shown in FIG. 10B, the tungsten film 58 is formed by using the CVD method, for example, using tungsten hexafluoride and silane as the source gas, and a film forming temperature of 200 to 400 ° C. and a pressure of 0.1 to 10 Pa. Then, a film is selectively formed to a thickness of about 5 to 40 nm on the gate electrodes 54a and 54b and the source / drain diffusion layers 56a and 56b.

  At this time, the film formation rate is different between the nMOS region 52a and the pMOS region 52b, and the pMOS region 52b is thinner than the nMOS region 52a. Here, unlike the semiconductor device manufacturing methods of the first and second embodiments, the tungsten film 58 in the pMOS region 52b is formed so as to have an optimum thickness.

  Further, as shown in FIG. 11A, an etching stop silicon oxide film 59 and a silicon nitride film 60 having a compressive stress are sequentially stacked on the nMOS region 52a and the pMOS region 52b so as to cover the tungsten film 58. For example, the CVD method is used to form the etching stop silicon oxide film 59 with a thickness of about 1 to 20 nm and the silicon nitride film 60 with a thickness of about 20 to 100 nm.

  Next, the pMOS region 52b is masked with a photoresist mask (not shown), and dry etching is performed as shown in FIG. 11B, whereby the silicon nitride film 60 and the etching stop silicon oxide film in the nMOS region 52a are etched. 59 is removed.

Then, the tungsten film 58 formed on the gate electrode 54a and the source / drain diffusion layer 56a in the nMOS region 52a is subjected to a chemical treatment using any one of sulfuric acid / hydrogen peroxide / aqueous ammonia, or a combination thereof. Remove. For example, the composition of sulfuric acid (H ₂ SO ₄ ) when using sulfuric acid / hydrogen peroxide is 50 to 95%, for example, and the composition of hydrochloric acid (HCl) in hydrochloric acid / water is 0.1 to 25%, The composition of ammonia (NH ₄ OH) in the ammonia overwater is, for example, 0.1 to 25%, and the temperature of the chemical solution is, for example, 30 to 150 ° C. in any chemical treatment.

  Thereafter, for example, a natural oxide film (not shown) formed on the surface of the gate electrode 54a and the surface of the source / drain diffusion layer 56a of the nMOS region 52a by plasma treatment such as hydrogen or ammonia or dilute hydrofluoric acid treatment. Remove.

  Then, as shown in FIG. 12A, a tungsten film 61 is selectively formed on the gate electrode 54a and the source / drain diffusion layer 56a in the nMOS region 52a. The tungsten film 61 is formed by CVD using, for example, a source gas of tungsten hexafluoride and silane with a film forming temperature of 200 to 400 ° C. and a pressure of 0.1 to 10 Pa, and a film thickness of about 5 to 40 nm. .

  Through such a process, the tungsten film 61 is not formed in the pMOS region 52b that is still covered with the silicon nitride film 60, and the tungsten film 61 can be deposited only in the nMOS region 52a with a desired thickness. it can. As a result, the film thickness of the tungsten film 58 in the pMOS region 52b can be set to the optimum value.

  Thereafter, as shown in FIG. 12B, the silicon nitride film 60 in the pMOS region 52b and the silicon nitride film having a tensile stress on the nMOS region 52a and the silicon nitride film 60 having a tensile stress so as to cover the tungsten film 61. Films 63 are sequentially stacked. For example, using the CVD method, the etching stop silicon oxide film 62 is formed with a thickness of about 1 to 20 nm, and the silicon nitride film 63 is formed with a thickness of about 20 to 100 nm.

  Then, the nMOS region 52a is masked with a photoresist mask (not shown), and the pMOS region 52b is dry-etched as shown in FIG. 13 to dry the silicon nitride film 63 and the etching stop silicon oxide film 62 in the pMOS region 52b. Remove.

  By covering the nMOS with the silicon nitride film 63 having tensile stress, tensile strain is applied to the channel region, high electron mobility can be realized, and the operation speed of the nMOS can be improved. By covering the pMOS with the silicon nitride film 60 having a compressive stress, a compressive strain is applied to the channel region, a high hole mobility can be realized, and the operating speed of the pMOS can be improved.

  As described above, in the method of manufacturing the semiconductor device according to the third embodiment, when the tungsten film 58 is simultaneously formed in the nMOS region 52a and the pMOS region 52b, the tungsten film 58 in the pMOS region 52b has a target thickness. Then, the tungsten film 58 in the nMOS region 52a that is too thick is removed, and the tungsten film 61 is formed again in the target film thickness only in the nMOS region 52a. As a result, the tungsten film 61 in the nMOS region 52a becomes too thick, and the possibility of contact between the tungsten film 61 on the gate electrode 54a and the tungsten film 61 in the source / drain diffusion layer 56a can be reduced, and the tungsten film in the pMOS region 52b can be reduced. Since the film thickness can be as high as 58, the resistance difference between nMOS and pMOS can be reduced.

  In the semiconductor device manufacturing method of the third embodiment, silicon is formed on the gate electrode 54b of the pMOS region 52b and the source / drain diffusion layer 56, as in the method of manufacturing the semiconductor device of the first embodiment. Although the germanium film 57 is formed, the silicon germanium film 57 may not be formed as in the method of manufacturing the semiconductor device according to the first embodiment.

Next, a method for manufacturing the semiconductor device of the fourth embodiment will be described.
In the method of manufacturing a semiconductor device according to the fourth embodiment, when a tungsten film is simultaneously formed in an nMOS region and a pMOS region, the tungsten film in the pMOS region which is thinner than the nMOS region is removed, and nickel silicide is formed instead. By doing so, the resistance difference between the nMOS and the pMOS is reduced.

14 to 17 are cross-sectional views in each step of the semiconductor device manufacturing method according to the fourth embodiment.
FIG. 14A is the same as the cross-sectional view shown in FIG. 7C, and up to this step is the same as the semiconductor device manufacturing method of the second embodiment. Next, in the semiconductor device manufacturing method of the second embodiment, a tungsten film in the pMOS region 32b is additionally deposited. In the semiconductor device manufacturing method of the fourth embodiment, as shown in FIG. Thus, the tungsten film 39 in the pMOS region 32b is removed.

  The tungsten film 39 is removed by a chemical treatment using any one of sulfuric acid / hydrogen peroxide, hydrochloric acid / aqueous ammonia, or a combination thereof. For example, the composition of sulfuric acid in the case of using sulfuric acid / hydrogen peroxide is, for example, 50 to 95%, the composition of hydrochloric acid in hydrochloric acid / water is, for example, 0.1 to 25%, and the composition of ammonia in ammonia / water is For example, it is set to 0.1 to 25%, and the temperature of the chemical solution is 30 to 150 ° C. in any chemical treatment, for example.

  Thereafter, for example, a natural oxide film (not shown) formed on the surface of the gate electrode 34b and the surface of the source / drain diffusion layer 36b of the pMOS region 32b by plasma treatment such as hydrogen or ammonia or dilute hydrofluoric acid treatment. Remove.

  Next, as shown in FIG. 15A, a metal film, for example, a nickel film 70 is formed so as to cover the silicon nitride film 41 in the nMOS region 32a, the gate electrode 34b in the pMOS region 32b, and the source / drain diffusion layer 36b. A titanium nitride (TiN) film 71 having a thickness of 5 to 30 nm is formed by a PVD (Physical Vapor Deposition) method as an antioxidant film for the nickel film 70. Here, when forming the nickel film 70, for example, a sputtering method using a nickel target to which 1 to 10 atom% of platinum (Pt) is added may be used. Further, as the antioxidant film, for example, a titanium film having a film thickness of 5 to 30 nm may be used.

Next, as shown in FIG. 15B, by performing a first heat treatment, for example, 200 to 400 ° C. for 10 to 300 seconds, the nickel film 70 in the pMOS region 32b, the upper portion of the gate electrode 34b, and the source / The upper part of the drain diffusion layer 36b is reacted to form a silicide film, for example, a dinickel silicide (Ni ₂ Si) film 72.

  Next, as shown in FIG. 16A, the unreacted portion of the nickel film 70 and the titanium nitride film 71 are removed by chemical treatment. For example, it is removed by chemical treatment using any one of sulfuric acid / hydrogen peroxide / hydrochloric acid / aqueous ammonia, aqua regia, or a combination thereof. For example, the composition of sulfuric acid in the case of using sulfuric acid / hydrogen peroxide is, for example, 50 to 95%, the composition of hydrochloric acid in hydrochloric acid / water is, for example, 0.1 to 25%, and the composition of ammonia in ammonia / water is For example, it is set to 0.1 to 25%, and the temperature of the chemical solution is 30 to 150 ° C. in any chemical treatment, for example.

  Thereafter, for example, a second heat treatment is performed at 300 to 500 ° C. for 10 to 300 seconds to cause the phase change of the die nickel silicide film 72, and as shown in FIG. 16B, a nickel monosilicide (NiSi) film 73. Form.

At this time, no silicide is formed in the nMOS region 32a that is still covered with the silicon nitride film 41, and a silicide film can be formed only in the pMOS region 32b.
Next, as shown in FIG. 17A, an etching stop silicon oxide film 74 and a compression are formed on the nMOS region 32a and the pMOS region 32b so as to cover the nickel monosilicide film 73 and the silicon nitride film 41 in the nMOS region 32a. A silicon nitride film 75 having stress is sequentially laminated. For example, using the CVD method, the etching stop silicon oxide film 74 is deposited about 1 to 20 nm, and the silicon nitride film 75 is deposited about 20 to 100 nm.

  Then, as shown in FIG. 17B, the pMOS region 32b is masked with a photoresist mask (not shown), and the nMOS region 32a is dry-etched, whereby the silicon nitride film 75 and the etching stop silicon in the nMOS region 32a are etched. The oxide film 74 is removed.

  By covering the nMOS with the silicon nitride film 41 having a tensile stress, tensile strain is applied to the channel region, high electron mobility can be realized, and the operation speed of the nMOS can be improved. By covering the pMOS with the silicon nitride film 75 having a compressive stress, a compressive strain is applied to the channel region, a high hole mobility can be realized, and the operating speed of the pMOS can be improved.

  As described above, in the method of manufacturing the semiconductor device according to the fourth embodiment, when the tungsten film 39 is simultaneously formed in the nMOS region 32a and the pMOS region 32b, the tungsten film 39 in the pMOS region 32b that is thinner than the nMOS region 32a. And a silicide film (nickel monosilicide film 73 in the above example) having a desired film thickness can be formed instead, thereby reducing the resistance of the pMOS and reducing the resistance difference between the nMOS and pMOS. be able to.

  In the above description, the nickel monosilicide film 73 is formed by a high-temperature heat treatment after the die nickel silicide film 72 is formed by a relatively low-temperature heat treatment, but the nickel monosilicide film 73 is formed by a single heat treatment. May be formed.

  In the above description, the nickel monosilicide film 73 is formed using the nickel film 70 as the metal film, but the present invention is not limited to this. For example, cobalt, tantalum (Ta), rhenium (Re), zirconium (Zr), titanium, hafnium (Hf), tungsten, platinum, chromium (Cr), palladium (Pd), vanadium (V), and niobium (Nb). Of these, a metal film made of any one or more metals may be used.

The formed silicide film may be a silicide film made of one or more of the above metals.
Further, the protective film is not limited to the titanium nitride film 71, and the above metal or a nitride thereof may be used.

  In the semiconductor device manufacturing method of the fourth embodiment, silicon is formed on the gate electrode 34b of the pMOS region 32b and the source / drain diffusion layer 36b, as in the method of manufacturing the semiconductor device of the second embodiment. Although the germanium film 38 is formed, it is not necessary to form the silicon germanium film 38 as in the method of manufacturing the semiconductor device of the first embodiment.

In the above-described semiconductor device manufacturing methods according to the second to fourth embodiments, the case where the silicon germanium film is formed on the source / drain diffusion layer and the gate electrode of the pMOS has been described. A silicon carbon (Si _1-x C _x ) film having a composition ratio x of 0 <x <1 may be formed on the diffusion layer and the gate electrode.

Further, although an etching stop silicon oxide film is used as an etching stopper, it is not always necessary.
(Appendix 1) Forming an n-channel MOSFET and a p-channel MOSFET having a gate electrode and source / drain diffusion layers on a semiconductor substrate;
Selectively forming a first tungsten film on the gate electrode and the source / drain diffusion layer;
Forming an insulating film so as to cover the first tungsten film;
Removing the insulating film in the formation region of the p-channel MOSFET;
Selectively forming a second tungsten film on the first tungsten film in the formation region of the p-channel MOSFET;
A method for manufacturing a semiconductor device, comprising:

  (Additional remark 2) The said insulating film is a tensile stress film | membrane, It further has the process of forming a compressive-stress film | membrane so that the said 2nd tungsten film may be covered, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.

(Appendix 3) Forming an n-channel MOSFET and a p-channel MOSFET having a gate electrode and source / drain diffusion layers on a semiconductor substrate;
Selectively forming a first tungsten film on the gate electrode and the source / drain diffusion layer;
Forming an insulating film so as to cover the first tungsten film;
Removing the insulating film in the formation region of the n-channel MOSFET;
Removing the first tungsten film in the n-channel MOSFET formation region;
Selectively forming a second tungsten film on the gate electrode and the source / drain diffusion layer of the n-channel MOSFET;
A method for manufacturing a semiconductor device, comprising:

  (Additional remark 4) The said insulating film is a compressive-stress film | membrane, and further has the process of forming a tensile stress film so that the said 2nd tungsten film may be covered, The manufacturing method of the semiconductor device of Additional remark 3 characterized by the above-mentioned.

(Appendix 5) Forming an n-channel MOSFET and a p-channel MOSFET having a gate electrode and source / drain diffusion layers on a semiconductor substrate;
Selectively forming a tungsten film on the gate electrode and the source / drain diffusion layer;
Forming an insulating film so as to cover the tungsten film;
Removing the insulating film in the formation region of the p-channel MOSFET;
Removing the tungsten film in the formation region of the p-channel MOSFET;
Forming a silicide film on the gate electrode and the source / drain diffusion layer in the formation region of the p-channel MOSFET;
A method for manufacturing a semiconductor device, comprising:

(Additional remark 6) The said insulating film is a tensile stress film | membrane, It further has the process of forming a compressive stress film so that the said silicide film may be covered, The manufacturing method of the semiconductor device of Additional remark 5 characterized by the above-mentioned.
(Supplementary Note 7) The metal film used for forming the silicide film is any one of nickel, cobalt, tantalum, rhenium, zirconium, titanium, hafnium, tungsten, cobalt, platinum, chromium, palladium, vanadium, and niobium, or The manufacturing method of a semiconductor device according to appendix 5 or 6, characterized by comprising the above metal.

  (Appendix 8) On the metal film, any one or more of nickel, cobalt, tantalum, rhenium, zirconium, titanium, hafnium, tungsten, cobalt, platinum, chromium, palladium, vanadium and niobium or 8. A method of manufacturing a semiconductor device according to appendix 7, wherein a protective film made of the nitride is deposited.

  (Supplementary Note 9) The silicide film is made of any one or more of nickel, cobalt, tantalum, rhenium, zirconium, titanium, hafnium, tungsten, cobalt, platinum, chromium, palladium, vanadium, and niobium. 9. The method for manufacturing a semiconductor device according to any one of appendices 5 to 8, wherein the semiconductor device is silicide.

  (Supplementary Note 10) In the step of removing the first tungsten film or the tungsten film, the first tungsten is obtained by chemical treatment using any one of sulfuric acid / hydrogen peroxide / aqueous ammonia or a combination thereof. The method for manufacturing a semiconductor device according to any one of appendices 3 to 9, wherein the film or the tungsten film is removed.

(Supplementary Note 11) An Si _1-x Ge _x film having a composition ratio x of 0 <x <1 is formed on the p-channel MOSFET, the n-channel MOSFET, or any of the gate electrodes or the source / drain diffusion layers. 11. The method of manufacturing a semiconductor device according to any one of appendices 1 to 10, wherein a Si _1-x C _x film having a composition ratio x of 0 <x <1 is formed.

(Additional remark 12) The said insulating film is a lamination | stacking of a nitride film and an oxide film, The manufacturing method of the semiconductor device as described in any one of Additional remark 1 thru | or 11 characterized by the above-mentioned.
(Additional remark 13) The said gate electrode is polysilicon or amorphous silicon, The manufacturing method of the semiconductor device as described in any one of additional remark 1 thru | or 12 characterized by the above-mentioned.

It is sectional drawing in each process of the manufacturing method of the semiconductor device of 1st Embodiment (the 1). It is sectional drawing in each process of the manufacturing method of the semiconductor device of 1st Embodiment (the 2). It is sectional drawing in each process of the manufacturing method of the semiconductor device of 1st Embodiment (the 3). It is a figure which shows the sheet resistance of the tungsten film formed at the process of FIG. 18, (A) is a sheet resistance of nMOS, (B) is a figure which shows the sheet resistance of pMOS. It is a figure which shows the sheet resistance of the tungsten film formed at the process of this Embodiment, (A) is a sheet resistance of nMOS, (B) is a figure which shows the sheet resistance of pMOS. It is sectional drawing in each process of the manufacturing method of the semiconductor device of 2nd Embodiment (the 1). It is sectional drawing in each process of the manufacturing method of the semiconductor device of 2nd Embodiment (the 2). It is sectional drawing in each process of the manufacturing method of the semiconductor device of 2nd Embodiment (the 3). It is sectional drawing in each process of the manufacturing method of the semiconductor device of 2nd Embodiment (the 4). Sectional drawing in each process of the manufacturing method of the semiconductor device of 3rd Embodiment which is 1). Sectional drawing in each process of the manufacturing method of the semiconductor device of 3rd Embodiment which is the 2). Sectional drawing in each process of the manufacturing method of the semiconductor device of 3rd Embodiment which is 3). Sectional drawing in each process of the manufacturing method of the semiconductor device of 3rd Embodiment which is 4). Sectional drawing in each process of the manufacturing method of the semiconductor device of 4th Embodiment (the 1). Sectional drawing in each process of the manufacturing method of the semiconductor device of 4th Embodiment 2). Sectional drawing in each process of the manufacturing method of the semiconductor device of 4th Embodiment which is 3). Sectional drawing in each process of the manufacturing method of the semiconductor device of 4th Embodiment which is 4). It is sectional drawing which shows each process in the case of forming a tungsten film in CMOSFET.

Explanation of symbols

10 Silicon substrate 11 STI
12a nMOS region 12b pMOS region 13a, 13b Gate insulating film 14a, 14b Gate electrode 15a, 15b Side wall insulating film 16a, 16b Source / drain diffusion layer 17, 20 Tungsten film 18, 21 Etching stop silicon oxide film 19, 22 Silicon nitride film

Claims (7)

Forming an n-channel MOSFET and a p-channel MOSFET having a gate electrode and a source / drain diffusion layer on a semiconductor substrate;
Selectively forming a first tungsten film on the gate electrode and the source / drain diffusion layer;
Forming an insulating film so as to cover the first tungsten film;
Removing the insulating film in the formation region of the p-channel MOSFET;
Selectively forming a second tungsten film on the first tungsten film in the formation region of the p-channel MOSFET;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a compressive stress film so as to cover the second tungsten film, wherein the insulating film is a tensile stress film. Forming an n-channel MOSFET and a p-channel MOSFET having a gate electrode and a source / drain diffusion layer on a semiconductor substrate;
Selectively forming a first tungsten film on the gate electrode and the source / drain diffusion layer;
Forming an insulating film so as to cover the first tungsten film;
Removing the insulating film in the formation region of the n-channel MOSFET;
Removing the first tungsten film in the n-channel MOSFET formation region;
Selectively forming a second tungsten film on the gate electrode and the source / drain diffusion layer of the n-channel MOSFET;
A method for manufacturing a semiconductor device, comprising:   4. The method of manufacturing a semiconductor device according to claim 3, wherein the insulating film is a compressive stress film, and further includes a step of forming a tensile stress film so as to cover the second tungsten film. Forming an n-channel MOSFET and a p-channel MOSFET having a gate electrode and a source / drain diffusion layer on a semiconductor substrate;
Selectively forming a tungsten film on the gate electrode and the source / drain diffusion layer;
Forming an insulating film so as to cover the tungsten film;
Removing the insulating film in the formation region of the p-channel MOSFET;
Removing the tungsten film in the formation region of the p-channel MOSFET;
Forming a silicide film on the gate electrode and the source / drain diffusion layer in the formation region of the p-channel MOSFET;
A method for manufacturing a semiconductor device, comprising:   6. The method of manufacturing a semiconductor device according to claim 5, wherein the insulating film is a tensile stress film, and further includes a step of forming a compressive stress film so as to cover the silicide film. An Si _1-x Ge _x film having a composition ratio x <0 <x <1 or a composition ratio x is formed on the p-channel MOSFET, the n-channel MOSFET, or any of the gate electrode or the source / drain diffusion layer. The method of manufacturing a semiconductor device according to claim 1, wherein an Si _1-x C _x film _satisfying 0 <x <1 is formed.

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