JP2009151844A - Sram cell circuit and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SRAM (Static Random Access Memory) cell circuit which makes a dedicated read line unnecessary by suppressing limiting conditions on transistor dimensions in ensuring certain write operation and read operation and reducing the number of transistors used, and to provide its driving method. <P>SOLUTION: In the SRAM cell circuit, a positive feedback circuit is constituted by connecting an output node of a first inverter and an input node of a second inverter and also connecting the output node of the second inverter and the input node of the first inverter with a feedback control transistor. The SRAM cell circuit is caused to be in a write state or a read state by making either a write control transistor or a read control transistor into a conducting state after disconnecting the positive feedback circuit by placing the feedback control transistor in the non-conducting state. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an SRAM (Static Random Access Memory) cell circuit and a driving method thereof.

  For convenience of explanation, a node of a circuit in an electric network is referred to as a node. Of course, a node can play two roles. That is, when a partial circuit network having a certain function in a certain circuit network is referred to as a partial circuit, when an electric signal of a partial circuit at one node is output (output node), that node When viewed from other partial circuits connected to, the node may be a node (input node) to which an electric signal is input. The name of the node represents the logic signal of the node (the logic value is 1 or 0, and the logic signal level is represented by a high level H or a low level L). Furthermore, a terminal refers to an electrode provided for electrical connection of circuit elements such as transistors, resistors, and capacitors used in the circuit to the outside. Electrically, a terminal can also serve as a node. In particular, a wiring that supplies power to the circuit is referred to as a power supply line, and a wiring that feeds back a current from the power supply line through the circuit is referred to as a power supply feedback line.

  In the specification, a transistor is a specific example of an electrical switch that has at least one control signal input terminal and at least two signal output terminals, and controls conduction and non-conduction between the two output terminals according to the control signal. This is one of the forms. The transistor is generally an insulated gate field effect transistor (MOST), a bipolar transistor (BPT) or the like. In the case of MOST, its gate is used as a control signal input terminal, and its drain and source are used as two signal output terminals. In the case of BPT, the base is used as a control signal input terminal, and the collector and emitter are used as two signal output terminals. In the following description, a case where MOST is used will be described as an example.

  The SRAM cell circuit using this MOST is, for example, the dual bit line SRAM cell 10 of FIG. That is, the drains of the P-type MOST (PMOST) 20 and the N-type MOST (NMOST) 22 are connected to the output node Q1, the gate electrodes are connected to the input node I1, and the source of the PMOST20 is supplied with power at the node VD1. Connect to line VDDL. Further, the source of the NMOS T22 is connected to the power supply feedback line VSSL at the node VS1 and is an inverter 12 (an inverter is a circuit that outputs an inverted logic signal of a logic signal applied to an input node to an output node, and is used in the same meaning hereinafter. ) Is configured.

  The drains of the P-type MOST (PMOST) 24 and the N-type MOST (NMOST) 26 are connected to the output node Q2, and the gate electrodes are connected to the input node I2. The source of the PMOS T24 is connected to the power supply line VDDL at the node VD2, and the source of the NMOS T26 is further connected to the power supply feedback line VSSL at the node VS2 to constitute the inverter 14.

Output node Q1 of inverter 12 is connected to input node I2 of inverter 14, and output node Q2 is connected to input node I1 of inverter 12 to form a positive feedback circuit (also simply referred to as a feedback circuit or a latch circuit). .
Further, the output node Q1 is connected to the source (or drain) of the NMOS T16, which is an access transistor, and the drain (or source) of the NMOS T16 is connected to the bit line BL at the node D1.

Output node Q2 is connected to the source (or drain) of NMOST18, which is another access transistor, and the drain (or source) of NMOST18 is connected to bit line BLB at node D2.
The gates of the NMOSTs 16 and 18 are connected to the word line WL at nodes P1 and P2, respectively, to constitute one SRAM cell. Note that the logic signal levels of the output nodes Q1 and Q2 are complementary in a steady state (if one is at a high level H, the other is at a low level L).

  For example, when the output node Q1 is at a high level and the output node Q2 is at a low level, the storage contents are determined to store a logic 1 and vice versa. The NMOSTs 16 and 18 serve as read access transistors when reading the stored contents of the SRAM cells to the bit lines BL and BLB, or the logical signals of the bit lines BL and BLB (in this case, BL and BLB are complementary). It is also used as a write access transistor when writing to the SRAM cell.

The output nodes of the two inverters constituting the positive feedback circuit such as the output nodes Q1 to Q2 are also referred to as storage nodes. Further, the logic signal level in the SRAM cell circuit may be different from the logic signal level of the logic circuit outside the memory device using the SRAM cell circuit.
A memory device using a large number of SRAM cells is required to operate at high speed and to have a large memory capacity. For this reason, it is desirable to reduce the area of the SRAM cell, that is, to set the size of each transistor to the smallest possible size.

  However, when reading the stored contents of the SRAM cell, there are potential problems such as preventing malfunctions that cause the stored contents to be inverted and ensuring that the stored contents are written correctly. It is not possible.

  In general, the channel lengths of the NMOSTs 22 and 26, which are the NMOSTs of the inverter, are the minimum dimension (the channel width is often larger than the minimum dimension in consideration of the area and operation speed), and the NMOST16 and 18 of the access transistor are However, the current driving capability is weakened (for example, the channel width is reduced, the channel length is increased, or both), and the current driving capability is stronger than the PMOSTs 20 and 24 that are the PMOSTs of the inverter (for example, PMOST20 and 24). The channel length is set to be longer than that of the NMOSTs 16 and 18, and the channel width is decreased to the opposite, or both).

However, since there is a constraint that the channel width cannot be made smaller than the minimum feasible dimension, the channel width of each transistor must be set to be equal to or larger than the minimum dimension in consideration of this. Therefore, the area of the SRAM cell is increased correspondingly, and the stray capacitance is also increased, resulting in a decrease in the operation speed.
As one means for reducing the cell area, the 40 single bit line SRAM cell circuit of FIG. 8 is proposed in which the number of the two bit lines in FIG. 7 is one and the number of transistors is reduced by one.

  In FIG. 8, each drain of a P-type MOST (PMOST) 50 and an N-type MOST (NMOST) 52 is connected to an output node Q3, and each gate electrode is connected to an input node I3. The source of the PMOST 50 is connected to the power supply line VDDL at the node VD3. Further, the source of the NMOS T52 is connected to the power supply feedback line VSSL at the node VS3 to constitute the inverter 42.

The drains of the P-type MOST (PMOST) 54 and the N-type MOST (NMOST) 56 are connected to the output node Q4, and the gate electrodes are connected to the input node I4.
The source of the PMOST 54 is connected to the power supply line VDDL at the node VD4. Further, the source of the NMOS T56 is connected to the power supply feedback line VSSL at the node VS4 to constitute the inverter 44.

Further, output node Q3 of inverter 42 is connected to input node I4 of inverter 44, and output node Q4 is connected to input node I3 of inverter 42 to constitute a positive feedback circuit.
Furthermore, the output node Q4 is connected to the source (or drain) of the NMOS T46 which is an access transistor. The drain (or source) of the NMOS T46 is connected to the bit line BL at the node D3. The gate of the NMOS T 46 is connected to the word line WL at the node P 3 to constitute one single bit line SRAM cell circuit.

  In the single bit line SRAM cell circuit of FIG. 8, the reading and writing of the stored contents are naturally performed using one bit line BL. In particular, the difference from the dual bit line SRAM cell circuit of FIG. 7 is a write operation, and the potential of the bit line BL is transferred to the output node Q4 of the inverter 44 simultaneously with the input node I3 of the inverter 42 through the access transistor 46. In this case, it must be possible to change the stored contents of the SRAM cell, that is, the logical signal levels of the storage nodes Q3 and Q4 by reliably transferring the logical signal level of the BL, regardless of whether it is high or low.

Low level writing is important when Q4 is high. At this time, if the PMOST 54 is in a conducting state, the conduction resistance of the PMOS T54 is R54, and the conduction resistance of the NMOS T46 of the access transistor is R46L, the potential of Q4 becomes VDD * R46L / (R46L + R54).
The dimensions of transistors 46 and 54 must be set so that this value is sufficiently lower than the logic threshold level VTRI42 of inverter 42 (often set to about VDD / 2).
Here, VDD is the potential of the power supply line VDDL, and the potential of the power supply feedback line VSSL is set to the ground potential (0 V) for simplicity.

On the other hand, high level writing is important when Q4 is at low level. At this time, the NMOS T56 is in a conducting state, and assuming that the conducting resistances of the NMOS Ts 46 and 56 are R46H and R56, respectively, the potential of Q4 becomes VDD * R56 / (R46H + R56), and this value is the logic threshold level VTRI42 of the inverter 42. The dimensions of each NMOS T 46 and 56 must be set to sufficiently exceed.
However, the logic high level of the bit line BL is assumed to be equal to VDD.

  These conditions are stricter requirements than the dual bit line SRAM cell circuit of FIG. The reason for this is that at the time of writing, in the dual bit line SRAM cell circuit of FIG. 7, one of the bit lines of BL or BLB is always at a low level, so that the stored contents can be rewritten through the access transistor on that side. It can be said that it is only necessary to satisfy the low-level write condition.

In the read operation, the bit line potential is set to a high level in advance to be in a high impedance state, and then the word line potential is set to VTRI42.
If the storage node Q4 is at a high level, the high impedance bit line potential hardly changes. However, if the storage node Q4 is at a low level, the access transistor 46 becomes conductive, and the high impedance bit line potential is caused by the NMOS T46 and the conductive NMOS T56. It is discharged and the potential drops.
This difference is detected to detect whether the stored content is high level or low level. Of course, the threshold voltage VTN of the NMOST 46 must be smaller than the VTRI42.

Further, only the potential VTRI42 lower than VDD (about ½ of VDD) can be applied to the gate of the NMOS T46, and the conduction resistance per unit channel width of the NMOS T46 cannot be made sufficiently small, so that the reading speed is slowed down.
In addition, a word line control circuit that generates two types of high-level potentials, VDD and VTRI42, is required, and there is a concern that the memory device as a whole may increase in area and power consumption.

  As one countermeasure against the above-mentioned drawback, the potential VDDL of the SRAM cell circuit is lowered only during the write operation (the potential of the word line WL is kept as it is) to lower the logic threshold level and drive the inverters 42 and 44. A method has been proposed in which a write operation is ensured by temporarily making an inverter with a weak (less charge / discharge current for load capacitance) inverter, but all SRAM cells connected to the same word line WL are proposed. It is necessary to operate the circuit, and a cell power supply voltage control circuit having a high current driving capability is required, and there is a concern that the memory device as a whole further increases in area and power consumption.

The SRAM cell circuit 60 of FIG. 9 solves the problem by providing a read-only bit line as a circuit for relaxing the constraint condition in the read operation of the single bit line SRAM cell circuit, and outputting the contents of the storage node to this through a buffer. It has been known.
In FIG. 9, each drain of a P-type MOST (PMOST) 80 and an N-type MOST (NMOST) 82 is connected to an output node Q5, and each gate electrode is connected to an input node I5.

The source of the PMOST 80 is connected to the power supply line VDDL at the node VD5, and further, the source of the NMOS T82 is connected to the power supply feedback line VSSL at the node VS5 to constitute the inverter 62.
The drains of the P-type MOST (PMOST) 84 and the N-type MOST (NMOST) 86 are connected to the output node Q6, the gate electrodes are connected to the input node I6, and the source of the PMOST84 is the power supply line at the node VD6. Connect to VDDL.
Further, the source of the NMOS T86 is connected to the power supply feedback line VSSL at the node VS6 to constitute the inverter 64.

  Further, the output node Q5 of the inverter 62 is connected to the input node I6 of the inverter 64, and the output node Q6 is connected to the input node I5 of the inverter 62 to constitute a positive feedback circuit.

Further, the input node I5 is connected to the source (or drain) of the NMOS T66 that is the access transistor, and the drain (or source) of the NMOS T66 is connected to the write-only bit line W-BL at the node D4.
The output node Q5 is connected to the gate of the NMOS T68, and the source of the NMOS T68 is connected to the power supply feedback line VSSL at the node VS7.
The drain of the NMOS T68 is connected to the source (or drain) of the NMOS T70, the drain (or source) of the NMOS T70 is connected to the read-only bit line R-BL at the node D5, and the gate of the NMOS T70 is connected to the node P5. The read control dedicated word line RWL is connected.

The outline of the operation is as follows.
First, in a holding state in which neither a read operation nor a write operation is performed, the potentials of the write control dedicated word line WWL and the read control dedicated word line RWL are low, the NMOSTs 66 and 70 are non-conductive, and the storage node is write only. Logic of output nodes Q5 and Q6 separated from the bit line W-BL and the read-only bit line R-BL, and output nodes (also “storage nodes” for storing states) by a positive feedback circuit composed of inverters 62 and 64 The level is maintained.

In the read operation, for example, the potential of the read-only bit line R-BL is previously set to a high level and then set to a high impedance state, and then the potential of the read-control dedicated word line RWL is set to a high level to make the NMOS T 70 conductive.
If the output node (storage node) Q5 is at a low level, the NMOS T68 is in a non-conductive state, and therefore there is almost no change in the potential of the read-only bit line R-BL.
On the other hand, if the output node (storage node) Q5 is at the high level, the NMOS T68 is in a conductive state, and the read-only bit line R-BL is grounded through the NMOS T68 and 70, so that the potential decreases. The stored contents can be read by detecting the potential difference between these read-only bit lines R-BL.

  In this read operation, a low-impedance current path from the storage node to the read-only bit line R-BL line and the write-only bit line W-BL line is not configured, so that the storage contents change during the read operation period. There is no need to determine the dimensions of each transistor in consideration. That is, it can be said that there are no restrictions on the size of each transistor for performing the read operation in the SRAM cell circuit of FIGS.

On the other hand, in the write operation, the potential of the read control dedicated word line RWL is kept at a low level so that the stored contents of this cell are not affected by the potential of the read dedicated bit line R-BL, and the potential of the write control dedicated word line WWL is The NMOST 66 which is an access transistor is set in a conductive state at a high level.
As a result, the potential of the write-only bit line W-BL is transferred to the input node I5 of the inverter 62. If the potential of input node I5 becomes equal to or lower than logic threshold value VTRI62 of inverter 62, output node Q5 is at a high level, and therefore input node I6 is also at a high level, so that output node Q6 is at a low level.

On the contrary, if the potential of the input node I5 becomes VTRI62 or higher, the output node Q5 becomes low level, and therefore I6 also becomes low level, so that the output node Q6 becomes high level.
However, the input node I5 is connected to the output node Q6, and the output node Q6 is at the low level or the high level immediately before the write operation. That is, the output node Q6 is connected to the power supply feedback line VSSL through the NMOS T86. Or is connected to the power supply line VDDL by the PMOST 84.

Therefore, the stable write operation cannot be performed unless the dimensions of the transistors, NMOST66, PMOST84 and NMOST86 are set appropriately, as in FIG. When the threshold voltage of the access transistor 66 is VT66 and the high level potential of the WWL line is VDD, the input node I5 becomes the maximum VDD−VT66, and this value must be larger than the VTRI62 to invert the inverter 62. .
For this reason, the dimensional constraint may increase such that the current drive capability of the PMOST 80 is smaller than that of the NMOS T82 and the value of the VTRI 62 is intentionally reduced, for example, about (VDD−VT66) / 2.

  As a method for solving the disadvantages of the SRAM cell circuit newly provided with the read-only bit line, a single bit line SRAM cell circuit 90 shown in FIG.

In FIG. 10, the drains of the P-type MOST (PMOST) 110 and the N-type MOST (NMOST) 112 are connected to the output node Q8, the gate electrodes are connected to the input node I8, and the source of the PMOST110 is connected to the node VD8. The inverter 92 is configured by connecting to the power supply line VDDL and further connecting the source of the NMOS T112 to the power supply feedback line VSSL at the node VS8.
The drains of the P-type MOST (PMOST) 114 and the N-type MOST (NMOST) 116 are connected to the output node Q9, the gate electrodes are connected to the input node I9, and the source of the PMOST114 is supplied with power at the node VD9. Connect to line VDDL.

Further, the source of the NMOST 116 is connected to the power supply feedback line VSSL at the node VS9 to constitute an inverter 94.
Further, the output node Q8 of the inverter 92 is connected to the input node I9 of the inverter 94, the output node Q9 is connected to the drain (or source) of the PMOST100, and the source (or drain) of the PMOST100 is connected to the input node I8 of the inverter 92. Thus, a positive feedback circuit is configured.

  Further, the gate of the PMOST100 is connected to the write-only word line WWL at the node P6, the input node I8 is connected to the source (or drain) of the NMOST102 which is an access transistor, and the drain (or source) of the NMOST102 is write-only at the node D6. It is connected to the bit line W-BL.

  The output node Q8 of the inverter 92 is connected to the gate of the NMOS T104, the source of the NMOS T104 is connected to the power supply feedback line VSSL at the node VS10, the drain of the NMOS T104 is connected to the source (or drain) of the NMOS T106, and the drain ( Or the source) is connected to the read-only bit line R-BL at the node D7, and the gate of the NMOS T106 is connected to the read-only word line RWL at the node P7. The control circuit 120 appropriately controls the potential of the decoding circuit for selecting this cell, the WWL line, and the RWL line.

The outline of the operation is as follows.
First, in a holding state in which neither a read operation nor a write operation is performed, the potentials of the write-only word line WWL and the read-only word line RWL are at a low level, the NMOSTs 106 and 102 are non-conductive, and the storage node is a write-only bit line W -BL and read-only bit line R-BL are separated from each other, and PMOST100 is in a conductive state to form a positive feedback circuit by inverters 92 and 94 so that the logic levels of storage nodes Q8 and Q9 are maintained.

The read operation is as follows.
The potential of the write-only word line WWL is set to the low level, the input node I8 of the inverter 92 is disconnected from the read-only word line W-BL, and at the same time, the PMOST 100 is turned on to configure the positive feedback circuit to keep the stored contents.
Next, for example, the potential of the read-only bit line R-BL is previously set to a high level and then set to a high impedance state, and then the potential of the read control dedicated word line RWL is set to a high level to make the NMOS T106 conductive.

  The subsequent operation is the same as that in FIG. In this read operation, a low-impedance current path is not formed from each storage node to the read-only bit line R-BL line and the read-only word line W-BL line. It is not necessary to determine the dimensions of each transistor in consideration of the content variation. That is, it can be said that there are no restrictions on the size of each transistor for performing the read operation in the SRAM cell circuit of FIGS.

On the other hand, the write operation is as follows. First, the potential of the read control dedicated word line RWL line remains at a low level, and the output nodes Q8 and Q9 serving as storage nodes are disconnected from the read only bit line R-BL, and the stored contents of this cell 90 are stored in the read only bit line R-BL. The BL line potential is not affected, and conversely, it is not affected.
Next, the potential of the write-only word line WWL line is set to the high level to make the access transistor 102 conductive, and at the same time, the feedback control transistor 100 is made nonconductive to disconnect the positive feedback circuit.
Then, the potential of the write-only bit line W-BL is transferred only to the input node I8 of the inverter 92.

When the potential of input node I8 is sufficiently lower than logic threshold value VTRI92 of inverter 92, output node Q8 is at a high level. Therefore, input node I9 of inverter 94 is also at a high level, so that output node Q9 is at a low level. .
Conversely, if the potential of input node I8 is sufficiently VTRI92 or higher, output node Q8 is at a low level, and therefore input node I9 is also at a low level, so that output node Q9 is at a high level.
After the states of the potentials of the output nodes Q8 and Q9 are thus determined, the potential of the write-only word line WWL line is returned to the low level, the access transistor 102 is turned off, and the cell is disconnected from the write-only bit line W-BL. Further, the feedback control transistor 100 is turned on to reconfigure the positive feedback circuit, and the logic levels of the output nodes Q8 and Q9 as storage are stabilized.

  In this write operation, since the access transistor 102 is only connected to the input node I8 in the high impedance state, there is no size constraint by the write operation in the case of FIGS. However, if the threshold voltage of the access transistor 102 is VT102 and the high level potential of the write-only word line WWL line is VDD, the potential of the input node I8 is VDD-VT102 at maximum, and this value inverts the inverter 92. It is the same as in FIG. 9 that it is necessary to be larger than VTRI 92 sufficient for the reason, and therefore, there are cases where the constraints on the dimensions of the PMOST 110 and the NMOST 112 increase.

  Further, the feedback control transistor 100 is simultaneously controlled by the same control signal of the write-only word line WWL line as the write control transistor 102, thereby causing the following drawbacks. For example, if the storage node Q9 is at a high level and a low level is written from this state, the PMOSTs 100 and 114 and the NMOST102 are in a conductive state at the initial stage of the write operation, and the power supply line VDDL is transferred to the write-only bit line W-BL. Current paths may be formed. Therefore, there is a concern that the rate of decrease in the potential of the input node I8 may be slow.

As described above, the SRAM cell circuit of FIG. 10 has few restrictions on the transistor size due to ensuring the write operation and the read operation, so that, for example, a transistor with the smallest size capable of realizing the SRAM cell circuit can be formed. In principle, it is possible to use only as many as possible.
Therefore, although there is a possibility that the area of the SRAM cell circuit can be reduced, there are still concerns about factors that increase the area, such as requiring a read-only bit line in addition to one bit line, and a large number of transistors, such as eight. There is also a concern that power consumption increases due to an increase in stray capacitance.
US Pat. No. 6,853,578

  SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to suppress a constraint condition on transistor dimensions associated with ensuring a write operation and a read operation, to reduce the number of transistors used, and to eliminate a read-only line. To provide a circuit and a driving method thereof.

In order to achieve the above object, the present invention basically employs the following solutions.
(1) The SRAM cell circuit outputs a first inverter that outputs an inverted signal of the logic signal applied to the input node to the output node, and a second inverter that outputs the inverted signal of the logic signal applied to the input node to the output node. Inverter, a feedback control transistor rendered conductive or non-conductive by a feedback circuit control signal, a write control transistor rendered conductive or non-conductive by a write control signal, and a read control rendered conductive or non-conductive by a read control signal A transistor and a control circuit for outputting all the control signals; the first and second inverters are connected to a power supply line and a power feedback line; and the output node of the first inverter is an input of the second inverter Connected between the output node of the second inverter and the input node of the first inverter. The input node of the first inverter and the bit line are connected by a write control transistor, and the output node of the second inverter and the bit line are connected by a read control transistor.
(2) A potential holding circuit is provided in the SRAM cell circuit of (1) so as to suppress fluctuations in operation in the driving state.
(3) In the SRAM cell circuit of (1), the output node of the first inverter is connected to the input node of the second inverter, and between the output node of the second inverter and the input node of the first inverter. A positive feedback circuit is configured by connecting with feedback control transistors.
(4) In the driving method of the SRAM cell circuit described in the above (3), after the feedback control transistor is turned off and the positive feedback circuit is disconnected, either the write control transistor or the read control transistor is turned on, and the write state is set. Or, it is in a read state.

In the present invention, since the positive feedback circuit is disconnected during the read and write operations, malfunctions such as inversion of stored contents are less likely to occur. Therefore, it is not necessary to adjust and set the dimensions of each transistor, the area occupied by the SRAM cell can be reduced, and the power consumption can be reduced.
In addition, since the positive feedback circuit is disconnected during the read and write operations, restrictions on the design of the SRAM cell circuit are reduced and the design is facilitated. For example, all transistor elements constituting the SRAM cell can have the same dimensions. Furthermore, the dimensions of all the transistor elements constituting the SRAM cell can be set to the minimum dimension as long as the operation can be ensured.
In the present invention, since the positive feedback circuit is disconnected at the time of reading and writing operation, it is possible to suppress the restriction condition on the transistor size associated with ensuring the writing operation and the reading operation, reducing the number of transistors used, and reading. A dedicated line can be dispensed with.
According to the present invention, since the potential holding circuit is provided in the SRAM cell circuit, the operation fluctuation in the driving state can be suppressed.

  Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention.
In FIG. 1, each drain of a P-type MOST (PMOST) 210 and an N-type MOST (NMOST) 212 is connected to an output node Q202, each gate electrode is connected to an input node I202, and the source of the PMOST210 is at a node VD202. The first inverter 202 is configured by connecting to the power supply line VDDL and connecting the source of the NMOS T212 to the power supply feedback line VSSL at the node VS202.

  Further, the drains of the P-type MOST (PMOST) 214 and the N-type MOST (NMOST) 216 are connected to the output node Q204, the gate electrodes are connected to the input node I204, and the source of the PMOST214 is supplied with power at the node VD204. The second inverter 204 is configured by connecting to the line VDDL and connecting the source of the NMOS T216 to the power supply feedback line VSSL at the node VS204.

  The output node Q202 of the inverter 202 is connected to the input node I204 of the inverter 204, the output node Q204 is connected to the drain (or source) of the PMOS T220, and the source (or drain) of the PMOST220 is connected to the input node I202 of the inverter 202. A positive feedback circuit is configured.

  The gate of the PMOS T220 is connected to a feedback circuit control dedicated word line CWL that supplies a feedback circuit control signal at the node P10, the input node I202 is connected to the source (or drain) of the NMOS T222 that is an access transistor, and the drain (or source) of the NMOS T222. ) Is connected to the bit line BL at a node D8, and the gate is connected to a write control dedicated word line WWL for supplying a write control signal at a node P8.

The output node Q204 of the inverter 204 is connected to the source (or drain) of the NMOS T224 that is an access transistor, the drain (or source) of the NMOS T224 is connected to the bit line BL at the node D9, and the gate of the NMOS T224 is read at the node P9. It is connected to a read control dedicated word line RWL that supplies a control signal.
The control circuit 230 appropriately controls the potential of the decoding circuit for selecting the cell, the write control dedicated word line WWL, the feedback circuit control dedicated word line CWL, and the read control dedicated word line RWL, and generates the respective control signals. To do.

In the following, the outline of the operation will be described with the high level of the logic signal in the SRAM cell circuit 200 as the potential VDD of the power supply line VDDL and the low level as the potential of the power supply feedback line VSSL (ground, 0 V).
In addition, a transistor is in a low resistance state that is practically sufficient as a conductive state, and a non-conductive state is a high resistance state that is practically sufficient (in recent micro-sized transistors, it cannot be said that this resistance value is sufficiently large. The increase in leakage current is a problem).

First, in a holding state in which neither a read operation nor a write operation is performed, the potentials of the write control dedicated word line WWL and the read control dedicated word line RWL line are at a low level (LL), that is, the gates of the NMOSTs 222 and 224 have a low level. Levels are applied, these are in a non-conductive state, and the output nodes Q202 and 204 serving as storage nodes are disconnected from the bit line BL (actually, they can be regarded as being connected with high resistance).
Further, the feedback circuit control dedicated word line CWL is also at a low level, and a low level is applied to the gate of the PMOST 220, which is in a conductive state, and a positive feedback circuit is configured by the inverters 202 and 204 to serve as a storage node. The logical levels of the nodes Q202 and Q204 are maintained.
Further, the bit line BL is kept at a high level (HL) and is in a low impedance state. However, when the leakage current through the SRAM cell circuit in the holding state cannot be ignored as the power consumption, the high impedance state is set. In that case, the level of the bit line may drop from HL.

Next, the reading operation will be described. FIG. 2 shows temporal changes in the potentials of the feedback circuit control dedicated word line CWL, the read control dedicated word line RWL, and the bit line BL at that time.
First, the potential of the write control dedicated word line WWL is not shown, but is kept at a low level (LL), the NMOS T222 is turned off, and the input node I202 of the inverter 202 is disconnected from the bit line BL. Note that the potential of the write control dedicated word line WWL line is not set to the high level unless the write operation is started.

From this state, the battery is once charged to a high level, and then the bit line BL is temporarily set in a high impedance state to start a read operation.
Next, the feedback circuit control dedicated word line CWL is set to a high level (HL) to turn off the PMOST 220 and disconnect the feedback circuit.
The two operation timings may be simultaneous. Thereafter, after a predetermined time TRE1, the potential of the read control dedicated word line RWL is set to a high level (HL), the NMOS T224 is turned on, and the reading of the specific stored contents is started. The fixed time TRE1 is desirably set to a time for which the PMOST 220 is in a sufficiently high resistance state.

If the storage node Q204 is at high level (HL), the potential of the bit line BL remains almost HL as shown in the figure.
In this case, since there is almost no difference from the high level, data indicating the high level is output from the sense amplifier or the like connected to the bit line BL.

The pulse width TWR of the read control dedicated word line RWL is set to a time sufficient to output this data, and the potential of the read control dedicated word line RWL line is kept at a high level during that time.
Thereafter, the potential of the read control dedicated word line RWL is set to a low level to disconnect the storage node Q204 from the bit line BL.
Further, after a predetermined time TRE2, the potential of the feedback circuit control dedicated word line CWL line is set to the low level to make the PMOST 220 conductive, and the positive feedback circuit by the inverters 202 and 204 is reconfigured. The fixed time TRE2 is desirably set to a time when the NMOS T224 is in a sufficiently high resistance state.
Thereafter, the potential of the bit line is charged again to the high level, and the holding state (HOLD) is entered. This operation may be the same as the timing for returning the feedback circuit control dedicated word line CWL to the low level.

If the storage node Q204 is at a low level, a current path from the bit line BL to the power supply feedback line VSSL is formed by the conductive NMOSTs 224 and 216, so that the potential of the bit line BL starts to decrease, and the difference from the high level after TDR time. Is at a level that can be detected by a sense amplifier or the like, data indicating that the sense amplifier is at a low level is output.
The potential of the read control dedicated word line RWL line is kept at the high level (HL) for the pulse width TRW of the read control dedicated word line RWL, but this pulse width TRW is not a sufficient time to output this data. must not.

After that, similarly to the case where the storage node Q204 is at the high level (HL), the potential of the read control dedicated word line RWL is set to the low level to disconnect the storage node Q204 from the bit line BL. The positive feedback circuit by the inverters 202 and 204 is reconfigured by setting the potential of the control-dedicated word line CWL to a low level and bringing the PMOST 220 into a conductive state.
The fixed time TRE2 is a time until the NMOS T224 becomes sufficiently high in resistance.
Thereafter, the potential of the bit line is returned to a high level and low impedance state, and a holding state (HOLD) is entered.
This operation may be the same as the timing of returning the feedback circuit control dedicated word line CWL line to the low level.

In both the high-level read operation and the low-level read operation, the pulse width TCW for holding the feedback circuit control-dedicated word line CWL line at the high level (HL) is the time until the above operations are completely completed. That's it.
When the positive feedback circuit is reconfigured after the read operation, it is important to recover the state before the read operation. During the read operation period, the input node I202 is in a high impedance state because the PMOST220 and the NMOST222 are in a non-conducting state, so that the capacitance connected to this node (for example, the parasitic capacitance due to the gate capacitance of 210, 212, wiring, etc.) Thus, since the potential is held in the previous state, the previous state can be recovered even after the memory state is read.

If the holding time of the potential at the input node I202 is insufficient, the operation speed is slowed down. However, the capacitor may be intentionally connected to the node I202 to adjust the holding time to be longer.
Further, in the read operation, the output node Q204 and the node I202 are separated by the non-conducting PMOST 220, and therefore the influence of the potential of the output node Q204 on the input node I202 is very small. That is, it is not necessary to consider a malfunction in which the potential of the input node I202, that is, the potential of the output node Q202 (the input node I204 is also the same potential) is inverted due to a temporary increase or decrease in the potential of the output node Q204. Therefore, it can be said that there are very few restrictions on the dimensions of each transistor in the read operation.

On the other hand, the write operation is as follows. FIG. 3 shows temporal changes in the potentials of the feedback circuit control dedicated word line CWL, read control dedicated word line RWL, and bit line BL at that time. Since the operation to invert the stored contents is important, the time change at that time is shown.
First, although the potential of the RWL line is not shown, the NMOS T 224 is kept in a non-conductive state while keeping the low level (LL), and the output node Q204 of the inverter 204 is disconnected from the BL.

Next, the bit line BL is set to a logic level (HL or LL) desired to be written, and a low impedance state is set to start a write operation. After the logic bell of this bit line is determined, the positive feedback circuit is disconnected by setting the potential of the feedback circuit control dedicated word line CWL line to the high level and the PMOST 220 in a non-conductive state.
Thereafter, after the time of TWR, the WWL line is set to the high level to make the NMOS T222 conductive, and transfer of the potential of the bit line BL to the input node I202 of the inverter 202 is started. This TWR1 is a time during which the PMOST 220 is in a sufficiently high resistance state when the potential state of each node is as described above.

First, when the bit line is at a low level (LL) and the input node is at a high level (HL) (denoted as 1 in the waveform of FIG. 3), a discharge path is formed from the input node I202 to the bit line BL through the NMOS T222. Therefore, the potential of the input node I202 starts to decrease.
When the potential becomes equal to or lower than the logical threshold value VT202 of inverter 202, the potential of output node Q202 of inverter 202 starts to rise from the low level to the high level.
Since this potential is also the potential of the input node I204 of the inverter 204, the potential of the output node Q204 falls from the high level to the low level.

Thus, after the potential of each node is determined, the potential of the WWL line is changed from the high level to the low level, the NMOS T222 is turned off, and the input node I202 is disconnected from the bit line.
The potential of the WWL line is held at a high level (HL) for a fixed time TWW that is equal to or longer than the time during which the potential of each node is stabilized.
Thereafter, the potential of the feedback circuit control dedicated word line CWL is returned to the low level after 2 hours of TWR, and the PMOST 220 is turned on to reconfigure the positive feedback circuit. This TWR2 is a time during which the NMOS T222 is in a sufficiently high resistance state when the potential state of each node is as described above.

However, in this case, since the potentials of the source and drain of the PMOST 220 are at a low level, the PMOST 220 becomes conductive when either potential increases by the absolute value of the threshold value VT220 (<0).
The output node Q204 is kept at a low level because the NMOS T116 is in a conductive state, but the impedance of the input node I202 is high unless the PMOS T220 is in a low resistance state, and there is a possibility of being charged by the leakage current of the NMOS T222. is there.

However, if the potential rise becomes equal to or greater than the absolute value of VT220, PMOST220 becomes conductive and further potential rise stops. If the absolute value of VT 220 is less than or equal to the logical threshold value VT 202 of inverter 202, the stored contents are not inverted.
Further, the feedback circuit control dedicated word line CWL is further lowered from the low level (LL) to the LL-absolute value (VT220), and if it is set below, the PMOST220 can be made conductive even in the above potential state, and the potential of I202 is set to the low level. Can be stabilized.

Next, when the bit line is at a high level (HL) and the input node is at a low level (LL) (denoted by 2 in the waveform of FIG. 3), a charging path from the bit line BL to the input node I202 through the NMOS T222 is established. As a result, the potential of the input node I202 starts to rise. However, the maximum value is HL−VT222 when the NMOST222 threshold voltage is VT222.
However, if the potential is equal to or higher than the logical threshold value VT202 of inverter 202, the potential of output node Q202 of inverter 202 starts to decrease from the high level to the low level. Since this potential is also the potential of the input node I204 of the inverter 204, the potential of the output node Q204 rises from the low level to the high level.

Thus, after the potential of each node is determined, the potential of the write control dedicated word line WWL is changed from the high level to the low level, the NMOS T222 is turned off, and the input node I202 is disconnected from the bit line.
The pulse width TWW in which the write control dedicated word line WWL line is held at the high level (HL) is also a fixed time longer than the time during which the potential of each node is stabilized.
Further, after TWR 2 hours, the potential of the feedback circuit control dedicated word line CWL is returned to the low level, and the PMOST 220 is turned on to reconfigure the positive feedback circuit.

  This TWR2 (delay time from the rise of the pulse of the feedback circuit control dedicated word line CWL and the fall of the pulse of the write control dedicated word line WWL) is sufficiently high resistance when the NMOS T222 is in the potential state of each node as described above. It is also the time to become a state. In this case, since the potential of both the source and drain of the PMOST 220 is at a high level, the PMOS T220 is always in a conductive state, and the potential of the input node I202 rises from HL-VT222 to HL as shown in FIG. In order for the high level HL of the bit line BL to be transferred to the input node I202 as it is, the high level of the write control dedicated word line WWL may be set higher than HL + VT222 instead of HL.

In both the high-level write operation and the low-level write operation, the pulse width TCWW for holding the feedback circuit control dedicated word line CWL at the high level (HL) is longer than the time until the above-described operation is completed with certainty. Keep it as
In the write operation described above, the input node I202 is charged to the capacitance at the input node I202 because no other low-impedance current path is connected to the bit line BL through the NMOS T222. It is only necessary to discharge or charge the charge through its current path. For this reason, it can be said that there are no restrictions on the relative dimensional relationship between the NMOST 222 and other transistors.

  FIG. 4 shows a second embodiment of the present invention, which is another SRAM cell circuit 300 in which the feedback control transistor is NMOST.

  In FIG. 4, each drain of a P-type MOST (PMOST) 310 and an N-type MOST (NMOST) 312 is connected to an output node Q302, each gate electrode is connected to an input node I302, and the source of the PMOST310 is at a node VD302. The first inverter 302 is configured by connecting to the power supply line VDDL and further connecting the source of the NMOS T312 to the power supply feedback line VSSL at the node VS302.

  The drains of the P-type MOST (PMOST) 314 and the N-type MOST (NMOST) 316 are connected to the output node Q304, the gate electrodes are connected to the input node I304, and the source of the PMOST314 is supplied with power at the node VD304. The second inverter 304 is configured by connecting to the line VDDL and further connecting the source of the NMOS T316 to the power supply feedback line VSSL at the node VS304.

Further, output node Q302 of inverter 302 is connected to input node I304 of inverter 304, output node Q304 is connected to the drain (or source) of NMOS T320, and the source (or drain) of 320 is connected to input node I302 of inverter 302. Thus, a positive feedback circuit is configured.
Further, the gate of the NMOS T320 is connected to the feedback circuit control dedicated word line CWL that supplies the feedback circuit control signal at the node P13, the input node I302 is connected to the source (or drain) of the NMOS T322 that is an access transistor, and the drain ( Or the source) is connected to the bit line BL at the node D10, and the gate is connected to the write control dedicated word line WWL for supplying a write control signal at the node P11.

  The output node Q304 of the inverter 304 is connected to the source (or drain) of the NMOS T324 that is an access transistor, the drain (or source) of the NMOS T324 is connected to the bit line BL at the node D11, and the gate of the NMOS T324 is read at the node P12. It is connected to a read control dedicated word line RWL that supplies a control signal.

  The control circuit 330 appropriately controls the potentials of the decoding circuit for selecting the cell, the write control dedicated word line WWL, the feedback circuit control dedicated word line CWL line and the read control dedicated word line RWL line, and the respective control signals. Is generated.

In this embodiment, the outline of the operation is substantially the same if the phase of the control signal of the feedback circuit control dedicated word line CWL is opposite to that in the case of FIG.
Further differences are as follows. First, although the feedback control transistor 320 is an NMOST, the NMOST is generally poor in high-level transfer efficiency even when a signal to be in a conductive state is applied to its gate, and is transferred if its threshold voltage is VT320. The high level is HL−VT320 and the threshold voltage is lowered.

Therefore, when the node I302 and the node Q304 are at the high level in the holding state, and the bit line BL is at the low level due to the low level write to another cell, the leakage current of the access transistor 322 from the node I302 May cause a leakage current path to the bit line BL, and the potential may decrease.
When the threshold voltage VT320 of the feedback control transistor 320 decreases from the high level, the feedback control transistor 320 becomes a low-resistance conductive state, and current is supplied from the power supply line VDDL through the PMOST 314 of the inverter 304, so that HL−VT320, It will never be

If this value is equal to or higher than the logical threshold voltage VT302 of the inverter 302, the inverter 302 is not inverted and the stored content is held as it is.
In addition, when the bit line BL is returned to the high level, the leakage current path current flows from the bit line to the node I302, so that the potential of the node I302 may be recovered. Absent.
Since the NMOST has a low level transfer efficiency if a signal that makes a conductive state is applied to its gate, when the node I302 and the node Q304 are at a low level, the VSSL line passes from the node I302 through the NMOST316 of the inverter 304. Since the current path to (the potential of which is at a low level) is formed, the potential of I302 is stabilized, so that the stored contents are not inverted regardless of the potential of the bit line.

  When the feedback control transistor 320 is always in a low resistance conductive state in the above holding state, the potential of the node I302 can be prevented from dropping from a high level. For this purpose, the high level of the feedback circuit control dedicated word line CWL may be set higher than HL by VT320 or more.

When the feedback control transistor in FIG. 1 is PMOST, the low level of the feedback circuit control dedicated word line CWL needs to be lower than VSSL (0 V), but a higher positive voltage is supplied than a negative voltage is supplied. This embodiment is advantageous because it is easier.
Actually, the power supply voltage (VDDL potential of VDDL) of the SRAM cell circuit tends to be lower than the power supply voltage (VDDG) of the external circuit in order to increase the operation speed and reduce the power consumption. There is a possibility that this can be solved by setting the high level of the dedicated word line CWL line, the read control dedicated word line RWL, and the write control dedicated word line WWL to the external power supply voltage VDDG.
Of course, it is desirable that VDDG ≧ VDD + VT320 (or the threshold voltage of the access NMOST, such as VT322 or VT324).

Specifically, in the case of FIG. 1 in which the NMOST 500 is used as the feedback control transistor, as shown in FIG. 5, the NMOS T500 is used as a potential holding circuit, and its gate and drain are connected to connect an external power supply line. It is connected to VDDO, and its source is connected to the power supply line VDDL of the SRAM cell.
FIG. 5 is a configuration diagram of an SRAM cell circuit in which a potential holding circuit is provided in the circuit of FIG.
At this time, the threshold voltage of the NMOST 500 may be set to VT320 or higher. Further, the NMOST 500 is not necessary for each cell, and may be common to cells connected to the same power supply line VDDL.

In the case of FIG. 1 in which the PMOST220 is used as the feedback control transistor, as shown in FIG. 6, the PMOST400 is used, and its gate and drain are connected to the external power supply feedback line VSSO, and its source is connected. Is connected to the power supply feedback line VSSL of the SRAM cell.
FIG. 6 is a configuration diagram of an SRAM cell circuit in which a potential holding circuit is provided in the circuit of FIG.
At this time, the threshold voltage of the PMOST 400 may be set to VT220 or less. Further, the PMOST 400 is not necessary for each cell, and may be common to cells connected to the same power supply feedback line VSSL. In this way, it is not necessary to apply a negative voltage (below the voltage of VSSO) to the gate of the PMOST220.

As described above, since the SRAM cell circuit of the present invention has few restrictions on the transistor size due to ensuring the write operation and the read operation, for example, a transistor with the smallest size that can realize the SRAM cell circuit can be formed. In principle, it is possible to use only the structure.
In particular, for example, a so-called fin-type double layer composed of crystalline silicon on an insulating layer on a substrate as disclosed in, for example, Japanese Patent No. 3543117 and US Pat. In an insulated gate gate field effect transistor (two gate electrodes are formed integrally with a channel sandwiched between them and one that is electrically separated from each other), the channel width is the height of the fin. It is not easy to change the height of each transistor.
However, when an SRAM cell circuit is configured using these, if the present invention is applied, the SRAM cell circuit can be configured with the same channel width, so that a high-performance memory device can be configured with simpler processes.

FIG. 2 is a configuration diagram of an SRAM cell circuit having a feedback circuit control transistor with a single bit line according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of a read operation in the first embodiment of the present invention. FIG. 6 is an explanatory diagram of a write operation in the first embodiment of the present invention. It is a block diagram of the SRAM cell circuit which has a feedback circuit control transistor by the single bit line of 2nd Example of this invention. FIG. 5 is a configuration diagram of an SRAM cell circuit in which a potential holding circuit is provided in the circuit of FIG. 4. FIG. 2 is a configuration diagram of an SRAM cell circuit in which a potential holding circuit is provided in the circuit of FIG. 1. It is a block diagram of a conventional dual bit line SRAM cell circuit. It is a block diagram of a conventional single bit line SRAM cell circuit. It is a block diagram of an SRAM cell circuit having a conventional single bit line and a read-only line. It is a block diagram of an SRAM cell circuit having a conventional single bit line and a read-only line and having a feedback circuit control transistor.

Explanation of symbols

16, 18, 46, 66, 70, 102, 106, 222, 224, 322, 324: Access transistors 20, 24, 50, 54, 80, 84, 110, 114, 210, 214, 310, 314: Inverter Configured PMOST
22, 26, 52, 56, 82, 86, 112, 116, 212, 216, 312, 316: NMOST constituting an inverter
68, 104: NMOST for read buffer
100, 220, 320: feedback control transistor 400: PMOST constituting a potential holding circuit
500: NMOST constituting the potential holding circuit
BL, BLB: Bit line W-BL: Write-only bit line R-BL: Read-only bit line WL: Read and write control word line WWL: Write-control dedicated word line RWL: Read-control-only word line CWL: Feedback circuit Control-only word lines I1, I2, I3, I4, I5, I6, I8, I9, I202, I204, I302, I304, Q1, Q2, Q3, Q4, Q5, Q6, Q8, Q9, Q202, Q204, Q302, Q304, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, VS1, VS2, VS3, VS4, VS5, VS6, VS8, VS9, VS202, VS204, VS302, VS304, VD1, VD2, VD3 VD4, VD5, VD6, VD8, VD9, VD202, VD204, VD302, VD304: nodes 12, 14, 42, 44, 62, 64, 92, 94, 202, 204: inverters 120, 230, 330: control circuit 10, 40, 60, 90, 200: SRAM cell circuit HL: High level LL: Low level VDDL: Power supply line VSSL: Power feedback line TCW, TCWW: CWL line pulse width TRW, TWW: RWL pulse width TRE1: RWL line Delay time TRE2 from the rise of the pulse on the CWL line: Decrease of the pulse of the CWL line, Delay time from the fall of the pulse of the RWL line TWR1: Delay of the pulse of the WWL line, Pulse of the CWL line Delay time TWR2 from rising edge: CWL line pass Of the scan of the falling, the delay time from the falling pulse our WWL line TDR: Time high level of the bit line is lowered to a potential sufficient to read VT222: NMOST222 threshold voltage

Claims (19)

A first inverter that outputs an inverted signal of the logic signal applied to the input node to the output node, a second inverter that outputs an inverted signal of the logic signal applied to the input node to the output node, and a feedback circuit control signal A feedback control transistor that is turned on or off by a write control transistor, a write control transistor that is turned on or off by a write control signal, a read control transistor that is turned on or off by a read control signal, and all the control signals A control circuit that outputs
The first and second inverters are connected to the power supply line and the power supply feedback line, the output node of the first inverter is connected to the input node of the second inverter, the output node of the second inverter and the first inverter The input nodes of the first inverter are connected by a feedback control transistor, the input node of the first inverter and the bit line are connected by a write control transistor, the output node of the second inverter and the bit line are connected by a read control transistor,
Positive feedback by connecting the output node of the first inverter and the input node of the second inverter and connecting the output node of the second inverter and the input node of the first inverter with a feedback control transistor. An SRAM cell circuit comprising a circuit.   The control circuit outputs a control signal for making each of the write control transistor and the read control transistor non-conductive, and outputs a control signal for making the feedback control transistor conductive to the feedback control transistor, 2. The SRAM cell circuit according to claim 1, wherein the SRAM circuit is brought into a holding state.   When the control circuit outputs a write control signal for making it conductive to the write control transistor, the control circuit outputs a control signal for making it non-conductive to the feedback control transistor, and outputs it to the read control transistor. 2. The SRAM cell circuit according to claim 1, wherein a control signal for turning off the power supply is output to put the SRAM circuit in a write state.   The control circuit, when outputting a read control signal for making it conductive to the read control transistor, outputs a control signal for making it non-conductive to the feedback control transistor, and outputs it to the write control transistor. 2. The SRAM cell circuit according to claim 1, wherein a control signal for turning off the semiconductor memory is output to place the SRAM circuit in a read state.   The control circuit adjusts a time difference between the output of the write control signal and the feedback circuit control signal so that the feedback control transistor is turned off before the write control transistor is turned on. 2. The time difference between the write control signal and the output of the feedback circuit control signal is adjusted so that the feedback control transistor is turned on after the transistor is turned from a conductive state to a non-conductive state. The described SRAM cell circuit.   The control circuit adjusts a time difference between the output of the read control signal and the feedback circuit control signal so that the feedback control transistor is turned off before the read control transistor is turned on, and the read control transistor 2. The SRAM according to claim 1, wherein a time difference between the output of the read control signal and the feedback circuit control signal is adjusted so that the feedback control transistor is turned on after the state is changed from a conductive state to a non-conductive state. Cell circuit.   In the control circuit, the write control transistor and the read control transistor are n-type field effect transistors, respectively, and the high level of the write control signal and the read control signal is at least higher than the potential of the power supply line, respectively. 2. The SRAM cell circuit according to claim 1, wherein a threshold voltage of the read control transistor is increased.   In the control circuit, the write control transistor and the read control transistor are p-type field effect transistors, respectively, and the low level of the write control signal and the read control signal is at least higher than the potential of the power supply feedback line, respectively. 2. The SRAM cell circuit according to claim 1, wherein an absolute value of a threshold voltage of the read control transistor is lowered.   2. The SRAM cell circuit according to claim 1, wherein the feedback control transistor is a p-type insulated gate field effect transistor.   The feedback control transistor is a p-type field effect transistor, and the control circuit lowers the low level of the feedback control signal by at least the absolute value of the threshold voltage of the feedback control transistor from the potential of the power supply feedback line. The SRAM cell circuit according to claim 1.   The feedback control transistor is an n-type field effect transistor, and the control circuit has a high level of the feedback control signal higher than a potential of a power supply line by at least a threshold voltage of the feedback control transistor. The SRAM cell circuit according to claim 1.   The write control transistor, the read control transistor, and the previous feedback control transistor are n-type field effect transistors, respectively, and at least the potential of the power supply line is higher than the high level of the write control signal, the read control signal, and the feedback control signal. 2. The SRAM cell circuit according to claim 1, wherein threshold voltages of the write control transistor, the read control transistor, and the feedback control transistor are lowered.   Each of the write control transistor, the read control transistor, and the previous feedback control transistor is a p-type field effect transistor, and at least the potential of the power supply line is lower than the low level of the write control signal, the read control signal, and the feedback control signal. 2. The SRAM cell circuit according to claim 1, wherein the SRAM cell circuit is higher than absolute values of threshold voltages of the write control transistor, the read control transistor, and the feedback control transistor.   11. The method of driving an SRAM cell circuit according to claim 10, wherein after the feedback control transistor is turned off and the positive feedback circuit is disconnected, either the write control transistor or the read control transistor is turned on. A driving method of an SRAM cell circuit, wherein the driving state is a writing state or a reading state.   15. The method of driving an SRAM cell circuit according to claim 14, wherein each of the write control transistor and the read control transistor is turned off, the feedback control transistor is turned on, and the SRAM circuit is held.   15. The SRAM cell according to claim 14, wherein when the write control transistor is in a conductive state, the feedback control transistor is nonconductive, the read control transistor is nonconductive, and the SRAM circuit is in a write state. Circuit driving method.   15. The SRAM according to claim 14, wherein when the read control transistor is in a conductive state, the feedback control transistor is nonconductive, the write control transistor is nonconductive, and the SRAM circuit is in a read state. A driving method of a cell circuit.   The feedback control transistor is turned off before the write control transistor is turned on, and the feedback control transistor is turned on after the write control transistor is turned off. 15. A method for driving an SRAM cell circuit according to claim 14.   The control circuit sets the feedback control transistor to a non-conductive state before the read control transistor becomes conductive, and sets the feedback control transistor to a conductive state after the read control transistor changes from a conductive state to a non-conductive state. 15. The method of driving an SRAM cell circuit according to claim 14, wherein:

Images