JP2009141213A - Semiconductor device and method for inspecting the same - Google Patents

Semiconductor device and method for inspecting the same Download PDF

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JP2009141213A
JP2009141213A JP2007317498A JP2007317498A JP2009141213A JP 2009141213 A JP2009141213 A JP 2009141213A JP 2007317498 A JP2007317498 A JP 2007317498A JP 2007317498 A JP2007317498 A JP 2007317498A JP 2009141213 A JP2009141213 A JP 2009141213A
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substrate
opening
semiconductor element
semiconductor chip
filler
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Tatsunori Sato
龍典 佐藤
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Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device exhibiting high reliability by preventing an air bubble or a foreign matter into a filling agent which is filled in a gap between a semiconductor and a substrate and by sufficiently reinforcing a junction section between the semiconductor device and the substrate. <P>SOLUTION: As shown in Fig.1, the semiconductor chip 10 includes projection portions 12, 12, 12, 12 for holding the distances between the semiconductor chip 10 and a substrate 20 at a predetermined distance, the substrate 20 includes a digged-in part 21 formed into a shape corresponding to the semiconductor chip 10 and fitted with the semiconductor chip 10, and a first opening 22 and a second opening 23 communicating with the digged-in part 21 to outside. In the first opening 22, an under-filling agent 31 of the predetermined amount is filled into a gap between the semiconductor chip 10 and the substrate 20 while discharging air from the second opening 23, in the state of closely contacting the semiconductor chip 10, the substrate 20 and a nozzle 32 for filling the under-filling agent 31, to reinforce a junction between the semiconductor chip 10 and the substrate 20. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置に関し、より詳細には、半導体装置の製造工程における充填剤の充填状態を検査する技術に関する。   The present invention relates to a semiconductor device, and more particularly to a technique for inspecting a filling state of a filler in a manufacturing process of a semiconductor device.

従来、ＩＣチップ等の半導体素子を樹脂等で被覆するパッケージ方法として、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）が広く知られている。このＢＧＡは、平板状の直方体のパッケージの下面に外部入力／出力用の端子となる略球形のはんだ等をアレイ状に配列する方法である。
このＢＧＡ型のパッケージを基板に実装して構成される半導体装置では、該パッケージと基板との隙間に熱硬化性樹脂等からなる充填剤を充填し、所定の温度で所定の時間保持して、該充填剤を硬化させることによって、半導体素子と基板との接合部分を補強して、熱膨張による接合部分の破断等の劣化を防止している。 Conventionally, BGA (Ball Grid Array) is widely known as a packaging method for coating a semiconductor element such as an IC chip with a resin or the like. This BGA is a method in which a substantially spherical solder or the like serving as an external input / output terminal is arranged in an array on the lower surface of a flat rectangular parallelepiped package.
In a semiconductor device configured by mounting this BGA type package on a substrate, a filler made of a thermosetting resin or the like is filled in a gap between the package and the substrate, and held at a predetermined temperature for a predetermined time, By curing the filler, the joint portion between the semiconductor element and the substrate is reinforced, and deterioration such as breakage of the joint portion due to thermal expansion is prevented.

しかし、充填剤の充填不足、又は充填剤の広がりに際する気泡（ボイド）の発生若しくは異物の混入などの充填不良により、硬化後の充填層における強度が不均一となり、半導体素子と基板との接合部分の補強が十分ではないという問題が起こる。   However, due to insufficient filling of the filler, or generation of bubbles (voids) during the spreading of the filler or mixing of foreign matters, the strength in the filled layer after curing becomes non-uniform, and the semiconductor element and the substrate The problem arises that the joints are not sufficiently reinforced.

このような問題を解消する技術として、所定角度に傾けた基板と半導体素子との間に、第一の加熱装置により所定温度に加熱された充填剤を上方から流し込み、該充填剤が流し込む位置と反対側の位置に到達することを認識した後に、前記基板を水平位置に変更する技術が公知となっている（特許文献１参照）。
上記のように構成することにより、充填剤を流し込む途中に加熱することにより、流れ性を良好にし、かつ、流下するに従って細糸状に絞られることによって、気泡を脱気させることができ、さらに、流れ出し途中にある充填剤を毛細管現象により戻すことができ、充填剤のはみ出し具合のばらつきを均一化できる。
しかしながら、充填剤が半導体素子と基板との隙間に広がる際に、当該隙間の空気を巻き込む可能性がある。そして、上記のような構成では、充填剤の中に気泡（ボイド）が残っているかどうかを検出する手段を具備しないために、半導体素子と基板との接合部分の補強が十分であるという確証を得ることができない点で不利である。 As a technique for solving such a problem, a filler heated to a predetermined temperature by a first heating device is poured from above between a substrate tilted at a predetermined angle and a semiconductor element, and the position where the filler flows A technique for changing the substrate to a horizontal position after recognizing reaching the opposite position is known (see Patent Document 1).
By configuring as described above, by heating in the middle of pouring the filler, the flowability is improved, and by being squeezed into a fine thread shape as it flows down, bubbles can be degassed, The filler in the middle of flowing out can be returned by capillarity, and variation in the amount of protrusion of the filler can be made uniform.
However, when the filler spreads in the gap between the semiconductor element and the substrate, there is a possibility that the air in the gap is involved. In the configuration as described above, since there is no means for detecting whether or not air bubbles (voids) remain in the filler, it is confirmed that the joint portion between the semiconductor element and the substrate is sufficiently reinforced. It is disadvantageous in that it cannot be obtained.

また、基板上の充填剤の充填が最も遅れる位置近傍に検出パターンを設けて、該検出パターンをビデオカメラで認識することによって、該検出パターンが充填剤に浸ることによる形状の変化を認識して、充填剤の充填が完了したことを検出する技術は公知となっている（特許文献２参照）。
しかしながら、上記のような構成においても、前記検出パターンが設けられる位置にまで充填剤が充填されているか否かを検出するだけに留まり、充填剤の中に気泡（ボイド）が残っているかどうかを検出することはできない。 In addition, by providing a detection pattern near the position where filling of the filler on the substrate is most delayed and recognizing the detection pattern with a video camera, it is possible to recognize a change in shape due to the detection pattern being immersed in the filler. A technique for detecting the completion of filling with a filler is known (see Patent Document 2).
However, even in the configuration as described above, it only remains to detect whether or not the filler is filled up to the position where the detection pattern is provided, and whether or not bubbles (voids) remain in the filler. It cannot be detected.

また、基板上に形成されるフィレット部をカメラで撮像することによって、その幅を検出し、所定の幅より小さい場合は、前記フィレット部の幅が所定の幅以上になるまで充填剤を追加して吐出する技術は公知となっている（特許文献３参照）。
上記のように構成することにより、フィレット充填間隙における気泡の発生を防止することができる。また、カメラによる撮像によって得られる画像データに基づいて正確にフィレット部の幅を検出することができ、充填剤の追加吐出量をより正確に算出することができる。
さらに、前記フィレット部の検出された幅が所定の基準幅以上となった後に、該フィレット部を撮像して得られた画像データに基づいて、該フィレット部における気泡の生成を検出する技術も公知となっている（同じく特許文献３参照）。
しかしながら、上記のような構成においても、半導体素子の下方に気泡、又は異物の混入があった場合にこれらを検出する手段はなく、正常に近いフィレット部が形成されてしまい、半導体素子と基板との接合部分の補強が十分であるという確証を得ることができない点で不利である。
特開２０００−８２７１５号公報（段落「００１２」〜「００１４」、図１） 特開平１０−７０１４５号公報（段落「００１６」〜「００１８」、図１） 特開２００７−１９４４０３号公報（段落「００６１」、「００６５」、「００８８」、図１） In addition, the width of the fillet formed on the substrate is detected by imaging with a camera. If the width is smaller than a predetermined width, a filler is added until the width of the fillet is equal to or larger than the predetermined width. The technique for discharging is known (see Patent Document 3).
By configuring as described above, it is possible to prevent the generation of bubbles in the fillet filling gap. Further, the width of the fillet portion can be accurately detected based on the image data obtained by imaging with the camera, and the additional discharge amount of the filler can be calculated more accurately.
Further, a technique for detecting the generation of bubbles in the fillet portion based on image data obtained by imaging the fillet portion after the detected width of the fillet portion becomes equal to or greater than a predetermined reference width is also known. (See also Patent Document 3).
However, even in the configuration as described above, there is no means for detecting these when bubbles or foreign substances are mixed under the semiconductor element, and a fillet portion close to normal is formed, and the semiconductor element and the substrate This is disadvantageous in that it cannot be confirmed that the joint is sufficiently reinforced.
JP 2000-82715 A (paragraphs “0012” to “0014”, FIG. 1) JP-A-10-70145 (paragraphs “0016” to “0018”, FIG. 1) JP 2007-194403 A (paragraphs “0061”, “0065”, “0088”, FIG. 1)

本発明は、以上の如き状況を鑑みてなされたものであり、半導体素子と基板との隙間に充填される充填剤への気泡又は異物の混入を防止し、かつ、前記半導体素子と基板との接合部分を十分に補強することにより信頼性の高い半導体装置を提供することを課題とする。   The present invention has been made in view of the above situation, and prevents bubbles or foreign matter from being mixed into the filler filled in the gap between the semiconductor element and the substrate. It is an object to provide a highly reliable semiconductor device by sufficiently reinforcing a joint portion.

本発明の解決しようとする課題は以上の如くであり、次にこの課題を解決するための手段を説明する。   The problems to be solved by the present invention are as described above. Next, means for solving the problems will be described.

請求項１においては、半導体素子と基板との隙間に配置したはんだにより前記半導体素子と前記基板とを接合するとともに、前記隙間に充填剤を充填して前記半導体素子と基板との接合を補強する半導体装置であって、前記半導体素子は、該半導体素子と前記基板との隙間を所定の距離に保持する突起部を具備し、前記基板は、前記半導体素子に対応した形状に形成され、該半導体素子が嵌合される掘り込み部と、前記掘り込み部と外部とを連通する第一開口部および第二開口部と、を具備し、前記第一開口部において、前記半導体素子と、前記基板と、前記充填剤を充填するノズルと、を密着させた状態で、前記半導体素子と前記基板との隙間に、前記ノズルによって前記充填剤を前記第二開口部から空気を放出しながら所定量充填することにより、前記半導体素子と前記基板との接合を補強したものである。   According to another aspect of the present invention, the semiconductor element and the substrate are joined by solder disposed in a gap between the semiconductor element and the substrate, and the gap is filled with a filler to reinforce the joining between the semiconductor element and the substrate. In the semiconductor device, the semiconductor element includes a protrusion that holds a gap between the semiconductor element and the substrate at a predetermined distance, and the substrate is formed in a shape corresponding to the semiconductor element. A digging portion into which an element is fitted, and a first opening and a second opening communicating the digging portion and the outside, wherein the semiconductor element and the substrate are provided in the first opening. And a nozzle for filling the filler, and a predetermined amount of the filler is filled into the gap between the semiconductor element and the substrate while discharging air from the second opening by the nozzle. To do Accordingly, those reinforced bonding between the substrate and the semiconductor element.

請求項２においては、前記基板に、前記第二開口部より放出される充填剤の量を検出する手段を設けたものである。   According to a second aspect of the present invention, the substrate is provided with means for detecting the amount of the filler released from the second opening.

請求項３においては、前記充填剤の充填量は、前記第一開口部において、前記半導体素子と、前記基板と、前記ノズルと、を密着させた状態において、前記半導体素子と、前記基板と、前記ノズルと、前記はんだと、により形成される空間の体積と同量としたものである。   According to a third aspect of the present invention, the filling amount of the filler is determined so that the semiconductor element, the substrate, and the nozzle are in close contact with each other in the first opening. The volume of the space formed by the nozzle and the solder is the same.

請求項４においては、半導体素子と基板との隙間に配置したはんだにより前記半導体素子と前記基板とを接合するとともに、前記隙間に充填剤を充填して前記半導体素子と基板との接合を補強した半導体装置における前記充填剤の充填状態を検査する、半導体装置の検査方法であって、前記半導体素子と前記基板とを所定の距離に固定しつつ、前記半導体素子と前記基板との隙間を、一対の第一開口部および第二開口部を除いて密閉した状態で、前記半導体素子と前記基板とを接合したうえで、前記半導体素子と、前記第一開口部と、該第一開口部より充填剤を充填するノズルと、を密着させる密着工程と、前記ノズルによって、前記ノズルと、前記半導体素子と、前記基板と、前記はんだと、により形成される空間に対して、前記充填剤を前記第二開口部より空気を放出しながら所定量充填する充填工程と、前記第二開口部より放出される充填剤の量を検出することによって、充填剤の充填状態を検査する検査工程と、を具備したものである。   According to a fourth aspect of the present invention, the semiconductor element and the substrate are bonded to each other with solder disposed in a gap between the semiconductor element and the substrate, and the gap is filled with a filler to reinforce the bonding between the semiconductor element and the substrate. A semiconductor device inspection method for inspecting a filling state of the filler in a semiconductor device, wherein a gap between the semiconductor element and the substrate is paired while fixing the semiconductor element and the substrate at a predetermined distance. The semiconductor element and the substrate are joined in a sealed state except for the first opening and the second opening, and the semiconductor element, the first opening, and the first opening are filled. An adhesion step for closely adhering a nozzle for filling the agent, and the filler, with respect to a space formed by the nozzle, the semiconductor element, the substrate, and the solder by the nozzle. A filling step of filling a predetermined amount while discharging air from the second opening, and an inspection step of checking the filling state of the filler by detecting the amount of the filler released from the second opening; Is provided.

請求項５においては、前記充填剤の充填量を、前記ノズルと、前記半導体素子と、前記基板と、前記はんだと、の隙間に形成される空間の体積と同量に設定したものである。   According to a fifth aspect of the present invention, the filling amount of the filler is set equal to the volume of the space formed in the gap between the nozzle, the semiconductor element, the substrate, and the solder.

本発明によれば、半導体素子と基板との隙間に充填される充填剤に気泡又は異物の混入を防止し、かつ、前記半導体素子と基板との接合部分を十分に補強することにより信頼性の高い半導体装置を提供することができる。   According to the present invention, it is possible to prevent air bubbles or foreign matter from entering the filler filled in the gap between the semiconductor element and the substrate, and to sufficiently reinforce the bonding portion between the semiconductor element and the substrate, thereby improving reliability. A high semiconductor device can be provided.

以下では、図１〜図４を参照して、本発明に係る半導体装置の実施の一形態である半導体モジュール１について説明する。なお、本実施形態において図１に示す矢印Ａの指す方向を前方向、この方向と逆方向を後方向とし、係る前後方向と水平方向に直交する方向を左右方向とし、係る前後方向と垂直方向に直交する方向を上下方向として規定する。
図１に示すように、半導体モジュール１は、半導体チップ１０、基板２０、アンダーフィル層等を具備し、半導体チップ１０を基板２０に実装してなる部材である。 Below, with reference to FIGS. 1-4, the semiconductor module 1 which is one Embodiment of the semiconductor device which concerns on this invention is demonstrated. In this embodiment, the direction indicated by the arrow A shown in FIG. 1 is the forward direction, the opposite direction to this direction is the rear direction, the direction perpendicular to the front-rear direction and the horizontal direction is the left-right direction, and the direction perpendicular to the front-rear direction A direction orthogonal to the vertical direction is defined as the vertical direction.
As shown in FIG. 1, the semiconductor module 1 includes a semiconductor chip 10, a substrate 20, an underfill layer, and the like, and is a member formed by mounting the semiconductor chip 10 on the substrate 20.

半導体チップ１０は、本発明に係る半導体素子の実施の一形態であり、板状の半導体を樹脂で被覆し、その下面に外部入力／出力用端子となる複数のパッドを配置する。
図２に示すように、本実施形態における半導体チップ１０は、ＢＧＡパッケージによって構成されており、前記各パッドにははんだ等にて構成されるバンプ１１が付設されている。 The semiconductor chip 10 is an embodiment of the semiconductor element according to the present invention, in which a plate-like semiconductor is covered with a resin, and a plurality of pads serving as external input / output terminals are disposed on the lower surface thereof.
As shown in FIG. 2, the semiconductor chip 10 in the present embodiment is configured by a BGA package, and bumps 11 configured by solder or the like are attached to the pads.

基板２０は、本発明に係る基板の実施の一形態であり、ガラスエポキシ樹脂からなる板状の部材である。基板２０の表面には、実装する半導体チップ１０と通電可能な端子（ランド）を備えたプリント回路が形成される。   The board | substrate 20 is one Embodiment of the board | substrate which concerns on this invention, and is a plate-shaped member which consists of glass epoxy resins. On the surface of the substrate 20, a printed circuit including a semiconductor chip 10 to be mounted and a terminal (land) that can be energized is formed.

前記アンダーフィル層は、アンダーフィル剤３１を半導体チップ１０と基板２０との隙間（より厳密には、半導体チップ１０と基板２０との隙間であって、バンプ１１・１１・・・が配置された部分以外の部分に形成される空間）に充填し、アンダーフィル剤３１を硬化させることにより形成され、バンプ１１・１１・・・による半導体チップ１０と基板２０との固定を補強するものである。   In the underfill layer, the underfill agent 31 is a gap between the semiconductor chip 10 and the substrate 20 (more precisely, a gap between the semiconductor chip 10 and the substrate 20, and bumps 11, 11. Is formed by curing the underfill agent 31 to reinforce the fixation between the semiconductor chip 10 and the substrate 20 by the bumps 11, 11...

アンダーフィル剤３１は、本発明に係る充填剤の実施の一形態である。アンダーフィル剤３１は、主成分として、例えば、エポキシ樹脂等の、所定の温度に加熱すると硬化する熱硬化性樹脂を含む。硬化前のアンダーフィル剤３１は、一般的に液体状で流動性を有し、ディスペンサ、ノズル等で吐出することにより所望の位置に充填すること、又は、ハケ、スキージ等を用いて所望の面に塗布することが可能であり、充填または塗布した後に加熱することで硬化させることができる。   The underfill agent 31 is an embodiment of the filler according to the present invention. The underfill agent 31 includes, as a main component, a thermosetting resin that cures when heated to a predetermined temperature, such as an epoxy resin. The underfill agent 31 before curing is generally liquid and fluid, and is filled in a desired position by being discharged by a dispenser, a nozzle or the like, or a desired surface using a brush, squeegee, or the like. It can be applied to the substrate, and can be cured by heating after filling or application.

以下では、図１及び図２を参照して、本実施形態に係る半導体チップ１０について詳細に説明する。
図１及び図２に示すように、半導体チップ１０は、バンプ１１・１１・・・と、突起部１２・１２・１２・１２と、を具備する。本実施形態において、半導体チップ１０は平面視矩形状を有する。 Below, with reference to FIG.1 and FIG.2, the semiconductor chip 10 which concerns on this embodiment is demonstrated in detail.
As shown in FIGS. 1 and 2, the semiconductor chip 10 includes bumps 11, 11... And protrusions 12, 12, 12, and 12. In the present embodiment, the semiconductor chip 10 has a rectangular shape in plan view.

バンプ１１・１１・・・は、本発明に係るはんだの実施の一形態であり、略球状に形成されるはんだである。バンプ１１・１１・・・は、半導体チップ１０と基板２０との隙間に配置される。バンプ１１・１１・・・は、半導体チップ１０の下面に配置される前記複数のパッドにそれぞれ溶着するとともに、基板２０のプリント回路における端子に溶着することにより、半導体チップ１０を基板２０に接合する。
このように、バンプ１１・１１・・・は、それぞれ半導体チップ１０と基板２０とを機械的に接合する機能に加えて、両者間の電気的な導通経路としての機能を有する。そのため、バンプ１１・１１・・・は隣り合うバンプ１１・１１・・・との間で短絡が起きることがないように互いに所定の間隔を置いて配置される。
従って、半導体チップ１０と基板２０との隙間において、バンプ１１・１１・・・が配置された部分以外の部分には空間が形成される。 The bumps 11, 11... Are one embodiment of the solder according to the present invention, and are formed in a substantially spherical shape. The bumps 11, 11... Are arranged in the gap between the semiconductor chip 10 and the substrate 20. The bumps 11, 11... Are welded to the plurality of pads disposed on the lower surface of the semiconductor chip 10, and are welded to terminals in the printed circuit of the substrate 20, thereby joining the semiconductor chip 10 to the substrate 20. .
As described above, each of the bumps 11, 11... Has a function as an electrical conduction path between the semiconductor chip 10 and the substrate 20 in addition to the function of mechanically joining the semiconductor chip 10 and the substrate 20. Therefore, the bumps 11, 11... Are arranged at predetermined intervals so as not to cause a short circuit between the adjacent bumps 11, 11.
Therefore, in the gap between the semiconductor chip 10 and the substrate 20, a space is formed in a portion other than the portion where the bumps 11, 11,.

突起部１２・１２・１２・１２は、本発明に係る突起部の実施の一形態であり、半導体チップ１０の下面四隅から下方に突出する部材である。突起部１２・１２・１２・１２の高さは、バンプ１１・１１・・・より少し低く設定されており、バンプ１１・１１・・・によって半導体チップ１０と基板２０とを接合可能な高さとなっている。
このように構成される突起部１２・１２・１２・１２は、半導体チップ１０と基板２０とをバンプ１１・１１・・・によって接合する際に、基板２０の接合面に当接して半導体チップ１０と基板２０との隙間を所定の距離に保持するものである。
従って、半導体チップ１０と基板２０との隙間において、バンプ１１・１１・・・が配置された部分以外の部分に形成される空間の体積Ｖ１（図４（ａ）に示す部分）は、突起部１２・１２・１２・１２により一定に保持される。
なお、この空間の体積Ｖ１は、実験、および数値シミュレーション等により予め算出することが可能であり、本実施形態では、前記空間の体積Ｖ１は予め算出されているものとする。
なお、本発明に係る突起部は、本実施形態の突起部１２・１２・１２・１２に限定されず、半導体素子と基板との隙間を所定の距離に保持するものを広く含む。 The protrusions 12, 12, 12, 12 are one embodiment of the protrusion according to the present invention, and are members that protrude downward from the four corners of the lower surface of the semiconductor chip 10. The heights of the protrusions 12, 12, 12, 12 are set slightly lower than the bumps 11, 11..., And the height at which the semiconductor chip 10 and the substrate 20 can be joined by the bumps 11, 11. It has become.
The protrusions 12, 12, 12, 12 configured in this way abut against the bonding surface of the substrate 20 when the semiconductor chip 10 and the substrate 20 are bonded by the bumps 11, 11. And the substrate 20 are held at a predetermined distance.
Therefore, in the gap between the semiconductor chip 10 and the substrate 20, the volume V1 (the portion shown in FIG. 4A) formed in the portion other than the portion where the bumps 11, 11,. 12, 12, 12 and 12 are held constant.
The volume V1 of the space can be calculated in advance by experiments, numerical simulations, and the like. In this embodiment, the volume V1 of the space is calculated in advance.
Note that the protrusions according to the present invention are not limited to the protrusions 12, 12, 12, and 12 of the present embodiment, and widely include those that hold the gap between the semiconductor element and the substrate at a predetermined distance.

以下では、図１、図３及び図４を参照して、本実施形態に係る基板２０について詳細に説明する。
図１に示すように、基板２０は、掘り込み部２１、第一開口部２２、第二開口部２３、目盛り２４を具備する。 Below, the board | substrate 20 which concerns on this embodiment is demonstrated in detail with reference to FIG.1, FIG3 and FIG.4.
As shown in FIG. 1, the substrate 20 includes a dug portion 21, a first opening portion 22, a second opening portion 23, and a scale 24.

掘り込み部２１は、本発明に係る掘り込み部の実施の一形態であり、平面視において半導体チップ１０に対応した形状、つまり半導体チップ１０の外郭と同一形状を有し、半導体チップ１０を掘り込み部２１に係合することにより固定する。図１及び図３に示すように、本実施形態では、掘り込み部２１は半導体チップ１０と同じく平面視において矩形状に形成され、その掘り込み深さは、突起部１２・１２・１２・１２を含む半導体チップ１０の高さより低く設定し、半導体チップ１０を基板２０に実装した際に、半導体チップ１０の上面が基板２０の上面より高くなるように設定する。さらに、掘り込み部２１の上面周囲には、半導体チップ１０を掘り込み部２１に誘い込むための誘い込み溝２１ａ（図１及び図３参照）が形成される。
誘い込み溝２１ａは、掘り込み部２１の周縁側から内側へ向かって深さ方向へ傾斜する傾斜面にて構成されている。 The digging portion 21 is an embodiment of the digging portion according to the present invention, has a shape corresponding to the semiconductor chip 10 in plan view, that is, the same shape as the outline of the semiconductor chip 10, and digs the semiconductor chip 10. It is fixed by engaging the recess 21. As shown in FIGS. 1 and 3, in the present embodiment, the digging portion 21 is formed in a rectangular shape in plan view like the semiconductor chip 10, and the digging depth is the protrusions 12, 12, 12, 12. Is set lower than the height of the semiconductor chip 10 including the semiconductor chip 10 so that when the semiconductor chip 10 is mounted on the substrate 20, the upper surface of the semiconductor chip 10 is set higher than the upper surface of the substrate 20. Further, a guiding groove 21 a (see FIGS. 1 and 3) for guiding the semiconductor chip 10 into the digging portion 21 is formed around the upper surface of the digging portion 21.
The guide groove 21 a is configured by an inclined surface that inclines in the depth direction from the peripheral side of the digging portion 21 toward the inside.

第一開口部２２は、本発明に係る第一開口部の実施の一形態であり、掘り込み部２１の前端面に連接され、半導体チップ１０と基板２０との隙間にアンダーフィル剤３１を充填する際の充填口となるものである。
第一開口部２２は上方に向けて開口しており、半導体チップ１０を掘り込み部２１に係合させて半導体チップ１０と基板２０とを接合した際には、半導体チップ１０と基板２０との隙間と外部とが第一開口部２２により連通される。
第一開口部２２の掘り込み深さは、半導体チップ１０を基板２０に実装した状態で、両者の隙間へアンダーフィル剤３１をスムーズに充填できるたけの深さとなるように設定する。
また、第一開口部２２の上方への開口部は、アンダーフィル剤３１を充填するノズル３２の先端部３３の形状に沿う形状を有する。さらに、第一開口部２２の上面周囲には、ノズル３２の先端部３３を第一開口部２２に誘い込むための誘い込み溝２２ａ（図１、図３及び図４参照）が形成される。また、ノズル３２の先端部３３は誘い込み溝２２ａに沿って第一開口部２２に密着可能である（図４参照）。
なお、誘い込み溝２２ａは、第一開口部２２の周縁側から内側へ向かって深さ方向へ傾斜する傾斜面にて構成されている。 The first opening 22 is an embodiment of the first opening according to the present invention, is connected to the front end surface of the digging portion 21, and fills the gap between the semiconductor chip 10 and the substrate 20 with the underfill agent 31. It becomes the filling port when doing.
The first opening 22 opens upward. When the semiconductor chip 10 and the substrate 20 are joined by engaging the semiconductor chip 10 with the digging portion 21, the first opening 22 is formed between the semiconductor chip 10 and the substrate 20. The gap and the outside communicate with each other through the first opening 22.
The digging depth of the first opening 22 is set so that the underfill agent 31 can be smoothly filled in the gap between the semiconductor chip 10 and the semiconductor chip 10 mounted on the substrate 20.
In addition, the opening above the first opening 22 has a shape that follows the shape of the tip 33 of the nozzle 32 that fills the underfill agent 31. Further, a guiding groove 22 a (see FIGS. 1, 3, and 4) for guiding the tip 33 of the nozzle 32 into the first opening 22 is formed around the upper surface of the first opening 22. Moreover, the front-end | tip part 33 of the nozzle 32 can be closely_contact | adhered to the 1st opening part 22 along the guidance groove | channel 22a (refer FIG. 4).
The guide groove 22a is configured by an inclined surface that inclines in the depth direction from the peripheral side of the first opening 22 toward the inside.

第二開口部２３は、本発明に係る第二開口部の実施の一形態であり、掘り込み部２１の後端面に連接されていて、第一開口部２２から半導体チップ１０と基板２０との隙間に充填されるアンダーフィル剤３１により外部へ放出される空気の出口となっている。図１に示すように、本実施形態では、第二開口部２３を第一開口部２２と水平方向に対向する側に設ける。第二開口部２３は、上方に向けて開口し、その掘り込み深さは、半導体チップ１０を基板２０に実装した際に、半導体チップ１０の下面の位置よりも少し低くなるように設定されていて、半導体チップ１０を掘り込み部２１に係合させて半導体チップ１０と基板２０とを接合した際には、半導体チップ１０と基板２０との隙間と外部とが第二開口部２３により連通される。
また、第二開口部２３の開口幅（左右幅）は、第一開口部２２の開口幅に比べて十分に小さいものとする（図３参照）。 The second opening 23 is an embodiment of the second opening according to the present invention, is connected to the rear end surface of the digging portion 21, and connects the semiconductor chip 10 and the substrate 20 from the first opening 22. It is an outlet for air discharged to the outside by the underfill agent 31 filled in the gap. As shown in FIG. 1, in the present embodiment, the second opening 23 is provided on the side facing the first opening 22 in the horizontal direction. The second opening 23 opens upward, and the digging depth is set to be slightly lower than the position of the lower surface of the semiconductor chip 10 when the semiconductor chip 10 is mounted on the substrate 20. When the semiconductor chip 10 is engaged with the digging portion 21 and the semiconductor chip 10 and the substrate 20 are joined, the gap between the semiconductor chip 10 and the substrate 20 and the outside are communicated by the second opening 23. The
The opening width (left-right width) of the second opening 23 is sufficiently smaller than the opening width of the first opening 22 (see FIG. 3).

目盛り２４は、本発明に係る第二開口部より放出される充填剤の量を検出する手段の実施の一形態である。図１及び図３に示すように、本実施形態では、第二開口部２３の一側（右側）及び上面の一側（右側）に所定の間隔を空けて複数の切れ込みを設けることにより目盛り２４を構成する。そして、半導体チップ１０と基板２０との隙間にアンダーフィル剤３１を充填するに際し、目盛り２４と、第二開口部２３より放出されるアンダーフィル剤３１と、をカメラ２５によって撮像し、撮像された画像データを画像処理装置（不図示）によって画像処理することにより、アンダーフィル剤３１の放出量を検出する。
なお、目盛り２４と、第二開口部２３より放出されるアンダーフィル剤３１と、を作業者が目視にて確認することにより、アンダーフィル剤３１の放出量を検出しても良い。 The scale 24 is an embodiment of a means for detecting the amount of filler released from the second opening according to the present invention. As shown in FIGS. 1 and 3, in the present embodiment, a scale 24 is provided by providing a plurality of cuts at predetermined intervals on one side (right side) of the second opening 23 and one side (right side) of the upper surface. Configure. Then, when the underfill agent 31 is filled in the gap between the semiconductor chip 10 and the substrate 20, the scale 24 and the underfill agent 31 released from the second opening 23 are imaged by the camera 25. The amount of release of the underfill agent 31 is detected by subjecting the image data to image processing by an image processing device (not shown).
In addition, you may detect the discharge | release amount of the underfill agent 31 by an operator confirming visually the scale 24 and the underfill agent 31 discharged | emitted from the 2nd opening part 23. FIG.

以下では、図３及び図４を参照して、以上のように構成される基板２０に半導体チップ１０を実装して、ノズル３２によってアンダーフィル剤３１を充填する際の、半導体チップ１０、バンプ１１・１１・・・、突起部１２・１２・１２・１２、基板２０、掘り込み部２１、第一開口部２２、第二開口部２３、ノズル３２、先端部３３の関係について詳細に説明する。   In the following, referring to FIG. 3 and FIG. 4, the semiconductor chip 10 and the bump 11 when the semiconductor chip 10 is mounted on the substrate 20 configured as described above and the underfill agent 31 is filled with the nozzle 32. ..., 11, 12, 12, 12, substrate 20, digging portion 21, first opening portion 22, second opening portion 23, nozzle 32, and tip portion 33 will be described in detail.

図３及び図４（ａ）に示すように、半導体チップ１０を基板２０に実装するに際し、突起部１２・１２・１２・１２によって、半導体チップ１０と基板２０の掘り込み部２１底部との間には一定の距離が保持され、かつ、半導体チップ１０と基板２０との隙間は、アンダーフィル剤３１の充填口となる第一開口部２２と、空気の放出口となる第二開口部２３と、を除いて密閉された状態となる。   As shown in FIGS. 3 and 4A, when the semiconductor chip 10 is mounted on the substrate 20, the protrusions 12, 12, 12, and 12 cause the gap between the semiconductor chip 10 and the bottom of the digging portion 21 of the substrate 20. The gap between the semiconductor chip 10 and the substrate 20 includes a first opening 22 serving as a filling port for the underfill agent 31 and a second opening 23 serving as an air discharge port. Except for, it becomes a sealed state.

図４（ｂ）に示すように、半導体チップ１０と基板２０との隙間にアンダーフィル剤３１を充填するに際し、充填用のノズル３２は上方から下方に向けて移動し、ノズル３２の先端部３３は、誘い込み溝２２ａを介して第一開口部２２と密着した状態となる。言い換えれば、ノズル３２の先端部３３と、半導体チップ１０と、基板２０と、が密着した状態となり、空気の放出口である第二開口部２３を除いて密閉された空間（つまり、第一開口部２２の内部空間と、掘り込み部２１における半導体チップ１０と基板２０との隙間に形成される空間とで構成される空間）が形成される。   As shown in FIG. 4B, when filling the gap between the semiconductor chip 10 and the substrate 20 with the underfill agent 31, the filling nozzle 32 moves downward from above and the tip 33 of the nozzle 32. Is in close contact with the first opening 22 through the guiding groove 22a. In other words, the tip 33 of the nozzle 32, the semiconductor chip 10, and the substrate 20 are in close contact with each other, and the space (that is, the first opening) is sealed except for the second opening 23 that is an air outlet. A space formed by the internal space of the portion 22 and the space formed in the gap between the semiconductor chip 10 and the substrate 20 in the digging portion 21 is formed.

また、図４（ｂ）に示すように、ノズル３２の先端部３３と、半導体チップ１０と、基板２０と、が密着した状態において、先端部３３が下方に移動し停止する位置は第一開口部２２により決定され、半導体チップ１０と基板２０との隙間（より厳密には、半導体チップ１０と基板２０との隙間であって、バンプ１１・１１・・・が配置された部分以外の部分に形成される空間）の体積Ｖ１（図４（ａ）に示す部分）は突起部１２・１２・１２・１２によって一定に保持されているので、先端部３３と、半導体チップ１０と、基板２０（第二開口部２３を除く）と、バンプ１１・１１・・・と、により形成される空間の体積Ｖ２（図４（ｂ）に示す部分）は、常に一定に保持される。
なお、この空間の体積Ｖ２は、実験、および数値シミュレーション等により予め算出することが可能であり、本実施形態では、前記空間の体積Ｖ２は予め算出されているものとする。 As shown in FIG. 4B, the position where the tip 33 moves downward and stops in the state where the tip 33 of the nozzle 32, the semiconductor chip 10, and the substrate 20 are in close contact is the first opening. , Which is determined by the portion 22, and is a gap between the semiconductor chip 10 and the substrate 20 (more precisely, a gap between the semiconductor chip 10 and the substrate 20, other than the portion where the bumps 11, 11. Since the volume V1 (the portion shown in FIG. 4A) of the space to be formed is held constant by the protrusions 12, 12, 12, and 12, the tip portion 33, the semiconductor chip 10, and the substrate 20 ( The volume V2 (portion shown in FIG. 4B) of the space formed by the bumps 11, 11... Except the second opening 23) is always kept constant.
Note that the volume V2 of this space can be calculated in advance by experiments, numerical simulations, and the like. In this embodiment, the volume V2 of the space is calculated in advance.

そして、ノズル３２の先端部３３と、半導体チップ１０と、基板２０と、が密着した状態において、ノズル３２によって、前記空間の体積Ｖ２と同量のアンダーフィル剤３１を充填する。   In the state where the tip portion 33 of the nozzle 32, the semiconductor chip 10, and the substrate 20 are in close contact with each other, the nozzle 32 is filled with the underfill agent 31 in the same amount as the volume V <b> 2 of the space.

従って、ノズル３２によって、前記空間の体積Ｖ２と同量のアンダーフィル剤３１を充填するに際し、先端部３３と、半導体チップ１０と、基板２０（第二開口部２３を除く）と、バンプ１１・１１・・・とで形成する空間の体積Ｖ２は、常に一定に保持されるため、体積Ｖ２を有する前記空間に隙間なくアンダーフィル剤３１が充填された場合には、前記空間の外部にアンダーフィル剤３１が放出されることはない。
これに対し、ノズル３２によって、前記空間の体積V２と同量のアンダーフィル剤３１を充填するに際し、前記空間の内部に気泡又は異物が混入している場合は、第二開口部２３から放出される空気とともに、その混入している気泡又は異物の体積分のアンダーフィル剤３１が放出される。この放出されるアンダーフィル剤３１を検出することにより、半導体チップ１０と基板２０との隙間に充填されるアンダーフィル剤３１の内部の気泡又は異物の混入、並びに、アンダーフィル剤３１の充填不足を検出することができ、アンダーフィル剤３１の充填状態を検査することが可能となる。
上述のような検査を行うことにより、半導体チップ１０と基板２０との隙間にアンダーフィル剤３１の気泡や異物が残ることがなく、かつ、半導体チップ１０と基板２０との接合部分において十分に補強された信頼性の高い半導体モジュール１を得ることができる。
さらに、第二開口部より放出される充填剤の量を検出する手段となる目盛り２４は、第二開口部２３の一側（本実施形態では右側）及び上面一側（同じく右側）に所定の間隔を空けて複数の切れ込みを設けることにより、簡易に構成できる。この目盛り２４をカメラ２５等で撮像し、画像処理を行うことにより、アンダーフィル剤３１の充填放出量を確実に検出することができ、確実にアンダーフィル剤３１の充填状態（気泡又は異物混入の有無、並びに、充填不足）を検査できるので、半導体装置製造コストの低減に寄与できる。 Therefore, when the underfill agent 31 having the same amount as the volume V2 of the space is filled by the nozzle 32, the tip portion 33, the semiconductor chip 10, the substrate 20 (except for the second opening portion 23), the bumps 11. Since the volume V2 of the space formed by 11 and so on is always kept constant, when the space having the volume V2 is filled with the underfill agent 31 without any gap, the underfill is formed outside the space. The agent 31 is not released.
On the other hand, when filling the underfill agent 31 in the same amount as the volume V2 of the space by the nozzle 32, if bubbles or foreign substances are mixed in the space, it is discharged from the second opening 23. The underfill agent 31 corresponding to the volume of bubbles or foreign matters mixed therein is released together with the air. By detecting the released underfill agent 31, bubbles or foreign matters inside the underfill agent 31 filled in the gap between the semiconductor chip 10 and the substrate 20, and insufficient filling of the underfill agent 31 are detected. It can be detected, and the filling state of the underfill agent 31 can be inspected.
By performing the inspection as described above, bubbles or foreign substances of the underfill agent 31 do not remain in the gap between the semiconductor chip 10 and the substrate 20, and sufficient reinforcement is provided at the junction between the semiconductor chip 10 and the substrate 20. Thus, the highly reliable semiconductor module 1 can be obtained.
Further, the scale 24 serving as a means for detecting the amount of the filler discharged from the second opening is predetermined on one side of the second opening 23 (right side in the present embodiment) and one side of the upper surface (also right side). By providing a plurality of notches at intervals, the configuration can be simplified. The graduation 24 is imaged with a camera 25 or the like, and image processing is performed, so that the amount of filling and discharging of the underfill agent 31 can be detected with certainty. Presence / absence and insufficient filling) can be inspected, which can contribute to a reduction in semiconductor device manufacturing cost.

以下では、図５〜図７を参照して、半導体装置の検査方法の実施の一形態について説明する。   Hereinafter, an embodiment of an inspection method for a semiconductor device will be described with reference to FIGS.

図７に示すように、本発明に係る半導体装置の検査方法の実施の一形態は、密着工程１００、充填工程２００、及び検査工程３００等を具備する。   As shown in FIG. 7, an embodiment of the inspection method for a semiconductor device according to the present invention includes an adhesion process 100, a filling process 200, an inspection process 300, and the like.

密着工程１００は、本発明に係る密着工程の実施の一形態であり、半導体チップ１０を基板２０に接合して固定した状態で、ノズル３２を第一開口部２２に密着させて（本実施形態において、厳密にはノズル３２の先端部３３を第一開口部２２に密着させて）、半導体チップ１０と、第一開口部２２と、ノズル３２と、を密着させる工程である。   The adhesion process 100 is an embodiment of the adhesion process according to the present invention, and the nozzle 32 is adhered to the first opening 22 in a state where the semiconductor chip 10 is bonded and fixed to the substrate 20 (this embodiment). (Strictly speaking, the tip 33 of the nozzle 32 is in close contact with the first opening 22), and the semiconductor chip 10, the first opening 22 and the nozzle 32 are in close contact with each other.

密着工程１００において、まず、図５（ａ）及び図５（ｂ）に示すように、半導体チップ１０を下方へ移動させ、誘い込み溝２１ａに沿って基板２０に設けられる掘り込み部２１に係合させ、半導体チップ１０と基板２０とをバンプ１１・１１・・・により接合する。
この半導体チップ１０と基板２０とを接合した状態では、半導体チップ１０と基板２０との隙間は、一対の第一開口部２２および第二開口部２３を除いて密閉した状態となっている。
次に、図５（ｃ）に示すように、ノズル３２を下方へ移動させ、誘い込み溝２２ａに沿って基板２０に設けられる第一開口部２２に密着させる。
このとき、第一開口部２２はノズル３２の密着により閉じられ、ノズル３２と、半導体チップ１０と、基板２０と、の隙間の空間は第二開口部２３を除いて密閉された状態となる。
密着工程１００終了後、充填工程２００に移行する。 In the adhesion process 100, first, as shown in FIGS. 5A and 5B, the semiconductor chip 10 is moved downward and engaged with the digging portion 21 provided in the substrate 20 along the guiding groove 21a. The semiconductor chip 10 and the substrate 20 are joined by the bumps 11, 11.
In a state where the semiconductor chip 10 and the substrate 20 are joined, the gap between the semiconductor chip 10 and the substrate 20 is in a sealed state except for the pair of the first opening 22 and the second opening 23.
Next, as shown in FIG. 5C, the nozzle 32 is moved downward and brought into close contact with the first opening 22 provided in the substrate 20 along the guide groove 22a.
At this time, the first opening 22 is closed by the close contact of the nozzle 32, and the space between the nozzle 32, the semiconductor chip 10, and the substrate 20 is sealed except for the second opening 23.
After the adhesion process 100 ends, the process proceeds to the filling process 200.

充填工程２００は、本発明に係る充填工程の実施の一形態であり、ノズル３２によって、半導体チップ１０と基板２０との隙間（本実施形態において、厳密にはノズル３２の先端部３３と、半導体チップ１０と、基板２０（第二開口部２３を除く）と、バンプ１１・１１・・・と、により形成される空間）に、アンダーフィル剤３１を所定量充填する工程である。   The filling step 200 is an embodiment of the filling step according to the present invention, and the gap between the semiconductor chip 10 and the substrate 20 (in the present embodiment, strictly, the tip 33 of the nozzle 32 and the semiconductor by the nozzle 32). This is a step of filling a predetermined amount of the underfill agent 31 into the chip 10, the substrate 20 (excluding the second opening 23), and the bumps 11, 11,...

充填工程２００において、図５（ｄ）に示すように、ノズル３２によって、ノズル３２の先端部３３と、半導体チップ１０と、基板２０（第二開口部２３を除く）と、バンプ１１・１１・・・と、により形成される空間の体積Ｖ２と同量のアンダーフィル剤３１を充填する。
このとき、半導体チップ１０と基板２０との隙間に存在していた空気は第二開口部２３を通じて外部に放出される。
充填工程２００終了後、検査工程３００に移行する。 In the filling step 200, as shown in FIG. 5 (d), the tip 32 of the nozzle 32, the semiconductor chip 10, the substrate 20 (excluding the second opening 23), and the bumps 11, 11,. The underfill agent 31 is filled in the same amount as the volume V2 of the space formed by
At this time, the air existing in the gap between the semiconductor chip 10 and the substrate 20 is released to the outside through the second opening 23.
After completion of the filling process 200, the process proceeds to the inspection process 300.

検査工程３００は、本発明に係る検査工程の実施の一形態であり、基板２０に設けられる第二開口部２３より放出されるアンダーフィル剤３１を検出することによって、アンダーフィル剤３１の充填状態を検査する工程である。   The inspection process 300 is an embodiment of the inspection process according to the present invention, and the underfill agent 31 is filled by detecting the underfill agent 31 released from the second opening 23 provided in the substrate 20. This is a process for inspecting.

検査工程３００において、図６（ａ）に示すように、第二開口部２３と、目盛り２４と、をカメラ２５等にて検出した際に、第二開口部２３よりアンダーフィル剤３１の放出がない場合（又は、放出量が極少量の場合）は、所定量のアンダーフィル剤３１が半導体チップ１０と基板２０との隙間（本実施形態において、厳密にはノズル３２の先端部３３と、半導体チップ１０と、基板２０（第二開口部２３を除く）と、バンプ１１・１１・・・と、により形成される空間）に行き渡っている良好な充填状態であり、かつ、充填されたアンダーフィル剤３１の内部に気泡及び異物の混入がない状態であると判定される。
一方、図６（ｂ）に示すように、第二開口部２３と、目盛り２４と、をカメラ２５等にて検出した際に、第二開口部２３よりアンダーフィル剤３１の放出がある場合は、所定量のアンダーフィル剤３１が半導体チップ１０と基板２０との隙間（本実施形態において、厳密にはノズル３２の先端部３３と、半導体チップ１０と、基板２０（第二開口部２３を除く）と、バンプ１１・１１・・・と、により形成される空間）に行き渡っていない充填不足である、又は充填されたアンダーフィル剤３１の内部に気泡（又は異物）の混入があると判定される。
検査工程３００終了後、適宜アンダーフィル剤３１の硬化工程等に移行する。 In the inspection process 300, as shown in FIG. 6A, when the second opening 23 and the scale 24 are detected by the camera 25 or the like, the underfill agent 31 is released from the second opening 23. When there is no (or when the discharge amount is extremely small), a predetermined amount of underfill agent 31 is a gap between the semiconductor chip 10 and the substrate 20 (in this embodiment, strictly, the tip 33 of the nozzle 32 and the semiconductor). Underfill that is in a good filling state and spreads across the chip 10, the substrate 20 (excluding the second opening 23), and the bumps 11, 11... It is determined that there are no bubbles and foreign matter inside the agent 31.
On the other hand, as shown in FIG. 6B, when the second opening 23 and the scale 24 are detected by the camera 25 or the like, the underfill agent 31 is released from the second opening 23. The predetermined amount of underfill agent 31 is a gap between the semiconductor chip 10 and the substrate 20 (in this embodiment, strictly speaking, the tip 33 of the nozzle 32, the semiconductor chip 10, and the substrate 20 (excluding the second opening 23). ) And the bumps 11, 11, and so on) are not sufficiently filled, or it is determined that bubbles (or foreign matter) are mixed in the filled underfill agent 31. The
After the inspection process 300 is completed, the process proceeds to a curing process for the underfill agent 31 as appropriate.

半導体素子が基板に実装される前の本発明に係る半導体装置の実施の一形態を示す斜視図。The perspective view which shows one Embodiment of the semiconductor device which concerns on this invention before a semiconductor element is mounted in a board | substrate. 本発明に係る半導体素子の実施の一形態を示す斜視図。The perspective view which shows one Embodiment of the semiconductor element which concerns on this invention. 半導体素子が基板に実装された後の本発明に係る半導体装置の実施の一形態を示す斜視図。The perspective view which shows one Embodiment of the semiconductor device which concerns on this invention after the semiconductor element was mounted in the board | substrate. 本発明に係る半導体装置の実施の一形態を示す側面断面図。（ａ）は半導体素子が基板に固定された状態を示す側面断面図。（ｂ）はノズルが第一開口部に密着した状態を示す側面断面図。1 is a side sectional view showing an embodiment of a semiconductor device according to the present invention. (A) is side surface sectional drawing which shows the state by which the semiconductor element was fixed to the board | substrate. (B) is side surface sectional drawing which shows the state which the nozzle contact | adhered to the 1st opening part. 本発明に係る密着工程及び充填工程の実施の一形態を示す側面断面図。（ａ）は半導体素子を基板に固定する工程を示す側面断面図。（ｂ）は半導体素子を基板に固定する工程を示す側面断面図。（ｃ）はノズルを第一開口部に密着させる工程を示す側面断面図。（ｄ）はノズルによって充填剤を充填する工程を示す側面断面図。Side surface sectional drawing which shows one Embodiment of the contact | adherence process and filling process which concern on this invention. (A) is side surface sectional drawing which shows the process of fixing a semiconductor element to a board | substrate. (B) is side surface sectional drawing which shows the process of fixing a semiconductor element to a board | substrate. (C) is side surface sectional drawing which shows the process of closely_contact | adhering a nozzle to a 1st opening part. (D) is side surface sectional drawing which shows the process of filling a filler with a nozzle. 本発明に係る検査工程の実施の一形態を示す側面断面図。（ａ）は良好な充填状態を示す側面断面図。（ｂ）は第二開口部より充填剤の放出がある状態を示す側面断面図。Side surface sectional drawing which shows one Embodiment of the test process which concerns on this invention. (A) is side surface sectional drawing which shows a favorable filling state. (B) is side surface sectional drawing which shows the state with discharge | release of a filler from a 2nd opening part. 本発明に係る半導体装置の検査方法の実施の一形態を示すフロー図。The flowchart which shows one Embodiment of the test | inspection method of the semiconductor device which concerns on this invention.

符号の説明Explanation of symbols

１ 半導体モジュール（半導体装置）
１０ 半導体チップ（半導体素子）
１１ バンプ（はんだ）
１２ 突起部
２０ 基板
２１ 掘り込み部
２２ 第一開口部
２３ 第二開口部
３１ アンダーフィル剤（充填剤）
３２ ノズル 1 Semiconductor module (semiconductor device)
10 Semiconductor chip (semiconductor element)
11 Bump (Solder)
12 Protrusion 20 Substrate 21 Excavation 22 First Opening 23 Second Opening 31 Underfill Agent (Filler)
32 nozzles

Claims (5)

半導体素子と基板との隙間に配置したはんだにより前記半導体素子と前記基板とを接合するとともに、前記隙間に充填剤を充填して前記半導体素子と基板との接合を補強する半導体装置であって、
前記半導体素子は、該半導体素子と前記基板との隙間を所定の距離に保持する突起部を具備し、
前記基板は、前記半導体素子に対応した形状に形成され、該半導体素子が嵌合される掘り込み部と、前記掘り込み部と外部とを連通する第一開口部および第二開口部と、を具備し、
前記第一開口部において、前記半導体素子と、前記基板と、前記充填剤を充填するノズルと、を密着させた状態で、前記半導体素子と前記基板との隙間に、前記ノズルによって前記充填剤を前記第二開口部から空気を放出しながら所定量充填することにより、前記半導体素子と前記基板との接合を補強する、半導体装置。 A semiconductor device that joins the semiconductor element and the substrate with solder disposed in a gap between the semiconductor element and the substrate, and reinforces the bonding between the semiconductor element and the substrate by filling the gap with a filler,
The semiconductor element comprises a protrusion that holds a gap between the semiconductor element and the substrate at a predetermined distance,
The substrate is formed in a shape corresponding to the semiconductor element, and includes a digging portion into which the semiconductor element is fitted, and a first opening and a second opening that communicate the digging portion with the outside. Equipped,
In the first opening, in a state where the semiconductor element, the substrate, and a nozzle filling the filler are in close contact with each other, the filler is inserted into the gap between the semiconductor element and the substrate by the nozzle. A semiconductor device that reinforces the bonding between the semiconductor element and the substrate by filling a predetermined amount while discharging air from the second opening. 前記基板に、前記第二開口部より放出される充填剤の量を検出する手段を設ける、ことを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the substrate is provided with means for detecting an amount of the filler released from the second opening. 3. 前記充填剤の充填量は、前記第一開口部において、前記半導体素子と、前記基板と、前記ノズルと、を密着させた状態において、前記半導体素子と、前記基板と、前記ノズルと、前記はんだと、により形成される空間の体積と同量である、ことを特徴とする請求項２に記載の半導体装置。   The filling amount of the filler is such that, in the first opening, the semiconductor element, the substrate, and the nozzle are in close contact with each other, the semiconductor element, the substrate, the nozzle, and the solder. The semiconductor device according to claim 2, wherein the volume is the same as the volume of the space formed by. 半導体素子と基板との隙間に配置したはんだにより前記半導体素子と前記基板とを接合するとともに、前記隙間に充填剤を充填して前記半導体素子と基板との接合を補強した半導体装置における前記充填剤の充填状態を検査する、半導体装置の検査方法であって、
前記半導体素子と前記基板とを所定の距離に固定しつつ、前記半導体素子と前記基板との隙間を、一対の第一開口部および第二開口部を除いて密閉した状態で、前記半導体素子と前記基板とを接合したうえで、前記半導体素子と、前記第一開口部と、該第一開口部より充填剤を充填するノズルと、を密着させる密着工程と、
前記ノズルによって、前記ノズルと、前記半導体素子と、前記基板と、前記はんだと、により形成される空間に対して、前記充填剤を前記第二開口部より空気を放出しながら所定量充填する充填工程と、
前記第二開口部より放出される充填剤の量を検出することによって、充填剤の充填状態を検査する検査工程と、
を具備する半導体装置の検査方法。 The filler in a semiconductor device in which the semiconductor element and the substrate are joined by solder arranged in a gap between the semiconductor element and the substrate, and the gap is filled with a filler to reinforce the junction between the semiconductor element and the substrate. An inspection method of a semiconductor device for inspecting a filling state of
While fixing the semiconductor element and the substrate at a predetermined distance, the gap between the semiconductor element and the substrate is sealed except for a pair of the first opening and the second opening. An adhesion step of bringing the semiconductor element, the first opening, and a nozzle filled with a filler from the first opening into close contact with each other after bonding the substrate;
Filling the space formed by the nozzle, the semiconductor element, the substrate, and the solder with the nozzle by filling the filler with a predetermined amount while discharging air from the second opening. Process,
An inspection process for inspecting the filling state of the filler by detecting the amount of the filler released from the second opening;
A method for inspecting a semiconductor device comprising: 前記充填剤の充填量を、
前記ノズルと、前記半導体素子と、前記基板と、前記はんだと、の隙間に形成される空間の体積と同量に設定する、ことを特徴とする請求項４に記載の半導体装置の検査方法。 The filling amount of the filler is
5. The method for inspecting a semiconductor device according to claim 4, wherein the volume is set to be equal to a volume of a space formed in a gap between the nozzle, the semiconductor element, the substrate, and the solder.
JP2007317498A 2007-12-07 2007-12-07 Semiconductor device and method for inspecting the same Pending JP2009141213A (en)

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US9368414B2 (en) 2014-03-20 2016-06-14 Samsung Electronics Co., Ltd. Semiconductor inspecting apparatus and method of inspecting and manufacturing semiconductor device using the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014241366A (en) * 2013-06-12 2014-12-25 富士通株式会社 Heat transfer structure plate, heat transfer structure plate module, and undersea device
JP2015018971A (en) * 2013-07-11 2015-01-29 富士通株式会社 Heat radiation plate, and submarine apparatus
US9368414B2 (en) 2014-03-20 2016-06-14 Samsung Electronics Co., Ltd. Semiconductor inspecting apparatus and method of inspecting and manufacturing semiconductor device using the same

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