JP2009129402A - Semiconductor device for ic card, ic card and terminal for ic card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily increase usable memory areas by suppressing cost increase and to easily cope also with security processing with respect to data in the memory areas. <P>SOLUTION: This semiconductor device (100) for an IC card has a memory card interface control circuit (160) which performs input/output control with an external memory card in addition to an input/output interface control circuit (120) which performs input/output control with the outside, and the semiconductor device (100) has a host function of a memory card. A central processor (150) responds to a security processing request supplied to the input/output interface control circuit. The central processor can also give an instruction of memory card access to the memory card interface control circuit. A transfer control circuit (140) responds to a memory card access processing request supplied to the input/output interface control circuit, and gives an instruction of the memory card access to the memory card interface control circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an IC card semiconductor device that responds to security processing and memory card access processing, an IC card on which the semiconductor device is mounted, and an IC card terminal device connected to the IC card.

  IC cards are widely used in transportation systems and authentication devices as devices that replace conventional magnetic cards. An IC card generally has a configuration in which a small microcomputer incorporating a mechanism that resists current difference analysis and physical tampering, and a contact or non-contact interface is incorporated in a card having a shape such as ID-0 or ID-1. Prepare. Since this IC card can take a method in which information in the card cannot be accessed without performing electrical authentication, it has a characteristic that it is resistant to reading defects due to unauthorized tampering and wear, which has been a problem with conventional magnetic cards. is there. In addition, the property of being electrically readable and writable facilitates downsizing, which is very difficult with a magnetic card, and is excellent as an authentication device in a small terminal such as a mobile phone.

  Currently, an IC card or an IC card chip (semiconductor device for IC card) is used as an authentication device for various devices, and demands for functions and performance of the IC card or IC card chip are increasing year by year. In particular, with the diversification and enlargement of applications stored in the IC card chip, the storage capacity required for the IC card chip is also increasing, and this tends to increase in the future. Furthermore, an increase in the amount of data in the IC card chip also leads to an increase in the amount of data processed in the IC card chip and an increase in the amount of data exchanged with the terminal device, thereby improving the capability of the IC card with the existing mechanism. Is getting harder.

  In such a flow, a standard for an IC card having a high-speed communication interface as described in ISO / IEC 7816-12 has been established, and a certain solution to the problem relating to the speed of the interface portion. Has been made. However, to increase the data capacity in the IC card chip, incorporating a large-capacity flash memory in the IC card is a solution, but the cost of the flash memory is larger than the cost of the IC card chip. For this reason, it is a great burden for IC card manufacturers.

  As one of solutions to such a problem, a configuration in which an IC card and a memory card are mixedly mounted on a single card with independent interfaces as shown in Patent Document 1 can be considered. In this case, since the IC card part and the flash memory part can be manufactured independently, there is an effect that the conventional product can be used as it is for each interface, but the price as a product increases as a single product or as a total. There is a problem to say. Further, since the circuit is independent, it is difficult to use for the purpose of storing a part of the security data of the IC card.

JP-A-2005-322109

  As described above, for increasing the storage capacity of the IC card, means for incorporating a large-capacity memory on the terminal device using the IC card or connecting the memory card device can be considered. Therefore, it is not suitable for solving the problem relating to the storage capacity of the IC card.

  An object of the present invention is for an IC card that can easily increase the available non-volatile memory area while suppressing an increase in cost and can easily cope with security processing for data in the non-volatile memory area. It is to provide a semiconductor device.

  Another object of the present invention is an IC card that can easily increase the available non-volatile memory area while suppressing an increase in cost and can easily cope with security processing for data in the non-volatile memory area. An object of the present invention is to provide an IC card terminal device suitable for the IC cards in a line.

  Still another object of the present invention is to provide a terminal device for an IC card that can independently access a memory card that can be accessed by an IC card having a memory card host function.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the IC card semiconductor device has a memory card interface control circuit that performs input / output control with an external memory card in addition to an input / output interface control circuit that performs input / output control with the outside, Has card host function. The central processing unit responds to the security processing request supplied to the input / output interface control circuit. The central processing unit can give a memory card access instruction to the memory card interface control circuit. The transfer control circuit responds to the memory card access processing request supplied to the input / output interface control circuit and gives a memory card access instruction to the memory card interface control circuit.

  According to the above means, in order to increase the non-volatile memory area used by the IC card semiconductor device, a memory card connected to the memory card interface control circuit may be added outside the semiconductor device. Since the transfer control circuit responds to the memory card access processing request, the burden on the central processing unit is reduced. The central processing unit can also use an external memory card for storing data subjected to security processing.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, by adding an external memory card, the data in the external memory card can be handled directly from the IC card semiconductor device, and the available nonvolatile memory area can be suppressed from increasing in cost. And can easily cope with security processing for the data in the nonvolatile memory area.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings that are referred to with parentheses in the outline description of the representative embodiment merely exemplify what is included in the concept of the component to which the reference numeral is attached.

  [1] The IC card semiconductor device (105) includes an input / output interface control circuit (120) for performing input / output control with the outside in accordance with a predetermined input / output interface specification, and a memory card interface control circuit (160). ), A central processing unit (150), and a transfer control circuit (140). The memory card interface control circuit performs input / output control with an external memory card in accordance with a predetermined memory card interface specification. The central processing unit performs data processing in response to a security processing request supplied to the input / output interface control circuit, and gives a memory card access instruction to the memory card interface control circuit. The transfer control circuit gives a memory card access instruction to the memory card interface control circuit in response to a memory card access processing request supplied to the input / output interface control circuit.

  According to the above means, the IC card semiconductor device has a memory card host function. Therefore, in order to increase the nonvolatile memory area to be used, a memory card is added to the outside of the semiconductor device and added to the memory card interface control circuit. Just connect. Since the transfer control circuit responds to the memory card access processing request, the burden on the central processing unit is reduced. The central processing unit can also use an external memory card for storing data subjected to security processing. Therefore, the available non-volatile memory area can be increased while suppressing an increase in cost, and security processing for data in the non-volatile memory area can be easily handled.

  [2] The IC card semiconductor device according to [1] further includes a buffer (145) between the transfer control circuit and the memory card interface control circuit. The transfer control circuit controls transfer of write data to the memory card to the buffer, and the memory card interface control circuit controls transfer of read data from the memory card to the buffer. Since the buffer memory becomes a shared buffer by the transfer control circuit and the memory card interface control circuit, it can contribute to easy data transfer control of write data and read data to the memory card.

  [3] The IC card semiconductor device of item 2 further includes an internal bus (130) for connecting the input / output interface control circuit and the central processing unit, and the input / output interface control circuit via the transfer control circuit. Internal buses (133A, 133B) leading to the data buffer are separately provided. It becomes easy to avoid data transfer bus contention between the memory card access process and the security process, which can contribute to the efficiency of the data process.

  [4] In the semiconductor device for an IC card according to item 1, the memory card interface control circuit has an instruction queue (165) in which an access command instructing an access operation of the memory card is stored. The central processing unit and the transfer control circuit can write an access command to the instruction queue. The memory card interface control circuit performs interface control for an external memory card in accordance with an access command written in the instruction queue.

  [5] In the IC card semiconductor device of item 4, when the memory card access processing request supplied to the input / output interface control circuit is a write, the transfer control circuit sets the transfer path from the transfer control circuit to the buffer. A bus right is acquired and write data is transferred to an empty area of the buffer. Then, a write access command is transferred to the instruction queue of the memory card interface control circuit, and the memory card interface control circuit starts control to write the write data in the buffer to the memory card. Since the write access command is set to the instruction queue after the write data is transferred to the buffer, the previously set write access command or read access command is executed even if there is no free space in the buffer. If there is no free space in the buffer, it is sufficient to wait until it is free.

  [6] In the semiconductor device for an IC card according to item 4, when the memory card access processing request supplied to the input / output interface control circuit is a read, the transfer control circuit reads the read request to the instruction queue of the memory card interface control circuit. The access command is transferred, and the memory card interface control circuit reads data from the memory card and stores it in an empty area of the buffer. Then, the bus right of the transfer path from the buffer to the transfer control circuit is acquired, and the read data of the buffer is supplied to the input / output interface control circuit.

  [7] In the IC card semiconductor device according to [6], when the memory card interface control circuit responds to the read access command and there is no free space in the buffer, the write access command stored in the instruction queue First, write in to secure a free area in the buffer. Since the read access command to the instruction queue is set before the read data is transferred to the buffer, if there is no free space in the buffer, there is no free space in the buffer. By executing the write access command first, it is possible to forcibly reserve an empty area in the buffer.

  [8] In the IC card semiconductor device according to item 4, when the memory card access processing request supplied to the input / output interface control circuit is erased, the transfer control circuit erases it in the instruction queue of the memory card interface control circuit. The access command is transferred to cause the memory card interface control circuit to start an erasing operation on the memory card.

  [9] An IC card (100) to which the IC card semiconductor device according to [1] is applied is connected to a card substrate with the IC card semiconductor device (105) and an input / output interface control circuit of the IC card semiconductor device. And a second interface terminal (702, 703, 706, 707) connected to the memory card interface control circuit of the IC card semiconductor device. For example, when the first interface terminal and the second interface terminal are interfaced to the IC card terminal device, an additional memory card attached to the IC card terminal device is connected to the second interface terminal inside the IC card terminal device. Just do it. If the second interface terminal can directly attach and detach the memory card, the memory card can be directly attached to the IC card for expansion. When the memory card is a semiconductor device formed of a single semiconductor chip, the device can be incorporated in advance in the IC card.

  [10] One IC card terminal device (180) in which the IC card of item 9 is used is connected to the first interface terminal exposed to the outside of the IC card among the first interface terminals of the IC card. A first terminal interface terminal (182), and a second terminal interface terminal (181A) connected to the second interface terminal exposed to the outside of the IC card among the second interface terminals in the IC card of Item 9. Have. Furthermore, it has a third terminal interface terminal (181B) to which the memory card is connected, and a bypass path (183) for connecting the second terminal interface terminal to the third terminal interface terminal. Thereby, an IC card terminal device suitable for the IC card can be realized.

  [11] An IC card semiconductor device (105) according to another aspect includes an input / output interface control circuit (120) for performing input / output control with the outside in accordance with a predetermined input / output interface specification, and a memory card interface. A control circuit (160), a first data processing device (150), and a second data processing circuit (140) are included. The memory card interface control circuit performs input / output control with an external memory card in accordance with a predetermined memory card interface specification. The first data processing device performs data processing in response to a security processing request supplied to the input / output interface control circuit. The second data processing circuit gives a memory card access instruction to the memory card interface control circuit in response to the memory card access processing request supplied to the input / output interface control circuit. At this time, the memory card interface control circuit has a first voltage detection circuit (210) having an input terminal connected to a power supply terminal for supplying operating power to the memory card. When the voltage is not supplied from the memory card, an access operation to the memory card is started.

  According to the above means, since the IC card semiconductor device has a memory card host function, in order to increase the nonvolatile memory area to be used, a memory card is added to the outside of the semiconductor device and added to the memory card interface control circuit. Just connect. Since the transfer control circuit responds to the memory card access processing request, the burden on the central processing unit is reduced. Further, by having the first voltage detection circuit, the IC card semiconductor device itself can avoid that the access from the IC card having the memory card host function competes with the access from the terminal device.

  [12] In the IC card semiconductor device of item 11, the first data processing device can give a memory card access instruction to the memory card interface control circuit. As a result, the first data processing apparatus can also use an external memory card for storing data subjected to security processing.

  [13] An IC card (100) to which the IC card semiconductor device according to Item 11 is applied is connected to a card substrate with the IC card semiconductor device and an input / output interface control circuit of the IC card semiconductor device. An interface terminal; and a second interface terminal connected to the memory card interface control circuit of the IC card semiconductor device. For example, when the first interface terminal and the second interface terminal are interfaced to the IC card terminal device, an additional memory card attached to the IC card terminal device is connected to the second interface terminal inside the IC card terminal device. Just do it.

  [14] One IC card terminal device (180A) in which the IC card of item 13 is used is connected to a first interface terminal exposed to the outside of the IC card among the first interface terminals of the IC card. A first terminal interface terminal (182); and a second terminal interface terminal (181A) connected to a second interface terminal exposed to the outside of the IC card among the second interface terminals in the IC card. Furthermore, the input terminal is connected to the power terminal of the third terminal interface terminal (181B) to which the memory card is connected and the second terminal interface terminal for supplying operating power from the IC card to the memory card. A second voltage detection circuit (220), and starts an access operation to the memory card via the third terminal interface terminal when no voltage is supplied from the outside by the second voltage detection circuit. As a result, the IC card terminal device has the second voltage detection circuit, so that the IC card terminal device itself can avoid conflict with access to the memory card by the IC card having the memory card host function.

2. Details of Embodiments Embodiments will be further described in detail. Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. Note that members having the same function are denoted by the same reference symbols throughout the drawings for describing the best mode for carrying out the invention, and the repetitive description thereof will be omitted.

  FIG. 1 shows an example of an IC card (ICCRD) 100 according to the present invention. The IC card 100 can be interfaced with a terminal device (TRML) 180 and a memory card 190 connected to the terminal device 180 can be accessed via the terminal device 180. The IC card 100 is configured by mounting an IC card chip (ICCRDCHP) 105 on a card substrate having an external interface terminal. The IC card chip 105 is formed on a semiconductor substrate such as single crystal silicon for the complementary MOS integrated circuit manufacturing technique, for example, and constitutes a microcomputer or a data processor. The external interface terminal is a contact terminal or an antenna terminal for a non-contact interface.

  The IC card chip 105 has a terminal interface control circuit (TRMIFCNT) 120, which is an input / output interface control circuit interfaced to the terminal device 180 via an external interface terminal, and interface control similar to that of a card host with respect to the memory card 190. A memory card control circuit (MCRDCNT) 160 for performing The terminal interface control circuit 120 can interface with the external interface terminal 182 of the terminal device (TRML) 180 via the input / output interface 127. The memory card control circuit 160 is coupled to the interface terminal 181A of the terminal device 180 via the memory card interface 167A. The memory card 190 is coupled to the interface terminal 181B of the terminal device 180 via the memory card interface 167B. The interface terminals 181A and 181B can be connected to each other by a bus 183 whose corresponding terminal forms a bypass path or a through path in the terminal device 180.

  In order to perform overall control of the IC card chip 105, a central processing unit (CPU) 150 and a buffer memory (MEM) 155 are provided, which are connected to the terminal interface control circuit 120 and the memory card via the internal bus 130. Connected to the control circuit 160. The central processing unit 150 has a configuration as a processor core, for example. The central processing unit 150 performs security processing such as encryption / decryption and authentication, and uses a memory card as an auxiliary storage device for various data processing as necessary. In addition, the memory card 190 can be used as a storage for the terminal device 180 to store a large amount of stream data such as image data. When the memory card 190 is controlled to be usable in response to a request from the terminal device 180, a transfer control circuit (TRCNT) 140, a selector 132, and a buffer (BUFF) 145 are provided to reduce the load on the CPU 150. The terminal interface control circuit 120 and the transfer control circuit 140 are connected by a bus 133A, the transfer control circuit 140 and the bus 130 are selectively connected to the bus 141 via the selector 141, and the buffer 141 is connected to the bus 141.

  The input / output interface 270 of the terminal interface control circuit 120 and the terminal device 180 may be an appropriate interface such as a USB (universal serial bus) interface. For example, the terminal interface control circuit 120 accepts an access (simply MSC access) request via the USB mass storage class driver software of the terminal device and accepts an IC card command for security processing. When an instruction and data for data storage processing accompanied by an MSC access request and data (also simply referred to as an MSC data stream) are input, the terminal interface control circuit 120 stores this in the MSC buffer (MSCBUF) 120A, and an IC command is stored. When an instruction and data (hereinafter also simply referred to as an ICC data stream) for accompanying security processing are supplied, they are stored in an ICC buffer (ICCBUF) 120B. When the MSC access request is a read request, the terminal interface control circuit 120 waits for the read data that responds to the internal transfer to the MSC buffer 120A and outputs it to the terminal device 180, and the security process issues the read request. At the same time, the read data responding thereto is output to the terminal device 180 after waiting for the internal transfer to the ICC buffer 120B.

  When the MSC data stream is stored in the MSCBUF 120A, the terminal interface control circuit 120 issues a transfer request to the TRCNT 140. The TRCNT 140 performs use right acquisition of the bus 141, read / write control of the BUFF 145, and operation control for the MCRDCNT 160 in response to a request for writing, reading, or erasing the MSC access request to the MCRD 190. In the case of writing, the TRCNT 140 acquires the right to use the bus 141, switches the bus switch 132 to the TRCNT 140 side, transfers the write data to the empty area of the BUFF 145, and writes the write command (write command) to the instruction queue (IQUE) 165 of the MCRDCNT 160. ) And the control register (CREG) 163 is operated. Operations on the instruction queue 165 and the control register 163 are performed via the bus 134. As a result, the MCRDCNT 160 performs write control of the memory card 190 for writing the write data stored in the BUFF 145 to the MCRD 190. In the case of reading, the TRCNT 140 transfers a read command (read command) to the instruction queue (IQUE) 165 of the MCRDCNT 160 via the bus 134 and operates the control register (CREG) 163. Then, after waiting for a read data transfer request from MCRDCNT 160, the right to use bus 141 is acquired, bus switch 132 is switched to TRCNT 140, and read data transferred to the free area of BUFF 145 by MCRDCNT 160 is transferred to MSCBUF 120A. Do. In the case of erasure, the TRCNT 140 transfers an erase command (erase instruction) to the instruction queue (IQUE) 165 of the MCRDCNT 160 via the bus 134, operates the control register (CREG) 163, and sends an address area according to the erase command to the MCRDCNT 160. Are deleted from the MCRD 190. When the TRCNT 140 is not processing the MSC data stream received from the terminal device, the TRCNT 140 notifies the CPU 150 of the status.

  When the terminal interface control circuit 120 stores the ICC data stream in the ICCCBUF 120B, the terminal interface control circuit 120 requests the CPU 150 for an interrupt. In response to the interrupt request, the CPU 150 reads the ICC BUF 120B ICC data stream and executes security processing possessed by the IC card command. When access to the MCRD 190 is required for the security processing, the access command is issued to the MCDCNT 163 on condition that the TRCNT 140 is not processing the MSC data stream. When a read request accompanies the security processing by the IC card conand, the CPU 150 internally transfers read data in response to the ICC buffer 120B.

  The system of FIG. 1 will be described in further detail. The terminal 180 is a device such as a mobile phone, a PC, an automatic teller machine, an IC card reader / writer, and a network terminal. However, if the device has an input / output interface (IF) and a processing unit, It is not limited to this example. Examples of such IF include USB (registered trademark), MMC (registered trademark) IF, Bluetooth (registered trademark), WiMAX (registered trademark), Ethernet (registered trademark), ATA IF, and non-contact IF based on ISO 14443. Is applicable. The IC card 100 is an IC card having an ID-1 or ID-0 shape defined by ISO 7810, but may be a USB token or a memory card, and security processing such as authentication processing can be safely performed. This is not the case if it is a simple device. The memory card 190 is not limited to a memory card such as an SD (abbreviation of Secure Digital) card, an MMC (abbreviation of MultiMediaCard), a memory stick (registered trademark), and a compact flash (registered trademark). Such a device may be a NAND flash (registered trademark) with a controller or the like, and is not limited to this as long as it is a device for data storage. In these cases, the memory card control circuit 160 is a control circuit suitable for the corresponding device. However, since the present invention does not depend on the type of the data storage device to be connected, the case where the memory card control circuit 160 is realized by the MMC is representative here. Is described. The input / output interface 127 and the terminal interface control circuit 167 may be assigned to terminals of an IC card defined by ISO7816, or may be connected using other terminals. For example, when the standard of the IC card terminals C1 to C8 is adopted as the input / output interface 127, USB communication is performed using C1: VCC, C4: (D +), C5: GND, C8: (D-). , C1: VCC, C2: CMD, C3: CLK, C5: GND, C6: VCC2, C7: DATA may be used to perform MMC communication. Here, C6 is used as a terminal for power supplied from the IC card 100 to the memory card 190. The IC card 100 with this configuration is different from the configuration of Japanese Patent Laid-Open No. 2005-322109 in that the memory card 190 is driven by the IC card chip 105, and as a result, the clock, command, data, and power are supplied to the memory card. Therefore, the signal input / output is reversed. In short, they are supplied from the IC card chip 105 to the memory card 190. Similar to Japanese Patent Laid-Open No. 2005-322109, the function may be realized using a terminal different from the IC card standard terminal. Here, if the memory card 190 is a device of a parallel transfer system such as a compact flash and there are too many numbers to be assigned as the interface of the IC card 100, a terminal different from the IC card is mounted and accessed using this terminal. It is good as well. The assignment of the IC card 100 to the interface is for mounting with an emphasis on compatibility when applied to the IC card, and is not limited to this as long as it can be operated by providing another terminal. The assignment to the terminals is not limited to this.

  Instructions and data included in the ICC data stream sent via the input / output interface 127 are sent to the CPU 150 and the memory 155 via the internal bus 130 for processing. Here, in addition to the arithmetic processing unit, the CPU 150 is an accelerator for processing a specific operation such as remainder division at high speed, a memory for storing a program or data such as a mask ROM or EEPROM, a work memory such as an SRAM. Refers to things that contain etc. If the CPU 150 wants to store a large amount of data, the data can be stored in the memory card 190 via the memory card control circuit 160. At this time, the data stored in the memory card 190 may be only a part of the entire data to be stored, or the remaining data may be stored in the EEPROM of the CPU 150. When data is stored, it may be encrypted by the CPU 150 or the memory card control circuit 160 and stored. At that time, the hash value of the data to be stored may be stored in the EEPROM of the CPU 150, and tampering may be detected by comparing with the hash value at the time of reading. In addition to the data to be originally written, data for concealing the data to be written may be written, and the data storage locations may be distributed by using an address conversion table or an address conversion formula. For example, when data is encrypted and stored, the encrypted data is converted into data having random properties that are difficult to correlate with the original data. Therefore, writing random numbers at an arbitrary timing has the effect of making it difficult for an attacker to determine which data is correct.

  The memory card 190 may be supplied with power and a transfer clock from the memory card control circuit 160, and may transfer commands and data based on the transfer clock. However, when data transfer is connected by asynchronous memory card interfaces 167A and 167B, there is no need for a transfer clock. In FIG. 1, since the memory card interfaces 167A and 167B are once connected to the memory card 190 via the terminal device 180, the power supply for the memory card 190 can be supplied from the terminal. In this case, since power to the memory card 190 is controlled on the terminal device 180 side, when data is to be transferred, data transfer from the memory card control circuit 160 to the terminal device 180 is started using some means. Or the memory card 190 must always be turned on. As a means for notifying the terminal device 180 of the start of data communication, a method using a clock signal line from the memory card control circuit 160 or a case where data transfer is not necessary using a signal line for command or data transfer A mechanism for pulling down and notifying the start of data transfer by pulling up when data transfer is necessary may be used. In addition to the purpose of storing data from the IC card 100, the memory card 190 may be used for the purpose of storing data of the terminal device 180 in some cases. At this time, it is also possible to perform control by using the power supply line or the clock signal line of the input / output interface 167.

  FIG. 2 illustrates another terminal device 180A. The terminal device 180A is different from the terminal device 180 of FIG. 1 in that the terminal device 180A has a direct access function to the memory card 190 and has an access conflict avoidance configuration. That is, a signal level detection circuit (SIGDTC) 210 is arranged in the memory card control circuit 160, a signal level detection circuit (SIGDTC) 220 is arranged in the terminal device 180A, and a memory card interface is provided between the signal level detection circuits 210 and 220. 230 shows an example in which the signal level detection circuit 220 and the memory card 190 are connected by the memory card interface 235. The memory card interface 230 corresponds to 167A in FIG. 1, and the memory card interface 230 corresponds to 167B in FIG. 240 indicates a power supply direction when the terminal device 1809 accesses the memory card 190, and 241 indicates a power supply direction when the memory card control circuit 160 accesses the memory card 190.

  FIG. 3 is a flowchart for determining which of the terminal device 180 and the IC card 100 controls the memory card 190 based on the configuration of FIG. When the memory card 190 is not used, it is assumed that the power is turned off and the clock is stopped to reduce power consumption. When an access request from the IC card 100 to the memory card 190 is generated (310), the memory card control circuit 160 uses the signal level detection circuit 210 to measure the power level supplied to the memory card interface 230 (320). ). When power from the memory card interface 230 is detected in a state where the power is not supplied, the terminal device 180 is accessing the memory card 190 because the terminal device 180 is supplying power. Means. At this time, the IC card 100 waits until the power supply is stopped and makes a determination again (330). When power is not detected, the signal level detection circuit 210 starts power supply to the memory card 190 (340) and accesses the memory card 190. Conversely, when the terminal device 180 issues an access request to the memory card 190 (350), the terminal device 180 uses the signal level detection circuit 220 to measure the power supply level from the memory card interface 230 (360). When the power from the memory card interface 230 is detected in a state where the power is not supplied, the IC card 100 is accessing the memory card 190 because the power is supplied from the IC card 100. Means that. At this time, the terminal device 180 waits until the power supply from the IC card 100 stops and makes a determination again (370). If power supply is not detected, the terminal device 180 starts power supply to the memory card 190 (380) and accesses the memory card 190. If the memory card 190 is not ready in step 330 or step 370, the write data may be cached using the memory built in the IC card 100 or the terminal device 180, and the writing may be completed. . At this time, if the memory is a volatile memory, it is necessary to consider the power shut-off and a note on the write size. If the memory is volatile and the power is turned off before the actual writing is completed, the data to be written cannot be guaranteed. When a data write request exceeding the data size prepared in the cache occurs, the cache cannot be relied on, and it is necessary to wait until the bus is released.

  Thus, when controlling from both the terminal 180 and the IC card 100, the mechanism of exclusive control becomes complicated. As shown in FIG. 1, even when an access request to the memory card 190 from the terminal device 180 is written via the IC card 100, as represented by the use of the MSC data stream, If so, there is an effect that the control can be simplified. Hereinafter, the control mode in that case will be described in detail.

  When the terminal interface control circuit 120 is an interface capable of controlling a plurality of data streams such as USB, a path for processing a data stream such as the ICC data stream for security processing such as authentication and key exchange, content, A route for processing a data stream such as the MSC data stream for data transfer processing such as a file is separated. Thereby, efficient processing becomes possible. For example, as described with reference to FIG. 1, when data is stored in the ICCBUF 120B as an endpoint for a data stream for security processing such as authentication and key exchange, the data is read and processed by the CPU 150. The On the other hand, when data is stored in the MSCBUF 120A as an endpoint for a data stream for data transfer processing of contents and files, a dedicated control circuit is used instead of the CPU 150, and the CPU 150 resource is hardly consumed. The process to do is performed. For this purpose, for example, a control module represented by the transfer control circuit 140, the selector 132, the buffer 145, the instruction queue 165, and the control register 163 is provided.

  FIG. 6 illustrates details of the instruction queue 165 and the control register 163. The instruction queue 165 is a buffer for queuing an instruction code (INST) 610, and may include a request type 612, a request source 614, a transfer size 616, a buffer address 618, and a parameter 620. The request type 612 stores the type of instruction to be transferred to the memory card 190 such as read (read), write (write), erase (erase), and may store a command code in the SD card or MMC. The request source 614 stores information on whether the processing request is issued by the terminal device 180 or the CPU 150. The transfer size stores the size of the data to be actually transferred, and the buffer address 618 indicates where the data is stored on the buffer 145. A parameter 620 is additional information, and stores an address for calling data from the memory card 190, an option number, a security parameter, and the like. The control register 630 may include a queue pointer 630, a base pointer 632, an empty buffer register 634, a transfer request register 636, a write lock register 638, a bus enable register 640, a card disable register 642, and a process end register 644. The queue pointer 630 and the base pointer 632 represent addresses on the instruction code queue 165. Normally, the memory card control circuit 160 starts the search from the base pointer 632. If there is no free buffer for reading during the read processing, the pointer is advanced and the write processing accumulated in the queue is executed. If the buffer is freed by this process, the memory card control circuit 160 executes the read process of the base pointer 632. When the instruction code 610 from the transfer control circuit 140 or the CPU 150 is to be set, the instruction code 610 is stored at the position of the queue pointer 630 of the instruction code queue 165, and the pointer is advanced by one. The empty buffer register 634 is a register for managing an empty address of the buffer 145. Normally, read / write to the memory card 190 is performed based on a prescribed data size such as 512 bytes. Therefore, it is more efficient to manage the buffer managed by the register with this size. For example, when managing in units of 512 bytes, a buffer of up to 16 KB can be managed if a 32-bit register is prepared. The transfer request register 636 indicates where in the buffer 145 the data transferred by the transfer circuit to the input / output control circuit 120 at the time of a read request is stored. This information may be expressed by setting “1” in an area in which data to be transferred is stored in the same manner as the empty buffer register 634 and setting “0” in other areas, or an absolute address. Alternatively, notification may be made by storing a valid relative address or a fixed address with the transfer circuit 140. Two or more transfer requests 636 may be prepared for processing a read request from the terminal device 180 and a read request from the CPU 150. Instead of adopting such a method, this information may be stored in the buffer address 618 at the time of a read request. The write lock register 638 is a register for prohibiting setting of an additional write request when there is no empty buffer at the time of a read request. The bus enable register 640 is a register for switching access to the buffer 145 between the transfer circuit 140 and the bus 130. The card disable register 642 is a register for notifying the transfer circuit 140 or the CPU 150 that the card cannot be used. The process end register 644 is a register for notifying that the process set in the instruction code queue 165 has been completed. Instead of using the process end register 644, an area for storing a process end notification may be provided in a part of the instruction code. In this case, it is the transfer control circuit 140 or the CPU 150 that deletes the instructions queued in the instruction queue 163. The data control unit of the memory card control circuit 160 may perform access restriction using information of the request source 614 when someone other than the request source tries to delete the queue. Further, in order to enable maintenance, a request when the transfer source is the terminal 180 may be deleted from the CPU 150. When the queue is erased, the transfer control circuit 140 may treat the process as being reset when a read request is made.

  FIG. 4 illustrates an operation flow of the transfer control circuit 140. The transfer control circuit 140 confirms the transfer request from the terminal interface control circuit 120 by generating an interrupt (or polling) (410). If there is a transfer request, it is first determined whether it is a write request (412). If it is a write request, the transfer control circuit 140 checks whether the buffer 145 can be accessed by reading the bus enable register 640 (432). If the bus enable register 640 is not set, the bus enable register 640 is set, and the selector 132 is set to be accessible from the transfer control circuit 140 to the buffer 145 (436). If the bus enable register 640 has already been set, it waits until it is reset (434) and checks again. However, if the CPU 150 occupies the bus with the memory card 190 and the bus is not released for a certain period according to the agreement with the terminal, the processing may be interrupted as an error. After switching the selector 132 to enable data transfer, the transfer control circuit 140 checks whether or not the buffer 145 has an empty space by using the empty buffer register 634 (438). If there is no space, the process waits until there is space in the buffer 145 (440), and checks again whether there is space in the buffer 145. Normally, when a request is issued directly from the terminal device 180 to the memory card 190, they are not executed simultaneously. That is, the state where the buffer 145 is not empty means a case where there is a memory access from the CPU 150. Therefore, the buffer 145 becomes empty as time passes. However, as a case where there is no empty space, a case where a failure occurs in the memory card 190 can be considered. When the memory card control circuit 160 detects that a problem has occurred in the memory card 190, the memory card control circuit 160 may set the card disable register 642 and notify the transfer circuit 140 that there is an error. The card disable register 642 is set when an access request to the memory card 190 is generated and the memory card 190 cannot be initialized at that time, or when reinitialization processing after a transfer error fails. If the buffer 145 is empty, the transfer control circuit 140 sets an instruction based on the write request in the instruction queue 165 and sets the empty buffer register 634 (442). Thereafter, the data in the terminal interface control circuit 120 is stored in the buffer 145 (444), and the bus use right is released by resetting the bus enable register 640 (446). The transfer control circuit 140 determines whether the writing is completed using the processing end register 644 (448). Further, the transfer circuit 140 may determine the end of the processing when the instruction in the instruction queue 165 is deleted. When it is confirmed that the writing has been completed, the terminal interface control circuit 120 is notified of this.

  Next, the case (414) of responding to the read request in FIG. 4 will be described. If the read request is met, the transfer control circuit 140 sets an instruction based on the read request in the instruction queue 165 (462). The memory card control circuit 160 performs a reading process on the memory card 190 in accordance with the set instruction. In this example, the memory card control circuit 160 secures the buffer 145 for temporarily storing read data from the memory card 190, but the transfer control circuit 140 or the CPU 150 may also secure it. When the memory card control circuit 160 performs, the transfer control circuit 140 waits until reading from the memory card is completed. The transfer control circuit 140 uses the transfer request register 636 and the process end register 644 to check whether the reading is completed. In the transfer request register 636, the address of the buffer 145 may be described, or the buffer may be divided into a plurality of areas and displayed as a bitmap indicating the presence / absence of data in the area. This address information may be realized by other methods, such as when the address information is unique or calculated from notification by a relative address. Two sets of transfer request registers 636 and processing end registers 644 may be provided for transfer with the terminal device 180 and transfer with the CPU 150. Also, instead of having a plurality of sets of these registers, the instruction code 610 is expanded, the address where the data is stored is given to Buffer Addr. 618 and an end notification is added as additional data, and the transfer circuit 140 writes the instruction code written by itself. 160 may be confirmed. In this case, it is the role of the transfer control circuit 140 to delete the instruction in the instruction queue 165 after the transfer. When there is a transfer request, the transfer control circuit 140 uses the bus enable register 640 to check whether the buffer 145 can be accessed (466). If the bus enable register 640 is already set, it waits until the bus is released (468). When the bus becomes available, the bus use right is set by setting the bus enable register 640, and the selector 132 switches so that the buffer 145 can be accessed from the transfer control circuit 140 (470). Thereafter, the data is transferred to the terminal interface control circuit 120 (472), the bus use right is released by resetting the bus enable register 640, the corresponding instruction in the instruction queue 165 is deleted, and the empty buffer register which has been used. 634 is cleared (474). When these processes are completed, the input / output control circuit 120 is notified of completion (476).

  If the process is neither a write request nor a read request, it is determined whether it is a delete request (416). In the case of a deletion request, the transfer control circuit 140 sets an instruction based on the deletion request in the instruction queue 165 (492). In accordance with the command, the memory card control circuit 160 performs a deletion process on the memory card 190. After the setting, the transfer control circuit 140 checks whether or not the deletion process is completed using the process end register 644 (494). When the processing is completed, the completion is notified to the input / output control circuit 120 (496).

  If the request does not apply to any of these, the CPU 150 may be notified and processing left to the CPU 150 (418). Examples of such processing include locking the memory card 190, reading ID, setting protection, and security processing. However, these processing may be performed by the transfer control circuit 140.

  FIG. 5 illustrates an operation flow of the memory card control circuit 160. The memory card control circuit 160 refers to the contents of the instruction code queue 165 at the position of the base pointer 632 and confirms whether the instruction code 610 exists (510). When the positions of the queue pointer 630 and the base pointer 632 are the same, the queue is not accumulated, so it may be determined that the queue pointer 630 and the base pointer 632 are not stacked. If so, it is determined whether the instruction is a read request (512). The read system request indicates a request that needs to store some information extracted from the memory card 190 in the buffer 145. If it is a read request, it is checked whether there is a free capacity designated by the transfer size 616 in the free buffer register 634 (514). If there is no free space, the write lock register 638 is set so as not to generate an additional write request (516). If there is no danger that a large delay occurs due to insertion of another write instruction during the write process, or if the delay does not cause a problem, the process using the write lock 638 may not be performed. . Next, the next instruction of the base pointer 632 is examined (530), and it is confirmed whether or not a write instruction is loaded (532). If there is no write request, the pointer is advanced again to confirm the write request. The pointer may be advanced again when the instruction is a read instruction. When the method described here is used, the read command does not require the buffer 145 until immediately before execution. Therefore, the buffer 145 is not empty because the write command is loaded or transferred to the CPU 150 or the transfer control circuit 140. It can be determined that there is data inside. When data is being transferred, the processing is completed and the buffer 145 is emptied over time. However, the write command does not generate a vacant buffer unless the process is advanced. Free space can be secured. When sharing of the buffer 145 is required due to a transfer request from the terminal device 180 and a transfer request from the CPU 150, it is difficult to estimate the communication volume of the other party. However, if an empty space is provided in the buffer 145 assuming that fact, a part of the buffer 145 remains empty even when there is no communication on one side, resulting in poor efficiency. If this method is used, there is an effect that scheduling can be performed efficiently even though it is a very simple method. This loop is repeated until the queue pointer 630 is reached. As a result, if there is no write request (534), the state of the empty buffer 634 is confirmed again. If there is a write request, write processing is performed (540). Here, the write process refers to a combination of the processes 552, 554, and 556. If it is found in step 514 that the empty buffer register 634 has an empty space, the empty buffer register 634 is set, and if the write lock register 638 is set, it is reset (518). Next, a command for the memory card 190 is generated (520). A command such as an SD card or MMC is composed of a command number and a parameter, which can be generated by using a request type 612 and a parameter 620. When the command is generated, reading of data from the memory card 190 is started using the command (522). When the reading is completed (524), the location of the buffer 145 being used for the transfer request is set in the buffer address 618 or the transfer request 634, and the end of transfer is notified by setting the processing end register 644 (526).

  If it is not a read request in step 512, it is determined whether it is a write request (550). The write system request corresponds to a process of transferring some value stored in the buffer 145 to the memory card 190. If it is a write request, a command for the memory card 190 is generated in the same manner as in the procedure 520 (552), and a write process to the memory card 190 is started (554). Thereafter, the instruction in the instruction queue 165 is deleted, the base pointer is advanced, the empty buffer register 634 used is released, and the write end is notified (556). At this time, the transfer circuit 140 may receive the end of the processing by checking the transfer request register 636, or may determine the end of the processing when the instruction in the instruction queue 165 is deleted.

  If it is determined in step 550 that the instruction is not a write system, the instruction is processed as an instruction that does not involve data transfer. The memory card control circuit 160 generates a command in the same manner as the procedure 520 (570), and starts processing for the memory card 190 (572). Thereafter, the current queue is deleted, the base pointer is advanced, and the end of processing is notified (574).

  By adopting the above mechanism, the IC card 100 operates as a host of the memory card 190, operates as a memory card reader / writer from the terminal, and seems to be an extended data area from the IC card 100. Can be operated.

  The IC card 100 having the above-described mechanism can operate in a state where compatibility with a conventional IC card terminal device is maintained.

  FIG. 7 shows a configuration considering compatibility with an existing system. UARTCNT 740 is a serial interface control circuit such as UART (Universal Asynchronous Receiver / Transmitter), and OTHCNT is another control circuit, for example, a circuit module connected to the internal bus 130. Symbol 710 means that the signal propagation direction is one direction indicated by an arrow. CLKDTC720 is a clock detection circuit, and LVLDTC730 is a potential detection circuit.

  When UART (Universal Asynchronous Receiver / Transmitter) is valid in the terminal device, the terminal device 180 inputs a clock to the terminal C3 and a reset signal to the terminal C2 after power-on, but the memory card control circuit 160 is connected to the memory card 190. When these communications occur when the power is not turned on, the IC card chip 100 can detect the state by the clock detection circuit 720 or the like. For this reason, the IC card 100 may be able to recognize that a normal operation using UART is expected. For example, when a clock is input from the terminal C3: 703, the circuit can be switched to operate the UART control circuit (UARTCNT) 740 by using the clock detection circuit (CLKDTC) 720. Further, when there is an electrical access to the terminal C6 from the outside, the IC card 100 can detect that the terminal C6 is used for another purpose, so the operation of the memory card control circuit 160 is turned off, Functions may be assigned. For example, when the potential from the terminal C6: 706 is detected by the potential detection circuit (LVLDTC) 730 before the memory card control circuit 160 is operated, another control circuit (OTHCNT) using the terminal C6: 706 is used. ) The circuit can be switched to use 750.

  By adopting the above-described configuration typified by FIG. 1, the terminal device 180 can be used by the user as if it were a terminal device with an IC card 100 and a memory card slot. For example, the terminal device 180 is a mobile phone. The cellular phone has a SIM (registered trademark) card slot and a memory card slot, but the conventional model has no strong correlation between the two. However, by applying the present invention, the data stored in the memory card 190 is encrypted regardless of the vulnerability of the software of the terminal device, and the address scramble is applied, although the configuration looks exactly the same from the user. The memory card 190 can be locked using a random number generated in the IC card 100. Further, when the IC card 100 wants to store data in the memory card 190, it is possible to store the data in the memory card 190 in the safest manner possible. For example, if the written data is encrypted together with a random number and the hash value is held in the IC card 100, it is possible to adopt a mechanism in which tampering and eavesdropping are very difficult. If the memory card 190 is provided with a function capable of establishing a secure session with the IC card 100, data flowing on the memory card interfaces 167A and 167B can be concealed.

  FIG. 8 shows a second example to which the IC card chip 105 is applied. The IC card chip 105 having the memory card host function can be incorporated in a device having a USB interface 820 such as a USB token (USNTKN) 810. At this time, the USB token 810 has a memory card slot 830. By connecting the terminal of the memory card slot 830 to the memory card control circuit 160 of the IC card chip 105, a USB token with a memory card slot can be realized. By adopting this configuration, there is an effect that the number of parts on the terminal device side can be reduced. Further, as described above, since data to be written to the memory card 190 can be encrypted and address scrambled by the IC card chip 105, and further, card locking can be performed by using data that is difficult to predict as a password. There is an effect that safety can be improved as compared with a case where a memory card is directly used by using a terminal device such as a reader / writer. In general, a token is an authentication device that can be carried by storing a certificate or the like in the same manner as an IC card. However, an IC card requires a reader, whereas a token does not require a reader. It can be connected to a standard USB port or the like.

  FIG. 9 shows a third example to which the IC card chip 105 is applied. The IC card chip 105 is applied to a SIM (Subscriber Identity Module) card 910 which is an IC card in which contractor information issued by a mobile phone company is recorded. The IC card chip 105 is mounted on the substrate of the SIM card 910, and a single unit having a flash memory card interface circuit (FMCNT) 921 and a flash memory (FMEM) 922 arranged on the substrate for signals from the memory card control circuit 160 By connecting to a flash memory card chip (FMCRCHP) 920 as a chip, a SIM card with a large capacity flash memory can be realized. The flash memory card interface circuit 921 has a flash memory controller that receives a command supplied from the memory card controller 160 and issues a flash memory command for accessing the flash memory 922 to the flash memory 922, and a card host interface function. . By adopting this configuration, when a large-capacity flash memory is normally mounted externally, it is necessary to mount a complex and large-scale flash memory controller on an IC chip with a low unit price. There was a problem that the cost was greatly affected. At this time, by using the flash memory card chip 920 with a memory card interface circuit, a complicated flash memory controller can be brought to a flash memory unit having a high unit price, so that the problem related to the compatibility of the flash memory is taken care of. This eliminates the need for the communication and can communicate with the serial interface, so that the wiring can be simplified.

  FIG. 10 shows a modification of the IC card chip. An IC chip (ICCRDCHP) 1070 shown in the figure has a plurality of memory card control circuits (MCRDCNT) 160 and 1030, and has a configuration capable of connecting a plurality of memory cards (MCRD) 190 and 1020. In this case, the memory card 190 and the memory card 1020 may be the same type of device or different types of devices. The number of expansions of the memory card control circuit may be 3 or more. For example, in FIG. 10, an IC card chip 1070 is applied to a memory card reader / writer (MCRDRD / WR) 1060. In this configuration, by supporting various memory card specifications, any memory card can be securely managed by encryption or address scrambling. Similarly to the example of FIG. 1, the usage can be divided so that the memory card 190 is used as the data storage of the terminal device and the memory card 1020 is used as the expansion memory of the IC card chip 1070. In this case, there is an effect that it is not necessary to include a mechanism for avoiding bus contention in the memory card control circuits 160 and 1030. Here, a USB interface (USBIF) 1050 is provided as an input / output interface, and a terminal interface control circuit (TRMIFCNT) 1080 is connected to the memory card control circuits 160 and 1030 via dedicated buses, respectively, and has the same configuration as FIG. .

  FIG. 11 shows still another modification of the IC card chip. An IC chip (ICCRDCHP) 1190 shown in the figure has a USB control circuit 1160 instead of the memory card control circuit 160, and has a configuration in which a USB device can be connected via USB interfaces (USBIF) 1130 and 1110. As described above, when the terminal device interface control circuit 1150 is USB, it is also possible to transfer data to the memory card 190 using a transfer control circuit such as 140 for a data stream such as a file. Here, data other than the data stream processed by the IC card chip 1190 is directly transferred to the USBIF 1130, 1110, or a new endpoint controlled by the CPU 150 is added. For example, FIG. 11 illustrates a case where the present invention is applied to the USB hub 1180. By adopting this configuration, it is possible to encrypt the data stream from the USBIF 1170 without applying a load to the terminal device.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the terminal interface control circuit as the input / output interface control circuit is not limited to the USB interface, the memory card interface control circuit is not limited to the MMC interface, the memory card is not limited to the flash memory card, and can be changed as appropriate. . An IC card semiconductor device is synonymous with a microcomputer capable of security processing such as encryption / decryption processing or authentication processing. It goes without saying that the IC card semiconductor device may include other peripheral circuits and arithmetic circuits not shown in FIG.

It is a block diagram which shows an example of the IC card to which this invention is applied. It is a block diagram which shows the example which makes a memory card accessible not only from an IC card but from a terminal device. It is a flowchart for determining which of a terminal device and an IC card controls a memory card based on the configuration of FIG. It is an operation | movement flowchart which shows the process by the transfer control circuit. It is an operation | movement flowchart which shows the process by a memory card control circuit. It is explanatory drawing which illustrates the detail of an instruction queue and a control register. It is a block diagram which illustrates the structure for maintaining the compatibility with the conventional IC card in the IC card of FIG. It is a schematic block diagram which shows the example which applied the IC card chip to the USB token card with a memory card slot. It is a schematic block diagram which shows the example which applied the IC card chip to the SIM card with a large capacity flash memory. It is a schematic block diagram which shows the modification of the IC card chip applied to the secure memory card reader / writer. It is a schematic block diagram which shows the modification of the IC card chip applied to the secure USB hub.

Explanation of symbols

100 IC card (ICCRD)
105 IC card chip (ICCRDCHP)
120 Terminal interface control circuit (TRMIFCNT)
120A MSC buffer (MSCBUF)
120B ICC buffer (ICCBUF)
127 I / O interface 130 Internal bus 132 Selector 132
140 Transfer control circuit (TRCNT)
145 buffer (BUFF)
150 Central processing unit (CPU)
155 Internal memory (MEM)
160 Memory card control circuit (MCRDCNT)
163 Control register (CREG)
165 Instruction queue (IQUE)
167A, 167B Memory card interface 180 Terminal device (TRML)
181A, 181B Interface terminal 190 Memory card (MCRD)
270 I / O interface

Claims (14)

An input / output interface control circuit that performs input / output control with the outside in accordance with a predetermined input / output interface specification;
A memory card interface control circuit for performing input / output control with an external memory card in conformity with a predetermined memory card interface specification;
A central processing unit capable of performing data processing in response to a security processing request supplied to the input / output interface control circuit, and giving a memory card access instruction to the memory card interface control circuit;
A transfer control circuit for giving a memory card access instruction to the memory card interface control circuit in response to a memory card access processing request supplied to the input / output interface control circuit; A buffer memory between the transfer control circuit and the memory card interface control circuit;
2. The IC according to claim 1, wherein the transfer control circuit controls transfer of write data to the memory card to the data buffer, and the memory card interface control circuit controls transfer of read data from the memory card to the data buffer. Card semiconductor device.   3. The IC according to claim 2, further comprising an internal bus connecting the input / output interface control circuit and a central processing unit and an internal bus extending from the input / output interface control circuit to the buffer via a transfer control circuit. Card semiconductor device. The memory card interface control circuit has an instruction queue in which an access command instructing an access operation of the memory card is stored.
The central processing unit and the transfer control circuit can write an access command to the instruction queue;
2. The IC card semiconductor device according to claim 1, wherein the memory card interface control circuit performs interface control for an external memory card in accordance with an access command written in an instruction queue.   When the memory card access processing request supplied to the input / output interface control circuit is a write, the transfer control circuit acquires the bus right of the transfer path from the transfer control circuit to the buffer, and writes to the empty area of the buffer 5. The data transfer is performed, a write access command is transferred to an instruction queue of the memory card interface control circuit, and control for writing the write data of the buffer to the memory card is started by the memory card interface control circuit. IC card semiconductor device.   When the memory card access processing request supplied to the input / output interface control circuit is a read, the transfer control circuit transfers a read access command to an instruction queue of the memory card interface control circuit, and the memory card interface control circuit To read data from the memory card and store it in an empty area of the buffer, acquire the bus right of the transfer path from the buffer to the transfer control circuit, and supply the buffer read data to the input / output interface control circuit, The semiconductor device for IC cards according to claim 4.   When the memory card interface control circuit responds to the read access command, if there is no free space in the buffer, the memory card interface control circuit first performs the write with the write access command stored in the instruction queue to secure the free space in the buffer. The semiconductor device for an IC card according to claim 6.   The transfer control circuit transfers an erase access command to an instruction queue of the memory card interface control circuit when the memory card access processing request supplied to the input / output interface control circuit is erase, and the memory card interface control circuit The IC card semiconductor device according to claim 4, wherein an erasing operation on the memory card is started.   An IC card semiconductor device according to claim 1, a first interface terminal connected to an input / output interface control circuit of the IC card semiconductor device, and a memory card interface control circuit of the IC card semiconductor device. An IC card having a second interface terminal to be connected.   10. The first terminal interface terminal connected to the first interface terminal exposed to the outside of the IC card among the first interface terminals in the IC card according to claim 9, and the second interface in the IC card according to claim 9. Of the terminals, a second terminal interface terminal connected to the second interface terminal exposed to the outside of the IC card, a third terminal interface terminal to which a memory card is connected, and the second terminal interface terminal to the third terminal And a bypass path connected to the interface terminal. An input / output interface control circuit that performs input / output control with the outside in accordance with a predetermined input / output interface specification;
A memory card interface control circuit for performing input / output control with an external memory card in conformity with a predetermined memory card interface specification;
A first data processing device for performing data processing in response to a security processing request supplied to the input / output interface control circuit;
A second data processing circuit for giving a memory card access instruction to the memory card interface control circuit in response to a memory card access processing request supplied to the input / output interface control circuit;
The memory card interface control circuit includes a voltage detection circuit having an input terminal connected to a power supply terminal for supplying operating power to the memory card, and the memory is detected when no voltage is supplied from the outside by the voltage detection circuit. An IC card semiconductor device that starts an access operation to a card.   12. The semiconductor device for an IC card according to claim 11, wherein the first data processing device is capable of giving a memory card access instruction to the memory card interface control circuit.   An IC card semiconductor device according to claim 11, a first interface terminal connected to an input / output interface control circuit of the IC card semiconductor device, and a memory card interface control circuit of the IC card semiconductor device. An IC card having a second interface terminal to be connected;   14. A first terminal interface terminal connected to a first interface terminal exposed to the outside of the IC card among the first interface terminals in the IC card according to claim 13, and the second interface terminal in the IC card according to claim 13. A second terminal interface terminal connected to the second interface terminal exposed to the outside of the IC card, a third terminal interface terminal connected to the memory card, and for supplying operating power from the IC card to the memory card And a voltage detection circuit having an input terminal connected to a power supply terminal of the second terminal interface terminals of the second terminal interface terminal via the third terminal interface terminal when no voltage is supplied from the outside by the voltage detection circuit. IC card terminal device for starting access operation to memory card .

Images