JP2009118209A - Data communication system - Google Patents

Data communication system Download PDF

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JP2009118209A
JP2009118209A JP2007289168A JP2007289168A JP2009118209A JP 2009118209 A JP2009118209 A JP 2009118209A JP 2007289168 A JP2007289168 A JP 2007289168A JP 2007289168 A JP2007289168 A JP 2007289168A JP 2009118209 A JP2009118209 A JP 2009118209A
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circuit boards
nth
data
control board
communication system
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Masaharu Ito
正治 伊藤
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Tamagawa Seiki Co Ltd
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Tamagawa Seiki Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem: it is difficult to apply a conventional data communication system to a case where a wide wiring space can not be secured, since circuit boards are connected to a control substrate in parallel with each other and N pieces of wiring are required between a driving device and a control device. <P>SOLUTION: In a data communication system according to the present invention, first to N-th circuit boards 1-n are connected in series in order within a driving device, the N-th circuit board (n) is connected to a control substrate 21 of a control device 20 and within one frame of a transmission signal 13 to be transmitted from the first circuit board 1 through the second to N-th circuit boards 2-n to the control substrate, first to N-th data 13a-13n are superimposed in order which are created by the circuit boards 1-n, respectively. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、シリアル通信データのデータ通信システムに関し、特に、制御対象内において第１〜第Ｎ回路基板が順に直列に接続されるとともに、前記第Ｎ回路基板が制御基板に接続され、第１回路基板から第２〜第Ｎ回路基板を経由して制御基板に伝送される伝送信号のフレーム内に、第１〜第Ｎ回路基板が各々作成した第１〜第Ｎデータが順に重畳されることで、制御対象と制御装置との間の配線数を少なくできるとともに、制御基板のポート数を少なくできるようにするための新規な改良に関するものである。   The present invention relates to a data communication system for serial communication data, and in particular, first to Nth circuit boards are sequentially connected in series in a controlled object, and the Nth circuit board is connected to a control board, and the first circuit The first to Nth data created by the first to Nth circuit boards are superimposed in order in the frame of the transmission signal transmitted from the board to the control board via the second to Nth circuit boards. The present invention relates to a novel improvement for reducing the number of wires between a control target and a control device and reducing the number of ports of a control board.

一般的な技術であるため特に文献名は挙げていないが、従来用いられていたこの種のデータ通信システムは、図３に示すように構成されている。図３は、従来のデータ通信システムを示すブロック図である。
図において、制御対象である駆動装置１０内には、第１〜第Ｎ回路基板１〜Ｎが設けられている（Ｎは任意の正の整数）。この駆動装置１０を制御する制御装置２０内には、制御基板２１が設けられている。前記第１〜第Ｎ回路基板１〜Ｎの例えばＲＳ４２２等の出力ポート１１ａ〜１１ｎは、第１〜第Ｎ信号線１４ａ〜１４ｎを介して、前記制御基板２１の入力ポート２２に各々接続されている。すなわち、前記各回路基板１〜Ｎは、前記制御基板２１に対して互いに並列に接続されている。前記各回路基板１〜Ｎが作成した第１〜第Ｎデータ１３ａ〜１３ｎは、１ビットずつ順に前記制御基板２１に送信される。すなわち、複数のシリアル通信が並列に実施される。 Although it is a general technique, no particular literature name is given, but this type of data communication system conventionally used is configured as shown in FIG. FIG. 3 is a block diagram showing a conventional data communication system.
In the figure, the first to Nth circuit boards 1 to N are provided in the drive device 10 to be controlled (N is an arbitrary positive integer). A control board 21 is provided in the control device 20 that controls the drive device 10. The output ports 11a to 11n such as RS422 of the first to Nth circuit boards 1 to N are connected to the input port 22 of the control board 21 via the first to Nth signal lines 14a to 14n, respectively. Yes. That is, the circuit boards 1 to N are connected to the control board 21 in parallel with each other. The first to Nth data 13a to 13n created by the circuit boards 1 to N are sequentially transmitted to the control board 21 bit by bit. That is, a plurality of serial communications are performed in parallel.

上記のような従来のデータ通信システムでは、前記各回路基板１〜Ｎが前記制御基板２１に対して互いに並列に接続されているので、駆動装置１０と制御装置２０との間にＮ本の配線が必要であり、配線スペースを広く確保できない場合に適用が困難である。また、前記制御基板２１の入力ポート２２のポート数が多くなり、コスト増大の要因になる。   In the conventional data communication system as described above, each of the circuit boards 1 to N is connected to the control board 21 in parallel with each other, so that N wirings are provided between the driving device 10 and the control device 20. Therefore, it is difficult to apply when a wide wiring space cannot be secured. Further, the number of input ports 22 of the control board 21 increases, which causes an increase in cost.

本発明は、上記のような課題を解決するためになされたものであり、その目的は、制御対象と制御装置との間の配線数を少なくできるとともに、制御基板のポート数を少なくできるデータ通信システムを提供することである。   The present invention has been made in order to solve the above-described problems, and an object of the present invention is to perform data communication that can reduce the number of wirings between a control target and a control device and the number of ports on a control board. Is to provide a system.

本発明に係るデータ通信システムは、制御対象内に設けられた第１〜第Ｎ回路基板（但し、Ｎは２以上の任意の正の整数）と、前記制御対象を制御する制御装置内に設けられた制御基板とを備え、前記制御対象内において前記第１〜第Ｎ回路基板が順に直列に接続されるとともに、前記第Ｎ回路基板が前記制御基板に接続され、前記第１回路基板から前記第２〜第Ｎ回路基板を経由して前記制御基板に伝送される伝送信号の１フレーム内に、前記第１〜第Ｎ回路基板が各々作成した第１〜第Ｎデータが順に重畳されている。   A data communication system according to the present invention is provided in first to Nth circuit boards (where N is an arbitrary positive integer greater than or equal to 2) provided in a control target and a control device that controls the control target. And the first to Nth circuit boards are sequentially connected in series within the controlled object, and the Nth circuit board is connected to the control board, from the first circuit board to the control board. The first to Nth data created by the first to Nth circuit boards are superimposed in sequence in one frame of a transmission signal transmitted to the control board via the second to Nth circuit boards. .

本発明のデータ通信システムによれば、前記制御対象内において前記第１〜第Ｎ回路基板が順に直列に接続されるとともに、前記第Ｎ回路基板が前記制御基板に接続され、前記第１回路基板から前記第２〜第Ｎ回路基板を経由して前記制御基板に伝送される伝送信号の１フレーム内に、前記第１〜第Ｎ回路基板が各々作成した第１〜第Ｎデータが順に重畳されているので、駆動装置と制御装置との間の配線を１本と少なくできる。これにより、配線スペースを広く確保できない場合にも容易に適用できる。
また、前記制御基板の入力ポートのポート数も１つと少なくでき、コスト増大を抑えることができる。特に、回路基板の数が増えても、前記制御基板では１つの入力ポートで対応できるため、回路基板の増設等に有利である。 According to the data communication system of the present invention, the first to Nth circuit boards are sequentially connected in series in the controlled object, the Nth circuit board is connected to the control board, and the first circuit board is connected. The first to Nth data respectively created by the first to Nth circuit boards are superimposed in order in one frame of a transmission signal transmitted to the control board via the second to Nth circuit boards. Therefore, the number of wires between the driving device and the control device can be reduced to one. Thereby, it can be easily applied even when a wide wiring space cannot be secured.
Further, the number of input ports of the control board can be reduced to one, and an increase in cost can be suppressed. In particular, even if the number of circuit boards increases, the control board can cope with one input port, which is advantageous for the addition of circuit boards.

以下、本発明を実施するための最良の形態について、図面を参照して説明する。
実施の形態１．
図１は、本発明の実施の形態１によるデータ通信システムを示すブロック図である。図において、制御対象である駆動装置１０内には、第１〜第Ｎ回路基板１〜Ｎが設けられている（但し、Ｎは任意の正の整数）。これら第１〜第Ｎ回路基板１〜Ｎは、駆動装置１０内において、順に直列に接続されている。換言すると、第１〜第Ｎ回路基板１〜Ｎは、数珠繋ぎされている。具体的には、第１回路基板１の出力ポート１１ａは第２回路基板２の入力ポート１２ｂに第１信号線１４ａを介して接続され、第２回路基板２の出力ポート１１ｂは第３回路基板の入力ポート（図示せず）に第２信号線１４ｂを介して接続され、第Ｎ−１回路基板の出力ポート（図示せず）は第Ｎ回路基板ｎの入力ポート１２ｎに第Ｎ−１信号線１４ｎ−１を介して接続されている。すなわち、Ｘを１〜Ｎ−１の任意の正の整数としたときに、第Ｘ回路基板の出力ポートは、第Ｘ信号線を介して、前記第Ｘ＋１回路基板の入力ポートに接続されている。 The best mode for carrying out the present invention will be described below with reference to the drawings.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a data communication system according to Embodiment 1 of the present invention. In the figure, the first to Nth circuit boards 1 to N are provided in the drive device 10 to be controlled (where N is an arbitrary positive integer). The first to Nth circuit boards 1 to N are sequentially connected in series in the driving device 10. In other words, the first to Nth circuit boards 1 to N are connected in a daisy chain. Specifically, the output port 11a of the first circuit board 1 is connected to the input port 12b of the second circuit board 2 via the first signal line 14a, and the output port 11b of the second circuit board 2 is connected to the third circuit board. Is connected to the input port (not shown) of the N-1 circuit board via the second signal line 14b, and the output port (not shown) of the N-1 circuit board is connected to the input port 12n of the Nth circuit board n. They are connected via a line 14n-1. That is, when X is an arbitrary positive integer from 1 to N-1, the output port of the Xth circuit board is connected to the input port of the X + 1th circuit board via the Xth signal line. .

前記駆動装置１０を制御するための制御装置２０内には、制御基板２１が設けられている。前記第Ｎ回路基板ｎの出力ポート１１ｎは、第Ｎ信号線１４ｎを介して、前記制御基板２１の入力ポート２２に接続されている。   A control board 21 is provided in the control device 20 for controlling the driving device 10. The output port 11n of the Nth circuit board n is connected to the input port 22 of the control board 21 via an Nth signal line 14n.

前記第１回路基板１は、前記第２〜第Ｎ回路基板２〜ｎを経由して前記制御基板２１に伝送信号１３を入力する。前記第１〜第Ｎ回路基板１〜ｎは、各々が作成した第１〜第Ｎデータ１３ａ〜１３ｎを、この伝送信号１３の１フレーム内に順に重畳する。   The first circuit board 1 inputs a transmission signal 13 to the control board 21 via the second to Nth circuit boards 2 to n. The first to N-th circuit boards 1 to n superimpose the first to N-th data 13 a to 13 n created by each in order within one frame of the transmission signal 13.

次に、データの重畳についてより具体的に説明する。図２は、図１の各回路基板１〜ｎ及び伝送信号１３をより詳細に示す説明図である。図において、各回路基板１〜ｎには、例えばＡ／Ｄ変換部等、図示しないセンサからの情報が入力される複数の情報入力部３０と、例えばＦＰＧＡ（Ｆｉｅｌｄ Ｐｒｏｇｒａｍｍａｂｌｅ Ｇａｔｅ Ａｒｒａｙ）等の第１〜第Ｎ演算部３１ａ〜３１ｎが設けられている。   Next, the data superposition will be described more specifically. FIG. 2 is an explanatory diagram showing the circuit boards 1 to n and the transmission signal 13 of FIG. 1 in more detail. In the figure, each of the circuit boards 1 to n includes a plurality of information input units 30 to which information from a sensor (not shown) such as an A / D conversion unit is input, and a first such as a field programmable gate array (FPGA). To N-th arithmetic units 31a to 31n are provided.

図１の伝送信号１３は、複数のフレーム１３０（図２参照）によって構成される。第１演算部３１ａは、情報入力部３０からの情報に基づいて第１データ１３ａを作成するとともに、この第１データ１３ａを基礎データ１３１とともに、フレーム１３０に組み入れる。なお、基礎データ１３１は、同期を取るためのＳＹＮＣフレームと、フレーム数をカウントするためのフレームカウンタとから構成される。   The transmission signal 13 in FIG. 1 includes a plurality of frames 130 (see FIG. 2). The first calculation unit 31 a creates the first data 13 a based on the information from the information input unit 30, and incorporates the first data 13 a together with the basic data 131 into the frame 130. The basic data 131 is composed of a SYNC frame for synchronization and a frame counter for counting the number of frames.

第２演算部３１ｂは、前記第１演算部３１ａと同様に、情報入力部３０からの情報に基づいて第２データ１３ｂを作成する。また、第２演算部３１ｂは、第２回路基板２の入力ポート１２ｂに入力されたフレーム１３０に第２データ１３ｂを重畳し、このフレーム１３０を出力ポート１１ｂから出力する。すなわち、第２演算部３１ｂは、フレーム１３０に既に組み込まれている基礎データ１３１及び第１データ１３ａに変更を加えない。   Similar to the first calculation unit 31a, the second calculation unit 31b creates the second data 13b based on information from the information input unit 30. The second arithmetic unit 31b superimposes the second data 13b on the frame 130 input to the input port 12b of the second circuit board 2, and outputs the frame 130 from the output port 11b. That is, the second calculation unit 31b does not change the basic data 131 and the first data 13a that are already incorporated in the frame 130.

第３回路基板（図示せず）から第Ｎ回路基板ｎにおいても、第２演算部３１ｂによるデータ重畳と同様の処理が行われる。すなわち、第Ｎ回路基板ｎから制御基板２１に伝送信号１３が入力されるときには、１つのフレーム１３０に基礎データ１３１と第１〜第Ｎデータ１３ａ〜１３ｎとが順に重畳されている。   From the third circuit board (not shown) to the Nth circuit board n, the same processing as the data superposition by the second arithmetic unit 31b is performed. That is, when the transmission signal 13 is input from the Nth circuit board n to the control board 21, the basic data 131 and the first to Nth data 13 a to 13 n are sequentially superimposed on one frame 130.

つまり、従来システムでは複数のシリアル通信を並列に実施していたところを、この実施の形態では、１つのシリアル通信すなわち１つの伝送信号１３内に、Ｎ個のチャンネルを設け、各チャンネルを利用して、第１〜第Ｎデータ１３ａ〜１３ｎを制御基板２１に送信するように構成している。なお、１つのフレーム１３０に組み込まれる第１〜第Ｎデータ１３ａ〜１３ｎのデータ量、及びフレーム１３０に設けられるチャンネル数は、予め外部から設定される。   That is, in the conventional system, a plurality of serial communications are performed in parallel. In this embodiment, N channels are provided in one serial communication, that is, one transmission signal 13, and each channel is used. Thus, the first to Nth data 13a to 13n are configured to be transmitted to the control board 21. The data amount of the first to Nth data 13a to 13n incorporated in one frame 130 and the number of channels provided in the frame 130 are set in advance from the outside.

このようなデータ通信システムでは、駆動装置１０と制御装置２０との間の信号線を第Ｎ信号線１４ｎの１本のみと少なくできる。これにより、配線スペースを広く確保できない場合でも容易に適用できる。また、制御基板２１の入力ポート２２のポート数を１つと少なくでき、回路基板増大によるコスト増大を抑えることができる。仮に、駆動装置１０内に回路基板を増設することがあっても、制御基板２１の入力ポート２２のポート数を変えずに済み、回路基板の増設に有利である。   In such a data communication system, the number of signal lines between the driving device 10 and the control device 20 can be reduced to only one of the Nth signal lines 14n. Thereby, even when a wide wiring space cannot be secured, it can be easily applied. Further, the number of input ports 22 of the control board 21 can be reduced to one, and an increase in cost due to an increase in circuit boards can be suppressed. Even if a circuit board is added in the driving device 10, it is not necessary to change the number of input ports 22 of the control board 21, which is advantageous for the addition of the circuit board.

なお、実施の形態１では、第１〜第Ｎ回路基板１〜ｎは、駆動装置１０内で第１〜第Ｎ−１信号線１４ａ〜１４ｎ−１により接続されると説明したが、これら信号線は、例えばマザーボードの回路であってもよい。   In the first embodiment, it has been described that the first to Nth circuit boards 1 to n are connected by the first to N-1th signal lines 14a to 14n-1 in the driving device 10. The line may be, for example, a motherboard circuit.

本発明の実施の形態１によるデータ通信システムを示すブロック図である。It is a block diagram which shows the data communication system by Embodiment 1 of this invention. 図１の各回路基板及び伝送信号をより詳細に示す説明図である。It is explanatory drawing which shows each circuit board and transmission signal of FIG. 1 in detail. 従来のデータ通信システムを示すブロック図である。It is a block diagram which shows the conventional data communication system.

符号の説明Explanation of symbols

１〜ｎ 回路基板
１０ 駆動装置（制御対象）
１１ａ〜１１ｎ 出力ポート
１２ａ〜１２ｎ，２２ 入力ポート
１３ａ〜１３ｎ 第１〜第Ｎデータ
１３ 伝送信号
１３０ フレーム
１４ａ〜１４ｎ 第１〜第Ｎ信号線
２０ 制御装置
２１ 制御基板 1 to n circuit board 10 drive device (control target)
11a to 11n Output port 12a to 12n, 22 Input port 13a to 13n First to Nth data 13 Transmission signal 130 Frame 14a to 14n First to Nth signal line 20 Controller 21 Control board

Claims (1)

制御対象（１０）内に設けられた第１〜第Ｎ回路基板（１〜ｎ、但し、Ｎは２以上の任意の正の整数）と、
前記制御対象（１０）を制御する制御装置（２０）内に設けられた制御基板（２１）と
を備え、
前記制御対象（１０）内において前記第１〜第Ｎ回路基板（１〜ｎ）が順に直列に接続されるとともに、前記第Ｎ回路基板（ｎ）が前記制御基板（２１）に接続され、
前記第１回路基板（１）から前記第２〜第Ｎ回路基板（２〜ｎ）を経由して前記制御基板（２１）に伝送される伝送信号（１３）の１つのフレーム（１３０）内に、前記第１〜第Ｎ回路基板（１〜ｎ）が各々作成した第１〜第Ｎデータ（１３ａ〜１３ｎ）が順に重畳されていることを特徴とするデータ通信システム。 First to Nth circuit boards (1 to n, where N is an arbitrary positive integer of 2 or more) provided in the controlled object (10);
A control board (21) provided in a control device (20) for controlling the control object (10),
In the controlled object (10), the first to Nth circuit boards (1 to n) are sequentially connected in series, and the Nth circuit board (n) is connected to the control board (21),
In one frame (130) of a transmission signal (13) transmitted from the first circuit board (1) to the control board (21) via the second to Nth circuit boards (2-n). A data communication system, wherein first to Nth data (13a to 13n) respectively created by the first to Nth circuit boards (1 to n) are sequentially superimposed.
JP2007289168A 2007-11-07 2007-11-07 Data communication system Pending JP2009118209A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07186961A (en) * 1993-12-27 1995-07-25 East Japan Railway Co Data adding system data relay transmitter
JPH11306451A (en) * 1998-04-17 1999-11-05 Alps Electric Co Ltd Theft monitoring system
JP2005333471A (en) * 2004-05-20 2005-12-02 Mitsubishi Electric Corp Data transmission system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07186961A (en) * 1993-12-27 1995-07-25 East Japan Railway Co Data adding system data relay transmitter
JPH11306451A (en) * 1998-04-17 1999-11-05 Alps Electric Co Ltd Theft monitoring system
JP2005333471A (en) * 2004-05-20 2005-12-02 Mitsubishi Electric Corp Data transmission system

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