JP2009117540A - Surface emitting laser element - Google Patents

Surface emitting laser element Download PDF

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JP2009117540A
JP2009117540A JP2007287582A JP2007287582A JP2009117540A JP 2009117540 A JP2009117540 A JP 2009117540A JP 2007287582 A JP2007287582 A JP 2007287582A JP 2007287582 A JP2007287582 A JP 2007287582A JP 2009117540 A JP2009117540 A JP 2009117540A
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mesa post
layer
current injection
injection region
emitting laser
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JP5100316B2 (en
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Koji Hiraiwa
浩二 平岩
Norihiro Iwai
則広 岩井
Keishi Takaki
啓史 高木
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Furukawa Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrode structure for preventing the collapse of the mesa post of an oxidized layer-constricted VCSEL element. <P>SOLUTION: The VCSEL element 100 has a rectangular-shape current injection region 20a in an oxidized constricted layer 20. An electrode lead wire 30 which is formed on the upper part of the mesa post 50 and connected to a p-side electrode 26 to supply an oscillating current to the mesa post 50 is formed at an angle position corresponding to one of peaks of the rectangular-shape current injection region 20a. Stress to be applied from the p-side electrode lead wire 30 to the mesa post 50 is reduced to prevent the collapse of the mesa post 50 due to the stress of the oxidized constricted layer 20. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、面発光型レーザ素子に関し、更に詳細には、素子寿命が長く、信頼性に優れた酸化層狭窄型の面発光型レーザ素子に関する。   The present invention relates to a surface emitting laser element, and more particularly, to an oxide layer confined surface emitting laser element having a long element lifetime and excellent reliability.

面発光型レーザ素子は、基板面に対して直交方向に光を出射させる半導体レーザ素子である。面発光型レーザ素子は、従来のファブリペロー共振器型半導体レーザ素子とは異なり、同じ基板上に2次元アレイ状に多数の面発光型レーザ素子を配列できることもあって、近年、データ通信分野で特に注目されている。   A surface emitting laser element is a semiconductor laser element that emits light in a direction orthogonal to a substrate surface. Unlike conventional Fabry-Perot resonator type semiconductor laser elements, surface-emitting laser elements can be arranged in a two-dimensional array on the same substrate, and in recent years in the field of data communications. Particular attention has been paid.

面発光型レーザ素子(以下、VCSEL(Vertical-cavity Surface-emitting laser)素子と呼ぶ)は、GaAsやInPといった半導体基板上に1対の多層膜反射鏡(DBRミラー)を形成し、その1対のDBRミラーの間に発光領域となる活性層を含むレーザ共振部を備えている。各々のDBRミラーは、高屈折率層/低屈折率層からなる対の半導体層や誘電体層を多数対(ペア)積層することによって形成されている。VCSEL素子では、このDBRミラー内に、或いは活性層に近接して、電流を閉じ込めるための酸化狭窄層が形成される、電流注入領域及び電流阻止領域を有する酸化層狭窄型の素子構造が従来から知られている。酸化層狭窄型のVCSEL素子は、例えば特許文献1及び2に記載されている。酸化狭窄層には、電流狭窄機能の他に光狭窄機能を有するものも知られている。   A surface emitting laser element (hereinafter referred to as a VCSEL (Vertical-cavity Surface-emitting laser) element) is formed by forming a pair of multilayer mirrors (DBR mirrors) on a semiconductor substrate such as GaAs or InP. A laser resonator including an active layer serving as a light emitting region is provided between the DBR mirrors. Each DBR mirror is formed by laminating a large number of pairs of semiconductor layers and dielectric layers composed of a high refractive index layer / low refractive index layer. In the VCSEL device, an oxide confinement type device structure having a current injection region and a current blocking region, in which an oxide confinement layer for confining current is formed in the DBR mirror or in the vicinity of the active layer, has been conventionally used. Are known. An oxide layer constriction type VCSEL element is described in Patent Documents 1 and 2, for example. In addition to the current confinement function, an oxide confinement layer having a light confinement function is also known.

図5を参照して、従来の酸化層狭窄型のVCSEL素子の構成を説明する。VCSEL素子200は、n−GaAs基板60上に、それぞれの層の厚さがλ/(4n)(λは発振波長、nは屈折率)のn−Al0.2Ga0.8As/n−Al0.9Ga0.1Asの35ペアからなる下部DBRミラー62、下部クラッド層64、量子井戸活性層66、上部クラッド層68、及び、それぞれの層の厚さがλ/(4n)(λは発振波長、nは屈折率)のp−Al0.2Ga0.8As/p−Al0.9Ga0.1Asの25ペアからなる上部DBRミラー70を含む積層構造を備えている。n−Al0.2Ga0.8As層及びp−Al0.2Ga0.8As層がDBRミラー62、70の高屈折率層を構成し、n−Al0.9Ga0.1As層及びp−Al0.9Ga0.1As層がDBRミラー62、70の低屈折率層を構成する。 With reference to FIG. 5, the configuration of a conventional oxide layer constriction type VCSEL element will be described. The VCSEL element 200 has an n-Al 0.2 Ga 0.8 As / n-Al 0.9 Ga layer on the n-GaAs substrate 60 having a thickness of each layer of λ / (4n) (λ is an oscillation wavelength and n is a refractive index). The lower DBR mirror 62 consisting of 35 pairs of 0.1 As, the lower cladding layer 64, the quantum well active layer 66, the upper cladding layer 68, and the thickness of each layer is λ / (4n) (λ is the oscillation wavelength, n is It has a laminated structure including an upper DBR mirror 70 composed of 25 pairs of p-Al 0.2 Ga 0.8 As / p-Al 0.9 Ga 0.1 As of (refractive index). The n-Al 0.2 Ga 0.8 As layer and the p-Al 0.2 Ga 0.8 As layer constitute the high refractive index layers of the DBR mirrors 62 and 70, and the n-Al 0.9 Ga 0.1 As layer and the p-Al 0.9 Ga 0.1 As layer The low refractive index layers of the DBR mirrors 62 and 70 are configured.

上部DBRミラー70には、活性層66に近い側の一層のp−Al0.9Ga0.1As層に代えて、例えばAl0.97Ga0.03As層で構成され、かつ中央の電流注入領域72a以外の周囲のAlが選択的に酸化されて電流阻止領域72bを構成する酸化狭窄層72が形成されている。酸化狭窄層72は、VCSEL素子200における電流狭窄構造及び光狭窄閉じ込め構造を構成している。 The upper DBR mirror 70 is formed of, for example, an Al 0.97 Ga 0.03 As layer instead of the single p-Al 0.9 Ga 0.1 As layer on the side close to the active layer 66, and has a periphery other than the central current injection region 72a. An oxidized constricting layer 72 constituting the current blocking region 72b is formed by selectively oxidizing the Al. The oxidized confinement layer 72 constitutes a current confinement structure and an optical confinement confinement structure in the VCSEL element 200.

前記積層構造のうち、上部DBRミラー70は、フォトリソグラフィー及びエッチング加工により、酸化狭窄層72よりも下方の活性層66に近い層まで、例えば直径30μmの円柱形状のメサポスト74に加工されている。   In the laminated structure, the upper DBR mirror 70 is processed into a cylindrical mesa post 74 having a diameter of, for example, 30 μm, by photolithography and etching, up to a layer close to the active layer 66 below the oxidized constricting layer 72.

上記酸化層狭窄型のVCSEL素子200の形成に際しては、メサポスト74に加工した積層構造を水蒸気雰囲気中にて、約400℃の温度で酸化処理を行い、AlGaAs層のメサポスト外周側の領域を酸化する。この選択酸化によって酸化狭窄層72が形成される。酸化狭窄層72は、外周側の幅が10μmの電流阻止領域72bと、中央の電流注入領域72aとから構成される。   When forming the oxide layer narrowing type VCSEL element 200, the laminated structure processed into the mesa post 74 is oxidized in a water vapor atmosphere at a temperature of about 400 ° C. to oxidize the region on the outer side of the mesa post of the AlGaAs layer. . By this selective oxidation, an oxidized constricting layer 72 is formed. The oxidized constricting layer 72 includes a current blocking region 72b having an outer peripheral width of 10 μm and a central current injection region 72a.

メサポスト74は、上部を平坦化するためにその周囲が例えばポリイミド層76により埋め込まれている。メサポスト74の上端には、その外周側に5μm〜10μm程度の幅でメサポスト74の上端に接触するリング状(環状)のp側電極78が設けられている。また、n−GaAs基板60の裏面には、基板裏面を適宜研磨し、基板厚さを例えば200μm厚に調整した後に、n側電極80が形成されている。更に、ポリイミド層76上には、外部端子とワイヤーで接続するためのp側電極パッド82が、p側電極78と接触するように形成されている。   The mesa post 74 is filled with, for example, a polyimide layer 76 in order to flatten the upper portion. At the upper end of the mesa post 74, a ring-shaped (annular) p-side electrode 78 that contacts the upper end of the mesa post 74 with a width of about 5 μm to 10 μm is provided on the outer peripheral side. Further, the n-side electrode 80 is formed on the back surface of the n-GaAs substrate 60 after the substrate back surface is appropriately polished and the substrate thickness is adjusted to, for example, 200 μm. Further, a p-side electrode pad 82 for connecting to an external terminal with a wire is formed on the polyimide layer 76 so as to be in contact with the p-side electrode 78.

なお、上記プロセスでは、メサポスト周囲の積層構造を全て除去する構造を示したが、この構造に代えて、酸化層狭窄型のVCSEL素子では、メサポスト74の形成に際して、メサポストよりも半径方向外側の外周部分に環状溝を形成し、環状溝の外側の半導体積層を残す構造も一般的に採用されている。この構造では、環状溝は、後にポリイミド層で埋め込まれ、電極パッドは、環状溝外周側の積層上部に形成される。
特開2003−110196号公報 特開2007−142375号公報
In the above process, the structure in which the laminated structure around the mesa post is completely removed is shown. Instead of this structure, in the oxide layer constricted VCSEL element, the outer periphery radially outward from the mesa post 74 is formed when the mesa post 74 is formed. A structure in which an annular groove is formed in a portion and a semiconductor stack outside the annular groove is left is generally employed. In this structure, the annular groove is later filled with a polyimide layer, and the electrode pad is formed on the upper layer of the annular groove on the outer peripheral side.
JP 2003-110196 A JP 2007-142375 A

酸化狭窄層72は、上記のようにAl0.98Ga0.02As層など、Gaを微量加えた三元組成のAlGaAs層から形成されている。この組成のAlGaAs層を用いると、酸化狭窄層内に形成される電流注入領域72aの形状は良好な円形に形成される。しかし、三元組成の半導体層の成膜では、また、微量の元素を含む三元組成の半導体層の場合には特に、その正確な組成制御(特に結晶成長バッチ間)が困難という問題がある。組成制御の精度が低いと、酸化狭窄層を形成する際の酸化速度にばらつきが生じ、電流注入領域の大きさがばらつく。電流注入領域の大きさは、VCSEL素子の電流特性(電流対電圧,電流対光出力)に影響を及ぼし、そのばらつきはVCSEL素子の歩留まりの低下を招く。 The oxidized constriction layer 72 is formed of an AlGaAs layer having a ternary composition to which a small amount of Ga is added, such as an Al 0.98 Ga 0.02 As layer as described above. When an AlGaAs layer having this composition is used, the shape of the current injection region 72a formed in the oxidized constricting layer is formed in a good circular shape. However, in the formation of a semiconductor layer having a ternary composition, there is a problem that it is difficult to accurately control the composition (particularly between crystal growth batches) particularly in the case of a ternary semiconductor layer containing a trace amount of elements. . If the composition control accuracy is low, variations occur in the oxidation rate when forming the oxide constriction layer, and the size of the current injection region varies. The size of the current injection region affects the current characteristics (current vs. voltage, current vs. optical output) of the VCSEL element, and the variation causes a decrease in the yield of the VCSEL element.

AlGaAs層に代えて、二元組成のAlAs層を用いる酸化狭窄層も知られている。しかし、酸化狭窄層にAlAs層を用いると、AlAs層を酸化してAl酸化層に転化させる際に、電流注入領域72aの形状が、メサポスト74の外周形状を正確に反映した円形状にならず、例えば略正方形になるという問題があった。電流注入領域の形状が円形状にならず、例えば略正方形状の場合には、メサポストに不均一な内部応力が発生し、強度不足によりメサポストが倒壊する場合があった。   An oxide constriction layer using a binary composition AlAs layer instead of the AlGaAs layer is also known. However, when an AlAs layer is used for the oxide constriction layer, the shape of the current injection region 72a does not become a circular shape that accurately reflects the outer peripheral shape of the mesa post 74 when the AlAs layer is oxidized and converted into an Al oxide layer. For example, there was a problem of becoming a substantially square. When the shape of the current injection region is not circular, for example, approximately square, non-uniform internal stress is generated on the mesa post, and the mesa post may collapse due to insufficient strength.

本発明は、上記に鑑み、従来の酸化層狭窄型の面発光型レーザ素子を改良し、電流注入領域が円形形状となりにくい材料を酸化狭窄層に用いた場合においても、メサポストの強度不足が生じにくく、耐久性に優れた面発光型レーザ素子を提供することを目的とする。   In view of the above, the present invention improves the conventional oxide layer constriction type surface emitting laser element, and even when a material in which the current injection region is difficult to be circular is used for the oxide constriction layer, the mesa post has insufficient strength. It is an object of the present invention to provide a surface-emitting laser element that is difficult and has excellent durability.

本発明者らは、VCSEL素子のメサポストの強度不足の問題に関し、鋭意研究を行った結果、その強度不足がVCSEL素子の電極の引出線との関係から発生することに想到し、以下の構成を採用することにより、本発明を完成するに至った。   As a result of earnest research on the problem of insufficient strength of the mesa post of the VCSEL element, the present inventors have conceived that the insufficient intensity occurs due to the relationship with the lead line of the electrode of the VCSEL element. By employing the present invention, the present invention has been completed.

本発明の第1の態様の面発光型レーザ素子は、基板と、該基板上に形成される下部DBRミラーと上部DBRミラーからなる1対のDBRミラー、活性層、及び、活性層近傍もしくは上部又は下部DBRミラーの内部に形成され、中心部に電流注入領域を有する酸化狭窄層を含む積層構造と、を備える面発光型レーザ素子において、
少なくとも前記酸化狭窄層を含む積層構造はメサポストを形成しており、
前記電流注入領域は、前記メサポストの中心軸を通り且つ相互に直交する2つの平面のそれぞれに関して略対称構造を有し、且つ、前記2つの平面とメサポスト外周とが交差する近傍の第1の外周部分が、前記2つの平面が成す角度を等分する平面と前記電流注入領域の外周とが交差する近傍の第2の外周部分よりも、メサポスト半径方向外側に突出しており、
前記メサポスト上部に形成され、前記電流注入領域に電流を供給する電極の引出線が、メサポストの中心から見て前記第1の外周部分と同じ角度位置で、メサポストからメサポストの半径方向外側に引き出されることを特徴とする。
A surface-emitting laser device according to a first aspect of the present invention includes a substrate, a pair of DBR mirrors formed on the substrate, each including a lower DBR mirror and an upper DBR mirror, an active layer, and the vicinity of or above the active layer. Or a surface-emitting laser element comprising a stacked structure including an oxide constriction layer formed in the lower DBR mirror and having a current injection region in the center,
The laminated structure including at least the oxidized constricting layer forms a mesa post,
The current injection region has a substantially symmetrical structure with respect to each of two planes passing through the central axis of the mesa post and orthogonal to each other, and a first outer periphery in the vicinity where the two planes intersect with the outer periphery of the mesa post The portion protrudes outward in the mesa post radial direction from the second outer peripheral portion in the vicinity where the plane that equally divides the angle formed by the two planes and the outer periphery of the current injection region intersect,
The lead line of the electrode formed on the mesa post and supplying current to the current injection region is drawn from the mesa post to the radially outer side of the mesa post at the same angular position as the first outer peripheral portion when viewed from the center of the mesa post. It is characterized by that.

本発明の第2の態様の面発光型レーザ素子は、基板と、該基板上に形成される下部DBRミラーと上部DBRミラーからなる1対のDBRミラー、活性層、及び、活性層近傍もしくは上部又は下部DBRミラーの内部に形成され、中心部に電流注入領域を有する酸化狭窄層を含む積層構造と、を備える面発光型レーザ素子において、
少なくとも前記酸化狭窄層を含む積層構造はメサポストを形成しており、
前記電流注入領域は、前記メサポスト中心軸を通り且つ相互に直交する2つの平面のそれぞれに関して略対称構造を有し、且つ、前記2つの平面とメサポスト外周とが交差する近傍の第1の外周部分が、前記2つの平面が成す角度を等分する平面と前記電流注入領域の外周とが交差する近傍の第2の外周部分よりも、メサポスト半径方向外側に突出しており、
前記メサポスト上部に形成され、前記電流注入領域に電流を供給する電極の引出線に、メサポストの半径方向外側で且つメサポストにメサポスト近傍に屈曲部分が形成されていることを特徴とする。
A surface-emitting laser device according to a second aspect of the present invention includes a substrate, a pair of DBR mirrors formed on the substrate and including a lower DBR mirror and an upper DBR mirror, an active layer, and the vicinity of or above the active layer. Or a surface-emitting laser element comprising a stacked structure including an oxide constriction layer formed in the lower DBR mirror and having a current injection region in the center,
The laminated structure including at least the oxidized constricting layer forms a mesa post,
The current injection region has a substantially symmetrical structure with respect to each of two planes passing through the mesa post central axis and orthogonal to each other, and a first outer peripheral portion in the vicinity where the two planes intersect with the outer periphery of the mesa post However, it protrudes outward in the mesa post radial direction from the second outer peripheral portion in the vicinity where the plane that equally divides the angle formed by the two planes and the outer periphery of the current injection region intersect,
A bent portion is formed on an outer side of the mesa post in the radial direction and in the vicinity of the mesa post on the lead line of the electrode that is formed on the mesa post and supplies current to the current injection region.

本発明の第1の態様のVCSEL素子では、酸化狭窄層の酸化に起因する応力が比較的に低く、従ってメサポストの強度が高い角度位置である、電流注入領域の第1の外周部分と同じ角度位置で、電極の引出線による応力がメサポストに印加される。このため、引出線からは、メサポストの倒壊に至るような外力がメサポストに印加されず、メサポストの耐久性が向上する。   In the VCSEL device according to the first aspect of the present invention, the stress caused by oxidation of the oxidized constricting layer is relatively low, and therefore the same angle as the first outer peripheral portion of the current injection region where the strength of the mesa post is high. In position, the stress from the electrode leader is applied to the mesa post. For this reason, the external force that causes the mesa post to collapse is not applied to the mesa post from the leader line, and the durability of the mesa post is improved.

本発明の第2の態様のVCSEL素子では、メサポストの半径方向外側で且つメサポスト近傍に、引出線に屈曲部分を形成したので、引出線からメサポストに印加される応力が緩和され、これによって、メサポストの耐久性が向上する。なお、この屈曲部は、引出線の全長のうち、中央よりメサポストよりに形成することが好ましい。   In the VCSEL device according to the second aspect of the present invention, since the bent portion is formed in the lead line on the outer side in the radial direction of the mesa post and in the vicinity of the mesa post, the stress applied to the mesa post from the lead line is relieved. Improves durability. In addition, it is preferable to form this bending part from mesa post from the center among the full length of a leader line.

本発明の実施形態の説明に先立って電流注入領域に発生する形状について説明する。図6(a)及び(b)はそれぞれ、VCSEL素子を製造する際に使用するウエハ44、及び、このウエハ内に形成されるVCSEL素子200の製造段階の平面図である。VCSEL素子を形成する際に使用する化合物半導体であるGaAs、AlAs、AlGaAsは、立方晶系の閃亜鉛構造を有する。ウエハ44は、図6(a)に示すように、この閃亜鉛構造の化合物半導体の(100)面を、半導体層を成長するためのウエハ面とし、(01*1*)面をオリフラ(Orientation Flat)方向とする。なお、“1*”は、“1”のトップバー付きを示す記号である。同図(b)に示すように、VCSEL素子200を構成する積層を成長し、円柱形状のメサポスト74に加工した後に、メサポスト74の外周側からAlAs層を酸化させて、電流注入領域72aを形成すると、この電流注入領域72aは、メサポスト74の円柱形状を反映した円形状にはならず、同図に示すような略正方形状になる。   Prior to the description of the embodiment of the present invention, the shape generated in the current injection region will be described. FIGS. 6A and 6B are plan views of the wafer 44 used in manufacturing the VCSEL element and the manufacturing stage of the VCSEL element 200 formed in the wafer, respectively. GaAs, AlAs, and AlGaAs, which are compound semiconductors used when forming a VCSEL device, have a cubic zinc flash structure. In the wafer 44, as shown in FIG. 6A, the (100) plane of the compound semiconductor having the zinc flash structure is used as a wafer plane for growing a semiconductor layer, and the (01 * 1 *) plane is oriented as an orientation flat. Flat) direction. “1 *” is a symbol indicating “1” with a top bar. As shown in FIG. 5B, after the stack constituting the VCSEL element 200 is grown and processed into a cylindrical mesa post 74, the AlAs layer is oxidized from the outer periphery of the mesa post 74 to form a current injection region 72a. Then, the current injection region 72a does not have a circular shape reflecting the cylindrical shape of the mesa post 74, but has a substantially square shape as shown in FIG.

電流注入領域72aが略正方形状になるのは、AlAs層は、結晶面が<100>で表される4箇所の外周部分の面が、即ち(010)、(01*0)、(001)、(001*)面が、他の部分例えば(01*1)面に比して、速い酸化速度を有するためである。この酸化速度の比率は、例えば約1.23倍にも達するものである。このような略正方形状の電流注入領域72aでは、酸化量の大小に起因して、略正方形状の頂点に対応する角度位置でメサポストは外部応力に対する耐性が最小になり、また、略正方形状の辺の中点に対応する角度位置でその外部応力に対する耐性が最大になる。   The current injection region 72a has a substantially square shape because the AlAs layer has four outer peripheral surfaces whose crystal planes are represented by <100>, that is, (010), (01 * 0), (001) This is because the (001 *) plane has a faster oxidation rate than other portions, for example, the (01 * 1) plane. The ratio of this oxidation rate reaches about 1.23 times, for example. In such a substantially square current injection region 72a, due to the amount of oxidation, the mesa post has a minimum resistance to external stress at an angular position corresponding to the apex of the substantially square shape. Its resistance to external stress is maximized at the angular position corresponding to the midpoint of the side.

VCSEL素子に電流を供給する電極の引出線も、その厚みに応じてメサポスト74に応力を与える。電流注入領域72aの形状に起因する最大応力の角度位置と、引出線の応力が印加される角度位置とが同じであると、メサポストに印加される応力は最大となり、メサポストに倒壊のおそれが生ずる。従って、本発明の一実施形態では、電流注入領域の形状に起因する応力が最小の角度位置に電極引出線を形成することで、メサポストの倒壊を防止する。また、他の実施形態では、電極引出線にメサポストの外周側の近傍で屈曲部分を形成し、引出線からメサポストにかかる応力を低減する構造を採用する。   The lead line of the electrode that supplies current to the VCSEL element also applies stress to the mesa post 74 according to its thickness. If the angle position of the maximum stress caused by the shape of the current injection region 72a is the same as the angle position where the lead line stress is applied, the stress applied to the mesa post is maximized, and the mesa post may collapse. . Therefore, in one embodiment of the present invention, the mesa post is prevented from collapsing by forming the electrode lead line at an angular position where the stress due to the shape of the current injection region is minimum. In another embodiment, a structure is adopted in which a bent portion is formed in the vicinity of the outer periphery of the mesa post on the electrode lead line to reduce the stress applied to the mesa post from the lead line.

以下、図面を参照し、本発明の実施形態について説明する。なお、実施形態例を示す各図では、同様な要素には同様な参照符号を付して示す。図1は、本発明の第1の実施形態に係るVCSEL素子の平面構造を示している。本実施形態のVCSEL素子100は、従来のVCSEL素子200とは、特にp側電極引出線30の引き出し方向が異なる。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing showing the embodiment, like elements are denoted by like reference numerals. FIG. 1 shows a planar structure of a VCSEL device according to the first embodiment of the present invention. The VCSEL element 100 of the present embodiment is different from the conventional VCSEL element 200 in particular in the direction in which the p-side electrode lead line 30 is drawn.

本実施形態のVCSEL素子100は、従来のVCSEL素子200と同様に、素子の中央部分に円柱形状のメサポスト50を有する。メサポスト50の内部に形成された酸化狭窄層は、中央に略正方形状の電流注入領域20aと、電流注入領域20aを囲む環状の電流阻止領域20bとを有する。メサポスト50の上部には、環状のp側電極26が形成され、p側電極26は、p側電極引出線30を介して、メサポスト50外周側の周囲領域52に形成されたp側電極パッド36に接続される。メサポスト50の下方に形成され、メサポスト50に電流を供給するn側電極は、n側電極引出線34を介して、周囲領域52に形成されたn側電極パッド38に接続される。   The VCSEL device 100 according to the present embodiment has a cylindrical mesa post 50 at the central portion of the device, similarly to the conventional VCSEL device 200. The oxidized constricting layer formed inside the mesa post 50 has a substantially square current injection region 20a at the center and an annular current blocking region 20b surrounding the current injection region 20a. An annular p-side electrode 26 is formed on the top of the mesa post 50, and the p-side electrode 26 is connected to the p-side electrode pad 36 formed in the peripheral region 52 on the outer peripheral side of the mesa post 50 via the p-side electrode lead wire 30. Connected to. An n-side electrode that is formed below the mesa post 50 and supplies a current to the mesa post 50 is connected to an n-side electrode pad 38 formed in the peripheral region 52 via an n-side electrode lead line 34.

図2は、上記実施形態のVCSEL素子100の構造を示す断面図である。VCSEL素子100は、アンドープGaAs基板10と、その上に堆積された積層構造とを有する。積層構造は、基板10側から順次に堆積された、アンドープ半導体から成る下部DBRミラー12、アンドープ半導体バッファ層14、n−コンタクト層16、nクラッド層、多重量子井戸構造を有するレーザ活性層18、電流注入領域20a及び電流阻止領域20bを含む酸化狭窄層20、p−クラッド層22、p+−コンタクト層24、環状のp側電極26、及び、誘電体層から成る上部DBRミラー28から構成される。積層構造では、レーザ活性層18から環状のp側電極26までの部分がメサポスト50に形成されており、メサポスト50の上部及びメサポスト50を囲む周辺領域52の一部には、誘電体DBRミラー28を構成する誘電体層40が形成されている。   FIG. 2 is a cross-sectional view showing the structure of the VCSEL element 100 of the above embodiment. The VCSEL device 100 has an undoped GaAs substrate 10 and a laminated structure deposited thereon. The stacked structure includes a lower DBR mirror 12 made of an undoped semiconductor, an undoped semiconductor buffer layer 14, an n-contact layer 16, an n-clad layer, and a laser active layer 18 having a multiple quantum well structure, which are sequentially deposited from the substrate 10 side. It comprises an oxide constriction layer 20 including a current injection region 20a and a current blocking region 20b, a p-cladding layer 22, a p + -contact layer 24, an annular p-side electrode 26, and an upper DBR mirror 28 made of a dielectric layer. . In the laminated structure, a part from the laser active layer 18 to the annular p-side electrode 26 is formed on the mesa post 50, and the dielectric DBR mirror 28 is formed on the upper part of the mesa post 50 and a part of the peripheral region 52 surrounding the mesa post 50. A dielectric layer 40 is formed.

n−コンタクト層16は、メサポスト50の下部から半径方向外側に延びており、その露出した表面に環状のn側電極32が形成されている。n−コンタクト層16の外周側は、誘電体DBRミラー28を構成する誘電体層40によって囲まれている。n側電極32の表面には、Auから成るn側電極引出線34が形成されている。n側電極引出線34は、誘電体層40が除かれた位置に形成され、n側電極32の表面から延び、n側電極パッド(38:図1)に終端している。環状のp側電極26は、メサポスト50の外周側頂部に形成されており、その表面にp側電極引出線30が形成され、この引出線30は、メサポスト50から延びて、周辺領域52に形成されたp側電極パッド(36:図1)に終端している。   The n-contact layer 16 extends radially outward from the lower portion of the mesa post 50, and an annular n-side electrode 32 is formed on the exposed surface thereof. The outer peripheral side of the n-contact layer 16 is surrounded by a dielectric layer 40 constituting the dielectric DBR mirror 28. An n-side electrode lead wire 34 made of Au is formed on the surface of the n-side electrode 32. The n-side electrode lead line 34 is formed at a position where the dielectric layer 40 is removed, extends from the surface of the n-side electrode 32, and terminates in an n-side electrode pad (38: FIG. 1). The annular p-side electrode 26 is formed on the outer peripheral side top of the mesa post 50, and the p-side electrode lead wire 30 is formed on the surface thereof. The lead wire 30 extends from the mesa post 50 and is formed in the peripheral region 52. The p-side electrode pad (36: FIG. 1) is terminated.

図1に戻り、p側電極引出線30は、略正方形形状の電流注入領域20aの正方形の頂点付近の角度位置から、メサポスト50の外周側に向かって半径方向に延びている。電流注入領域20aの頂点付近では、電流狭窄層20によるメサポスト50の外周側に向かう応力が最も小さい。従って、p側電極引出線30による応力は、電流狭窄層20からメサポスト50に印加される応力が最も小さい位置に働き、p側電極引出線30による応力でメサポスト50が倒壊するおそれを除いている。   Returning to FIG. 1, the p-side electrode lead wire 30 extends in the radial direction from the angular position near the apex of the square of the substantially square current injection region 20 a toward the outer peripheral side of the mesa post 50. In the vicinity of the apex of the current injection region 20a, the stress toward the outer peripheral side of the mesa post 50 by the current confinement layer 20 is the smallest. Therefore, the stress due to the p-side electrode lead wire 30 acts on the position where the stress applied from the current confinement layer 20 to the mesa post 50 is the smallest, and the possibility that the mesa post 50 collapses due to the stress due to the p-side electrode lead wire 30 is excluded. .

上記VCSEL素子100の製造プロセスについて、更に図2を参照して説明する。まず、アンドープGaAs基板上10に、エピタキシャル成長法により、下部DBRミラー12、アンドープ半導体バッファ層14、n−コンタクト層16、n−クラッド層多重量子井戸層を含むレーザ活性層18、酸化狭窄層20となるp−AlAs層、p−クラッド層22、p+−コンタクト層24を順次に成膜して積層構造を形成する。下部DBRミラー12は、例えば、GaAs層/Al0.9Ga0.1As層の34ペアから成り、レーザ活性層18は、層数が3のGaInNAs井戸層及び層数が4のGaAs障壁層を有する。 The manufacturing process of the VCSEL element 100 will be further described with reference to FIG. First, on the undoped GaAs substrate 10, a lower DBR mirror 12, an undoped semiconductor buffer layer 14, an n-contact layer 16, a laser active layer 18 including an n-clad multiple quantum well layer, an oxidized constricting layer 20, and the like are formed by epitaxial growth. A p-AlAs layer, a p-cladding layer 22 and a p + -contact layer 24 are sequentially formed to form a laminated structure. The lower DBR mirror 12 is composed of, for example, 34 pairs of GaAs layer / Al 0.9 Ga 0.1 As layer, and the laser active layer 18 has a GaInNAs well layer having 3 layers and a GaAs barrier layer having 4 layers.

積層構造の表面に、環状のp側電極26を蒸着法によって形成する。p側電極26には、Ti/Ptの金属積層を用いる。例えば、p側電極の外径は30μm、内径は14μmである。次いで、p側電極26の内側をマスクで覆い、p側電極26を金属マスクとするウェットエッチングによって、積層構造をメサポスト50に形成する。なお、該エッチングはn−コンタクト層16の途中まで行った。   An annular p-side electrode 26 is formed on the surface of the laminated structure by vapor deposition. A Ti / Pt metal laminate is used for the p-side electrode 26. For example, the outer diameter of the p-side electrode is 30 μm and the inner diameter is 14 μm. Next, a laminated structure is formed on the mesa post 50 by wet etching with the inside of the p-side electrode 26 covered with a mask and using the p-side electrode 26 as a metal mask. The etching was performed halfway through the n-contact layer 16.

得られたメサポスト中のAlAs層を、水蒸気雰囲気中でメサポスト50の外周側から酸化し、AlAs層の外周部分をAl酸化層とし、電流阻止領域20bに形成する。この際に、AlAs層の内周側に直径が6〜7μm程度の非酸化領域を残すことで、電流注入領域20aとする。次いで、メサポスト50の外壁を誘電体膜で覆い、その外周側のn−コンタクト層16の表面に、半環状のn側電極32を形成する。例えば、n側電極の外径は82μm、内径は42μmである。n側電極32には、例えばAuGeNi/Auの金属積層を用いる。次いで、引き出し電極30、34、36、38を形成した後、全面に誘電体DBRミラー28を形成する。誘電体DBRミラー28としては、例えばα‐Si/SiO,SiNx/SiO,α‐Si/Al等が用いられる。またそのペア数は材料の組み合わせで決まるが、例えばα‐Si/SiOを用いた場合には5〜6ペアである。次いで、p側電極26及びn側電極32の表面上に形成された誘電体層をエッチングで除去する。 The AlAs layer in the obtained mesa post is oxidized from the outer peripheral side of the mesa post 50 in a water vapor atmosphere, and the outer peripheral portion of the AlAs layer is formed as an Al oxide layer to be formed in the current blocking region 20b. At this time, the current injection region 20a is formed by leaving a non-oxidized region having a diameter of about 6 to 7 μm on the inner peripheral side of the AlAs layer. Next, the outer wall of the mesa post 50 is covered with a dielectric film, and a semi-annular n-side electrode 32 is formed on the outer surface of the n-contact layer 16. For example, the outer diameter of the n-side electrode is 82 μm and the inner diameter is 42 μm. For the n-side electrode 32, for example, a metal laminate of AuGeNi / Au is used. Next, after forming the extraction electrodes 30, 34, 36, and 38, the dielectric DBR mirror 28 is formed on the entire surface. As the dielectric DBR mirror 28, for example, α-Si / SiO 2 , SiNx / SiO 2 , α-Si / Al 2 O 3 or the like is used. The number of pairs is determined by the combination of materials. For example, when α-Si / SiO 2 is used, the number is 5 to 6 pairs. Next, the dielectric layers formed on the surfaces of the p-side electrode 26 and the n-side electrode 32 are removed by etching.

次いで、p側電極26及びn側電極32にそれぞれ接続する電極引出線30、34を、電極パッド36、38と共に、蒸着法によって形成する。電極パッド36、38の表面上の誘電体層40をエッチング除去して、電極パッド36、38の表面を露出する。最後にアンドープGaAs基板10を、上述した積層構造を形成した面とは反対側の裏側を研磨して、基板厚みを例えば、150μmに調整して、VCSEL素子の製品とする。例えば、製品の外径は250μm、メサポストの外径は約30μmである。   Next, electrode lead lines 30 and 34 respectively connected to the p-side electrode 26 and the n-side electrode 32 are formed together with the electrode pads 36 and 38 by vapor deposition. The dielectric layer 40 on the surfaces of the electrode pads 36 and 38 is etched away to expose the surfaces of the electrode pads 36 and 38. Finally, the undoped GaAs substrate 10 is polished on the back side opposite to the surface on which the above-described laminated structure is formed, and the substrate thickness is adjusted to, for example, 150 μm to obtain a VCSEL device product. For example, the outer diameter of the product is 250 μm, and the outer diameter of the mesa post is about 30 μm.

図3は、本発明の第2の実施形態例に係るVCSEL素子の平面図である。本実施形態例のVCSEL素子100Aは、p側電極引出線30の引き出し方向、及び、p側電極引出線30の形状が第1の実施形態例のVCSEL素子100と異なる。詳しくは、本実施形態のVCSEL素子100Aは、p側電極引出線30が、正方形状の電流注入領域20aの一辺の中心に対応する角度位置で、メサポスト50から引き出されている。また、p側電極引出線30は、メサポスト50の外側でメサポスト近傍に、S字状の屈曲部分30aが形成されている。その他の構成は、第1の実施形態例と同様である。S字状の屈曲部分30aは、電極引出線30からメサポスト50に印加される応力を低減し、メサポスト50の倒壊を防止している。なお、本実施形態例において、電極引出線30は正方形状の電流注入領域20aの一辺の中心に対応する角度位置で、メサポスト50から引き出されているが、電極引出線30のメサポストに対する角度位置は、任意の方向でよい。屈曲部分30aは、好ましくは、引出線の中央よりもメサポストに近い位置に配置する。   FIG. 3 is a plan view of a VCSEL device according to the second embodiment of the present invention. The VCSEL element 100A of the present embodiment example is different from the VCSEL element 100 of the first embodiment example in the lead-out direction of the p-side electrode lead line 30 and the shape of the p-side electrode lead line 30. Specifically, in the VCSEL device 100A of the present embodiment, the p-side electrode lead wire 30 is drawn from the mesa post 50 at an angular position corresponding to the center of one side of the square current injection region 20a. Further, the p-side electrode lead wire 30 has an S-shaped bent portion 30 a formed outside the mesa post 50 and in the vicinity of the mesa post. Other configurations are the same as those of the first embodiment. The S-shaped bent portion 30a reduces the stress applied to the mesa post 50 from the electrode lead wire 30 and prevents the mesa post 50 from collapsing. In this embodiment, the electrode lead wire 30 is drawn from the mesa post 50 at an angular position corresponding to the center of one side of the square current injection region 20a. However, the angle position of the electrode lead wire 30 with respect to the mesa post is , In any direction. The bent portion 30a is preferably arranged at a position closer to the mesa post than the center of the leader line.

図4は、本発明の第3の実施形態例に係るVCSEL素子の平面図である。本実施形態に係るVCSEL素子100Bは、電流注入領域20aの半径方向外側に、環状に並ぶ4つの分離溝54を形成した例である。各分離溝54は、メサポスト50の中心から見て略1/4の角度範囲に形成される。各分離溝54の相互間を分離する4つのブリッジ56は、略正方形状の電流注入領域20aの4つの頂点に角度位置が一致し、且つ、4つの頂点の1つは、p側電極26の電極引出線30の延びる角度位置に一致している。分離溝54を形成することにより、酸化狭窄層20の電流阻止領域20bに発生した応力が緩和される。この構成により、ブリッジ56は、酸化狭窄層20による応力が最も小さな角度位置に形成される。p側電極引出線30も、同様に酸化狭窄層20による応力が最も小さな角度位置に配置される。これによって、メサポスト50に印加される応力を低減し、メサポストの倒壊のおそれを除いている。   FIG. 4 is a plan view of a VCSEL element according to the third embodiment of the present invention. The VCSEL element 100B according to the present embodiment is an example in which four separation grooves 54 arranged in a ring shape are formed outside the current injection region 20a in the radial direction. Each separation groove 54 is formed in an angle range of approximately ¼ when viewed from the center of the mesa post 50. The four bridges 56 that separate the separation grooves 54 from each other coincide with the four vertexes of the substantially square-shaped current injection region 20a, and one of the four vertexes is the p-side electrode 26. It coincides with the angular position where the electrode lead line 30 extends. By forming the isolation groove 54, the stress generated in the current blocking region 20b of the oxidized constricting layer 20 is relaxed. With this configuration, the bridge 56 is formed at an angular position where the stress due to the oxidized constricting layer 20 is the smallest. Similarly, the p-side electrode lead line 30 is arranged at an angular position where the stress due to the oxidized constricting layer 20 is the smallest. This reduces the stress applied to the mesa post 50 and eliminates the possibility of the mesa post collapsing.

以上、本発明をその好適な実施形態例に基づいて説明したが、本発明の面発光型レーザ素子は、上記実施形態例の構成にのみ限定されるものではなく、上記実施形態例の構成から種々の修正及び変更を施したものも、本発明の範囲に含まれる。   Although the present invention has been described based on the preferred embodiment thereof, the surface emitting laser element of the present invention is not limited to the configuration of the above embodiment example, but from the configuration of the above embodiment example. Various modifications and changes are also included in the scope of the present invention.

例えば、上記実施形態では、電流注入領域が方形状に形成される例を示したが、電流注入領域は、必ずしも方形状でなくともよい。本発明は、電流注入領域が、例えば、メサポスト中心軸を通り且つ相互に直交する2つの平面のそれぞれに関して略対称構造を有し、且つ、直交する2つの平面が成す角度を等分する平面と前記電流注入領域の外周とが交差する近傍の第1の外周部分が、前記2つの平面とメサポスト外周とが交差する近傍の第2の外周部分よりも、メサポスト半径方向に突出している構造に対して適用可能である。   For example, in the above-described embodiment, an example is shown in which the current injection region is formed in a square shape, but the current injection region may not necessarily be a square shape. In the present invention, for example, the current injection region has a substantially symmetric structure with respect to each of two planes that pass through the central axis of the mesa post and are orthogonal to each other, and a plane that equally divides the angle formed by the two orthogonal planes. For a structure in which a first outer peripheral portion in the vicinity where the outer periphery of the current injection region intersects protrudes more in the mesa post radial direction than a second outer peripheral portion in the vicinity where the two planes and the mesa post outer periphery intersect It is applicable.

本発明の面発光型レーザ素子は、データ通信分野などで光ファイバを用いる光通信のための光源として使用できる。   The surface emitting laser element of the present invention can be used as a light source for optical communication using an optical fiber in the field of data communication.

本発明の第1の実施形態例に係るVCSEL素子の平面図。1 is a plan view of a VCSEL element according to a first embodiment example of the present invention. FIG. 図1のVCSEL素子の断面図。FIG. 2 is a cross-sectional view of the VCSEL element in FIG. 1. 本発明の第2の実施形態例に係るVCSEL素子の平面図。The top view of the VCSEL element which concerns on the 2nd Example of this invention. 本発明の第3の実施形態例に係るVCSEL素子の平面図。The top view of the VCSEL element which concerns on the 3rd Example of this invention. 従来のVCSEL素子の断面図。Sectional drawing of the conventional VCSEL element. VCSEL素子の酸化狭窄層の形成に関わる問題点を説明するための図で、(a)及び(b)はそれぞれ、ウエハの平面図、及び、VCSEL素子の平面模式図。2A and 2B are views for explaining problems related to formation of an oxidized constriction layer of a VCSEL element, and FIGS. 3A and 3B are a plan view of a wafer and a schematic plan view of a VCSEL element, respectively.

符号の説明Explanation of symbols

100、100A、100B:VCSEL素子
10:GaAs基板
12:下部DBRミラー
14:バッファ層
16:n−コンタクト層
18:レーザ活性層
20:酸化狭窄層
20a:電流注入領域
20b:電流阻止領域
22:p−クラッド層
24:p+−コンタクト層
26:p側電極
28:誘電体DBRミラー
30:p側電極引出線
30a:屈曲部分
32:n側電極
34:n側電極引出線
36:p側電極パッド
38:n側電極パッド
40:誘電体層
44:ウエハ
50:メサポスト
52:周囲領域
54:分離溝
56:ブリッジ
200:VCSEL素子
60:n−GaAs基板
62:下部DBRミラー
64:下部クラッド層
66:量子井戸活性層
68:上部クラッド層
70:上部DBRミラー
72:酸化狭窄層
72a:電流注入領域
72b:電流阻止領域
74:メサポスト
76:ポリイミド層
78:p側電極
80:n側電極
82:p側電極パッド
100, 100A, 100B: VCSEL element 10: GaAs substrate 12: Lower DBR mirror 14: Buffer layer 16: n-contact layer 18: Laser active layer 20: Oxide constriction layer 20a: Current injection region 20b: Current blocking region 22: p -Clad layer 24: p + -contact layer 26: p-side electrode 28: dielectric DBR mirror 30: p-side electrode lead wire 30a: bent portion 32: n-side electrode 34: n-side electrode lead wire 36: p-side electrode pad 38 : N-side electrode pad 40: dielectric layer 44: wafer 50: mesa post 52: surrounding region 54: separation groove 56: bridge 200: VCSEL element 60: n-GaAs substrate 62: lower DBR mirror 64: lower cladding layer
66: quantum well active layer 68: upper cladding layer 70: upper DBR mirror 72: oxidation constriction layer 72a: current injection region 72b: current blocking region 74: mesa post 76: polyimide layer 78: p-side electrode 80: n-side electrode 82: p-side electrode pad

Claims (6)

基板と、該基板上に形成される下部DBRミラーと上部DBRミラーからなる1対のDBRミラー、活性層、及び、活性層近傍もしくは上部又は下部DBRミラーの内部に形成され、中心部に電流注入領域を有する酸化狭窄層を含む積層構造と、を備える面発光型レーザ素子において、
少なくとも前記酸化狭窄層を含む積層構造はメサポストを形成しており、
前記電流注入領域は、前記メサポストの中心軸を通り且つ相互に直交する2つの平面のそれぞれに関して略対称構造を有し、且つ、前記2つの平面とメサポスト外周とが交差する近傍の第1の外周部分が、前記2つの平面が成す角度を等分する平面と前記電流注入領域の外周とが交差する近傍の第2の外周部分よりも、メサポスト半径方向外側に突出しており、
前記メサポスト上部に形成され、前記電流注入領域に電流を供給する電極の引出線が、メサポストの中心から見て前記第1の外周部分と同じ角度位置で、メサポストからメサポストの半径方向外側に引き出されることを特徴とする面発光型レーザ素子。
A pair of DBR mirrors comprising a substrate and a lower DBR mirror and an upper DBR mirror formed on the substrate, an active layer, and an active layer, formed near or in the upper or lower DBR mirror, and current injection at the center In a surface emitting laser device comprising a laminated structure including an oxidized constricting layer having a region,
The laminated structure including at least the oxidized constricting layer forms a mesa post,
The current injection region has a substantially symmetrical structure with respect to each of two planes passing through the central axis of the mesa post and orthogonal to each other, and a first outer periphery in the vicinity where the two planes intersect with the outer periphery of the mesa post The portion protrudes outward in the mesa post radial direction from the second outer peripheral portion in the vicinity where the plane that equally divides the angle formed by the two planes and the outer periphery of the current injection region intersect,
The lead line of the electrode formed on the mesa post and supplying current to the current injection region is drawn from the mesa post to the radially outer side of the mesa post at the same angular position as the first outer peripheral portion when viewed from the center of the mesa post. A surface-emitting laser element characterized by the above.
前記引出線に、メサポストの半径方向外側で且つメサポスト近傍に屈曲部分が形成されている、請求項1に記載の面発光型レーザ素子。   The surface emitting laser element according to claim 1, wherein a bent portion is formed on the lead line in the radial direction outside of the mesa post and in the vicinity of the mesa post. 基板と、該基板上に形成される下部DBRミラーと上部DBRミラーからなる1対のDBRミラー、活性層、及び、活性層近傍もしくは上部又は下部DBRミラーの内部に形成され、中心部に電流注入領域を有する酸化狭窄層を含む積層構造と、を備える面発光型レーザ素子において、
少なくとも前記酸化狭窄層を含む積層構造はメサポストを形成しており、
前記電流注入領域は、前記メサポスト中心軸を通り且つ相互に直交する2つの平面のそれぞれに関して略対称構造を有し、且つ、前記2つの平面とメサポスト外周とが交差する近傍の第1の外周部分が、前記2つの平面が成す角度を等分する平面と前記電流注入領域の外周とが交差する近傍の第2の外周部分よりも、メサポスト半径方向外側に突出しており、
前記メサポスト上部に形成され、前記電流注入領域に電流を供給する電極の引出線に、メサポストの半径方向外側で且つメサポストにメサポスト近傍に屈曲部分が形成されていることを特徴とする面発光型レーザ素子。
A pair of DBR mirrors comprising a substrate and a lower DBR mirror and an upper DBR mirror formed on the substrate, an active layer, and an active layer, formed near or in the upper or lower DBR mirror, and current injection at the center In a surface emitting laser device comprising a laminated structure including an oxidized constricting layer having a region,
The laminated structure including at least the oxidized constricting layer forms a mesa post,
The current injection region has a substantially symmetrical structure with respect to each of two planes passing through the mesa post central axis and orthogonal to each other, and a first outer peripheral portion in the vicinity where the two planes intersect with the outer periphery of the mesa post However, it protrudes outward in the mesa post radial direction from the second outer peripheral portion in the vicinity where the plane that equally divides the angle formed by the two planes and the outer periphery of the current injection region intersect,
A surface-emitting laser characterized in that a bent portion is formed on the lead line of an electrode that is formed on the mesa post and that supplies current to the current injection region, on the radially outer side of the mesa post and in the vicinity of the mesa post. element.
前記メサポストが、前記電流注入領域の半径方向外側に、環状に並ぶ複数の分離溝を有しており、該分離溝を分離するブリッジが、前記引出線と同じ角度位置に形成される、請求項1〜3の何れか一に記載の面発光型レーザ素子。   The mesa post has a plurality of annularly arranged separation grooves on the outer side in the radial direction of the current injection region, and a bridge separating the separation grooves is formed at the same angular position as the leader line. The surface emitting laser element according to any one of 1 to 3. 前記上部DBRミラーが、誘電体DBRミラーである、請求項1〜4の何れかに記載の面発光型レーザ素子。   The surface emitting laser element according to claim 1, wherein the upper DBR mirror is a dielectric DBR mirror. 前記誘電体ミラーを構成する誘電体層が、前記メサポストを囲む外周領域に形成され、前記引出線が、該誘電体層上に形成されている、請求項5に記載の面発光型レーザ素子。   The surface emitting laser element according to claim 5, wherein a dielectric layer constituting the dielectric mirror is formed in an outer peripheral region surrounding the mesa post, and the lead line is formed on the dielectric layer.
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