JP2009112182A - Dc/dc converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DC/DC converter capable of preventing occurrence of an excessive surge current at switching, regardless a state of loads. <P>SOLUTION: The DC/DC converter outputs a DC input voltage of an input terminal to an external load from an output terminal as a power of specified output voltage. Commutation diodes DU and DL are connected in parallel to main switching transistors SU and SL, respectively, that constitute a bridge circuit to be connected in series for power control and to be alternately turned on and off. One end of a main reactor L is connected to the connection point of both main switching transistors SU and SL, with the other end of the main reactor L connected to an output terminal. A first auxiliary circuit in which a resonance capacitor CU and a first switch Sc are connected in series is connected in parallel to the main switching transistor SU and/or SL. A second auxiliary circuit in which an auxiliary reactor Lr is connected in series to a second switch Sr is connected in parallel to the main reactor L. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a DC / DC converter.

  A resonant snubber type soft switching converter for the purpose of reducing switching loss is, for example, two main circuits connected in series as described in Japanese Patent Application Laid-Open No. 2004-129393 “DC / DC converter”. Resonant capacitors CU and CL are connected in parallel to the switching transistors SU and SL, respectively, and a main reactor L is connected to a connection point between the two main switching transistors SU and SL. On the other hand, the auxiliary reactor Lr and the auxiliary switch Sr are further connected in parallel. Then, for example, in the case of the pressure drop operation, the following operation is performed.

1) At the timing the main switching transistor SU of the upper (i.e. the upper arm) is turned off, the main reactor current I _L flowing in the main reactor is bypassed to the resonant capacitor CU, by charging the resonant capacitor CU, the main switching transistor SU Is a zero voltage switching operation. On the other hand, the timing of turning on the main switching transistor SL of the lower (i.e. the lower arm), by detecting the input voltage to the main reactor current I _L, the main switching transistor SL are set to be zero-voltage switching operation .

2) In addition, by turning on the auxiliary switch Sr, certain time passes a main reactor current I _L or more auxiliary reactor current Ir to the auxiliary reactor Lr. Within this time, the lower main switching transistor SL is turned off. When the lower main switching transistor SL is turned off, the resonance capacitors CU and CL and the auxiliary reactor Lr are resonated. When the electric charge of the resonant capacitor CU is discharged, the voltage across the upper main switching transistor SU becomes around 0V. By turning on the upper main switching transistor SU at a timing when the both-end voltage becomes around 0V, a zero voltage switching operation is performed.

By performing soft switching like this, it becomes possible to reduce the switching loss of the DC / DC converter.
JP 2004-129393 A

However, in the case of the conventional DC / DC converter as described in Patent Document 1, for example, the resonance capacitor CU is connected in parallel with the upper (that is, upper arm) main switching transistor SU. since, in the case of light load, the main reactor current I _L decreases during switching at the timing when the upper main switching transistor SU is turned off, before the resonant capacitor CU is fully charged, the lower (i.e. The main switching transistor SL of the lower arm is turned on, and the soft switching condition is not satisfied. As a result, an excessive surge current is generated at the moment when the lower main switching transistor SL is switched on, and the element may be damaged.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a DC / DC converter capable of preventing an excessive surge current from occurring at the time of switching regardless of the state of a load. It is said.

  In order to solve the above-mentioned problems, the present invention is characterized in that an auxiliary switch is connected in series to a resonance capacitor connected in parallel to the upper main switching transistor and / or the lower main switching transistor.

  According to the DC / DC converter of the present invention, since the auxiliary switch is connected in series to the resonance capacitor connected in parallel to the upper main switching transistor and / or the lower main switching transistor, the auxiliary switch is turned on. By controlling the timing of turning off / off, it is possible to suppress the occurrence of an excessive surge current at the time of switching regardless of the state of the load, so that the element can be prevented from being damaged. be able to.

  Hereinafter, the best embodiment of a DC / DC converter according to the present invention will be described in detail with reference to the drawings.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, first, the outline of the main features of the present invention will be described. The present invention relates to a DC / DC converter to which a soft switching method is applied, and constitutes a bridge circuit that alternately performs on / off operations to perform an upper side (that is, an upper arm) that performs a main switch operation as a DC / DC converter. ) Main switching transistor SU and lower (that is, lower arm) main switching transistor SL are connected in series, and the upper main switching transistor SU and / or the lower main switching transistor SL are connected to each other. This is characterized in that the auxiliary switch is connected in series as the first switch to the upper resonance capacitor CU and / or the lower resonance capacitor CL connected in parallel. is doing.

Here, a period for turning off the auxiliary switch, that the first switch from flowing through the main reactor L for smoothing the main Akutoru current I _L input and output voltages and the switching loss occurring in the DC / DC converter Based on the estimated result, control is performed so that an excessive surge current does not flow.

  Further, at the connection point between the upper main switching transistor SU and the lower main switching transistor SL, a smoothing main reactor L, a resonance auxiliary reactor Lr, and a resonance auxiliary switch serving as a second switch are provided. A circuit connected in series is connected to perform a resonance soft switching operation. That is, by controlling the auxiliary switch, that is, the first switch, the current at the time of turn-off of the upper main switching transistor SU and / or the lower main switching transistor SL is supplied to or cut off from the resonance capacitor CU and / or the resonance capacitor CL. By controlling the auxiliary switch, that is, the first switch and the resonance auxiliary switch, that is, the second switch, the resonance soft switching operation of the resonance capacitor CU and / or the resonance capacitor CL and the auxiliary reactor Lr is performed. It is configured.

  In the DC / DC converter according to the present invention, the resonance capacitor and the auxiliary switch connected in series may be connected in parallel to both the upper main switching transistor SU and the upper main switching transistor SU. Although only one side may be connected in parallel, in the following description of the embodiment, a case where only the upper main switching transistor SU is connected in parallel will be described for the sake of simplicity.

  In addition to the main switching transistors SU and SL, as the transistors constituting each switching element of the DC / DC converter, an IGBT (Insulated Gate Bipolar Transistor) may be used, or a MOS-FET ( Metal Oxide Semiconductor Field Effect Transistor) may be used, or in some cases, a bipolar transistor may be used. Further, it may be an NPN type transistor or, depending on the case, a PNP type transistor. In the following description of the embodiment, a case where an IGBT is used and an NPN transistor is used will be described.

(First embodiment)
First, a first embodiment of a DC / DC converter according to the present invention will be described. (Circuit configuration of the first embodiment)
As a first embodiment of the DC / DC converter according to the present invention, FIG. 1 shows a circuit diagram when the DC / DC converter according to the present invention is applied to a step-down chopper circuit. FIG. 1 is a circuit diagram showing the circuit configuration of the first embodiment of the DC / DC converter according to the present invention, and shows an example when applied to a step-down chopper circuit.

  In FIG. 1, an input power source Vi is a DC voltage source such as a battery. As described above, the switching element used for the main switching transistors SU and SL is formed by a transistor such as an IGBT (Insulated Gate Bipolar Transistor). Further, an upper (that is, upper arm) main switching transistor SU and a lower (that is, lower arm) main switching transistor SL that alternately perform on / off operations as a bridge circuit and perform a main switch operation as a DC / DC converter, The commutation diode DU and the commutation diode DL are connected in parallel to the upper main switching transistor SU and the lower main switching transistor SL, respectively. .

  That is, the emitter of the upper main switching transistor SU is connected to the collector of the lower main switching transistor SL, and the commutation diodes DU and DL are respectively connected from the emitter side to the collector side of the main switching transistors SU and SL. Are connected to the emitter side and the cathode side to the collector side. Further, the collector of the upper main switching transistor SU is connected to the positive side of the input power source Vi, and the emitter of the lower main switching transistor SL is connected to the negative side (here, ground) of the input power source Vi. .

  One end of the smoothing main reactor L is connected to a connection point P between the emitter of the upper main switching transistor SU and the collector of the lower main switching transistor SL. The other end of the main reactor L is connected to one terminal of the smoothing capacitor Co and a positive terminal of the converter output terminal, and electric power for an external load is supplied as an output voltage Vo through the converter output terminal. The Further, the other terminal of the smoothing capacitor Co is connected to the negative terminal of the converter output terminal and falls to the common ground with the negative terminal of the input power source Vi.

Further, a series circuit including a resonant capacitor CU and a first auxiliary switch Sc is connected in parallel to the upper main switching transistor SU as a first auxiliary circuit. The first auxiliary switch Sc is a parallel circuit consisting of the auxiliary switching transistors _{Q SC} made of IGBT and an auxiliary diode _{D SC,} auxiliary diode _{D SC} is a current from the emitter side to the collector side of the auxiliary switching transistor _{Q SC} The anode side is connected to the emitter side and the cathode side is connected to the collector side so that it can flow.

The auxiliary diode _DSC is arranged in such a direction that the current flowing from the positive electrode side of the input power source Vi can be cut off when the auxiliary switching transistor _QSC is turned off, and the charging current to the resonance capacitor CU is set. Inflow is blocked.

In addition, a series circuit including a resonance auxiliary reactor Lr and a second auxiliary switch Sr is connected in parallel to the main reactor L as a second auxiliary circuit. The second auxiliary switch Sr is a transistor made of an IGBT or the like, and is a one-way switch when applied to a step-down chopper circuit. That is, when the second auxiliary switch Sr is turned on, the auxiliary reactor current Ir can be supplied to the auxiliary reactor Lr in the direction opposite to the direction of the current assumed as the main reactor current IL flowing through the main reactor _L. It has become. Furthermore, the second auxiliary switch Sr can prevent the auxiliary reactor current Ir from flowing in the same direction as the current direction assumed as the main reactor current IL flowing in the main reactor _L.

(Operation of the first embodiment)
Next, an example of the operation of the DC / DC converter of this embodiment shown in FIG. 1 will be described based on the operation waveform shown in FIG. 2 and the current path shown in FIG. FIG. 2 is a waveform diagram for explaining an example of the operation of the DC / DC converter shown in FIG. 1, in which the main switching transistors SU and SL, the first auxiliary switch Sc, and the second auxiliary switch Sr are turned on. / Off timing, main reactor current I _L , auxiliary reactor current Ir, collector-emitter voltages V _SU and V _{SL of} each of main switching transistors SU and _SL , collector currents I _SU and I _SL , and first auxiliary the collector of the switch Sc - shows a signal waveform of the emitter voltage _{V SC} and the collector current _{I SC.}

  FIG. 3 is a schematic diagram for explaining a current path of a current flowing in each operation state of the DC / DC converter shown in FIG. 1, and an arrow indicates a current path flowing in the DC / DC converter for each operation state. Shown by.

  As shown in the on / off states of the main switching transistors SU and SL in FIG. 2, the main switching transistors SU and SL are respectively set to duty {D− (Td / Tcyc) at a predetermined switching cycle Tcyc. )} And duty {(1-D)-(Td / Tcyc)}, and PWM control is performed so as to repeat ON / OFF alternately. Here, D means the original duty, and Td means the dead time provided between the ON times of the two so that the main switching transistors SU and SL are not turned ON at the same time. The original duty D and dead time Td are controlled so that the output voltage Vo matches the target output voltage.

Further, during the period when the first auxiliary switch Sc is turned on / off, the switching loss generated in the DC / DC converter is estimated from the main reactor current IL flowing through the main reactor _L , the input voltage Vi, and the output voltage Vo. Control based on the result.

  That is, the first auxiliary switch Sc is pulse-driven by the same switching cycle Tcyc as the main switching transistors SU and SL, and is repeatedly turned on / off. Here, the first auxiliary switch Sc is turned on in a section in which the upper main switching transistor SU is turned on. Further, the first auxiliary switch Sc is turned off in a section during the dead time Td from when the upper main switching transistor SU is switched from on to off until the lower main switching transistor SL is turned on.

  Here, if the resonant capacitor CL and the first auxiliary switch Sc are connected in parallel to the lower main switching transistor SL, the first connected in parallel to the lower main switching transistor SL. The time point when the auxiliary switch Sc is turned on is within the period when the lower main switching transistor SL is on, and the time point when the first auxiliary switch Sc connected in parallel to the lower main switching transistor SL is turned off is lower side. After the main switching transistor SL is turned off, the dead time Td is provided immediately before the upper main switching transistor SU is turned on.

  In the example shown in FIG. 2, the time from when the upper main switching transistor SU is turned on to when the first auxiliary switch Sc is turned on is ΔTSc_on, and after the upper main switching transistor SU is turned off, the first auxiliary switch is turned on. The time until the switch Sc is turned off is defined as ΔTSc_off.

The second auxiliary switch Sr forming the second auxiliary circuit is also a main switching transistor SU, is pulse-driven by the same switching cycle Tcyc and SL, a main reactor current I _L and the input voltage Vi and output voltage Vo From this, the on / off period is determined.

  The second auxiliary switch Sr has a lower main switching transistor SL after the upper main switching transistor SU is turned off so that an auxiliary reactor current Ir sufficient for the auxiliary reactor Lr and the resonant capacitor CU to resonate can flow. Turns on during the interval until is turned off. Further, the second auxiliary switch Sr is turned off in a section in which the upper main switching transistor SU is turned on after the auxiliary reactor current Ir becomes 0 A after the resonance operation.

  That is, the second auxiliary switch Sr is accumulated in the resonance capacitor CU by the resonance action of the resonance capacitor CU and the auxiliary reactor Lr within the interval of the dead time Td before the upper main switching transistor SU is turned on. The on / off operation is controlled so that the electric charge is discharged and the voltage across the both terminals becomes zero.

  Hereinafter, the operation of the DC / DC converter (step-down chopper circuit) of FIG. 1 will be further described with reference to the waveform diagram of FIG. 2 and the schematic diagram of FIG.

  First, it is assumed that the first auxiliary switch Sc is turned on at time t0 shown in FIG. At this time, the upper main switching transistor SU is on, and a current flows through the current path in the state 1 shown in FIG. That is, a normal DC that flows from the positive side of the input power source Vi to the load side as the output voltage Vo from the main reactor L through the upper main switching transistor SU, and then returns to the negative side of the input power source Vi, that is, the ground. An operation as a / DC converter is performed. Here, if the resonance capacitor CU is not charged, no current flows through the first auxiliary switch Sc, and the state where the current flows through the main switching transistor SU is continued. Therefore, the first auxiliary switch Sc can be turned on without generating a surge current or switching loss.

Next, at time t1, the upper main switching transistor SU is turned off. Then, as shown in the state 2 in FIG. 3, a charging current flows from the positive electrode side of the input power source Vi through the first auxiliary switch Sc to the resonance capacitor CU. The charging current at this time is equal to the current value of the reactor current I _L (time t1). By main switching transistor SU of the upper is turned off, the collector current I _SU of the upper main switching transistor SU, as shown in FIG. 2, but will steeply 0A, the collector of the main switching transistor SU - emitter voltage V _{Since SU} rises slowly from 0 V as the resonant capacitor CU is charged, a zero voltage switching operation is performed, and switching loss can be greatly reduced.

Thereafter, at the time t2 (= t1 + ΔTSc_off) when the time ΔTSc_off has elapsed, the first auxiliary switch Sc is turned off. At this time, the resonant capacitor CU is charged from the charging current up to that point, and is cut off from the main current path as shown in state 3 in FIG. through the commutating diodes DL connected in parallel to the switching transistor SL, it made to flow reactor current I _L.

If the output current of the DC / DC converter is large and the time ΔTSc_off from when the upper main switching transistor SU is turned off to when the first auxiliary switch Sc is turned off is defined as the voltage across the resonance capacitor CU (input power supply voltage). vi + until a forward voltage) or voltage of the commutating diode DL, if the a time that can be charged with electric charge, before reaching the time t2, the main reactor current I _L, commutating diode DL Will be diverted to the side. In such a case, the commutating diodes DL connected in parallel with the main switching transistor SL of the lower, auxiliary switching transistor Q _SC of the first auxiliary switch Sc is zero voltage switching operation.

On the other hand, the first auxiliary switch Sc is turned off after the upper main switching transistor SU is turned off, as in the case of a light load where the output voltage Vo is close to the input power supply voltage Vi and the output current of the DC / DC converter is small. in up to the time ΔTSc_off time to, if not able to charge sufficiently resonant capacitor CU, the auxiliary switching transistor Q _SC of commutation diodes DL and the first auxiliary switch Sc is a hard switching operation Switching loss occurs. However, the reverse voltage of the commutation diode DL is lower than the input power supply voltage Vi by the voltage charged in the resonant capacitor CU. Therefore, switching loss occurring at commutation diode DL and an auxiliary switching transistor Q _SC can be reduced compared with the case of turning off the main switching transistor SU by hard switching operation.

Next, at time t3, the lower main switching transistor SL is turned on. At this point, since the resonant capacitor CU is already disconnected from the main current path by the first auxiliary switch Sc, unlike the prior art, a surge current for charging the resonant capacitor CU does not occur, it is possible to turn on the main switching transistor SL of the lower, a current path shown in state 4 of FIG. 3, through the commutating diode DL connected in parallel with the main switching transistor SL of the lower and the reactor current I _L flows to continue.

Further, at time t4, the second auxiliary switch Sr is turned on. Thereby, as shown in the state 5 of FIG. 3, the auxiliary reactor current Ir starts to flow through the auxiliary reactor Lr. The output voltage Vo is biased to the auxiliary reactor Lr, and the auxiliary reactor current Ir increases with time as shown in FIG. Note that the timing at time t4 is a control unit configured by a microcomputer or the like so that the main reactor current I _L and the converter input / output voltages Vi and Vo are detected by a sensor, and the auxiliary reactor current Ir necessary for resonant switching can flow. (Not shown in FIG. 1).

Then, at time t5, as shown in FIG. 2, the auxiliary reactor current Ir is larger than the main reactor current I _L, as a result, as shown in the state 6 in FIG. 3, the lower is on the side current through the main switching transistor SL (= auxiliary reactor current Ir- main reactor current _{I L)} is to flow in.

In this state, at time t6, the lower main switching transistor SL is turned off. Then, until then, current flowing through the main switching transistor SL of the lower (= auxiliary reactor current Ir- main reactor current I _L), as shown in the state 7 of FIG. 3, commutated, resonant capacitor CU, through an auxiliary diode D _SC connected in parallel to the auxiliary switching transistors Q _SC of the first auxiliary switch Sc, it flows in a direction which is regenerated to the input power supply Vi. At this time, the resonant capacitor CU and the auxiliary reactor Lr are resonating.

  During the resonance between the resonance capacitor CU and the auxiliary reactor Lr, the charge charged in the resonance capacitor CU between time t1 and time t2 is discharged.

When the charge charged in the resonance capacitor CU is completely discharged, as shown in the state 8 in FIG. 3, a current flows through the commutation diode DU, and the resonance operation of the resonance capacitor CU and the auxiliary reactor Lr is completed. To do. Accordingly, at the timing of time t7, the collector-emitter voltage V _SU of the main switching transistor SU has dropped to nearly 0V.

  As a result, at the timing from time t7 to time t8, the upper main switching transistor SU is turned on as shown in state 8 in FIG. 3 while the current continues to flow through the commutation diode DU. . That is, as a switching operation for turning on the upper main switching transistor SU, a zero voltage switching operation and a zero current switching operation can be performed.

Thereafter, the auxiliary reactor current Ir gradually decreases as shown in FIG. 2 because the auxiliary reactor Lr is biased in the reverse direction by the voltage of (input power supply voltage Vi−output voltage Vo). After time t8, when the auxiliary reactor current Ir flowing through the auxiliary reactor Lr is smaller than the main reactor current IL flowing through the main reactor _L , commutation occurs, and the current flows through the upper main switching transistor SU.

Furthermore, when the auxiliary reactor current Ir once reaches 0A at time t9, the reverse current flowing in the main current path is blocked by the second auxiliary switch Sr that is unidirectional as shown in FIG. Thereafter, as shown in the state 9 in FIG. 3, the current flowing through the main switching transistor SU becomes equal to the main reactor current IL flowing through the main reactor _L. After that, by turning off the second auxiliary switch Sr until the timing at which the upper main switching transistor SU is turned off, a zero current switching operation can be performed.

  Thereafter, the state returns to the state 1 in FIG. 3 and the above-described operation is repeated again.

  Next, the effect, that is, the operating range of the DC / DC converter shown in FIG. 1 will be described with reference to FIG.

  FIG. 4 is a characteristic diagram in which the operating range of the output voltage Vo and the output current Io of the DC / DC converter of this embodiment shown in FIG. 1 is obtained. For comparison, the characteristic diagram of FIG. 4 also includes the operation range of the conventional DC / DC converter in Patent Document 1.

  In the case of the conventional DC / DC converter of Patent Document 1, the capacitance value of the resonant capacitor CU is set to a small value so that a surge current is not generated at a light load with a small output current Io. On the other hand, the inductance of Lr becomes large, and on the contrary, when a load is high, a surge current is generated and a switching loss is increased, and the operating voltage range is limited as shown in FIG.

  On the other hand, in the case of the DC / DC converter of this embodiment, as shown in FIG. 4, the DC / DC converter is operated in a wide operating voltage range over almost the entire range from a light load to a high load. It is possible to reduce the switching loss without generating a surge current.

  As described in detail above, according to the present embodiment to which the DC / DC converter according to the present invention is applied, the resonance capacitor CU can be cut off from the main current path by the first auxiliary switch Sc. Even when perfect soft switching conditions are not satisfied, it is possible to suppress the surge current that accompanies a short circuit of the resonant capacitor CU, thereby reducing the switching loss and expanding the operating range of the DC / DC converter. become.

(Second embodiment)
Next, a second embodiment of the DC / DC converter according to the present invention will be described.

(Circuit configuration of the second embodiment)
As in the first embodiment described above, when the DC / DC converter according to the present invention is applied to the step-down chopper circuit, the output voltage Vo is close to the input voltage Vi, that is, the output current Io is small. There is a case where soft switching is not established in the light load region. Therefore, when it is intended to be applied to a DC / DC converter used for applications such as electric vehicles and hybrid vehicles, which frequently use the voltage region, the step-down chopper circuit of the first embodiment is used. In the configuration, the effect may be reduced.

  Therefore, in the present embodiment, an example in which the DC / DC converter according to the present invention is applied to a full-bridge type step-up / step-down bidirectional converter circuit will be described. In other words, in addition to the auxiliary reactor and resonant capacitor, a circuit configuration that enables switching operation in a wider range by adding an auxiliary switch to the full-bridge type buck-boost bidirectional converter circuit. Is described below.

  As a second embodiment of the DC / DC converter according to the present invention, FIG. 5 shows a circuit diagram when the DC / DC converter according to the present invention is applied to a full-bridge type step-up / step-down bidirectional converter circuit. FIG. 5 is a circuit diagram showing a circuit configuration of the second embodiment of the DC / DC converter according to the present invention, and shows an example when applied to a full-bridge type buck-boost bidirectional converter circuit. .

  In FIG. 5, an input power source Vi is a DC voltage source such as a battery. The switching elements used in the main switching transistors Q1 and Q2 for constituting the first bridge circuit are formed by transistors such as IGBTs (Insulated Gate Bipolar Transistors) as described above. Two transistors, an upper (that is, upper arm) main switching transistor Q1 and a lower (that is, lower arm) main switching transistor Q2 that perform the main switch operation as the first bridge circuit of the DC / DC converter, are connected in series. Further, a commutation diode D1 and a commutation diode D2 are connected in parallel to the upper main switching transistor Q1 and the lower main switching transistor Q2, respectively.

  That is, the emitter of the upper main switching transistor Q1 is connected to the collector of the lower main switching transistor Q2, and the commutation diodes D1 and D2 are respectively connected from the emitter side to the collector side of the main switching transistors Q1 and Q2. Are connected to the emitter side and the cathode side to the collector side. Further, the collector of the upper main switching transistor Q1 is connected to the positive side of the input power source Vi, and the emitter of the lower main switching transistor Q2 is connected to the negative side (here, ground) of the input power source Vi. .

  Similarly, the switching elements used in the main switching transistors Q3 and Q4 for constituting the second bridge circuit are also formed by transistors such as IGBTs. Two transistors, an upper (that is, upper arm) main switching transistor Q3 and a lower (that is, lower arm) main switching transistor Q4 that perform a main switch operation as a second bridge circuit of the DC / DC converter, are connected in series. Further, a commutation diode D3 and a commutation diode D4 are connected in parallel to the upper main switching transistor Q3 and the lower main switching transistor Q4, respectively.

  That is, the emitter of the upper main switching transistor Q3 is connected to the collector of the lower main switching transistor Q4, and the commutation diodes D3 and D4 are respectively connected from the emitter side to the collector side of the main switching transistors Q3 and Q4. Are connected to the emitter side and the cathode side to the collector side. Further, the collector of the upper main switching transistor Q3 is connected to the positive side of the output voltage terminal Vo, and the emitter of the lower main switching transistor Q4 is the negative side of the output voltage terminal Vo, that is, the negative side of the input power source Vi (here. Then, it is connected to the ground).

  One end of the smoothing main reactor L is connected to a connection point e1 between the emitter of the upper main switching transistor Q1 and the collector of the lower main switching transistor Q2 constituting the first bridge circuit. The other end of the main reactor L is connected to a connection point e2 between the emitter of the upper main switching transistor Q3 and the collector of the lower main switching transistor Q4 constituting the second bridge circuit.

  The collector of the upper main switching transistor Q3 constituting the second bridge circuit is connected to one terminal of the smoothing capacitor Co and the positive terminal of the converter output terminal, and an external load is connected through the converter output terminal. Is supplied as an output voltage Vo. Further, the emitter of the lower main switching transistor Q4 constituting the second bridge circuit is connected to the same ground as the other terminal of the smoothing capacitor Co and the output terminal on the negative side of the output voltage Vo, that is, the negative side of the input power source Vi. falling.

In addition, a series circuit composed of a first resonance capacitor Cr1 and a first auxiliary switch Sc1 is connected in parallel as the first auxiliary circuit to the upper main switching transistor Q1 constituting the first bridge circuit. Yes. The first auxiliary switch Sc1 is a parallel circuit with the first auxiliary switching transistor _{Q SC1} made of IGBT comprising a first auxiliary diode _{D SC1} Prefecture, the first auxiliary diode _{D SC1,} the first auxiliary switching is arranged to supply a current from the emitter side to the collector side of the transistor Q _SC1, the anode side to the emitter side, the cathode side is connected to the collector side.

The first auxiliary diode _DSC1 is arranged in such a direction that the current flowing from the positive electrode side of the input power source Vi can be cut off when the first auxiliary switching transistor _QSC1 is turned off. The charging current is prevented from flowing into one resonance capacitor Cr1.

Similarly, a series circuit including a second resonance capacitor Cr2 and a second auxiliary switch Sc2 is connected in parallel to the upper main switching transistor Q3 constituting the second bridge circuit as a second auxiliary circuit. ing. The second auxiliary switch Sc2 is a parallel circuit with the second auxiliary switching transistor _{Q SC2} made of IGBT consisting second uninterruptible diode _{D SC2} Prefecture, second auxiliary diode _{D SC2,} the second auxiliary switching The anode side is connected to the emitter side and the cathode side is connected to the collector side so that a current can flow from the emitter side to the collector side of the transistor _QSC2 .

The second auxiliary diode _DSC2 is arranged in such a direction that the current flowing from the positive electrode side of the input power source Vi can be cut off when the second auxiliary switching transistor _QSC2 is turned off. The charging current is prevented from flowing into the capacitor Cr2.

  In addition, a series circuit including a resonance auxiliary reactor Lr, a third auxiliary switch Sr1, and a fourth auxiliary switch Sr2 is connected to the main reactor L in parallel as a third auxiliary circuit. Both the third auxiliary switch Sr1 and the fourth auxiliary switch Sr2 form a bidirectional switch, and when one of them is turned on, the direction is different from the direction when the other is turned on. The auxiliary reactor current Ir flowing through the auxiliary reactor Lr can be supplied.

  Here, each of the third auxiliary switch Sr1 and the fourth auxiliary switch Sr2 is a circuit in which a transistor made of an IGBT or the like and a diode are connected in parallel, and each diode is a transistor made of an IGBT or the like. The anode side is connected to the emitter side and the cathode side is connected to the collector side so that a current can flow from the emitter side to the collector side, and the third auxiliary switch Sr1 and the fourth auxiliary switch Sr2 are connected in series. By doing so, a bidirectional switch is formed.

  In the following description, when the third auxiliary switch Sr1 is turned on temporarily, the direction of the auxiliary reactor current Ir flowing through the auxiliary reactor Lr is different from that of the upper main switching transistor Q3 constituting the second bridge circuit. Direction from the connection point e2 with the collector of the main switching transistor Q4 on the side to the connection point e1 between the emitter of the upper main switching transistor Q1 and the collector of the lower main switching transistor Q2 constituting the first bridge circuit Shall be. On the other hand, when the fourth auxiliary switch Sr2 is turned on, the direction of the auxiliary reactor current Ir flowing through the auxiliary reactor Lr is reversed, and the emitter and the lower side of the upper main switching transistor Q1 constituting the first bridge circuit are reversed. From the connection point e1 with the collector of the main switching transistor Q2 toward the connection point e2 between the emitter of the upper main switching transistor Q3 and the collector of the lower main switching transistor Q4 constituting the second bridge circuit. Shall.

(Operation of Second Embodiment)
Next, an example of the operation of the DC / DC converter of this embodiment shown in FIG. 5 will be described based on the operation waveform shown in FIG. 6 and the current path shown in FIG. FIG. 6 is a waveform diagram for explaining an example of the operation of the DC / DC converter shown in FIG. 5, and includes main switching transistors Q1 to Q4, a first auxiliary switch Sc1, a second auxiliary switch Sc2, and a second auxiliary switch Sc2. The timing at which the three auxiliary switches Sr1 are turned on / off, and the voltages V _{e1 of} the main reactor current I _L , the auxiliary reactor current Ir, the connection point e1 of the main switching transistors Q1 and Q2, and the connection point e2 of the main switching transistors Q3 and Q4. , V _e2 , the differential current between the collector currents I _{Q1 to} I _Q4 of the main switching transistors Q1 to _Q4 and the currents I _{D1 to} I _D4 flowing through the commutation diodes D1 to _D4 , and the first auxiliary switch Sc1, the second The signal waveforms of the collector currents I _SC1 and I _SC2 of the auxiliary switch Sc2 are shown.

  FIG. 7 is a schematic diagram for explaining a current path of a current flowing in each operation state of the DC / DC converter shown in FIG. 5. A current path flowing in the DC / DC converter for each operation state is shown in FIG. It is shown by extracting from the circuit configuration of FIG.

  As shown in the on / off states of the main switching transistors Q1 and Q2 in FIG. 6, the main switching transistors Q1 and Q2 constituting the first bridge circuit are respectively set at a predetermined switching cycle Tcyc. With the duty {d1- (Td / Tcyc)} and the duty {(1-d1)-(Td / Tcyc)}, PWM control is performed so as to repeat the on / off alternately. Here, d1 means the original duty of the first bridge circuit, and Td is provided between both ON times so that the main switching transistors Q1 and Q2 constituting the first bridge circuit do not turn on at the same time. Means dead time. The original duty d1 and dead time Td of the first bridge circuit are controlled so that the output voltage Vo matches the target output voltage.

  Similarly, the main switching transistors Q3 and Q4 constituting the second bridge circuit also have a duty {d2- (Td / Tcyc)} and a duty {(1-d2), respectively, with a predetermined switching cycle Tcyc set in advance. -(Td / Tcyc)}, and PWM control is performed so as to repeat ON / OFF alternately. Here, d2 means the original duty of the second bridge circuit, and Td is provided between both ON times so that the main switching transistors Q1 and Q2 constituting the second bridge circuit do not turn on at the same time. Means dead time. The original duty d2 and dead time Td of the second bridge circuit are controlled so that the output voltage Vo matches the target output voltage.

  In the case of a power running operation in which power is supplied from the input power supply Vi on the input side to the output voltage Vo on the output side, the upper main switching transistor Q1 constituting the first bridge circuit and the second bridge circuit are constituted. When the lower main switching transistor Q4 is turned on and when the lower main switching transistor Q2 constituting the first bridge circuit and the upper main switching transistor Q3 constituting the second bridge circuit are turned off Are controlled to be synchronized with each other.

  On the other hand, in the case of the regenerative operation in which power is supplied from the output voltage Vo on the output side to the input power source Vi on the input side, the lower main switching transistor Q2 and the second bridge circuit constituting the first bridge circuit. And when the upper main switching transistor Q3 constituting the first bridge circuit and the lower main switching transistor Q4 constituting the second bridge circuit are turned off. It controls to synchronize each time to do.

  Further, during the power running operation, during the dead time Td before the upper main switching transistor Q1 constituting the first bridge circuit and the lower main switching transistor Q4 constituting the second bridge circuit are turned on, During the regenerative operation, during the dead time Td before the lower main switching transistor Q2 constituting the first bridge circuit and the upper main switching transistor Q3 constituting the second bridge circuit are turned on, The third auxiliary switch Sr1, which forms the third auxiliary circuit, and the fourth auxiliary so that the charges accumulated in the resonance capacitors Cr1 and Cr2 are charged and discharged by the resonance action in FIG. The switch Sr2 is controlled. As a result, the voltage across the main switching transistor on the side on which the switching operation is to be performed becomes 0 V, and the zero voltage switching operation can be performed.

The first auxiliary switch Sc1 and the second auxiliary switch Sc2 are turned on / off from the main reactor current IL flowing through the main reactor _L , the input voltage Vi, and the output voltage Vo in the DC / DC converter. Control is performed based on the result of estimating the generated switching loss.

  That is, the first auxiliary switch Sc1 is pulse-driven by the same switching cycle Tcyc as the main switching transistors Q1 and Q2 constituting the first bridge circuit, and is repeatedly turned on / off. Here, the first auxiliary switch Sc1 is turned on in a section in which the upper main switching transistor Q1 is on. Further, the first auxiliary switch Sc1 is turned off in a section during the dead time Td from when the upper main switching transistor Q1 is switched from on to off until the lower main switching transistor Q2 is turned on.

  Here, if the first resonance capacitor Cr1 and the first auxiliary switch Sc1 are connected in parallel to the lower main switching transistor Q2 constituting the first bridge circuit, the lower main switching transistor Q2 is connected. The time when the first auxiliary switch Sc1 connected in parallel to the switching transistor Q2 is turned on is within the period when the lower main switching transistor Q2 is on, and the first auxiliary switch Sc1 connected in parallel to the lower main switching transistor Q2 is turned on. The time point when the auxiliary switch Sc1 is turned off is within the period of the dead time Td provided immediately after the lower main switching transistor Q2 is turned on after the lower main switching transistor Q2 is turned off.

  In the example shown in FIG. 6, the time from when the upper main switching transistor Q1 is turned on to when the first auxiliary switch Sc1 is turned on is ΔTSc1_on, and after the upper main switching transistor Q1 is turned off, the first auxiliary switch is turned on. The time until the switch Sc1 is turned off is defined as ΔTSc1_off.

  Similarly, the second auxiliary switch Sc2 is pulse-driven by the same switching cycle Tcyc as the main switching transistors Q3 and Q4 constituting the second bridge circuit, and is repeatedly turned on / off. Here, the second auxiliary switch Sc2 is turned on in a section in which the upper main switching transistor Q3 is on. Further, the second auxiliary switch Sc2 is turned off in a section during the dead time Td from when the upper main switching transistor Q3 is switched from on to off until the lower main switching transistor Q4 is turned on.

  Here, if the second resonance capacitor Cr2 and the second auxiliary switch Sc2 are connected in parallel to the lower main switching transistor Q4 constituting the second bridge circuit, the lower main switching transistor Q4 is connected. The time when the second auxiliary switch Sc2 connected in parallel to the switching transistor Q4 is turned on is within the period in which the lower main switching transistor Q4 is on, and the second auxiliary switch Sc2 connected in parallel to the lower main switching transistor Q4. The time when the auxiliary switch Sc2 is turned off is within the period of the dead time Td provided immediately after the upper main switching transistor Q3 is turned on after the lower main switching transistor Q4 is turned off.

  In the example shown in FIG. 6, the time from when the upper main switching transistor Q3 is turned on to when the second auxiliary switch Sc2 is turned on is ΔTSc2_on, and after the upper main switching transistor Q3 is turned off, the second auxiliary switch is turned on. The time until the switch Sc2 is turned off is defined as ΔTSc2_off.

The third form a third auxiliary circuit, a fourth auxiliary switch Sr1, the Sr2 also be pulsed by the same switching cycle Tcyc and the main switching transistor Q1 to Q4, the main reactor current I _L and the input voltage The on / off period is determined from Vi and the output voltage Vo.

  In a powering operation for supplying power from the input side to the output side, the third auxiliary switch Sr1 has the lower main switching transistor Q2 after the upper main switching transistor Q1 constituting the first bridge circuit is turned off. Is turned on in the interval until the power is turned off, so that a sufficient auxiliary reactor current Ir can be supplied to resonate. The third auxiliary switch Sr1 is turned off in a section in which the upper main switching transistor Q1 is turned on after the auxiliary reactor current Ir becomes 0 A after the resonance operation.

  On the other hand, during the regenerative operation in which power is supplied from the output side to the input side, the fourth auxiliary switch Sr2 is configured so that the lower main switching is performed after the upper main switching transistor Q3 constituting the second bridge circuit is turned off. When the transistor Q4 is turned on during the period until it is turned off, the auxiliary reactor current Ir sufficient to resonate can flow. Then, after the auxiliary reactor current Ir becomes 0 A after the resonance operation, the auxiliary reactor current Ir is turned off in a section in which the upper main switching transistor Q3 is turned on.

  In the following, the case of the boosting power running operation in the DC / DC converter (full-bridge type step-up / step-down bidirectional converter circuit) of FIG. 5 will be further described with reference to the waveform diagram of FIG. 6 and the schematic diagram of FIG.

  First, first, the upper main switching transistor Q1 of the first bridge circuit and the upper main switching transistor Q3 of the second bridge circuit are turned on, and the first auxiliary switch Sc1 and the second auxiliary switch Sc2 are turned on. The main switching transistor Q1 on the upper side of the first bridge circuit in the current path shown in the state 1 in FIG. 7 when the third auxiliary switch Sr1 and the fourth auxiliary switch Sr2 are turned off. From the commutation diode D3 connected in parallel to the upper main switching transistor Q3 of the second bridge circuit to the load side via the main reactor L.

Next, at time t1 in FIG. 6, the upper main switching transistor Q1 of the first bridge circuit is turned off. Then, as shown in the state 2 of FIG. 7, a charging current flows from the positive electrode side of the input power source Vi through the first auxiliary switch Sc1 to the first resonance capacitor Cr1. The charging current at this time is equal to the current value of the reactor current I _L (time t1). When the main switching transistor Q1 of the upper is turned off, the collector current I _Q1 of the upper main switching transistor Q1, as shown in FIG. 6, but becomes rapidly 0A, the collector of the main switching transistor Q1 - emitter voltage V _Q1 is As shown in the change in the voltage V _e1 at the connection point e1 in FIG. 6, as the first resonant capacitor Cr1 is charged, the voltage slowly rises from 0V, so that the zero voltage switching operation is performed and the switching loss is greatly reduced. can do.

Thereafter, at the time t2 (= t1 + ΔTSc1_off) when the time ΔTSc1_off has elapsed, the first auxiliary switch Sc1 is turned off. At this time, the first resonance capacitor Cr1 is charged from the charging current up to that point, and is cut off from the main current path as shown in state 3 in FIG. through the commutating diodes D2 connected in parallel with the main switching transistor Q2 side becomes to flow reactor current I _L.

If the output current of the DC / DC converter is large and the time ΔTSc1_off from when the upper main switching transistor Q1 is turned off to when the first auxiliary switch Sc1 is turned off is the voltage across the first resonant capacitor Cr1 ( until it reaches the forward voltage) voltage above the input supply voltage Vi + commutating diode D2, if it is able was the time to charge the charge, before reaching the time t2, the main reactor current I _L, rolling It will commutate to the diversion diode D2. In such a case, the commutating diode D2 connected in parallel with the main switching transistor Q2 of the lower, first auxiliary switching transistor Q _SC1 of the first auxiliary switch Sc1 becomes zero voltage switching operation.

On the other hand, the first auxiliary switch Sc1 is turned off after the upper main switching transistor Q1 is turned off, as in the case of a light load where the output voltage Vo is close to the input power supply voltage Vi and the output current of the DC / DC converter is small. If the first resonant capacitor Cr1 cannot be sufficiently charged within the time ΔTSc1_off until the commutation, the commutation diode D2 and the first auxiliary switching transistor Q _SC1 of the first auxiliary switch Sc1 are used. Becomes a hard switching operation, and a switching loss occurs. However, the reverse voltage of the commutation diode D2 is lower than the input power supply voltage Vi by the voltage charged in the first resonance capacitor Cr1. For this reason, the switching loss generated in the commutation diode D2 and the first auxiliary switching transistor _QSC1 can be reduced as compared with the case where the main switching transistor Q1 is turned off by the hard switching operation.

Thereafter, the lower main switching transistor Q2 is turned on. At this time, since the first resonance capacitor Cr1 is disconnected from the main current path by the first auxiliary switch Sc1, unlike the prior art, the surge current for charging the first resonance capacitor Cr1 is The lower main switching transistor Q3 can be turned on without being generated, and the commutation diode D2 is connected in parallel to the lower main switching transistor Q3 through the current path shown in the state 3 of FIG. through, the reactor current _{I L} continues to flow.

Furthermore, at time t3, the third auxiliary switch Sr1 is turned on during the power running operation. Thereby, as shown in the state 4 of FIG. 7, the auxiliary reactor current Ir starts to flow through the auxiliary reactor Lr. The output voltage Vo is biased to the auxiliary reactor Lr, and the auxiliary reactor current Ir increases with time as shown in FIG. Note that the timing at time t3 is a control unit configured by a microcomputer or the like so that the main reactor current I _L and the converter input / output voltages Vi and Vo are detected by a sensor and the auxiliary reactor current Ir necessary for resonant switching can flow. (Not shown in FIG. 5) is determined.

Thereafter, as shown in FIG. 6, the auxiliary reactor current Ir is larger than the main reactor current I _L, as a result, in the state 4 in FIG. 7, the lower side of the main switching of the first bridge circuit are turned on A current flows through the transistor Q2 and the main switching transistor Q3 on the upper side of the second bridge circuit.

In this state, at time t4, the lower main switching transistor Q2 constituting the first bridge circuit and the upper main switching transistor Q3 constituting the second bridge circuit are turned off. Then, so far, the main switching transistor Q2, the main switching transistor Q3 to flow though current (= auxiliary reactor current Ir- main reactor current I _L) is commutated, as shown in the state 5 in FIG. 7, the second resonant capacitor Cr2, the second auxiliary switching transistor _{Q SC2} of the second auxiliary switch Sc2, and a first resonance capacitor Cr1, through the first auxiliary diode _{D SC1} of the first auxiliary switch Sc1, the input power It flows in the direction of regeneration to Vi. At this time, the first resonance capacitor Cr1, the second resonance capacitor Cr2, and the auxiliary reactor Lr are resonating.

  During the resonance of the first resonance capacitor Cr1, the second resonance capacitor Cr2 and the auxiliary reactor Lr, the charge charged between the time t1 and the time t2 is discharged from the first resonance capacitor Cr1, while the first resonance capacitor Cr1 The second resonance capacitor Cr2 is charged.

  Thereafter, the second auxiliary switch Sc2 is turned off at time t5 (= t4 + ΔTSc2_off) during the dead time Td before the lower main switching transistor Q4 constituting the second bridge circuit is turned on. At this point, assuming that the second resonant capacitor Cr2 has been fully charged up to the output voltage Vo, current flows through the commutation diode D4 as shown in state 6 of FIG. The resonance operation of the second resonance capacitor Cr2 and the auxiliary reactor Lr is completed.

Also, if the complete discharge of the first resonant capacitor Cr1 is completed during the dead time Td before the main switching transistor Q1 constituting the first bridge circuit is turned on, as shown in the state 6 in FIG. Then, current flows through the commutation diode D1, and the resonance operation of the first resonance capacitor Cr1 and the auxiliary reactor Lr is completed. Therefore, at the timing of time t5, the collector-emitter voltage V _{Q1 of} the main switching transistor _Q1 and the collector-emitter voltage V _Q4 of the main switching transistor Q4 both decrease to near 0V.

  Thereafter, at the timing of time t6, while the current continues to flow through the commutation diode D1 and the commutation diode D4, as shown in the state 7 of FIG. 7, the upper side of the first bridge circuit is configured. The main switching transistor Q1 and the lower main switching transistor Q4 constituting the second bridge circuit are turned on. That is, as the switching operation to turn on the upper main switching transistor Q1 and the lower main switching transistor Q4, a zero voltage switching operation and a zero current switching operation can be performed.

Note that if the charging of the second resonance capacitor Cr2 is not completed at the time t5 when the second auxiliary switch Sc2 is turned off, the voltage across the second resonance capacitor Cr2 is lower than the output voltage Vo. With the voltage Vcr2 (time t5), the second resonant capacitor Cr2 is disconnected from the main current circuit, and then a current flows through the commutation diode D4. As a result, the second auxiliary switching transistor _QSC2 and the commutation diode D4 perform a hard switching operation, and a switching loss occurs. However, even in this case, the charging voltage of the second resonance capacitor Cr2, since the voltage across the inter-switching element according to the second auxiliary switching transistor Q _SC2 and commutating diode D4 is suppressed, the second auxiliary switching transistor The switching loss that occurs in _QSC2 and commutation diode D4 can be kept lower than when the main switching transistor Q3 is hard-switched.

Thereafter, the auxiliary reactor current Ir flowing through the auxiliary reactor Lr is biased in the reverse direction by the voltage of the input power supply voltage Vi, and therefore gradually decreases as shown in FIG. After time t7, when the auxiliary reactor current Ir flowing through the auxiliary reactor Lr is smaller than the main reactor current IL flowing through the main reactor _L , commutation occurs, and as shown in the state 8 of FIG. Flows from the upper main switching transistor Q1 constituting the bridge circuit via the main reactor L through the lower main switching transistor Q4 constituting the second bridge circuit.

Thereafter, at time t8, when the auxiliary reactor current Ir becomes 0A once, the reverse current flowing in the main current path is blocked by the third auxiliary switch Sr1 which is a one-way switch, and the auxiliary reactor current Ir is Thereafter, 0A is maintained, and as shown in the state 8 of FIG. 7, the series circuit composed of the auxiliary reactor Lr, the third auxiliary switch Sr1, and the fourth auxiliary switch Sr2 is the main auxiliary circuit. Completely disconnected from the current path. As a result, the current flowing through the main switching transistor Q4 of the lower constituting the main switching transistor Q1 and the second bridge circuit The upper, equal to the main reactor current I _L flowing through the main reactor. Note that, after time t8, by turning off the third auxiliary switch Sr1 between the time when the upper main switching transistor Q1 constituting the first bridge circuit is turned off, the zero current switching operation can be performed.

Next, at time t9, the lower main switching transistor Q4 constituting the second bridge circuit is turned off. Then, the main reactor current I _L, as shown in the state 9 of FIG. 7, through a second resonant capacitor Cr2 and the second auxiliary diode D _SC2, flows to the converter output terminal side. As a result, the electric charge charged in the second resonance capacitor Cr2 is discharged.

When the charge of the second resonant capacitor Cr2 is fully discharged, the main reactor current I _L will flow through the commutating diode D3 constituting the second bridge circuit. As a result, when the upper main switching transistor Q3 constituting the second bridge circuit is turned on at time t10, a zero voltage switching operation is performed.

If the converter output current is small, there is a concern that the charge of the second resonance capacitor Cr2 cannot be completely discharged. However, if the time t5 when the charging of the second resonance capacitor Cr2 is completed, that is, the time t5 when the second auxiliary switch Sc2 is turned off is controlled in advance, the residual charge amount Q of the second resonance capacitor Cr2 is controlled. _cr2 {= (capacity of Cr2) × (voltage across Cr2 Vcr2 (t5))} can be adjusted.

Specifically, the main reactor current I _L and the converter output voltage Vi, and Vo is detected by the sensor, the control unit constituted by a microcomputer by (not shown in FIG. 5), the residual of the resonant capacitor Cr2 After the upper main switching transistor Q3 constituting the second bridge circuit is turned off, the second main switching transistor Q3 is turned off so that the charge amount Q _cr2 can be switched to zero voltage switching operation of the upper main switching transistor Q3 at time t10. A time ΔTSc2_off until the auxiliary switch Sc2 is turned off is obtained, and the second auxiliary switch Sc2 may be turned off at the timing of time t5 (= t4 + ΔTSc2_off).

  Thereafter, the second auxiliary switch Sc2 is turned on after a time ΔTSc2_on from when the upper main switching transistor Q3 is turned on at the time t10 to when the second auxiliary switch Sc2 is turned on has elapsed. At this time, since the second resonant capacitor Cr2 is completely discharged, the second auxiliary switch Sc2 performs a zero current / zero voltage switching operation.

  Thereafter, the state returns to the state 1 in FIG. 7, and the above-described operation is repeated again.

  Next, the effect, that is, the operating range of the DC / DC converter shown in FIG. 5 will be described with reference to FIG.

  FIG. 8 is a characteristic diagram in which the operating range of the output voltage Vo and the output current Io of the DC / DC converter of this embodiment shown in FIG. 5 is obtained. For comparison, the characteristic diagram of FIG. 8 also includes the operation range of a conventional DC / DC converter in the case where a bidirectional buck-boost chopper circuit is configured based on the same concept as in Patent Document 1.

  In the case of a conventional DC / DC converter, the characteristics of the first and second resonance capacitors Cr1, Cr2 and the auxiliary reactor L are set so that the characteristics of the bidirectional buck-boost chopper circuit are optimized on the high load side where the output current Io is large. The case where a value is selected is shown. Therefore, conversely, at the time of light load, as shown in FIG. 8, there is a region where the operation cannot be performed due to the surge current and the increase of the switching loss due to the failure of the soft switching operation.

  On the other hand, in the case of the DC / DC converter of the present embodiment, as shown in FIG. 8, the DC / DC converter is operated in a wide operating voltage range over almost the entire region from a light load to a high load. The switching loss can be reduced without generating a surge current.

  As described in detail above, according to this embodiment to which the DC / DC converter according to the present invention is applied, the first auxiliary capacitor Sc1 and the second auxiliary switch Sc2 are used to generate the first resonance capacitor Cr1 and the second resonance capacitor Cr1. Since the resonant capacitor Cr2 can be cut off from the main current path, even if the complete soft switching condition is not satisfied depending on the load state, the first resonant capacitor Cr1 and the second resonant capacitor Cr2 are short-circuited. Surge current can be suppressed, switching loss can be reduced, and the operating range of the DC / DC converter can be expanded.

  In the above description of the present embodiment, the operation during the boosting power running operation has been described. However, even in the operation during the descending pressure running operation, only the values of the duties d1 and d2 are different, and the operations are exactly the same. Can be operated.

  Also in the case of the step-up regeneration operation and the step-down regeneration operation, in the above description, the upper main switching transistor Q1 constituting the first bridge circuit, the upper main switching transistor Q3 constituting the second bridge circuit, and the second Lower main switching transistor Q2 constituting one bridge circuit and lower main switching transistor Q4 constituting second bridge circuit, commutation diode D1 and commutation diode D3, commutation diode D2 and commutation diode D4 If the first auxiliary switch Sc1 and the second auxiliary switch Sc2, and the third auxiliary switch Sr1 and the fourth auxiliary switch Sr2 are read, the operation is exactly the same as in the power running operation. .

  In the present embodiment, the first auxiliary circuit in which the first resonance capacitor Cr1 and the first auxiliary switch Sc1 are connected in series, and the second resonance capacitor Cr2 and the second auxiliary switch Sc2 are connected in series. The example in which the second auxiliary circuit is connected in parallel with the upper main switching transistor Q1 constituting the first bridge circuit and the upper main switching transistor Q3 constituting the second bridge circuit has been described. The present invention is not limited to such a case. For example, such an auxiliary circuit, that is, a resonant capacitor and an auxiliary switch connected in series to the lower main switching transistor Q2 constituting the first bridge circuit and the lower side constituting the second bridge circuit. It may be connected in parallel with the main switching transistor Q4, or may be connected in parallel with all of the main switching transistors Q1 to Q4, and is essentially the same as in the above-described embodiment, It is obvious that the configuration is included as a specific configuration range of the DC / DC converter according to the present invention.

It is a circuit diagram which shows the circuit structure of 1st embodiment of the DC / DC converter by this invention. It is a wave form diagram for demonstrating an example of operation | movement of the DC / DC converter shown in FIG. It is a schematic diagram for demonstrating the current pathway of the electric current which flows in each operation state of the DC / DC converter shown in FIG. It is the characteristic view which calculated | required the operating range of the output voltage and output current of the DC / DC converter shown in FIG. It is a circuit diagram which shows the circuit structure of 2nd embodiment of the DC / DC converter by this invention. FIG. 6 is a waveform diagram for explaining an example of the operation of the DC / DC converter shown in FIG. 5. FIG. 6 is a schematic diagram for explaining a current path of a current flowing in each operation state of the DC / DC converter shown in FIG. 5. It is the characteristic view which calculated | required the operating range of the output voltage and output current of the DC / DC converter shown in FIG.

Explanation of symbols

Co ... smoothing capacitor, Cr1 ... first resonance capacitor, Cr2 ... second resonant capacitor, CU ... resonant capacitor, D1, D2, D3, D4 ... commutating diodes, D _{SC ...} auxiliary diode, _{D SC1 ...} first auxiliary diode, _{D SC2 ...} second auxiliary diode, DU, DL ... commutating diodes, I L _... main reactor current, Ir ... auxiliary reactor current, L ... main reactor, Lr ... auxiliary reactor, Q1, Q2, Q3, Q4 ... main switching transistor, _QSC ... auxiliary switching transistor, _QSC1 ... first auxiliary switching transistor, _QSC2 ... second auxiliary switching transistor, Sc ... first auxiliary switch, Sc1 ... first auxiliary switch, Sc2 ... Second auxiliary switch, Sr ... second auxiliary switch, Sr1 ... third auxiliary switch Auxiliary switch, Sr2 ... fourth auxiliary switch, SU, SL ... main switching transistor, Vi ... input power supply, Vo ... output voltage.

Claims (13)

  A DC / DC converter that outputs a DC input voltage as power of a predetermined output voltage to an external load, and is an upper main circuit that constitutes a bridge circuit that is connected in series and alternately turned on / off in order to control power A commutation diode is connected in parallel to each of the switching transistor and the lower main switching transistor, and one end of a smoothing main reactor is connected to the upper main switching transistor and the lower main switching transistor. In the DC / DC converter that connects the other end of the main reactor to an output terminal and outputs an output voltage from the output terminal to the outside, the upper main switching transistor and / or the lower main switching A transistor with a resonance capacitor and a first auxiliary switch connected in series. And a second auxiliary circuit in which a resonance auxiliary reactor and a second auxiliary switch are connected in series are connected in parallel to the main reactor. .   2. The DC / DC converter according to claim 1, wherein the first auxiliary switch includes an auxiliary switching transistor and an auxiliary diode capable of flowing a current in a direction opposite to a direction of the current flowing through the auxiliary switching transistor. 3. A DC / DC converter characterized by comprising a parallel connection configuration.   3. The DC / DC converter according to claim 1, wherein switching periods of the upper main switching transistor, the lower main switching transistor, the first auxiliary switch, and the second auxiliary switch are the same. DC / DC, wherein the upper main switching transistor and the lower main switching transistor are provided with a dead time immediately before being turned on so that they are not turned on at the same time. converter.   4. The DC / DC converter according to claim 3, wherein the first auxiliary switch is turned on / off from a main reactor current, an input voltage, and an output voltage flowing through the main reactor in the DC / DC converter. A DC / DC converter characterized by being controlled based on a result of estimating a generated switching loss.   5. The DC / DC converter according to claim 4, wherein the time point when the first auxiliary switch connected in parallel to the upper main switching transistor is turned on is within a period during which the upper main switching transistor is turned on, The time point when the first auxiliary switch connected in parallel to the upper main switching transistor is turned off is provided immediately before the lower main switching transistor is turned on after the upper main switching transistor is turned off. Within the dead time period and / or when the first auxiliary switch connected in parallel to the lower main switching transistor is turned on is within the period during which the lower main switching transistor is on. The first main switching transistor connected in parallel to the first The time point at which the auxiliary switch is turned off is within a dead time period provided immediately after the lower main switching transistor is turned on after the lower main switching transistor is turned off. / DC converter.   6. The DC / DC converter according to claim 3, wherein when the second switch is turned on, the lower main switching transistor is turned off after the upper main switching transistor is turned off. The time point when the second switch is turned off is within the period in which the upper main switching transistor is on after the auxiliary reactor current flowing through the auxiliary reactor becomes zero. Characteristic DC / DC converter.   A bi-directional DC / DC converter that converts power between a DC input voltage at an input terminal and an output voltage at an output terminal and outputs the converted voltage from one of the input / output terminals to the outside, and controls the power Therefore, two sets of an upper main switching transistor and a lower main switching transistor constituting each of the first bridge circuit on the input side and the second bridge circuit on the output side that are connected in series and alternately turned on / off are provided, A commutation diode is connected in parallel with each other, and one end of a smoothing main reactor is connected to a connection point between the upper main switching transistor and the lower main switching transistor constituting the first bridge circuit. And the other end of the main reactor is connected to the upper main switching transistor constituting the second bridge circuit and the lower main switch. In the DC / DC converter connected to the connection point with the switching transistor, a first resonance capacitor is connected to the upper main switching transistor and / or the lower main switching transistor constituting the first bridge circuit. A first auxiliary circuit connected in series with a first auxiliary switch is connected in parallel, and the upper main switching transistor and / or the lower main switching transistor constituting the second bridge circuit, A second auxiliary circuit in which a second resonance capacitor and a second auxiliary switch are connected in series is connected in parallel, and the main reactor is connected to a resonance auxiliary reactor, a third auxiliary switch, and a fourth auxiliary switch. A DC / DC converter comprising a third auxiliary circuit connected in series with an auxiliary switch connected in parallel .   8. The DC / DC converter according to claim 7, wherein the first auxiliary switch and the second auxiliary switch pass a current in a direction opposite to a direction of current flowing through the auxiliary switching transistor and the auxiliary switching transistor. A DC / DC converter characterized by comprising a configuration in which auxiliary diodes that can be connected are connected in parallel.   The DC / DC converter according to claim 7 or 8, wherein the upper main switching transistor and the lower main switching transistor constituting the first bridge circuit, and the upper main switching transistor constituting the second bridge circuit. The switching periods of the main switching transistor and the lower main switching transistor, the first auxiliary switch, the second auxiliary switch, the third auxiliary switch, and the fourth auxiliary switch are the same, In addition, the upper main switching transistor and the lower main switching transistor constituting the first bridge circuit are not simultaneously turned on, and the upper main switching transistor constituting the second bridge circuit is not turned on at the same time. A switching transistor and the lower main switching transistor Star A, so as not to turn on, DC / DC converter, characterized in that it dead time is provided immediately before each turned on at the same time.   10. The DC / DC converter according to claim 9, wherein a period during which the first auxiliary switch and the second auxiliary switch are turned on / off is determined from a main reactor current flowing through the main reactor, an input voltage, and an output voltage. A DC / DC converter controlled based on a result of estimating a switching loss occurring in the DC / DC converter.   11. The DC / DC converter according to claim 10, wherein the first auxiliary switch and the second auxiliary switch connected in parallel to the upper main switching transistor respectively constituting the first bridge circuit and the second bridge circuit. Is turned on within the period when the upper main switching transistors constituting the first bridge circuit and the second bridge circuit, respectively, are turned on, and the first bridge circuit and the second bridge circuit are turned on. When the first auxiliary switch and the second auxiliary switch connected in parallel to the upper main switching transistors constituting the second bridge circuit are turned off, respectively, the first bridge circuit and the second The upper main switching transistors constituting the two bridge circuits, respectively. Within a dead time period that is provided immediately after the lower main switching transistor that turns on each of the first bridge circuit and the second bridge circuit is turned on after the transistor is turned off, and / Or when turning on the first auxiliary switch and the second switch connected in parallel to the lower main switching transistor constituting the first bridge circuit and the second bridge circuit, respectively, The lower main switching transistors constituting the first bridge circuit and the second bridge circuit, respectively, are within the ON period, and the first bridge circuit and the second bridge circuit are respectively constituted. The first auxiliary switch connected in parallel to the lower main switching transistor. H and when the second switch is turned off, after the lower main switching transistors constituting the first bridge circuit and the second bridge circuit are turned off from on, respectively, A DC / DC converter characterized by being within a dead time period provided immediately before the upper main switching transistor constituting each of the bridge circuit and the second bridge circuit is turned on.   12. The DC / DC converter according to claim 9, wherein the time point at which the third auxiliary switch is turned on is during a power running operation and the upper side of the first bridge circuit is configured. It is within a period from when the main switching transistor is turned off to when the lower main switching transistor constituting the first bridge circuit is turned off, and the time point when the third auxiliary switch is turned off is during a power running operation. And after the auxiliary reactor current flowing through the auxiliary reactor becomes zero, it is within a period in which the upper main switching transistor constituting the second bridge circuit is on. DC / DC converter.   13. The DC / DC converter according to claim 9, wherein a time point at which the fourth auxiliary switch is turned on is a regenerative operation and the upper bridge constituting the second bridge circuit. It is within a period from when the main switching transistor is turned off to when the lower main switching transistor constituting the second bridge circuit is turned off, and the time when the fourth auxiliary switch is turned off is during the regenerative operation. And after the auxiliary reactor current flowing through the auxiliary reactor becomes zero, it is within a period in which the upper main switching transistor constituting the first bridge circuit is on. DC / DC converter.

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