JP2009110467A - Apparatus, system, program, and method for controlling memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that it takes time for suspend and resume operation. <P>SOLUTION: During suspension, updated data in a unit storage are stored in a second storage apparatus, and a check code for the updated data in the unit storage is generated. When an access to a first storage is detected, a check code for the data in the inactive unit storage is generated to be compared with the check code generated during the suspend. When they do not match each other, the data for the unit storage stored in the second storage apparatus are read and written to the unit storage. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory control device, system, program, and method, and more particularly, to a memory control device, system, program, and method having a resume function.

  In a computer with a resume function that restores the state immediately before power is turned off when the power is turned on, if the power supply to the memory that is being turned off is unstable, the memory contents are changed when the power is turned on (resume). There was a problem that there was something.

  To solve this problem, there is a related technique that provides a means for checking a change in memory contents when power is turned on (resume) to prevent malfunction (for example, Patent Document 1).

  Similarly, as another technique related to this problem, information stored in the memory is saved in the auxiliary storage means when the power is turned off (suspended), and information to be restored is transferred to the memory when the power is turned on (resume). There is a thing (for example, patent document 2). Another similar and related technique is to save information stored in the memory in the auxiliary storage means except for the free area and the discardable area (for example, Patent Document 3).

  As another related technique, there is a technique in which a memory circuit check is executed in units of pages when the system is started (for example, Patent Document 4).

JP 05-088795 A JP-A-10-289167 Japanese Patent Laid-Open No. 10-333997 JP 2000-293391 A

  However, the technique of Patent Document 1 has a problem that it takes time for the resume operation because the memory contents are checked at once for the entire memory.

  Further, the technique of Patent Document 2 has a problem that both a suspend operation and a resume operation take time because a large amount of information is stored in the auxiliary storage unit and restored from the auxiliary storage unit. Although the technique of Patent Document 3 is slightly improved compared to Patent Document 2, the problem that it takes time for both the suspend operation and the resume operation has not been sufficiently solved.

  An object of the present invention is to provide a memory control device, system, program, and method that solve the above-described problems.

The memory control device according to the present invention is a memory control device that controls a first storage device including a plurality of unit storage units and a second storage device, and the unit storage unit in the unit storage unit that is in a changed state at the time of suspension is provided. When data is stored in the second storage device, a check code of the data in the unit storage unit in a changed state is generated, and access to the first storage device is detected, the non-valid state The unit memory stored in the second storage device when the check code of the data in the unit storage unit is generated, the check code is compared with the check code generated at the time of suspend, and they do not match Means for reading the data in the unit and writing it in the unit storage unit.

  The program of the present invention is a program for controlling a first storage device and a second storage device comprising a plurality of unit storage units, and the data in the unit storage unit that is in a changed state at the time of suspension is stored in the first storage device. 2 is stored in the storage device of the second unit, the check code of the data in the unit storage unit in the changed state is generated, and when access to the first storage device is detected, in the unit storage unit not in the valid state The check code of the data is generated, the check code is compared with the check code generated at the time of suspension, and the data in the unit storage unit stored in the second storage device when they do not match Is executed by the computer.

  The method of the present invention is a method in which a computer controls a first storage device and a second storage device comprising a plurality of unit storage units, wherein the data in the unit storage unit that is in a changed state at the time of suspension Is stored in the second storage device, the check code of the data in the unit storage unit in the changed state is generated, and when the access to the first storage device is detected, the unit that is not in the valid state Generate the check code of the data in the storage unit, compare the check code with the check code generated at the time of suspend, and in the unit storage unit stored in the second storage device if they do not match Are read out and written into the unit storage unit.

  According to the present invention, it is possible to speed up the suspend operation and the resume operation.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  Note that the suspend indicates an operation of saving the state of the immediately preceding operation in the information processing apparatus and turning off the power when the use of the information processing apparatus such as a computer is interrupted. The state of the information processing apparatus thus turned off is called a suspended state. Resume indicates an operation of resuming work from a state immediately before the power is turned off when the information processing apparatus in the suspended state is turned on. In this embodiment, a configuration and operation for realizing suspend / resume for a memory according to the present invention are described.

  Note that each unit described in the following embodiments may be realized by hardware, software, or a mixture of hardware and software.

  Further, the physical configuration of each means is not limited to the description of the following embodiment, and may exist independently, may exist in combination, or may be separated. May be configured.

  In addition, each operation is not limited to the description of the following embodiment, and can be changed within a range that does not hinder the functional, performance, and other characteristics in carrying out the present invention. good.

Referring to FIG. 1, an example of the first embodiment of the present invention includes a first storage device 300 (for example, a memory and a hard disk) including a plurality of unit storage units 301 (for example, pages and segments), 2 storage devices 500 (for example, a memory and a hard disk) and a memory control device 600.
The memory control device 600 does not store the data in the unit storage unit 301 that is not changed in the second storage device 500 during suspension. The memory control device 600 stores the data in the unit storage unit 301 in the changed state in the second storage device 500 at the time of suspension. At the time of suspension, the memory control device 600 generates a check code corresponding to the data in the unit storage unit 301 in the changed state. Note that the memory control device 600 may be configured to store the data in the unit storage unit 301 that is not changed in the second storage device 500 when suspended.

  If there is a write instruction or read instruction to the first storage device 300 (the write instruction or read instruction is an example of access), the memory control device 600 detects this. If the unit storage unit 301 that has been instructed to write or read is not in the valid state, the memory control device 600 generates a check code corresponding to the data in the unit storage unit 301. Then, the memory control device 600 generates a check code corresponding to the generated data in the unit storage unit 301 not in the valid state, and a check code corresponding to the data in the unit storage unit 301 in the changed state generated at the time of suspension. Compare If these check codes do not match, the memory control device 600 reads data corresponding to the unit storage unit 301 that is stored in the second storage device 500 and that has been instructed to be written or read. Then, the memory control device 600 writes the read data in the unit storage unit 301.

  Further details will be described using another example of the first embodiment of the present invention.

  Referring to FIG. 2, another example of the first embodiment of the present invention includes a processor 1, a memory 3, a battery 4, auxiliary storage means 5, and a memory control device 6. The memory 3 is an example of the first storage device 300. The auxiliary storage unit 5 is an example of the second storage device 500. The processor 1 accesses the memory 3 via the memory control device 6.

  The battery 4 backs up the power supply of the memory 3.

The auxiliary storage unit 5 stores data in the memory 3.
The memory control device 6 includes a change state information holding unit 61, a check code holding unit 62, a valid state information holding unit 63, a change state information setting unit 64, a suspend processing unit 65, and a valid state information control unit 66. It is composed of

  The memory control device 6 controls the memory 3 by dividing it into pages of a predetermined size. FIG. 3 is a diagram showing the concept of a page 31 (hereinafter simply referred to as a page 31) of the memory 3. The page 31 is an example of the unit storage unit 301. The memory control device 6 controls the change state information 611, the check code 621, and the valid state information 631 for each page 31.

  FIG. 4 shows an example of the structure of the change state information holding unit 61, the check code holding unit 62, and the valid state information holding unit 63. In the example of FIG. 4, the change state information holding unit 61, the check code holding unit 62, and the valid state information holding unit 63 are realized in one table format.

  The change state information holding unit 61 holds change state information 611 for each page 31. In the present embodiment, as an example, in the change state information 611, “1” indicates that there is a change, and “0” indicates that there is no change. For example, “0” is set as the initial value of the change state information 611 after the initialization process of the memory control device 6.

  The check code holding unit 62 holds a check code 621 for each page 31. In the present embodiment, as an example, it is assumed that the check code 621 is a 32-bit checksum code. Note that the check code 621 in FIG. 4 represents a 32-bit binary number in hexadecimal.

  The check code 621 is not limited to the checksum code, and a cyclic redundancy check code value or a hash value may be used. Further, the check code 621 may have a redundancy that enables error correction.

  The valid state information holding unit 63 holds valid state information 631 for each page 31. In this embodiment, as an example, the valid state information 631 indicates that “1” indicates validity and “0” indicates invalidity. For example, “1” is set as the initial value of the valid state information 631 after the initialization process of the memory control device 6.

  When the memory control device 6 detects a write instruction from the processor 1 to the memory 3, the change state information setting unit 64 sets the change state information 611 of the corresponding page 31 to “1” with change.

  When the memory control device 6 detects a suspend processing instruction from the processor 1, the suspend processing unit 65 refers to the change state information 611 of each page 31 and auxiliary stores the data of the page 31 with “1” being changed. Write to means 5. Then, the suspend processing unit 65 generates a check code 621 for the data of the page 31. Next, the suspend processing unit 65 writes the generated check code 621 in the check code holding unit 62. Then, the suspend processing unit 65 sets the valid state information 631 of all pages 31 to invalid.

  When the memory control device 6 detects a write instruction or a read instruction from the processor 1 to the memory 3, the valid state information control unit 66 refers to the valid state information holding unit 63 and refers to the valid state information of the corresponding page 31. Check 631. Then, the valid state information control unit 66 generates a check code 621 for the data of the corresponding page 31 when the valid state information 631 is invalid “0”. Then, the valid state information control unit 66 compares the generated check code 621 with the check code 621 of the corresponding page 31 stored in the check code holding unit 62. The valid state information control unit 66 reads data corresponding to the corresponding page 31 from the auxiliary storage unit 5 when the check codes 621 do not match. Then, the valid state information control unit 66 writes the read data on the corresponding page 31. Then, the valid state information control unit 66 sets the valid state information 631 of the corresponding page 31 to valid “1”. In addition, when these check codes 621 match, the valid state information control unit 66 does not perform the recovery process of the corresponding page 31 from the auxiliary storage unit 5 and stores the valid state information 631 of the corresponding page 31. Set to valid "1".

  Next, the operation of the embodiment of the present invention will be described with reference to the drawings.

  FIG. 5 shows the operation of the suspend processing means 65 of the memory control device 6.

  The memory control device 6 detects a suspend process instruction from the processor 1 (step S800).

  The suspend processing unit 65 performs steps S802 to S806 for all pages 31 (step S801).

  First, the suspend processing unit 65 checks the change state information 611 (step S802).

  If the change state information 611 is “0” (NO in step S802), the suspend processing unit 65 sets the valid state information 631 to “0” (step S806), and proceeds to the processing of the next page 31.

  If the change state information 611 is “1” (in the case of YES in step S802), the suspend processing unit 65 writes the data of the corresponding page 31 to the auxiliary storage unit 5 (step S803). Then, the suspend processing unit 65 calculates a check code for the data of the corresponding page 31. Then, the suspend processing unit 65 writes the calculated check code as the check code 621 in the check code holding unit 62 (step S804). Next, the suspend processing unit 65 sets the change state information 611 to “0” (step S805). Next, the suspend processing unit 65 sets the valid state information 631 to “0” (step S806), and proceeds to the processing of the next page 31.

  When the above processing is completed for all the pages 31, the data of all the pages 31 and the data corresponding to each page 31 stored in the auxiliary storage unit 5 are in a consistent state. That is, the change state information 611 of all pages 31 is in a “0” state.

  After this processing, generally, the processor 1 performs power supply suspend processing in order to put the entire configuration of the first embodiment of the present invention into a hardware suspend state based on a suspend processing program (not shown). Proceed to However, the subsequent processing does not have a direct technical relationship with the present invention, and thus the description thereof is omitted.

  FIG. 6 shows the operation during resume.

  The power is turned on by means not shown, and the resume process is started (step S810).

  The processor 1 checks the normality of the memory control device 6 by the resume processing means 11 (step S811). If there is no problem with the memory control device 6 (YES in step S812), the resume processing unit 11 proceeds to resume, that is, resume the operation before suspending.

  If there is a problem with the memory control device 6 (NO in step S812), the resume processing unit 11 gives up the resume and passes control to an initialization boot process (not shown).

  FIG. 7 shows operations of the change state information setting unit 64 and the valid state information control unit 66 when the memory control device 6 detects a write instruction or a read instruction from the processor 1 to the memory 3.

  The memory control device 6 detects a write instruction or a read instruction from the processor 1 to the memory 3 (step S820).

  First, the valid state information control unit 66 checks the valid state information 631 of the page 31 that has been instructed to write or read (step S821). If the valid state information 631 is “1” (YES in step S821), the valid state information control unit 66 proceeds to step S826. If the valid state information 631 is “0” (NO in step S821), the valid state information control unit 66 proceeds to step S822.

  Then, the valid state information control unit 66 calculates a check code for the data of the corresponding page 31 (step S822).

  Next, the valid state information control unit 66 checks whether or not the generated check code matches the check code 621 stored in the check code holding unit 62 (step S823). The coincidence of these check codes indicates that the data of the corresponding page 31 has not changed and can be used as it is. Also, the fact that these check codes do not match indicates that the data of the corresponding page 31 has changed and should not be used as it is. If these check codes match (YES in S823), the valid state information control unit 66 proceeds to step S825. If these check codes do not match (NO in S823), the valid state information control unit 66 proceeds to step S824.

  Then, the valid state information control unit 66 reads data corresponding to the corresponding page 31 from the auxiliary storage unit 5. Then, the valid state information control unit 66 writes the read data on the corresponding page 31.

  Then, the valid state information control unit 66 sets the valid state information 631 of the corresponding page 31 to “1” (step S825).

  Next, the change state information setting unit 64 checks whether or not the instruction from the processor 1 is a write instruction (step S826). If the instruction from the processor 1 is a write instruction (YES in step S826), the change state information setting unit 64 proceeds to step S827. If the instruction from the processor 1 is not a write instruction (NO in step S826), the change state information setting unit 64 proceeds to the instructed read process.

  Then, the change state information setting unit 64 sets the change state information 611 of the corresponding page 31 to “1” (step S827), and proceeds to the instructed write process.

  Note that by using error detection and correction as the check code 621, if NO in step S823, the error correction of the data of the corresponding page 31 may be executed, and if the correction cannot be completed, the process may proceed to step S824.

  According to the memory control device of the first embodiment of the present invention, at the time of suspension, writing to the auxiliary storage means is performed on a page basis based on the change state information. Then, the validity of the data is checked based on the valid state information and the check code for each page at the time of writing or reading. With this configuration, there is an effect that the speed of the suspend process and the resume process can be increased.

Furthermore, according to the memory control apparatus of the first embodiment of the present invention, data corresponding to each page is read from the auxiliary storage means. With this configuration, when the data of a certain page has changed, or when the check code does not match, the resume operation can be performed by restoring the data of the corresponding page. This has the effect of eliminating the need for an integrated boot.

  Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

  Referring to FIG. 8, the second embodiment of the present invention includes a processor 1, a memory 3, a battery 4, auxiliary storage means 5, and a memory control device 8. The memory control device 8 includes an address conversion unit 2 and a memory management unit 7.

  FIG. 9 is a diagram showing a concept of a real page 33 (hereinafter simply referred to as a real page 33) in the memory 3. The real page 33 is equivalent to the page 31 of the first embodiment in physical / electrical aspects. FIG. 10 is a diagram showing the concept of a virtual page 53 (hereinafter simply referred to as a virtual page 53) of the virtual memory 50 stored in the auxiliary storage means 5. The virtual page 53 is equivalent to the page 31 of the first embodiment in a logical aspect viewed from the processor 1.

  The address conversion unit 2 and the memory management unit 7 cooperate to constitute a memory control device 8 that implements a virtual memory.

  The address conversion unit 2 refers to an address conversion table 71, which will be described later, and converts a virtual address (virtual page number 710) to a real address (real page number 720).

  The memory management unit 7 refers to an address conversion table 71 to be described later, and realizes a virtual memory that is larger than the capacity of the memory 3. Specifically, when the memory 3 becomes less empty, the memory management unit 7 creates the free real page 33 by writing the data of the real page 33 allocated to the virtual page 53 that is unnecessary for the time being to the auxiliary storage unit 5. In addition, the memory management unit 7 reads data corresponding to the virtual page 53 that is necessary for the operation from the auxiliary storage unit 5 and rearranges it in the memory 3.

  Since the technology relating to the address translation table and the virtual memory using the address translation means is well known to those skilled in the art, a detailed description thereof will be omitted in this specification. The above-mentioned technique is described in, for example, Kenichiro Noguchi, “IT Text Operating System”, Chapter 10 (Publisher: Ohmsha, ISBN 4-274-13250-1, issued on September 5, 2002). So you can refer.

  When the address conversion unit 2 detects a write instruction or a read instruction from the processor 1 to the memory 3, the address conversion unit 2 refers to an address conversion table 71 to be described later and refers to a virtual address (virtual page number 710) and a real address (real page number 720). ). When the memory 3 has not been assigned to the virtual address, that is, when the real page number 720 corresponding to the virtual page number 710 is not registered in the address conversion table 71 (for example, the real page number) When the part 720 is “00”, it is determined that it is not registered.) Fails in address translation and generates an address translation exception. When the address conversion unit 2 detects a write instruction or a read instruction from the processor 1 to the memory 3, the address conversion unit 2 refers to an address conversion table 71 described later and checks the valid bit 711 of the corresponding virtual page 53. Then, the address conversion unit 2 generates an address conversion exception when the valid bit 711 is invalid “0”. When an address translation exception occurs, control passes from the address translation unit 2 to the memory management unit 7.

  When the address conversion unit 2 detects a write instruction from the processor 1 to the memory 3, the address conversion unit 2 sets the change bit 712 to “1”.

  The memory management unit 7 includes an address conversion table 71, a checksum data table 72, a suspend processing unit 75, a checksum confirmation unit 76, a page-in processing unit 77, and a page-out processing unit 78.

  FIG. 11 shows the structure of the address conversion table 71. The address conversion table 71 has a valid bit 711 for each virtual page 53 as valid state information holding means. The address conversion table 71 has a change bit 712 for each virtual page 53 as a change state information holding unit. The address conversion table 71 indicates where in the memory 3 the address (virtual page number 710) accessed by the processor 1 corresponds (real page number 720). The valid bit 711 indicates whether or not the corresponding virtual page 53 is in a valid state with the real page 33 assigned thereto. When the valid bit 711 is “1”, it is valid, and when it is “0”, it is invalid. The change bit 712 indicates whether or not the data of the real page 33 to which the corresponding virtual page 53 is assigned has been changed. When the change bit 712 is “1”, there is a change, and when it is “0”, there is no change.

  FIG. 12 shows the structure of the checksum data table 72. The checksum data table 72 includes, as check codes, values of the checksum 722 corresponding to the data of each real page 33 and check bits 721 indicating whether or not the data of the corresponding real page 33 has been checked by the checksum 722. It is configured. The check bit 721 is “0” if the checksum 722 has not been checked, and “1” if it has been checked.

  When the memory management unit 7 detects a suspend process instruction from the processor 1, the suspend process unit 75 executes the suspend process. The suspend processing unit 75 refers to the change bit 712 of each virtual page 53 and writes the data of the real page 33 assigned to the virtual page 53 with change “1” in the auxiliary storage unit 5. Then, the suspend processing means 75 calculates the checksum 722 of the data of the real page 33. Next, the suspend processing means 75 writes the calculated checksum 722 into the checksum data table 72. Then, the suspend processing means 75 sets the valid bits 711 of all virtual pages 53 to invalid “0”.

  When an address translation exception occurs, the memory management means 7 executes an address translation exception process.

  When the cause of the address translation exception is that the valid bit 711 is invalid “0”, the memory management means 7 performs the following processing using the checksum confirmation means 76. The checksum confirmation unit 76 calculates the checksum 722 of the data of the corresponding real page 33. Then, the checksum confirmation unit 76 compares the calculated checksum 722 with the checksum 722 of the corresponding real page 33 stored in the checksum data table 72. The checksum confirmation unit 76 reads data corresponding to the corresponding virtual page 53 from the auxiliary storage unit 5 when the checksums 722 do not match. Then, the checksum confirmation unit 76 writes the read data to the corresponding real page 33. Then, the checksum confirmation unit 76 sets the check bit 721 of the corresponding real page 33 to “1”.

  Then, the memory management unit 7 sets the valid bit 711 of the corresponding virtual page 53 to valid “1”.

  If the cause of the address translation exception is that the real page number 720 corresponding to the virtual page number 710 to be accessed is not registered in the address translation table 71, the memory management means 7 performs a memory allocation process (not shown). Execute. In the memory allocation process, in the case of the virtual page 53 in which data is already stored in the auxiliary storage unit 5, the memory management unit 7 performs the page-in process by the page-in processing unit 77.

When the memory management unit 7 detects that the free space in the memory 3 has decreased, the page-out processing unit 78 performs page-out processing. Note that the timing for detecting that the memory 3 is low is immediately after the page-in process is executed, for example.

  Next, the operation of the second exemplary embodiment of the present invention will be described with reference to the drawings.

  FIG. 13 shows the operation of the memory management means 7 during suspension.

  The memory management unit 7 detects a suspend process instruction (step S830).

  The memory management unit 7 performs Steps S832 to S836 for all virtual page numbers 710 in the address conversion table 71 (Step S831).

  In the memory management unit 7, the suspend processing unit 75 checks the change bit 712 (step S832).

  When the change bit 712 is “1” (YES in step S832), the suspend processing unit 75 writes the data of the corresponding real page 33 to the auxiliary storage unit 5 (step S833).

  Furthermore, the suspend processing means 75 calculates a checksum for the data of the corresponding real page 33, and writes the calculated checksum as the check code 722 in the checksum data table 72 (step S834). Then, the suspend processing means 75 sets the change bit 712 to “0” (step S835). Then, the suspend processing means 75 sets the valid bit 711 to “0”. Then, the suspend processing means 75 sets the check bit 721 of the real page number 720 of the checksum data table 72 corresponding to the real page number 720 set in the address conversion table 71 to “0” (step S836). Then, the memory management unit 7 proceeds to the processing of the next virtual page 53.

  When the change bit 712 is “0” (NO in step S832), the suspend processing unit 75 sets the valid bit 711 to “0”. Then, the suspend processing means 75 sets the check bit 721 of the real page number 720 of the checksum data table 72 corresponding to the real page number 720 set in the address conversion table 71 to “0” (step S836). Then, the memory management unit 7 proceeds to the processing of the next virtual page 53.

  When the operation shown in FIG. 13 is completed, the change bits 712 of all virtual pages 53 are “0”, and the data stored in the memory 3 is consistent with the data stored in the auxiliary storage unit 5. It becomes a state.

  In addition, the valid bits 711 of all virtual pages 53 are set to “0” and the check bit 721 is set to “0”. Therefore, an address translation exception occurs in the access after resume.

  FIG. 14 shows the operation during resume.

  The power is turned on by means not shown, and the resume process is started (step S840).

  The processor 1 checks the memory management means 7 (step S841). If there is no problem as a result of the check (YES in step S842), the operation immediately before the suspend is resumed.

  If the result of the check is a problem (NO in step S842), the resume is given up and control is passed to an initialization boot process (not shown).

  FIG. 15 is a flowchart showing the operation of the address conversion unit 2 when a read instruction or a write instruction is detected.

  The address conversion unit 2 detects a write instruction or a read instruction from the processor 1 to the memory 3 (step S860).

  The address conversion unit 2 checks the valid bit 711 (step S861). If the valid bit 711 is “0” (NO in step S861), the address conversion unit 2 generates an address conversion exception. If the valid bit 711 is “1” (YES in step S861), the address conversion unit 2 proceeds to S862.

  Next, the address conversion unit 2 checks whether or not the real page number 720 is registered in the address conversion table 71 (step S862). If the real page number 720 is not registered (NO in step S862), the address conversion unit 2 generates an address conversion exception. If the real page number 720 is registered in the address conversion table 71 (YES in step S862), the address conversion unit 2 proceeds to S863.

  Next, the address conversion means 2 confirms whether or not it is a write instruction (step S863). If there is no write instruction (NO in step S863), the address conversion unit 2 proceeds to the address conversion process. If it is a write instruction (YES in step S863), the address conversion unit 2 proceeds to step S864.

  Then, the address conversion unit 2 sets the change bit 712 of the corresponding virtual page 53 to “1” (step S864). Then, the address conversion unit 2 proceeds to the address conversion process.

  FIG. 16 is a flowchart of the address translation exception operation of the memory management means 7 when the address translation means 2 generates an address translation exception.

  The memory management means 7 checks whether or not the real page number 720 is registered in the address conversion table 71 (step S851).

  If the real page number 720 is not registered (NO in step S851), the memory management unit 7 proceeds to the memory allocation process. If the real page number 720 is registered (YES in step S851), the memory management unit 7 proceeds to step 852.

  Next, the memory management means 7 confirms the change bit 712 (step S852). When the change bit 712 is “1” (YES in step S852), the process proceeds to step S858. If the change bit 712 is “0” (NO in step S852), the process proceeds to step S853.

  Next, the memory management unit 7 confirms the check bit 721 (step S853). If the check bit 721 is “1” (YES in step S853), the process proceeds to step S858. If the check bit 721 is “0” (NO in step S853), the process proceeds to step S854.

  Next, the checksum confirmation unit 76 calculates a checksum for the data of the target real page 33 (step S854). Then, it is confirmed whether or not the calculated checksum matches the checksum 722 stored in the checksum data table 72 corresponding to the target real page number 720 (step S855). If the two checksums match (YES in step S855), the process proceeds to step S857. The fact that the two checksums match indicates that the data of the corresponding real page 33 has not changed and can be used as it is. If the two checksums do not match (NO in step S855), the process advances to step S856. The fact that the two checksums do not match indicates that the data of the corresponding real page 33 has changed and cannot be used as it is.

  Then, the checksum confirmation unit 76 reads data corresponding to the target virtual page 53 from the auxiliary storage unit 5. Then, the checksum confirmation unit 76 writes the data corresponding to the read virtual page 53 to the target real page 33 (step S856). Thus, the data of the real page 33 is restored to the state before the change.

  Then, the checksum confirmation unit 76 sets the check bit 721 to “1” (step S857).

  Then, the memory management unit 7 sets the valid bit 711 to “1” (step S858). After that, when returning to the original processing, since the effective bit 711 is “1” this time, the address conversion by the address conversion means 2 is successful.

  FIG. 17 is a flowchart of the operation of page-in processing for reading data corresponding to the required virtual page 53 from the auxiliary storage means 5 and placing it in the memory 3 so that it can be accessed.

  The page-in processing unit 77 determines the position of the real page 33 in the memory 3 where the virtual page 53 is arranged, and registers the real page number 720 corresponding thereto in the address conversion table 71 (step S871).

  Next, the page-in processing unit 77 reads the data corresponding to the target virtual page 53 from the auxiliary storage unit 5 and writes it in the allocated real page 33 (step S872).

  Further, the page-in processing unit 77 calculates the checksum 722 for the data of the real page 33 and writes it in the checksum data table 72 (step S873).

  Then, the page-in processing unit 77 initializes the check bit 721 to “1”, the change bit 712 to “0”, and sets the valid bit 711 to “1” (step S874).

  FIG. 18 shows the operation of the page-out process for writing the data of the real page 33 allocated to the virtual page 53 that is unnecessary for the time being to the auxiliary storage means 5 to create the unused real page 33 when the memory 3 becomes small. It is a flowchart of.

  The page-out processing means 78 sets the valid bit 711 of the address conversion table 71 corresponding to the corresponding virtual page 53 to “0” (step S875).

  Next, the page-out processing unit 78 checks the change bit 712 corresponding to the corresponding virtual page 53 (step S876). If the change bit 712 is “0” (NO in step S876), the page-out processing unit 78 proceeds to step S878. If the change bit 712 is “1” (YES in step S876), the page-out processing unit 78 proceeds to step S877.

  Then, the page-out processing unit 78 writes the data of the corresponding real page 33 in the auxiliary storage unit 5 (step S877).

  Then, the page-out processing unit 78 clears the real page number 720 corresponding to the corresponding virtual page 53 in the address conversion table 71 and releases the corresponding real page 33 in the memory 3 (step S878).

  According to the second embodiment of the present invention, in the configuration for controlling the virtual memory, at the time of suspension, writing to the auxiliary memory is performed in units of real pages based on the change state information. In the configuration in which the virtual memory is controlled, the operation before the suspension is resumed only by checking the memory control device part at the time of resume. In the configuration for controlling the virtual memory, the validity of the data is checked based on the valid state information and the checksum for each real page at the time of writing or reading.

  Thus, in the configuration for controlling the virtual memory, the same effect as that of the first embodiment can be obtained.

  Further, according to the second embodiment of the present invention, the checksum is calculated at the time of page-in. Thus, if the data of the actual page is not rewritten thereafter, there is no need to perform the checksum calculation process at the time of suspend, and the suspend process can be speeded up.

  Next, a third embodiment of the present invention will be described with reference to the drawings. In addition, about the 3rd Embodiment of this invention, a different part from the 2nd Embodiment of this invention is demonstrated.

  Referring to FIG. 19, in the third embodiment of the present invention, in addition to the memory management means 7 of FIG. 8 showing the configuration of the second embodiment, the memory management means 7 stores a resume process table 79. It differs from the second embodiment in that it has. Further, the address conversion table 71 shown in FIG. 21 is added with a process ID 731 for each virtual page 53 as a process identifier holding unit as compared with the address conversion table 71 of the second embodiment shown in FIG. This is different from the second embodiment.

  The resume target process table 79 is a table for setting a process to be resumed. FIG. 20 shows the structure of the resume target process table 79. The memory management unit 7 according to the third exemplary embodiment of the present invention guarantees the resume for the process with the process ID 731 set in the resume target process table 79.

  Next, the operation of the third embodiment of the present invention will be described. The operation of the suspend processing by the suspend processing means 75 according to the third embodiment of the present invention is obtained by replacing the portion of step S833 in FIG. 13 with FIG. The operation of the address translation exception process by the memory management unit 7 according to the third embodiment of the present invention is obtained by replacing step S856 in FIG. 16 with FIG.

  Even when the change bit 712 is “1”, the suspend processing unit 75 does not write data to the auxiliary storage unit 5 unconditionally. The suspend processing unit 75 acquires the process ID 731 of the target virtual page 53 from the address conversion table 71. Then, the suspend processing means 75 refers to the resume target process table 79 and confirms whether or not the acquired process ID 731 is set in the resume target process table 79. When the process ID 731 is set in the resume target process table 79 (YES in step S881), the suspend processing unit 75 determines that the process is the virtual page 53 of the resume target process and proceeds to step S882. If the process ID 731 is not set in the resume target process table 79 (NO in step S881), the suspend processing means 75 determines that the process is not the resume target process virtual page 53 and proceeds to step S883.

  Then, the suspend processing unit 75 writes the data of the real page 33 allocated to the virtual page 53 corresponding to the auxiliary storage unit 5 (step S882).

  Then, the suspend processing unit 75 invalidates the corresponding part of the auxiliary storage unit 5 (step S883). As an invalidation processing method, for example, information (not shown) where the data of the real page 33 allocated to the corresponding virtual page 53 is stored in the auxiliary storage device 5 is cleared, and the auxiliary storage is performed. There is a method of releasing the corresponding area of the device 5.

  The processing by the checksum confirmation unit 76 in the address translation exception processing according to the third embodiment of the present invention has a configuration in which the operation in step S856 in FIG. 16 in the second embodiment is replaced with the operation in FIG. . In the third embodiment of the present invention, if the corresponding virtual page 53 of the auxiliary storage unit 5 is invalidated in step S856 of FIG. 16, the process using the virtual page 53 is used. Control is passed to the process for forcibly terminating (not shown). For this reason, when the data corresponding to the virtual page 53 of a process not set in the resume target process table 79 changes during the suspended state, the process is forcibly terminated after the resume.

  According to the third embodiment of the present invention, it is configured to guarantee the resume of only the process set in the resume target process table, and the amount of data written to the auxiliary storage unit 5 is reduced. It has the effect of speeding up.

  Since the embodiment described above is an example, for example, the location where the check code is held may be a memory or an auxiliary storage unit. Further, for example, the auxiliary storage means may be a disk or other nonvolatile memory, or may be a device having a storage process connected via a network.

  The present invention can be used for a computer having a resume function. The present invention can be used for, for example, a computer that requires a high-speed and highly reliable resume operation even in a situation where power supply to a memory in a suspended state is unstable.

It is a block diagram which shows an example of a structure of 1st Embodiment of this invention. It is a block diagram which shows an example of a structure of 1st Embodiment of this invention. It is a figure which shows the concept of the page of the memory in the 1st Embodiment of this invention. It is a figure which shows the structure of the change status information holding means in the 1st Embodiment of this invention, a check code holding means, and a valid state information holding means. It is a flowchart which shows the operation | movement of the suspend process in the 1st Embodiment of this invention. It is a flowchart which shows the operation | movement of the resume process in the 1st Embodiment of this invention. 4 is a flowchart showing an operation when a write instruction or a read instruction is detected in the first embodiment of the present invention. It is a block diagram which shows the structure of 2nd Embodiment of this invention. It is a figure which shows the concept of the real page of the memory in the 2nd Embodiment of this invention. It is a figure which shows the concept of the virtual page stored in the auxiliary storage means in the 2nd Embodiment of this invention. It is a figure which shows the structure of the address conversion table in the 2nd Embodiment of this invention. It is a figure which shows the structure of the checksum data table in the 2nd Embodiment of this invention. It is a flowchart which shows the operation | movement of the suspend process in the 2nd Embodiment of this invention. It is a flowchart which shows the operation | movement of the resume process in the 2nd Embodiment of this invention. It is a flowchart which shows operation | movement when the write instruction | indication or read instruction | indication in the 2nd Embodiment of this invention is detected. It is a flowchart which shows the operation | movement of the address translation exception process in the 2nd Embodiment of this invention. It is a flowchart which shows the operation | movement of the page-in process in the 2nd Embodiment of this invention. It is a flowchart which shows the operation | movement of the page-out process in the 2nd Embodiment of this invention. It is a block diagram which shows the structure of 3rd Embodiment of this invention. It is a figure which shows the structure of the resume object process table | surface in the 3rd Embodiment of this invention. It is a figure which shows the structure of the address conversion table | surface in the 3rd Embodiment of this invention. It is a flowchart which shows a part of operation | movement of the suspend process in the 3rd Embodiment of this invention. It is a flowchart which shows a part of operation | movement of the address translation exception process in the 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Processor 2 Address conversion means 3 Memory 4 Battery 5 Auxiliary storage means 6 Memory control apparatus 7 Memory management means 8 Memory control apparatus 11 Resume processing means 31 Page 33 Real page 50 Virtual memory 53 Virtual page 61 Change state information holding means 62 Check code Holding means 63 Valid state information holding means 64 Change state information setting means 65 Suspend processing means 66 Valid state information control means 71 Address conversion table 72 Checksum data table 75 Suspend processing means 76 Checksum confirmation means 77 Page-in processing means 78 Page-out Processing means 79 Resume target process table 300 First storage device 301 Unit storage unit 500 Second storage device 600 Memory control device 611 Change state information 621 Check code 631 Valid state information 7 0 virtual page number 711 valid bits 712 change bit 720 real page number 721 check bits 722 checksum 731 process ID

Claims (21)

A memory control device that controls a first storage device including a plurality of unit storage units and a second storage device,
Storing the data in the unit storage unit in the changed state in the second storage device at the time of suspension, and generating a check code of the data in the unit storage unit in the changed state;
When an access to the first storage device is detected, the check code of the data in the unit storage unit that is not in a valid state is generated, and the check code is compared with the check code generated at the time of suspend. A memory control device comprising means for reading the data in the unit storage unit stored in the second storage device and writing it in the unit storage unit when they do not match. 2. The memory control device according to claim 1, wherein the means does not store the data in the unit storage unit that is not changed when suspended in the second storage device. 3. The first storage device which is a memory configured by the unit storage unit in page units;
The second storage device being auxiliary storage means;
3. The memory control device according to claim 1, wherein the memory control device is controlled. The memory control device that manages the first storage device in units of the page,
Valid state information holding means for holding valid state information of the data of the page;
Check code holding means for holding the check code for the data of the page;
When the access to the first storage device is detected, the valid state information of the corresponding page is referred to. When the valid state information is invalid, the check code of the page is generated and the check is performed. If the code and the check code stored in the check code holding means are compared and do not match, the data corresponding to the page is read from the second storage device and written to the page, Valid state information control means for validly setting valid state information;
The memory control device according to claim 3. Change state information holding means for holding change state information of the data of the page;
A change state information setting means for setting the change state information of the corresponding page to changed when the data of the page is changed by a write instruction;
When a suspend processing instruction is detected, if there is a change with reference to the change state information, the data of the page is written to the second storage device, and a check code of the data of the page is generated. Suspend processing means for writing in the check code holding means;
The memory control device according to claim 4, further comprising: Having address translation means for virtual memory control;
The address conversion means detects access to the first storage device and notifies the effective state information setting means of the access; the change state information setting means;
The memory control device according to claim 4, comprising: 7. The memory control device according to claim 6, further comprising means for generating the check code and setting the valid state information valid when a page-in processing instruction is detected. A resume target process holding means for holding an identifier of a resume target process;
Process identifier holding means for holding the identifier of the process to which the page is allocated;
When detecting the suspend process instruction, the process identifier holding means of each page;
With reference to the resume process holding means, it is determined whether or not the page is assigned to the process to be resumed, and when the page is assigned to the process to be resumed, the page Means for writing the data in the second storage device;
The memory control device according to claim 3, comprising: The memory control device according to any one of claims 1 to 8,
The first storage device;
The second storage device;
A processor for accessing the first storage device via the memory control device;
A battery for backing up the power source of the first storage device;
Having a system. During the resume process, when it is detected that the memory control device is normal, the operation before suspend is resumed, and when it is detected that the memory control device is not normal, the memory control device and the first storage device The system according to claim 9, further comprising means for executing the initialization process. A program for controlling a first storage device comprising a plurality of unit storage units and a second storage device,
Storing the data in the unit storage unit in the changed state in the second storage device at the time of suspension, and generating a check code of the data in the unit storage unit in the changed state;
When an access to the first storage device is detected, the check code of the data in the unit storage unit that is not in a valid state is generated, and the check code is compared with the check code generated at the time of suspend. A program for causing a computer to execute a process of reading the data in the unit storage unit stored in the second storage device and writing the data in the unit storage unit when they do not match. The first storage device which is a memory configured by the unit storage unit in page units;
The second storage device being auxiliary storage means;
12. The program according to claim 11, wherein the program is controlled. The program for managing the first storage device in units of the page,
A valid state information holding unit for holding valid state information of the data of the page;
A check code holding unit for holding the check code for the data of the page;
As a work area,
When the access to the first storage device is detected, the valid state information of the page is referred to. When the valid state information is invalid, the check code of the page is generated, and the check code and The check code stored in the check code holding unit is compared, and if they do not match, the data corresponding to the page is read from the second storage device and written to the page, and the valid state The process of setting the information valid,
13. The program according to claim 12, which causes a computer to execute. A change state information holding unit for holding change state information of the data of the page is further used as a work area,
When the data of the page is changed by a write instruction, a process of setting the change state information of the corresponding page to changeable,
When a suspend processing instruction is detected, if there is a change with reference to the change state information, the data of the page is written to the second storage device, and a check code for the data of the page is generated. A suspend process for writing to the check code holding means;
The program according to claim 13, further causing the computer to execute. Processing for writing the data of the page to the second storage device when the process to which each page is allocated is the predetermined process to be resumed when the suspend process instruction is detected 15. The program according to claim 12, which causes a computer to execute. A method for controlling a first storage device and a second storage device, each comprising a plurality of unit storage units,
Storing the data in the unit storage unit in the changed state in the second storage device at the time of suspension, and generating a check code of the data in the unit storage unit in the changed state;
When an access to the first storage device is detected, the check code of the data in the unit storage unit that is not in a valid state is generated, and the check code is compared with the check code generated at the time of suspend. A method of reading the data in the unit storage unit stored in the second storage device and writing it in the unit storage unit when they do not match. The method according to claim 16, wherein the data in the unit storage unit that is not changed when suspended is not stored in the second storage device. The first storage device which is a memory configured by the unit storage unit in page units;
The method according to claim 17, wherein the second storage device which is auxiliary storage means is controlled. A method in which a computer manages the first storage device in units of pages,
When the access to the first storage device is detected, if the valid state information of the page is invalid, a check code of the data of the page is generated, and the check code and the check generated at the time of suspend are generated. 19. The method according to claim 18, wherein when the code does not match, the data corresponding to the page is read from the second storage device and written to the page, and the valid state information is set to be valid. When the data of the page is changed by a write instruction, the computer sets the change state information of the corresponding page to change,
20. When a suspend process instruction is detected, if the change state information is changed, the data of the page is written to the second storage device, and a check code of the data of the page is generated. Method. When a resume target process holding unit that holds an identifier of a process to be resumed in advance, a process identifier holding unit that holds the identifier of the process to which the page is allocated, and each of the pages when the suspend process instruction is detected 21. The method according to any one of claims 18 to 20, wherein the data of the page is written to the second storage device when the process to which is assigned is the predetermined process to be resumed.

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