JP2009110383A - Information processor, arithmetic processor, and branch prediction method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor, an arithmetic processor, and a branch prediction method capable of dynamically limiting reading of a part of a branch target address in performing branch prediction by using a branch target buffer. <P>SOLUTION: A recorder 10 as an information processor has a CPU 11 as an arithmetic processor, a DRAM 12, an NOR flash memory 13 as a first device, an HDD 14 as a second device, a display output part 15, an operation input part 16, and a tuner 17. Either the NOR flash memory 13 or the HDD 14 is selectively connected to a chip select signal line (chip select hereafter) of the CPU 11 via a switch 50. The CPU 11 has a branch prediction part 21 and a command acquisition part 22. Also, the CPU 11 functions as a function performance part including at least a switch part and a buffer change part by either an OS or a video recording program. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, an arithmetic processing apparatus, and a branch prediction method that perform branch prediction according to a branch instruction using a branch destination buffer.

  Some processors (arithmetic processing units) such as a CPU and a microprocessor use a pipeline system. In a processor using a pipeline system, pipeline disturbance due to a branch instruction is one of the factors that hinders performance improvement.

  One technique for suppressing pipeline disruption due to this branch instruction is to use dynamic branch prediction. A processor having a dynamic branch prediction function predicts a branch based on a history of past branch directions when executing a branch instruction. The past branch direction history (branch instruction address (branch source address) and branch destination address history) is stored in the branch destination buffer.

According to the technique of performing branch prediction according to a branch instruction using this type of branch destination buffer, the processor predicts the branch direction in advance based on the branch destination buffer, and the instruction at the address based on this prediction is pipelined. As a result, the probability of occurrence of pipeline disturbance can be reduced (see, for example, Patent Document 1).
JP-A-62-224829

  By the way, in particular, in an embedded system such as an HDD recording device, a mobile phone, or a digital camera, the ratio of the address space required by the operating system (hereinafter referred to as OS) is high with respect to the entire address space. There may be restrictions on the address space allocated to certain devices. In this case, if the same address space is shared by a plurality of devices and the devices allocated to the address space are dynamically changed, the address space can be used efficiently.

  However, in the conventional technique including the technique disclosed in Patent Document 1, no consideration is given to the case where the same address space is dynamically switched and allocated to a plurality of devices.

  Some devices have a state change caused by reading (reading) from the processor. For example, consider a case where the address space assigned to an executable device such as a NOR flash memory is assigned to this type of device by switching. If there is a branch destination address stored in the branch destination buffer that belongs to this address space, when a program that uses this device is executed, an unintended read is performed on this device by branch prediction. It may be broken. In this case, this device causes a state change unintended by a program that uses the device, resulting in inconvenience such as malfunction.

  The present invention has been made in consideration of the above-described circumstances, and when performing branch prediction using a branch destination buffer, an information processing apparatus capable of dynamically restricting reading of a part of a branch destination address, An object is to provide an arithmetic processing unit and a branch prediction method.

  In order to solve the above-described problem, an information processing apparatus according to the present invention stores branch prediction information in which an address of a branch instruction obtained by executing a branch instruction in advance and a branch destination address are associated with each other. A branch prediction unit having a buffer, the branch destination buffer, and performing branch prediction using the branch prediction information stored in the branch destination buffer; and reading an instruction of the branch destination address predicted by the branch prediction A reference address storage unit for storing a required address to be referred to at the time, an instruction acquisition unit for reading an instruction by referring to the reference address storage unit as necessary, and an address space allocated to the first device, A switching unit for switching so as to be assigned to the second device, and the reference address storage using information on an address belonging to the address space It is characterized in that it comprises a reference address changing unit for changing the stored the required address, to.

  On the other hand, the arithmetic processing unit according to the present invention stores branch prediction information in which the address of the branch instruction obtained by executing the branch instruction in advance and the branch destination address are associated in order to solve the above-described problem. A branch target buffer, a branch prediction unit that has the branch target buffer and performs branch prediction using the branch prediction information stored in the branch target buffer, and an instruction of the branch destination address predicted by the branch prediction A reference address storage unit that stores a required address to be referred to when reading data, a command acquisition unit that reads the command by referring to the reference address storage unit as necessary, and an address space allocated to the first device And a switching unit for switching to be assigned to the second device, and information on addresses belonging to the address space according to an instruction from the outside. A reference address changing unit for changing the predetermined address stored in the reference address storage unit and use, is characterized in that it comprises a.

  On the other hand, in order to solve the above-described problem, the branch prediction method according to the present invention provides branch prediction information in which the branch instruction address and the branch destination address obtained by executing the branch instruction in advance are associated with each other. A step of storing in a buffer, a step of storing in a reference address storage unit a required address to be referred to when an instruction at the branch destination address predicted by the branch prediction is read, and an address assigned to the first device A step of switching a space so as to be assigned to a second device, a step of changing the required address stored in the reference address storage unit using information on an address belonging to the address space, and the reference address And a step of referring to the storage unit as necessary to read out the instruction. A.

  According to the information processing device, the arithmetic processing device, and the branch prediction method according to the present invention, when branch prediction is performed using a branch destination buffer, it is possible to dynamically limit reading of a part of the branch destination address.

  Embodiments of an information processing apparatus, an arithmetic processing apparatus, and a branch prediction method according to the present invention will be described with reference to the accompanying drawings.

  As the arithmetic processing unit, a processor such as a CPU or a microprocessor having a branch prediction function for performing branch prediction according to a branch instruction using a branch destination buffer can be used. In the following description, an example in which a CPU is used as the arithmetic processing device will be described.

  As the information processing apparatus, an embedded system including an arithmetic processing apparatus having a branch prediction function can be used. In the following description, an example in which an HDD recording apparatus (hereinafter referred to as a recording apparatus) including a CPU having a branch prediction function is used as the information processing apparatus will be described.

  FIG. 1 is a schematic overall configuration diagram showing a first embodiment of an information processing apparatus (including an arithmetic processing apparatus) according to the present invention.

  The recording apparatus 10 as an information processing apparatus includes a CPU 11 as an arithmetic processing unit, a DRAM 12 (Dynamic Random access memory), a NOR flash memory (hereinafter referred to as NOR Flash 13) as a first device, and an HDD 14 as a second device. (Hard disk drive), display output unit 15, operation input unit 16, and tuner 17.

  As shown in FIG. 1, the CPU 11 includes a branch prediction unit 21 and an instruction acquisition unit 22.

  The branch prediction unit 21 has a BTB 23 (Branch Target Buffer) as a branch target buffer, and performs branch prediction according to the branch instruction with reference to the BTB 23. More specifically, the branch prediction unit 21 determines whether or not the address of the instruction notified from the instruction acquisition unit 22 matches the address of the branch instruction (branch source address) stored in the BTB 23. In this case, information on the branch destination address associated with the address of the matched branch instruction is read from the BTB 23 and given to the instruction acquisition unit 22.

  The BTB 23 serving as a branch destination buffer stores, for each branch instruction, branch prediction information obtained by associating the branch instruction address with the branch destination address obtained by the CPU 11 executing the branch instruction in advance.

  The instruction acquisition unit 22 sequentially reads instructions of various programs and gives them to the instruction decode of the CPU 11. The instruction acquisition unit 22 notifies the instruction address to the branch prediction unit 21 simultaneously with the reading. When a branch destination address is given from the branch prediction unit 21, the instruction acquisition unit 22 acquires an instruction from this branch destination address.

  The branch prediction unit 21, the instruction acquisition unit 22, and the BTB 23 are configured by hardware logic such as a circuit.

  Further, the CPU 11 controls the recording device 10 according to a program stored in the NOR Flash 13. The CPU 11 directly executes an instruction described in a BIOS (Basic Input Output System) stored in the NOR Flash 13 by directly accessing an address assigned to the NOR Flash 13 and starts the recording apparatus 10. .

  Further, the CPU 11 loads an operating system (OS), a recording program, and data necessary for executing the program stored in the NOR Flash 13 into the DRAM 12, and controls the recording device 10 according to the OS and the recording program.

  The DRAM 12 is loaded with the OS and the recording program stored in the NOR Flash 13 and used as a working storage area of the CPU 11, and temporarily stores data to be calculated, instructions, calculation results, and the like.

  As shown in FIG. 1, the NOR Flash 13 as the first device stores programs executed by the CPU 11 such as BIOS, OS, and recording program, and various data necessary for executing these programs.

  The HDD 14 as the second device stores the video data of the broadcasted program input via the tuner 17 as the recording data when the CPU 11 executes the recording program.

  One of the NOR Flash 13 and the HDD 14 is selectively connected to a chip select signal line (hereinafter referred to as a chip select) of the CPU 11 via the switch 50. It is assumed that the NOR Flash 13 is connected to the chip select when the recording apparatus 10 is activated. This is because the BIOS stored in the NOR Flash 13 is used at startup. The switch 50 is controlled by the CPU 11 to switch the chip select connection destination from the NOR Flash 13 to the HDD 14 as necessary.

  FIG. 2 is a simple explanatory diagram showing a state where the allocation device for the same address space is changed from the NOR Flash 13 to the HDD 14 by switching the connection destination of the chip select.

  This chip select corresponds to one address space. For this reason, as shown in FIG. 2, the address space allocated to the NOR Flash 13 when the recording apparatus 10 is started is the same as the address space allocated to the HDD 14 when the chip select connection is switched from the NOR Flash 13 to the HDD 14. It becomes.

  Note that the number of devices selectively connected to one chip select via the switch 50 is not limited to two, and may be three or more. In the following description, an example in which the NOR Flash 13 and the HDD 14 are selectively connected to one chip select via the switch 50 will be described.

  The CPU 11 can read data by accessing the DRAM 12 and the NOR Flash 13 by designating an address in an address space assigned in advance. For this reason, the DRAM 12 and the NOR Flash 13 are devices that can directly execute instructions in the assigned address space.

  The state of the DRAM 12 and the NOR Flash 13 is not changed by reading by the CPU 11. On the other hand, the HDD 14 is a device that can change its state when a read command is issued from the CPU 11 according to a program to an address in the allocated address space (the read (read) has meaning).

  For example, when data is read from the HDD 14, the number of times data should be read from the HDD 14 is determined by the size of the read data (for example, 512 bytes) (for example, 512 times if the data width is 8 bits). Since the HDD 14 controller counts the number of times of reading, the number of times of counting changes every time reading is performed.

  The operation receiving unit is configured by a general input device such as a keyboard, a touch panel, or a numeric keypad, and outputs an operation input signal corresponding to a user operation to the CPU 11.

  The display output unit 15 is configured by a general display output device such as a liquid crystal display or a CRT display, for example, and displays various information according to the control of the CPU 11.

  The tuner 17 receives a television broadcast signal and receives video data, audio data, EPG (Electronic Program Guide) data, and the like of a broadcast program.

  FIG. 3 is a schematic block diagram illustrating a configuration example of the function realizing unit 20 by the CPU 11 illustrated in FIG. Note that the function realization unit 20 may be configured by hardware logic such as a circuit without using the CPU 11.

  The CPU 11 functions as the function realizing unit 20 including at least the switching unit 31 and the buffer changing unit 32 by at least one of the OS and the recording program. Note that the function realization unit 20 may be configured by hardware logic such as a circuit without using the CPU 11.

  Next, the function realization part 20 of CPU11 is demonstrated.

  The switching unit 31 has a function of controlling the switch 50 and switching the chip select connection destination from the NOR Flash 13 to the HDD 14 as necessary. When this switching is performed, the address space allocated to the NOR Flash 13 when the recording apparatus 10 is started is allocated to the HDD 14.

  The buffer changing unit 32 has a function of deleting, from the BTB 23 of the branch prediction unit 21, branch prediction information including addresses belonging to the address space allocated to the HDD 14.

  Next, an example of the operation of the recording apparatus 10 according to the present embodiment will be described.

  FIG. 4 is a flowchart showing a procedure for dynamically restricting reading of a part of the branch destination address when the CPU 11 of the recording apparatus 10 shown in FIG. 1 performs branch prediction using the BTB 23. In FIG. 4, reference numerals with numbers added to S indicate steps in the flowchart.

  This procedure starts when the recording apparatus 10 is turned on and the NOR Flash 13 is connected to the chip select.

  In the following description of steps S1 to S4, an example in which the BTB 23 is changed at the initial startup of the OS after the BIOS has started will be described.

  First, in step S <b> 1, the CPU 11 directly executes an instruction described in the BIOS stored in the NOR Flash 13 by directly accessing an address assigned to the NOR Flash 13, and starts the recording apparatus 10.

  FIG. 5 is an explanatory diagram illustrating an example of a list of branch prediction information stored in the BTB 23.

  In step S1, the BIOS is directly executed on the address space assigned to the NOR Flash 13. Although the NOR Flash 13 has a low access speed, since the BIOS is executed only when the recording apparatus 10 is activated, it may be directly executed on the address space of the NOR Flash 13.

  When step S1 is executed, as a result of executing the branch instruction included in the instruction described in the BIOS, as shown in the left diagram of FIG. 5, the branch prediction including the address belonging to the address space of NOR Flash 13 in the list of BTB 23 Information is added.

  Next, in step S <b> 2, the CPU 11 develops the OS in the DRAM 12. The OS is frequently used while the recording apparatus 10 is activated. Since the NOR Flash 13 has a slower access speed than the DRAM 12, it is preferable that the NOR Flash 13 is loaded on the DRAM 12 and then executed on the DRAM 12 address space rather than directly on the NOR Flash 13 address space.

  Next, in step S <b> 3, the CPU 11 functions as the switching unit 31 by executing the OS and controls the switch 50 to switch the connection destination of the chip select signal line from the NOR Flash 13 to the HDD 14. As a result, the address space assigned to the NOR Flash 13 is assigned to the HDD 14.

  However, the BTB 23 stores branch prediction information including an address belonging to the address space already assigned to the HDD 14. For this reason, if the read address matches the branch source address of the BTB 23 while the recording program is executed, for example, while the HDD 14 driver is reading from the HDD 14, the branch destination address May be read (pre-read).

  This prefetching is unintentional reading by the program that causes the CPU 11 to execute reading from the HDD 14. If such prefetching, which is not intended by the program, interrupts even once, the number of times that the HDD 14 controller counts shifts, causing a problem in the read data.

  Therefore, it is necessary to be careful not to perform unintentional reading by a program on a device such as the HDD 14 whose state can change when a read command is issued to an address in the allocated address space.

  As a method for preventing unintentional reading from being performed on a device such as the HDD 14 whose state may change, for example, branch prediction information stored in the BTB 23 belongs to the address space assigned to the HDD 14. A method of deleting branch prediction information including an address is conceivable.

  In step S4, the CPU 11 functions as the buffer changing unit 32 by executing the OS, and deletes branch prediction information including addresses belonging to the address space assigned to the HDD 14 from the BTB 23 (see the right diagram in FIG. 5). As a result, it is possible to prevent the HDD 14 from performing prefetching that is not intended by the program.

  With the above procedure, when branch prediction is performed using the BTB 23, it is possible to dynamically limit reading of a part of the branch destination address.

  Note that the BTB 23 change (partial deletion of branch prediction information) executed in step S4 does not need to be executed immediately after the OS is started. For example, the program accesses the HDD 14 immediately before the recording program accesses the HDD 14. It only needs to be completed before doing. Further, if the BTB 23 changed in step S4 is performed immediately after or immediately before the switching performed in step S3, it is possible to efficiently prevent the occurrence of prefetching unexpected by the program.

  Furthermore, the functions of the switching unit 31 and the buffer changing unit 32 may be realized by the CPU 11 executing a program other than the OS. Since the program having the function of the switching unit 31 has information on the address space to be switched as a matter of course, the functions of the switching unit 31 and the buffer changing unit 32 may be realized based on the same program. .

  FIG. 6 is a flowchart briefly explaining the operation of the instruction acquisition unit 22 in the first embodiment. In FIG. 6, reference numerals with numbers added to S indicate steps in the flowchart.

  This procedure starts when the instruction acquisition unit 22 acquires the address of the instruction.

  In step S11, the branch prediction unit 21 is notified of the address of the instruction from the instruction acquisition unit 22, and whether the address that matches the address of this instruction is the address of the branch instruction (branch source address) stored in the BTB 23. Judge whether. If there is an address of a branch instruction that matches the address of this instruction, the process proceeds to step S12. On the other hand, if not, the process proceeds to step S13.

  Next, in step S12, the instruction acquisition unit 22 is given a branch destination address from the branch prediction unit 21, and acquires an instruction from this branch destination address.

  On the other hand, in step S13, the instruction acquisition unit 22 acquires an instruction from the address of the next instruction.

  By repeating the above procedure, the CPU 11 can sequentially read and execute instructions from the device.

  As illustrated in FIG. 6, when a branch destination address is given from the branch prediction unit 21, the instruction acquisition unit 22 reads the branch destination address. If the branch prediction information including addresses belonging to the address space assigned to the HDD 14 is deleted from the branch prediction information stored in the BTB 23 in advance, the instruction acquisition unit 22 is prevented from performing prefetching that is not intended by the program. can do.

  The recording apparatus 10 as the information processing apparatus according to the present embodiment includes a buffer changing unit 32 that deletes branch prediction information including addresses belonging to an address space allocated to the HDD 14 from the BTB 23. For this reason, in an information processing apparatus including an arithmetic processing unit having a branch prediction function, prefetching unintended by a program can be prevented when one address space is switched to a plurality of devices for use.

  Therefore, according to the information processing apparatus according to the present embodiment, in an information processing apparatus including an arithmetic processing unit having a branch prediction function, one address space is switched between a plurality of devices without causing unintentional prefetching of a program. Since the address space can be used efficiently, the size of the entire address space can be suppressed.

  Next, a second embodiment of the information processing apparatus (including the arithmetic processing apparatus) according to the present invention will be described.

  The information processing apparatus shown in the second embodiment does not have the buffer changing unit 32, and executes the reading with reference to the required address when the instruction acquiring unit 22 reads the instruction at the branch destination address predicted by the branch prediction. It differs from the information processing apparatus shown in the first embodiment in that it is determined whether or not to do so. Since other configurations and operations are not substantially different from those of the information processing apparatus shown in FIG. 1, the same components are denoted by the same reference numerals and description thereof is omitted.

  In the information processing apparatus according to the present embodiment, the BTB 23 is not changed at all even when the address space allocation is changed from the NOR Flash 13 to the HDD 14, and the program is not expected to be read ahead by limiting the addresses read by the instruction acquisition unit 22. Prevent occurrence.

  FIG. 7 is a schematic overall configuration diagram showing a second embodiment of the information processing apparatus (including the arithmetic processing apparatus) according to the present invention.

  A recording apparatus 10A as an information processing apparatus includes a CPU 11 as an arithmetic processing unit, a DRAM 12, a NOR Flash 13 as a first device, an HDD 14 as a second device, a display output unit 15, an operation input unit 16, and a tuner 17. .

  As shown in FIG. 7, the CPU 11 includes a branch prediction unit 21, an instruction acquisition unit 22, and a reference address storage unit 41.

  The instruction acquisition unit 22 sequentially reads instructions of various programs and gives them to the instruction decode of the CPU 11. The instruction acquisition unit 22 notifies the instruction address to the branch prediction unit 21 simultaneously with the reading. When a branch destination address is given from the branch prediction unit 21, the instruction acquisition unit 22 refers to the reference address storage unit 41 and acquires an instruction from the branch destination address as necessary.

  The reference address storage unit 41 stores a required address that is referred to by the instruction acquisition unit 22 when the instruction at the branch destination address predicted by the branch prediction is read.

  In the following description, an example in which the required address stored in the reference address storage unit 41 is an invalid address that belongs to the address space allocated from the NOR Flash 13 to the HDD 14 and should not be prefetched by the instruction acquisition unit 22. Will be described.

  FIG. 8 is a schematic block diagram illustrating a configuration example of the function realization unit 20 by the CPU 11 illustrated in FIG. 7. Note that the function realization unit 20 may be configured by hardware logic such as a circuit without using the CPU 11.

  The CPU 11 functions as the function realizing unit 20 including at least the switching unit 31 and the reference address changing unit 42 by at least one of the OS and the recording program. Note that the function realization unit 20 may be configured by hardware logic such as a circuit without using the CPU 11.

  Next, the function realization part 20 of CPU11 is demonstrated.

  The switching unit 31 has a function of controlling the switch 50 and switching the chip select connection destination from the NOR Flash 13 to the HDD 14 as necessary. When this switching is performed, the address space allocated to the NOR Flash 13 when the recording apparatus 10A is activated is allocated to the HDD 14.

  The reference address changing unit 42 has a function of adding and storing all addresses belonging to the address space assigned to the HDD 14 in the reference address storage unit 41.

  Next, an example of the operation of the recording apparatus 10A according to the present embodiment will be described.

  FIG. 9 is a flowchart showing another procedure for dynamically restricting reading of a part of the branch destination address when the CPU 11 of the recording apparatus 10A shown in FIG. 7 performs branch prediction using the BTB 23. . In FIG. 9, the code | symbol which attached | subjected the number to S shows each step of a flowchart. Steps equivalent to those in FIG. 4 are denoted by the same reference numerals, and redundant description is omitted.

  As another method for preventing the program from unintentionally reading from a device such as the HDD 14 whose state may change, for example, an address that may be prefetched (a prefetchable effective address) or prefetching may be used. An address that should not be read (an invalid address that cannot be prefetched) is stored in the reference address storage unit 41, and when the instruction acquisition unit 22 is given a branch destination address from the branch prediction unit 21, the reference address storage unit 41 must be referred to. Thus, a method of determining whether or not reading from the branch destination address may be executed is conceivable.

  In step S <b> 20, the CPU 11 functions as the reference address changing unit 42 by executing the OS, and additionally stores all addresses belonging to the address space allocated to the HDD 14 in the reference address storage unit 41.

  According to the above procedure, when branch prediction is performed using the BTB 23, it is possible to dynamically limit reading of a part of the branch destination address.

  FIG. 10 is a flowchart for briefly explaining the operation of the instruction acquisition unit 22 in the second embodiment. In FIG. 10, reference numerals with numbers added to S indicate steps in the flowchart.

  In step S <b> 21, the branch prediction unit 21 is notified of the instruction address from the instruction acquisition unit 22, and is the address that matches the instruction address included in the branch instruction address (branch source address) stored in the BTB 23? Judge whether. If there is an address of a branch instruction that matches the address of this instruction, the process proceeds to step S22. On the other hand, if not, the process proceeds to step S24.

  Next, in step S22, the instruction acquisition unit 22 refers to the reference address storage unit 41 in which the invalid address is stored, and determines whether there is an address that matches the branch destination address given from the branch prediction unit 21. If there is an invalid address that matches the branch destination address, reading from the branch destination address is not executed, and the series of procedures ends. On the other hand, if not, the process proceeds to step S23.

  Next, in step S23, the instruction acquisition unit 22 acquires an instruction from the branch destination address.

  On the other hand, in step S24, the instruction acquisition unit 22 acquires an instruction from the address of the next instruction.

  By repeating the above procedure, when the CPU 11 sequentially reads out and executes instructions from the device, the prefetching should not be performed even if the address that should not be prefetched by the instruction acquiring unit 22 remains registered in the BTB 23. You can restrict reading to addresses.

  The required address stored in the reference address storage unit 41 is an invalid address that should not be prefetched by the instruction acquisition unit 22 belonging to the address space allocated from the NOR Flash 13 to the HDD 14 from the address belonging to the entire address space. The deleted valid address may be prefetched by the instruction acquisition unit 22. In this case, the reference address changing unit 42 has a function of deleting addresses belonging to the address space allocated to the HDD 14 from information on addresses belonging to all address spaces stored in the reference address storage unit 41 in advance.

  The information processing apparatus shown in FIG. 7 also has the same effects as the information processing apparatus shown in FIG.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, the constituent elements over different embodiments may be appropriately combined.

  Further, in the embodiment of the present invention, each step of the flowchart shows an example of processing that is performed in time series in the order described. The process to be executed is also included.

  In addition, the present invention is applicable to an information processing apparatus including a processor having a branch prediction function. In particular, the present invention is suitable for an information processing apparatus whose address space is not so large. Therefore, the present invention is applied to an embedded system such as a mobile phone, a digital camera, an automobile, a vending machine, a game machine, and a PDA (Personal Digital Assistant) in addition to the HDD recording apparatus described in the above embodiment. It is possible.

1 is a schematic overall configuration diagram showing a first embodiment of an information processing apparatus (including an arithmetic processing apparatus) according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simple explanatory diagram showing a state where an allocation device for the same address space is changed from NOR Flash to HDD by switching the connection destination of chip select. FIG. 2 is a schematic block diagram illustrating a configuration example of a function realizing unit by a CPU illustrated in FIG. 1. 3 is a flowchart showing a procedure for dynamically restricting reading of a part of a branch destination address when the CPU of the recording apparatus shown in FIG. 1 performs branch prediction using BTB. Explanatory drawing which shows an example of the list of the branch prediction information memorize | stored in BTB. The flowchart which demonstrated briefly the operation | movement of the command acquisition part in 1st Embodiment. FIG. 3 is a schematic overall configuration diagram showing a second embodiment of an information processing apparatus (including an arithmetic processing apparatus) according to the present invention. FIG. 8 is a schematic block diagram illustrating a configuration example of a function implementing unit by a CPU illustrated in FIG. 7. The flowchart which shows the other procedure at the time of restrict | limiting dynamically reading with respect to a part of branch destination address, when performing branch prediction using BTB by CPU of the recording device shown in FIG. The flowchart which demonstrated briefly the operation | movement of the command acquisition part in 2nd Embodiment.

Explanation of symbols

10, 10A Recording device 11 CPU
12 DRAM
13 NOR Flash
14 HDD
15 Display Output Unit 16 Operation Input Unit 17 Tuner 20 Function Realization Unit 21 Branch Prediction Unit 22 Instruction Acquisition Unit 23 BTB
31 switching unit 32 buffer changing unit 41 reference address storage unit 42 reference address changing unit 50 switch

Claims (11)

A branch destination buffer for storing branch prediction information in which an address of the branch instruction and a branch destination address obtained by executing a branch instruction in advance are associated;
A branch prediction unit having the branch destination buffer and performing branch prediction using the branch prediction information stored in the branch destination buffer;
A reference address storage unit that stores a required address that is referred to when an instruction of the branch destination address predicted by the branch prediction is read;
An instruction acquisition unit that reads the instruction by referring to the reference address storage unit as necessary;
A switching unit that switches the address space allocated to the first device so as to be allocated to the second device;
A reference address changing unit that changes the required address stored in the reference address storage unit using information on addresses belonging to the address space;
An information processing apparatus comprising: The first device is:
A device capable of directly executing instructions on the assigned address space;
The second device is:
A device whose state can change when a read command is made to an address on the allocated address space.
The information processing apparatus according to claim 1. A switch that selectively connects one of the first device and the second device to one chip select signal line;
The switching unit is
The switch is controlled so that the connection destination of the chip select signal line is changed from the first device to the second device so that the address space assigned to the first device is assigned to the second device. Switch to
The information processing apparatus according to claim 1. The required address stored in the reference address storage unit is:
The instruction acquisition unit is an unreadable address,
The reference address changing unit
Add and store all addresses belonging to the switched address space in the reference address storage unit,
The command acquisition unit
When the address of the instruction read by the instruction acquisition unit matches the address of the branch instruction stored in the branch destination buffer, information on the branch destination address associated with the matched address is acquired from the branch destination buffer. Then, only when the branch destination address acquired from the branch destination buffer is different from the unreadable address stored in the reference address storage unit, further instructions are read from the branch destination address.
The information processing apparatus according to claim 1. The required address stored in the reference address storage unit is:
An address that can be read by the instruction acquisition unit,
The reference address changing unit
Delete all addresses belonging to the switched address space from the reference address storage unit,
The command acquisition unit
When the address of the instruction read by the instruction acquisition unit matches the address of the branch instruction stored in the branch destination buffer, information on the branch destination address associated with the matched address is acquired from the branch destination buffer. Then, only when the branch destination address acquired from the branch destination buffer matches the readable address stored in the reference address storage unit, further instructions are read from the branch destination address.
The information processing apparatus according to claim 1. A branch destination buffer for storing branch prediction information in which an address of the branch instruction and a branch destination address obtained by executing a branch instruction in advance are associated;
A branch prediction unit having the branch destination buffer and performing branch prediction using the branch prediction information stored in the branch destination buffer;
A reference address storage unit that stores a required address that is referred to when an instruction of the branch destination address predicted by the branch prediction is read;
An instruction acquisition unit that reads the instruction by referring to the reference address storage unit as necessary;
A switching unit that switches the address space allocated to the first device so as to be allocated to the second device;
A reference address changing unit that changes the required address stored in the reference address storage unit using information of an address belonging to the address space according to an instruction from the outside;
An arithmetic processing apparatus comprising: Storing branch prediction information in which the branch instruction address and the branch destination address obtained by executing the branch instruction in advance are associated with each other in a branch destination buffer;
Storing a required address referred to when reading an instruction of the branch destination address predicted by the branch prediction in a reference address storage unit;
Switching the address space assigned to the first device to be assigned to the second device;
Changing the required address stored in the reference address storage unit using information on addresses belonging to the address space;
Reading the instruction by referring to the reference address storage unit as necessary;
A branch prediction method characterized by comprising: The first device is:
A device capable of directly executing instructions on the assigned address space;
The second device is:
A device whose state can change when a read instruction is made to an address on the assigned address space;
The branch prediction method according to claim 7. Selectively connecting one of the first device and the second device to a chip select;
The step of switching the address space includes:
The chip select so that the chip select connected to the first device is connected to the second device so that the address space assigned to the first device is assigned to the second device. Is a step of switching the connection destination of
The branch prediction method according to claim 7. The required address stored in the reference address storage unit is:
The unreadable address,
The step of changing the required address includes:
Adding and storing all addresses belonging to the switched address space in the reference address storage unit;
Reading the instructions includes
When the address of the read instruction matches the address of the branch instruction stored in the branch destination buffer, the branch destination address information associated with the matched address is obtained from the branch destination buffer, and this branch Only when the branch destination address acquired from the destination buffer is different from the unreadable address stored in the reference address storage unit, further instructions are read from the branch destination address.
The branch prediction method according to claim 7. The required address stored in the reference address storage unit is:
The readable address,
The step of changing the required address includes:
Deleting all addresses belonging to the switched address space from the reference address storage unit,
Reading the instructions includes
When the address of the read instruction matches the address of the branch instruction stored in the branch destination buffer, the branch destination address information associated with the matched address is obtained from the branch destination buffer, and this branch Only when the branch destination address acquired from the destination buffer matches the readable address stored in the reference address storage unit, further instructions are read from the branch destination address.
The branch prediction method according to claim 7.

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