JP2009105131A - Semiconductor laser array element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-reliability semiconductor laser array element, reducing an electrical interference or an thermal interference between semiconductor laser elements adjacent to each other. <P>SOLUTION: This semiconductor laser array element is composed by stacking at least an n-type clad layer 2 formed on an n-type semiconductor substrate 1, an active layer 3 comprising a quantum well structure on the n-type clad layer 2; and p-type clad layers 4a and 4b located on the active layer 3 and each having a ridge part 16 and strip groove parts 15 on both sides of the ridge part 16. The semiconductor laser array element has an n-type semiconductor region 7 in the p-type clad layer 4a present on the lower side relative to the stripe groove part 15, and is characterized in that the thickness in the stacking direction of the n-type semiconductor region 7 is not smaller than 50% of that in the stacking direction of the p-type clad layer 4a present on the lower side relative to the stripe groove part 15. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor laser array element used as a light source in technical fields such as optical communication and optical information processing.

  In recent years, red semiconductor laser elements based on AlGaInP materials have attracted much attention as light sources for laser printer light sources, high-density optical disk pickups, POF (Plastic Optical Fiber) communications, and the like. Among them, a semiconductor laser array (semiconductor monolithic laser array) element has an excellent feature that a plurality of beams can be emitted and a high density can be achieved. Therefore, a high-speed laser printer, an optical disk pickup, an optical fiber communication, etc. It is used as a light source.

  The multiple laser beams emitted from the semiconductor laser array have a simple configuration of the semiconductor laser array and high positional accuracy, so that each element of the semiconductor laser array is as dense as possible so that it is focused through the same lens. Must be placed.

  Therefore, in recent years, development of a semiconductor laser array element in which the interval between laser oscillation parts is about several tens μm has been urgently developed. However, as the distance between each element becomes smaller, a semiconductor laser array arranged at a high density has a problem that electrical or thermal interference is likely to occur, and the element characteristics are affected by the operating conditions of adjacent elements. In order to solve this problem and allow each element of the semiconductor laser array to be driven independently, a high resistance region or reverse conductivity type that reaches a part of the n-cladding layer between adjacent elements A semiconductor laser array element in which a semiconductor region is formed has been developed.

  For example, in Patent Document 1, interference between adjacent elements is reduced by generating a disordered region including a quantum well structure between adjacent elements. FIG. 3 is a perspective view of the semiconductor laser array element described in Patent Document 1. In FIG. An n-AlGaAs cladding layer 502 epitaxially grown on the n-GaAs substrate 501 by MOCVD (Metal-Organic Chemical Vapor Deposition) method, an active region 503 having a quantum well structure made of AlGaAs / GaAs, a p-AlGaAs cladding layer 504, and a p- A GaAs cap layer 506 is formed. Further, the p-AlGaAs cladding layer 504 is etched halfway to form a striped ridge. Further, an insulating layer 508, a p-side electrode 509, and an n-side electrode on the back surface of the substrate 501 are formed. Has been. As a result, a plurality of semiconductor laser arrays are formed on the GaAs substrate. Further, in order to form two or more light emitting portions, a disordered region 507 including a quantum well structure is formed in the etching region by using the technique of “disordering the semiconductor multilayer film by impurity diffusion”. The disordered region 507 increases the forbidden band width and decreases the refractive index, thereby forming a current confinement structure and an optical confinement structure. As a result, the oscillation threshold current and heat generation of the element can be reduced, and interference between adjacent elements is reduced.

In Patent Document 2, thermal interference between adjacent elements is reduced by forming a high resistance region between adjacent semiconductor laser elements by an ion implantation technique. FIG. 4 is a diagram showing a semiconductor laser array described in Patent Document 2. As shown in FIG. An n-AlGaInP cladding layer 602, a GaInP active layer 603, a p-AlGaInP first cladding layer 604a, and p-GaAsP etching are performed on an n-GaAs substrate 601 through a GaAsP lattice disorder elimination layer 611 and an n-GaAsP buffer layer 612. A stop layer 605, a p-AlGaInP second cladding layer 604b, a p-GaInP hetero spike buffer layer 613, and a p-GaAsP contact layer 606 are formed by crystal growth. Further, a striped resist pattern having a predetermined interval is formed on the contact layer 606, and each layer up to the p-GaAsP etching stop layer 605 is etched, so that a plurality of layers are formed on the same substrate as shown in FIG. The ridge stripe structure is formed. A SiO ₂ insulating film is formed, and a p-side electrode 609 is formed on the p-GaAsP contact layer 606, and an n-side electrode 610 is formed on the back surface of the substrate 1. A high resistance region 607 is formed between the ridge stripe structures from the p-AlGaInP first cladding layer 604a to a part of the n-AlGaInP cladding layer 602 by using an ion implantation technique. As a result, a semiconductor laser array element capable of suppressing overflow of carriers from the active region to the cladding layer and reducing thermal interference between adjacent element portions is realized.

  In Patent Document 3, as shown in FIG. 5, an n-type AlGaAs cladding layer 102, an active layer 103, a p-type AlGaAs cladding layer 104, and a p-type GaAs contact layer 105 are formed on an n-type GaAs substrate 101. In order to suppress the spread of the injected current in the semiconductor laser 100 in which the cladding layer 104 is formed into a ridge stripe shape composed of the central ridge portion 104a and the flat portion 104b by etching. By providing the n-type dopant diffusion region 104c in a part of 104a and 104b, the spread of the current I in the direction along the p-type AlGaAs cladding layer 104b from the p-type GaAs contact layer 105 is suppressed, and a high kink level is obtained. A semiconductor laser is realized.

  As described above, in the prior art, a high resistance or reverse conductivity type semiconductor region is formed by diffusing or injecting an impurity from the surface into a region including the active layer between adjacent ridge stripes, thereby forming a lateral direction of current. In addition, the reactive current that does not contribute to light emission is reduced. In addition, the technology to disorder the semiconductor multilayer film widens the forbidden band width of the active region where impurities are diffused or implanted, and uses the difference in the actual refractive index to confine light in the lateral direction and reduce the oscillation threshold current. Therefore, the thermal influence between adjacent semiconductor laser elements is reduced.

Japanese Patent Laid-Open No. 6-97589 JP 2002-237657 A JP 2005-251821 A

  However, in the technique described in Patent Document 1, since the n-type semiconductor region is formed in a part of the n-type clad layer by the thermal diffusion method, a part of the drive current is used as the bias current as the n-type semiconductor region. Into the disordered region 507, and heat was generated by non-radiative recombination. This is especially true for AlGaInP-based materials, although the difference in the forbidden band width between the cladding layer and the active layer is not sufficient, the electrical resistivity is greatly reduced by increasing the impurity concentration in the disordered region 507. This is because the bias current increases.

  Furthermore, in the technique described in Patent Document 2, in order to form the high resistance region 607 between adjacent ridge stripes, it is necessary to perform a laborious process of destroying the pn junction portion by proton implantation. Further, the amorphized portion requires a long heat treatment to recover the crystal structure, and a thermal change occurs even in the active layer where protons are not implanted, which causes a significant problem in device reliability.

Furthermore, in the technique described in Patent Document 3, in order to avoid light absorption loss in the n-type diffusion region 104c, a description “the upper limit of the n-type dopant amount is 5 × 10 ¹⁸ cm ⁻³ ” By solving the thermal diffusion equation from the carrier concentration of the p-type cladding layer of the semiconductor laser using the AlGaInP-based material being 5 × 10 ¹⁷ cm ⁻³ or more and the carrier concentration of a general active layer, the cladding layer It can be seen that the distance between the pn junction interface formed in the active layer and the active layer is 1.4 times or more the thickness of the n-type region to be formed. At such a distance, in a narrow pitch laser element array, suppression of electrical influence between adjacent laser elements becomes insufficient.

  In view of the above problems, an object of the present invention is to provide a highly reliable semiconductor laser array element in which electrical interference or thermal interference between adjacent semiconductor laser elements is reduced.

  In order to solve the above problems, the present invention provides at least a first conductivity type semiconductor layer formed on a first conductivity type semiconductor substrate, and an active layer having a quantum well structure on the first conductivity type semiconductor layer. And a semiconductor laser array element formed by laminating a ridge portion on the active layer and a second conductivity type semiconductor layer having a stripe groove portion on both sides of the ridge portion, the semiconductor laser array element being below the stripe groove portion The first conductive type semiconductor region is formed of the first conductive type semiconductor in the second conductive type semiconductor layer, and the thickness of the first conductive type semiconductor region in the stacking direction is lower than the stripe groove portion. One feature is that it is 50% or more of the thickness in the stacking direction of the second conductivity type semiconductor layer present in FIG.

  Another feature of the present invention is that the first conductivity type semiconductor region exists above the active layer.

Another feature of the present invention is that the first conductivity type semiconductor region is formed by implanting impurities from the stripe groove portion, and the amount of the impurity implanted into the second conductivity type semiconductor layer is 3 × 10 ¹⁹ cm. ^-3 or less, and the amount of the impurity diffused in the active layer is 1 × 10 ¹⁶ cm ^-3 or less.

  Another feature of the present invention is that the impurities are implanted by a thermal diffusion method.

  According to the present invention, an electrically conductive semiconductor region is formed in the upper clad layer, and the electrical interference between adjacent semiconductor laser elements is determined by quantitatively defining the thickness of the semiconductor region and the amount of impurities. Alternatively, it is possible to provide a highly reliable semiconductor laser array element with reduced thermal interference.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a perspective view of a semiconductor laser array element according to an embodiment of the present invention.

  In the semiconductor laser array element shown in FIG. 1, a layer of a member having a relatively wide forbidden band called a clad layer 2, 4a, 4b is provided on a semiconductor substrate 1, and active between the clad layers 2, 4a, 4b. The active layer having a narrower forbidden band than the clad layers 2, 4 a, and 4 b, which is called a layer 3, is provided, and a plurality of ridge portions 16 are formed in stripes on the same semiconductor substrate 1. It has been done. In the following description, the first conductivity type is n-type and the second conductivity type is p-type. The clad layers 2, 4 a, and 4 b include an n-type clad layer 2 in which more electrons are present than holes and p-type clad layers 4 a and 4 b in which more holes are present than electrons. Electrons are injected into the active layer 3 from the n-type cladding layer 2, and holes are injected into the active layer 3 from the p-type cladding layers 4 a and 4 b. Electrons and holes are recombined in the active layer 3 to generate light having energy corresponding to the recombination.

An n-side electrode 10 is provided on the back surface (lower surface in the figure) of the semiconductor substrate 1, and the lower cladding layer 2, the active layer 3, the upper cladding layer 4 a, the etching stop layer 5, and the upper portion are formed on the surface of the substrate 1 from the bottom. The cladding layer 4b and the contact layer 6 are successively crystal-grown, and a stripe-shaped resist pattern with a predetermined interval is formed on the contact layer 6, and the layers up to the etching stop layer 5 are etched to form the same layer on the same substrate. A plurality of ridge stripe structures are formed. A p-side electrode 9 is formed on the contact layer 6, and an n-type impurity is introduced into the upper cladding layer 4 a between adjacent semiconductor laser array elements from the stripe groove 15 so that the n-type semiconductor region 7 is formed. Is formed. Reference numeral 8 denotes an insulating film (SiO ₂ ).

  In a semiconductor laser array element having a plurality of oscillation regions on the same substrate, there is a problem that electrical and thermal interference is likely to occur between adjacent elements, and the element characteristics are affected by the operating conditions of the adjacent elements. However, in this embodiment, in order to form the n-type semiconductor region 7 in the upper clad layer 4a made of a p-type semiconductor between adjacent semiconductor laser array elements, the amount of impurities to be introduced and the p-type clad layer 4a By defining the thickness of the n-type semiconductor region 7 quantitatively, a high-resistance region or a reverse conductivity type that reaches a part of the n-type cladding layer between adjacent devices in the conventional semiconductor laser array device The difference in effect from the semiconductor laser array element in which the semiconductor region is formed is clarified. Hereinafter, the embodiment will be described in detail.

  FIG. 2 is a cross-sectional view of a semiconductor laser array element according to an embodiment of the present invention.

The semiconductor substrate 1 is, for example, an n-type GaAs substrate. First, as shown in FIG. 2, an n-AlGaInP cladding layer 2 (n = 3 × 10 ¹⁷ cm ⁻³ , thickness: 2 μm) and an active layer 3 are grown on an n-GaAs substrate 1. The active layer 3 has an undoped MQW (Multiple Quantum Well) layer 3b sandwiched between an undoped AlGaInP lower guide layer 3a and an undoped AlGaInP upper guide layer 3c.

  In the semiconductor laser array device of Example 1, crystal growth by MOVPE (Metal-Organic Vapor Phase Epitaxy) method is used.

  In Example 1, the undoped MQW layer 3b has an MQW structure in which a well layer (well layer) is formed of a GaInP layer and a barrier layer is formed of an AlGaInP layer. For example, the well layer has a thickness of 5 nm, the number of layers is 3, the lattice mismatch rate is + 0.7%, and the barrier layer has a thickness of 4 nm, the number of layers is 4, and the well layer The barrier layer is alternately laminated.

  The undoped AlGaInP lower guide layer 3a and the undoped AlGaInP upper guide layer 3c are also called light guide layers, and the light guide layer can confine the laser beam in the vertical direction. The light guide layer spreads vertically depending on the composition and thickness of the light guide layer. The angle can be controlled.

Next, as shown in FIG. 2, on the active layer 3, a p-AlGaInP first cladding layer 4 a (p = 1 to 5.0 × 10 ¹⁷ cm ⁻³ , thickness: 0.15 to 0.45 μm). P-GaInP etching stop layer 5 (thickness: 10 nm), p-AlGaInP second cladding layer 4b (p = 5 × 10 ¹⁷ cm ⁻³ , thickness: 1.0 to 1.5 μm) and p-GaAs contact The layer 6 (p = 0.2 to 1 × 10 ¹⁹ cm ⁻³ , thickness: 0.2 to 0.7 μm) is sequentially grown.

  Then, a stripe-shaped resist pattern having a predetermined interval X (in this embodiment, the interval X is about 10 to 50 μm) is formed on the p-GaAs contact layer 6, and each layer up to the etching stop layer 5 is etched. To do. Thus, the ridge stripe structure of the semiconductor laser array element shown in FIG. 2 is formed. At this time, the width L of the ridge portion 16 of the semiconductor laser array element is about 2 to 3 μm.

  Next, n-type impurity silicon (Si) is implanted into the p-AlGaInP first cladding layer 4a from the etched stripe stripe portion 15 by a thermal diffusion method at 300 to 800 ° C. for 2 to 120 minutes to form the n-type semiconductor region 7. Then, an n-type semiconductor region 7 is formed in which the distance M in the stacking direction from the boundary surface between the p-AlGaInP first cladding layer 4a and the boundary surface between the p-AlGaInP first cladding layer 4a and the active layer 3 is 20 nm. In addition to the simple process, the thermal diffusion method can control the depth of diffusion with high accuracy, so that a shallow junction as in this embodiment can be formed. Therefore, in this embodiment, the thermal diffusion method is suitably used.

Here, the amount of the n-type impurity to be implanted varies depending on the diffusion temperature and depth of the impurity and can be doped until the crystal of the p-AlGaInP first cladding layer 4a is deteriorated, but the upper limit is about 3 × 10 ¹⁹ cm ⁻³ . It is considered to be. As the impurity to be implanted, sulfur, selenium, tin or the like can be used in addition to Si.

Here, in order not to deteriorate the function of the active layer 3 by the diffusion of the n-type impurity Si, it is considered that the upper limit of the amount of the impurity diffused in the active layer is about 1 × 10 ¹⁶ cm ⁻³ . Furthermore, the boundary surface between the n-type conductive semiconductor region 7 and the active layer 3 is in the vicinity of the active layer 3 and must not reach the active layer 3. For example, the distance M is preferably 100 nm or less. Furthermore, in this embodiment, the distance M is preferably 5 to 60 nm. In the present embodiment, as described above, the distance M is 20 nm, and the thickness Y of the p-AlGaInP first cladding layer 4a is 0.15 to 0.45 μm. Therefore, the thickness of the n-type semiconductor region 7 in the stacking direction. Z secures 50% or more of the above Y.

  In the technique described in Patent Document 3 which is a conventional technique, the distance from the pn junction interface between the p-type cladding layer 104b and the n-type dopant diffusion region 104c to the boundary surface between the p-type cladding layer 104b and the active layer 103 is Since it is 1.4 times or more the thickness of the n-type region 104c formed in the p-type cladding layer 104b in the stacking direction, the thickness of the n-type region 104c is 42 of the thickness of the p-type cladding layer 104b at the maximum. % Is secured, which is insufficient to suppress the spread of current in the lateral direction.

  An example in which the width of the depletion layer is calculated using a step junction model as a diode having an ideal pn junction is shown below. In the case of the step junction, the thickness W in the stacking direction of the depletion layer in the p-type region can be calculated using the following equation.

ここで、ε_０：真空の誘電率（８．８５４１８×１０^−１４Ｆ／ｃｍ）、ε：AlGaInPクラッド層の比誘電率、ｅ：電子の電荷量（１．６×１０^−１９Ｃ）、Ｎ_ａ：ｐ型キャリア濃度、Ｎ_ｄ：ｎ型キャリア濃度、Ｖ_ｂｉ：内部接合電位差である。

Here, ε ₀ : dielectric constant of vacuum (8.885418 × 10 ⁻¹⁴ F / cm), ε: relative dielectric constant of AlGaInP cladding layer, e: charge amount of electrons (1.6 × 10 ⁻¹⁹ C), N _a : p-type carrier concentration, N _d : n-type carrier concentration, V _bi : internal junction potential difference.

Substituting ε = 11.6, Nd = 5 × 10 ¹⁷ cm ⁻³ , N _a = 5 × 10 ¹⁷ cm ⁻³ , and V _bi = 1.9 V as numerical values according to this example, W becomes about 50 nm.

  In the present embodiment, when the thickness Y of the p-AlGaInP first cladding layer 4a is 200 nm and the thickness Z of the n-type semiconductor region 7 is 50% of the lower limit Y, the thickness Z is 100 nm. Then, when the thickness W of the depletion layer is taken into consideration, the effective thickness of the p-type region in the p-AlGaInP first cladding layer 4a is 200 nm-100 nm-50 nm = 50 nm. Therefore, the electrical resistance in the lateral direction is four times or more that in the case where the n-type semiconductor region 7 is not present, and the lateral current can be sufficiently stopped.

On the other hand, when the thickness of the p-type cladding layer 104b in Patent Document 3 is 200 nm and the upper limit of the doping amount as described above is 5 × 10 ¹⁸ cm ⁻³ , the thickness of the n-type region 104c is 200 / (1 + 1). .4) = 83 nm or less, and the remaining effective p-type cladding layer 104b has a thickness of 200 nm−83 nm−50 nm = 67 nm. Therefore, the electrical resistance in the lateral direction is the same as that in the case where the n-type region does not exist. 3 times or less. Further, when the doping amount is 2 × 10 ¹⁸ cm ⁻³ , the distance between the pn junction interface formed in the cladding layer and the active layer is determined by solving the thermal diffusion equation. It can be seen that the thickness is 2.5 times or more. Therefore, since the width of the n-type region is 200 / (1 + 2.5) = 57 nm and the width of the remaining effective p-type region is 200 nm−57 nm−50 nm = 93 nm, the electrical resistance in the lateral direction is doubled. Only to the extent. Therefore, a sufficient effect cannot be expected as compared with the present embodiment.

By forming the n-type semiconductor region 7 in this manner, a reverse bias is applied to the pn junction formed by the p-AlGaInP-type first cladding layer 4a and the n-type semiconductor region 7 when the semiconductor laser element oscillates. The spread of the current in the lateral direction can be completely suppressed by the spread of the depletion layer.
Further, the upper limit of the amount of n-type impurity Si diffused into the active layer 3 needs to be about 1 × 10 ¹⁶ cm ⁻³ , more preferably about 5 × 10 ¹⁵ cm ⁻³ . This is because, when the impurities are diffused, the impurities are continuously distributed, so that the impurities are also distributed in the active layer 3. Therefore, by defining the upper limit of the amount of Si in the active layer 3, the function of the active layer 3 is prevented from deteriorating.

  Next, after the insulating film 8 is deposited by the CVD (Chemical Vapor Deposition) method, the p-side electrode 9 is formed on the contact layer 6, and the back surface of the substrate 1 is about 100 μm thick by mechanical polishing and chemical etching. After grinding to n, the n-side electrode 10 is formed. Thus, the semiconductor laser array element according to Example 1 is completed.

  As described above, when a current is injected from the p-side electrode 9, a reverse bias is applied to the pn junction formed by the n-type semiconductor region 7 and the p-type cladding layer 4a. Due to the spread, the lateral diffusion current can be suppressed and the problem of electrical interference between adjacent elements can be avoided. Further, by providing the n-type semiconductor region 7, the current from the p-side electrode 9 to the active layer 3 can be narrowed to reduce the reactive current that does not contribute to light emission, the oscillation threshold current is small, and the element heat generation is reduced. A semiconductor laser array with reduced thermal interference can be obtained.

  As described above, the AlGaInP-based semiconductor laser array element has been described in the first embodiment. However, the present invention can be applied to a semiconductor laser array element made of a III-V group compound material such as an AlGaAs-based or InGaAsP-based material, and similar effects can be obtained.

1 is a perspective view of a semiconductor laser array element according to an embodiment of the present invention. It is sectional drawing of the semiconductor laser array element which becomes one Example of this invention. It is a figure which shows the example of the conventional semiconductor laser array element. It is a figure which shows the other example of the conventional semiconductor laser array element. It is a figure which shows the other example of the conventional semiconductor laser array element.

Explanation of symbols

1 ... n-GaAs substrate, 2 ... n-AlGaInP cladding layer, 3 ... active layer, 3a ... undoped
AlGaInP lower guide layer, 3b ... undoped MQW layer, 3c ... undoped AlGaInP upper guide layer, 4a ... p-type AlGaInP first cladding layer, 4b ... p-type AlGaInP second cladding layer, 5 ... p-type GaInP etching stop layer, 6 ... p-type GaAs contact layer, 7 ... n-type semiconductor region, 8 ... insulating film, 9 ... p-side electrode, 10 ... n-side electrode, 15 ... stripe groove portion, 16 ... ridge portion.

Claims (4)

At least a first conductivity type semiconductor layer formed on the first conductivity type semiconductor substrate; an active layer having a quantum well structure on the first conductivity type semiconductor layer; a ridge portion on the active layer; and A semiconductor laser array element configured by laminating a second conductivity type semiconductor layer having stripe groove portions on both sides of a ridge portion,
A first conductivity type semiconductor region formed of a first conductivity type semiconductor in the second conductivity type semiconductor layer existing below the stripe groove portion;
The thickness in the stacking direction of the first conductivity type semiconductor region is 50% or more of the thickness in the stacking direction of the second conductivity type semiconductor layer existing below the stripe groove portion. element. The semiconductor laser array device according to claim 1, wherein
The semiconductor laser array element, wherein the first conductivity type semiconductor region exists above the active layer. In the semiconductor laser array element according to claim 1 or 2,
The first conductivity type semiconductor region is formed by injecting impurities from the stripe groove portion,
The amount of the impurity implanted into the second conductivity type semiconductor layer is 3 × 10 ¹⁹ cm ⁻³ or less, and the amount of the impurity diffused into the active layer is 1 × 10 ¹⁶ cm ⁻³ or less. A semiconductor laser array element. The semiconductor laser array element according to any one of claims 1 to 3,
The semiconductor laser array device, wherein the impurity is implanted by a thermal diffusion method.

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