JP2009105068A - Electro-optical device, method for manufacturing electro-optical device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electro-optical device with quality of display improved by restraining generation of display unevenness, and to provide a method for manufacturing the same and an electronic apparatus. <P>SOLUTION: All transparent conductive layers 47 formed at each pixel 20 are made to be electrically connected with a conductive layer ML through contact holes H. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electro-optical device and a method for manufacturing the electro-optical device.

  There is an active matrix driving method as one of driving methods of a display display including a plurality of electro-optical elements such as a liquid crystal element, an organic EL element, an electrophoretic element, and an electron emitting element. Examples of the active matrix driving display include a top emission type display in which the cathode of each electro-optic element is formed of a transparent electrode, and light emitted from the organic EL element is emitted from the cathode side. .

  In this type of display, the transparent electrode is a transparent conductive thin film made of tin-doped indium oxide (ITO) and is formed over the entire surface of the display panel. In general, it is known that a transparent conductive thin film has a higher resistivity than a metal. Accordingly, the potential of the cathode of the electro-optic element varies depending on the position formed on the display panel. As a result, for example, when data signals having the same voltage level are supplied to all the pixels, a difference in luminance occurs depending on the position where the pixels are formed. As a result, so-called display unevenness occurs in the display panel unit. In particular, this display unevenness appears remarkably as the display panel is enlarged.

  For example, the potential of the cathode of the organic EL element OLED of the pixel formed in the central part of the display panel unit may be higher than the potential of the cathode of the organic EL element OLED of the pixel formed in the outer peripheral part. As a result, display unevenness occurs between the central portion and the outer peripheral portion of the display panel portion.

  Therefore, a display having a structure in which a conductive protrusion is provided on the substrate on the anode side of the display panel and the protrusion is connected to a transparent conductive thin film connected to the cathode of the organic EL element. Is known (see, for example, Patent Document 1). By doing in this way, it can suppress that the potential of the cathode of organic EL element OLED produces a difference by the position in which each pixel is formed.

JP 2000-36391 A

  However, it is technically difficult to form the conductive protrusions as described above. The present invention has been made to solve the above problems, and provides an electro-optical device, a method for manufacturing the electro-optical device, and an electronic apparatus that improve display quality by suppressing the occurrence of display unevenness. There is to do.

  An electro-optical device of the present invention includes an anode, a cathode formed at a position facing the anode, and a luminescent material provided between the anode and the cathode on a substrate, In the electro-optical device formed for each pixel provided with the light emitting material, a conductive layer formed between the substrate and the anode, and a connection for electrically connecting the cathode and the conductive layer Department.

  According to this, the said cathode and the said conductive layer were electrically connected through the connection part. Therefore, even if the cathode is a transparent conductive thin film having a relatively high resistivity, such as tin-doped indium oxide (ITO), the potential of the cathode does not vary from pixel to pixel. As a result, it is possible to suppress display unevenness depending on the position where the pixel is formed. Thus, an electro-optical device with excellent display quality can be provided.

In this electro-optical device, the connection portion may be provided for each pixel.
According to this, it is possible to reliably suppress the occurrence of display unevenness for each pixel depending on the position where it is formed.

In this electro-optical device, the connection portion may be formed of a contact hole.
According to this, the said connection part can be formed easily.

  In this electro-optical device, an element forming layer in which an active element for controlling a current supplied to the light emitting material is formed on the substrate is provided, and the element forming layer and the conductive layer are interposed between the element forming layer and the conductive layer. An insulating layer for electrically cutting the element formation layer and the conductive layer may be formed.

  According to this, in the electro-optical device in which the active element is formed above the conductive layer, it is possible to suppress display unevenness depending on the position where the pixel is formed.

In this electro-optical device, the insulating layer may have a thickness of 2ε / 3.5 μm or more, where ε is a dielectric constant.
According to this, the insulating layer was formed so that the film thickness was 2ε / 3.5 μm or more. Therefore, it is possible to reliably prevent the material constituting the conductive layer from diffusing into the active element formed on the insulating layer. Further, the parasitic capacitance formed between the conductive layer and the active element can be reduced, and the drive circuit can be stably operated, thereby improving the display quality of the electro-optical device.

In this electro-optical device, the conductive layer is made of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), vanadium (V), zirconium (Zr), and an alloy or silicide thereof. It may be composed of two.
According to this, a conductive layer can be formed easily.

  In this electro-optical device, the conductive layer may include a plurality of conductive layers including at least one metal layer.

  According to this, for example, a conductive layer formed in contact with another layer among the conductive layers is made of a material in which the material constituting the conductive layer is difficult to diffuse, thereby changing the physical properties of the other layer. You can avoid it.

In this electro-optical device, the substrate includes a base protective layer that protects the substrate, the base protective layer is made of silicon dioxide, and the plurality of conductive layers are first conductive layers in order from the base protective layer, A conductive layer composed of a second conductive layer, wherein the first conductive layer is one of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), and alloys or silicides thereof. The second conductive layer may be made of any one of aluminum (A1), nickel (Ni) and platinum (Pt), and alloys or silicides thereof.
According to this, it is possible to provide an electro-optical device provided with a conductive layer having excellent adhesion to the protective layer and low conductivity.

  In this electro-optical device, a base protective layer for protecting the substrate is provided on the substrate, the protective layer is made of silicon dioxide, and the plurality of conductive layers are arranged in order from the base protective layer, the first conductive layer, The first conductive layer is composed of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), and an alloy or silicide thereof. The second conductive layer is made of copper (Cu), aluminum (A1), nickel (Ni), platinum (Pt), and any one of these alloys or silicides, and the third conductive layer is Titanium nitride (TiN), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), and alloys or silicides thereof may be used.

  According to this, the 1st conductive layer was comprised with titanium (Ti). Therefore, the first conductive layer can be formed in close contact with the base protective layer. Moreover, the 2nd conductive layer was comprised with copper (Cu). Accordingly, the conductivity of the conductive layer can be increased. Furthermore, the third conductive layer was composed of titanium nitride (TiN). Therefore, it is prevented that the copper (Cu) constituting the second conductive layer reacts with the material constituting the layer formed on the third conductive layer, and as a result, the conductivity of the second conductive layer is lowered. can do.

In the electro-optical device, the conductive layer may include a protruding portion that protrudes from the substrate.
According to this, the potential of each cathode can be directly controlled without providing a connection means such as a special interface by directly connecting the protruding conductive layer to various external devices.

  An electro-optical device manufacturing method of the present invention includes an anode, a cathode formed at a position facing the anode, and a luminescent material provided between the anode and the cathode on a substrate. A bank layer for dividing the luminescent material into pixels, a conductive layer formed between the substrate and the anode, and a connection part for electrically connecting the cathode and the conductive layer. An element forming layer on which an active element for controlling a current supplied to the light emitting material is formed on the substrate; and the element forming layer between the element forming layer and the conductive layer; In an electro-optical device manufacturing method comprising an insulating layer for electrically cutting the conductive layer, the step of forming the conductive layer above the substrate, the insulating layer above the conductive layer, Forming the element forming layer, the anode, and the bank layer; Forming a connection portion opening pattern for electrically connecting the cathode and the conductive layer simultaneously with forming an opening pattern in the insulating layer, forming the luminescent material, and connecting Forming a transparent conductive film on the entire surface of the region including the light emitting material.

  According to this, even if the cathode is a transparent conductive thin film having a relatively high resistivity such as tin-doped indium oxide (ITO), it is possible to suppress display unevenness depending on the position where the pixel is formed. An electro-optical device that can be manufactured can be manufactured. In addition, an opening (contact hole, pixel light-emitting region, etc.) is formed in four to six insulating layers, and at the same time, a connection portion (contact hole) for electrically connecting the cathode and the conductive layer is formed. Therefore, a high-quality electro-optical device can be manufactured without changing the process.

In the method of manufacturing the electro-optical device, the conductive layer includes a conductive layer including a first conductive layer, a second conductive layer, and a third conductive layer, and the element formation layer supplies a signal to the active element. A first signal line and a second signal line, wherein the first conductive layer is formed simultaneously with the formation of the first signal line, and the second conductive layer forms the second signal line. It may be formed at the same time.
According to this, the said connection part can be formed easily.

  In the method of manufacturing the electro-optical device, the conductive layer may be formed by a sputtering method.

  According to this, compared with the case where it forms by other methods, such as a vapor deposition method, the film-forming temperature of the said conductive layer can be made low. As a result, it is possible to prevent the substrate or the like from being defective.

The electronic apparatus of the present invention includes the electro-optical device.
According to this, even if the cathode is a transparent conductive thin film having a relatively high resistivity such as tin-doped indium oxide (ITO), an electronic device with excellent display quality can be provided.

It is a block diagram for demonstrating the electrical structure of an organic electroluminescent display. It is a circuit diagram which shows the electrical structure of a display panel part and a data line drive circuit. It is a circuit diagram of a pixel. It is a partial cross section figure of the display panel part in a 1st embodiment. (A), (b), (c) is a figure for demonstrating the manufacturing method of the display panel part of 1st Embodiment. (A), (b), (c) is a figure for demonstrating the manufacturing method of the display panel part of 1st Embodiment. (A), (b) is a figure for demonstrating the manufacturing method of the display panel part of 1st Embodiment. It is a figure for demonstrating the manufacturing method of the display panel part of 1st Embodiment. (A), (b) is a figure for demonstrating the manufacturing method of the display panel part of 1st Embodiment. (A), (b) is a figure for demonstrating the manufacturing method of the display panel part of 1st Embodiment. It is a partial cross section figure of the display panel part in a 2nd embodiment. (A), (b), (c) is a figure for demonstrating the manufacturing method of the display panel part of 2nd Embodiment. (A), (b), (c) is a figure for demonstrating the manufacturing method of the display panel part of 2nd Embodiment. (A), (b) is a figure for demonstrating the manufacturing method of the display panel part of 2nd Embodiment. It is a perspective view which shows the structure of the mobile type personal computer for demonstrating 3rd Embodiment.

Embodiments in which the present invention is applied to a liquid crystal display device will be described below with reference to the drawings. Each embodiment shows one mode of the present invention, does not limit the present invention, and can be arbitrarily changed within the scope of the technical idea of the present invention. Furthermore, in each figure shown below, in order to make each layer and each member large enough to be recognized on the drawing, the scale is varied for each layer and each member.
(First embodiment)
1st Embodiment which actualized this invention is described according to FIGS. FIG. 1 is a block diagram for explaining an electrical configuration of an organic EL display. FIG. 2 is a circuit diagram showing an electrical configuration of the display panel unit and the data line driving circuit. FIG. 3 is a circuit diagram of a pixel in this embodiment. FIG. 4 is a partial cross-sectional view of the display panel unit in the present embodiment.

  As shown in FIG. 1, the organic EL display 10 includes a signal generation circuit 11, a display panel unit 12, a scanning line driving circuit 13, and a data line driving circuit 14. The signal generation circuit 11, the scanning line driving circuit 13, and the data line driving circuit 14 of the organic EL display 10 may be configured by independent electronic components. For example, each of the signal generation circuit 11, the scanning line driving circuit 13, and the data line driving circuit 14 may be configured by a one-chip semiconductor integrated circuit device. Further, all or a part of the signal generation circuit 11, the scanning line driving circuit 13, and the data line driving circuit 14 may be configured by a programmable IC chip, and the function may be realized by software by a program written in the IC chip. Good.

The signal generation circuit 11 receives a clock pulse CP and image digital data D supplied from an external device (not shown). The signal generation circuit 11 generates a horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC based on the clock pulse CP.
The signal generation circuit 11 outputs the generated horizontal synchronization signal HSYNC to the scanning line driving circuit 13 and outputs the vertical synchronization signal VSYNC to the data line driving circuit 14. Further, the signal generation circuit 11 outputs the image digital data D to the data line driving circuit 14.

  As shown in FIG. 2, the display panel unit 12 includes n scanning lines Y1, Y2,..., Yn extending along the row direction. Further, the display panel unit 12 includes m data lines X1, X2,..., Xm extending along the column direction. The scanning lines Y1, Y2,..., Yn are in order of the first scanning line Y1, the second scanning line Y2,..., The nth scanning line Yn from the upper side to the lower side of the display panel unit 12 in the figure. Is provided. Pixels 20 are formed at positions corresponding to the intersections of the scanning lines Y1, Y2,..., Yn and the data lines X1, X2,.

  Furthermore, the display panel unit 12 includes m power lines Lo extending in parallel with the data lines X1, X2,. The power supply voltage Vo is supplied to all the power supply lines Lo.

  Each pixel 20 is connected to the scanning line driving circuit 13 via a corresponding scanning line Y1, Y2,. Each pixel 20 is connected to the data line driving circuit 14 via corresponding data lines X1, X2,..., Xm. Further, each pixel 20 is connected to a power supply line Lo.

  Each of the pixels 20 includes a driving transistor Qd, a switching transistor Qsw, a holding capacitor Co, and an organic EL element OLED, as shown in FIG. FIG. 3 is an equivalent circuit diagram of the pixel 20 formed at a position corresponding to the intersection of the nth scanning line Yn and the mth data line Xm. Since all the electrical configurations of the respective pixels 20 are the same, only the pixels 20 formed at positions corresponding to the intersections of the nth scanning line Yn and the mth data line Xm will be described below for convenience of explanation. The description of other pixels 20 will be omitted.

  The drive transistor Qd is usually composed of a TFT (Thin Film Transistor). The drive transistor Qd has a P-type conductivity in this embodiment. The conductivity type of the switching transistor Qsw is N-type in this embodiment.

  The source of the switching transistor Qsw is connected to the data line Xm. The gate of the switching transistor Qsw is connected to the scanning line Yn. The drain of the switching transistor Qsw is connected to the gate of the driving transistor Qd. A holding capacitor Co is connected between the gate and source of the driving transistor Qd. The source of the driving transistor Qd is connected to the power supply line Lo. The drain of the driving transistor Qd is connected to the anode E1 of the organic EL element OLED.

  In the pixel 20 configured as described above, the cathode E2 of the organic EL element OLED is electrically connected through the contact hole H to the common cathode with other organic EL elements. The cathode E2 is connected to a connection port Po for connecting to an external device (not shown).

  The scanning line driving circuit 13 generates scanning signals SC1, SC2,. Each of the scanning signals SC1, SC2,..., SCn is a voltage signal having an L level and an H level. Further, the scanning line driving circuit 13 sequentially drives the scanning lines Y1, Y2,..., Yn by sequentially outputting H level scanning signals to the respective scanning lines Y1, Y2,..., Yn according to the horizontal synchronization signal HSYNC. .

  As shown in FIG. 2, the data line driving circuit 14 includes a plurality of single line drivers 14a. Each of the plurality of single line drivers 14a is connected to a corresponding data line X1, X2,. Each single line driver 14a receives the image digital data D output from the signal generation circuit 11. Each single line driver 14a creates data signals D1, D2,..., Dm, which are analog voltage signals of a level corresponding to the magnitude of the input image digital data D. The single line driver 14a receives the data signals D1, D2,..., Dm through the corresponding data lines X1, X2,..., Xm according to the vertical synchronization signal VSYNC output from the signal generation circuit 11. Output to 20 at once.

  When the scanning line driving circuit 13 outputs an H level scanning signal to one scanning line among the scanning lines Y1, Y2,..., Yn in accordance with the horizontal synchronization signal HSYNC, one line connected to the scanning line is output. Each of the switching transistors Qsw of all the pixels 20 is turned on. At this time, the data signals D1, D2,..., Dm are simultaneously output from the single line drivers 14a of the data line driving circuit 14 through the corresponding data lines X1, X2,. Then, a data signal is supplied to each holding capacitor Co of all the pixels 20 of the one row where the switching transistor Qsw is turned on. As a result, the internal state (charge amount of the holding capacitor Co) of the pixel 20 is set in the pixel 20 according to the data signal, and the conductivity of the driving transistor Qd is controlled accordingly. As a result, a driving current Iel having a level corresponding to the conductivity is supplied to the organic EL element OLED, and the organic EL element OLED emits light with a luminance corresponding to the current level of the driving current Iel.

  Thereafter, the data signals D1, D2,..., Dm are supplied to the respective pixels 20 by sequentially selecting the respective scanning lines Y1, Y2,..., Yn, and each organic EL element OLED corresponds to the current level of the drive current Iel. Emits light with high brightness. In this way, an image corresponding to the data signals D1, D2,..., Dm is displayed on the display panel unit 12.

  Next, the structure of the display panel unit 12 will be described with reference to FIG. FIG. 4 is a partial cross-sectional view of the display panel unit 12 including the drive transistor Qd and the organic EL element OLED. The cross-sectional view shown in FIG. 4 corresponds to a cross section taken along line AA in FIG.

As shown in FIG. 4, a base protective layer 31 made of silicon dioxide (SiO ₂ ) is formed on the glass substrate 30. A first conductive layer M <b> 1 is formed on the entire surface of the glass substrate 30 on the base protective layer 31. The first conductive layer M1 is made of a material having high conductivity and excellent adhesion with the base protective layer 31. The first conductive layer M1 of the present embodiment is made of titanium (Ti), which is a metal having excellent adhesion with silicon dioxide (SiO ₂ ). A second conductive layer M2 is formed on the first conductive layer M1.

  The second conductive layer M2 is made of a material having high conductivity. The second conductive layer M2 of this embodiment is made of copper (Cu). A third conductive layer M3 is formed on the second conductive layer M2.

The third conductive layer M3 is made of a material having high conductivity and suppressing diffusion of the material constituting the second conductive layer M2 into the base insulating film 32 formed on the third conductive layer M3. . By forming the third conductive layer M3 between the second conductive layer M2 and the base insulating film 32, the material forming the second conductive layer M2 reacts with the material forming the base insulating film 32, and the As a result, it is possible to prevent the physical properties of the second conductive layer M2 from changing and the conductivity thereof from decreasing or the insulating properties of the base insulating film 32 from decreasing. The third conductive layer M3 of the present embodiment is made of titanium nitride (TiN), which is a metal that is difficult to diffuse into silicon dioxide (SiO ₂ ). In the present embodiment, the first to third conductive layers M1, M2, and M3 constitute a conductive layer ML.

In addition, one end (right side in the figure) of the conductive layer ML protrudes outward. The protruding conductive layer ML corresponds to the connection port Po.
Except for the position where the contact hole H is formed on the third conductive layer M3, the third conductive layer M3 and the silicon layer 33, which will be described later, constituting the drive transistor Qd formed on the third conductive layer M3, data A base insulating film 32 for electrically insulating the lines X1, X2,..., Xm and the scanning lines Y1, Y2,. The base insulating film 32 is formed so as to have a thickness of 2ε / 3.5 μm or more. Here, ε is the dielectric constant of the material constituting the base insulating film 32. Thus, by setting the film thickness to 2ε / 3.5 μm or more, the silicon layer 33 formed on the base insulating film 32, the data lines X1, X2,..., Xm, the scanning lines Y1, Y2,. It is possible to reliably prevent the material constituting the conductive layer ML from diffusing. Further, the parasitic capacitance generated between the conductive layer ML, the silicon layer 33, the data lines X1, X2,..., Xm and the scanning lines Y1, Y2,. Quality can be improved. In the present embodiment, the base insulating film 32 is made of silicon dioxide (SiO ₂ ), but may be silicon nitride, silicon oxynitride, or other materials.

On the base insulating film 32, an island-shaped silicon layer 33 made of polycrystalline silicon is formed at a predetermined position. A gate insulating film 34 made of silicon dioxide (SiO ₂ ) or silicon nitride (SiN) is formed on the silicon layer 33 and the base insulating film 32. A gate electrode 35 is formed on the silicon layer 33 with the gate insulating film 34 interposed therebetween.

  A region of the silicon layer 33 facing the gate electrode 35 through the gate insulating film 34 is a channel region 33C. In the silicon layer 33, a low concentration drain region 33LD and a high concentration drain region 33HD are formed on the left side of the channel region 33C in the drawing. On the other hand, in the silicon layer 33, a low concentration source region 33LS and a high concentration source region 33HS are formed on the right side of the channel region 33C in the drawing.

On the gate electrode 35 and the gate insulating film 34, a first interlayer insulating film ID1 made of silicon dioxide (SiO ₂ ) is formed. A source electrode 36 and a drain electrode 37 are formed on the first interlayer insulating film ID1 at positions facing the high concentration source region 33HS and the high concentration drain region 33HD of the silicon layer 33, respectively. The gate insulating film 34 and the first interlayer insulating film ID1 are formed with first and second electrode contact holes C1 and C2 which are opened through the both. A conductive material such as copper (Cu) or aluminum (Al) is buried in the first and second electrode contact holes C1 and C2. Therefore, the source electrode 36 is electrically connected to the high concentration source region 33HS of the silicon layer 33 through the first electrode contact hole C1. The drain electrode 37 is electrically connected to the high concentration drain region 33HD of the silicon layer 33 through the second electrode contact hole C2.

The silicon layer 33, the gate electrode 35, the source electrode 36, and the drain electrode 37 constitute a drive transistor Qd.
A second interlayer insulating film ID2 made of silicon dioxide (SiO ₂ ) is formed on the first interlayer insulating film ID1. A planarization insulating film 40 is formed on the second interlayer insulating film ID2.

  The planarization insulating film 40 is made of an insulating material made of an organic material. The planarization insulating film 40 is formed of photosensitive polyimide in this embodiment. Further, the planarization insulating film 40 is formed so as to have a film thickness of 2000 nm in this embodiment. By forming the planarization insulating film 40, the light emitting layer 44 formed on the planarization insulating film 40 can be planarized. On the planarizing insulating film 40, a first electrode layer 41a made of a conductive material and a first bank layer 42a made of an inorganic material are formed.

  The first electrode layer 41a is an electrode layer corresponding to the anode E1 of the organic EL element OLED. In the present embodiment, the first electrode layer 41a is made of chromium (Cr). The first electrode layer 41a is connected to the drain electrode 37 through an anode contact hole Ca formed by opening the planarization insulating film 40 and the second interlayer insulating film ID2, respectively. The drain electrode 37 is electrically connected. The anode contact hole Ca is filled with the same material as the conductive material constituting the first electrode layer 41a. Accordingly, the drain electrode 37 is electrically connected to the first electrode layer 41a through the anode contact hole Ca. Further, a hole injection layer 43 and a light emitting layer 44 made of an organic material that emits light are stacked on the first electrode layer 41a.

The first bank layer 42 a partitions the hole injection layer 43 and the light emitting layer 44 from the hole injection layer and the light emitting layer formed adjacent to the hole injection layer 43 and the light emitting layer 44. The first bank layer 42a is made of a hydrophilic and insulating material. The first bank layer 42a is composed of an inorganic material SiO _2, TiO _2, SiN or the like. The first bank layer 42a is formed on the peripheral edge of the first electrode layer 41a. A second bank layer 42b is formed on the first bank layer 42a.

  Similar to the first bank layer 42 a, the second bank layer 42 b includes a hole injection layer 43 and a light emitting layer 44, and a hole injection layer and a light emitting layer formed adjacent to the hole injection layer 43 and the light emitting layer 44. Partition between layers. A region defined by the first and second bank layers 42 a and 42 b corresponds to one pixel 20. A contact hole H is provided in the second bank layer 42b. The contact hole H is formed through the first and second bank layers 42a and 42b, the planarization insulating film 40, the first and second interlayer insulating films ID1 and ID2, the gate insulating film 34, and the base insulating film 32, respectively. Has been. Therefore, the contact hole H of this embodiment is continuously opened up to the third conductive layer M3 constituting the conductive layer ML.

  An electron injection layer 46 is formed over the entire surface of the light emitting layer 44, the first bank layer 42 a and the second bank layer 42 b, and the contact hole H. The electron injection layer 46 is made of a transparent material. A transparent conductive layer 47 made of a transparent material is formed on the electron injection layer 46. The transparent conductive layer 47 is an electrode layer corresponding to the cathode E2 of the organic EL element OLED. Therefore, the transparent conductive layer 47 (the cathode E2 of the organic EL element OLED) is electrically connected to the third conductive layer M3 constituting the conductive layer ML via the electron injection layer 46.

  The transparent conductive layer 47 is made of tin-doped indium oxide (ITO) in this embodiment. The first electrode layer 41a, the transparent conductive layer 47, the hole injection layer 43, the light emitting layer 44, and the light emitting layer 44 formed at a position sandwiched between the first electrode layer 41a and the transparent conductive layer 47, and The electron injection layer 46 constitutes the organic EL element OLED.

  A thin film sealing layer 41 b made of a transparent material is formed on the transparent conductive layer 47. The thin film sealing layer 41b is made of a transparent inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc., which blocks the influence of moisture and oxygen in the air and deteriorates the characteristics of the organic EL element OLED. To prevent. A sealing substrate 50 made of transparent glass is formed on the thin film sealing layer 41b with a transparent adhesive 49 interposed therebetween.

  The display panel unit 12 is a so-called top emission type organic EL display in which light emitted from the light emitting layer 44 is emitted from the sealing substrate 50 facing the glass substrate 30.

  In the display panel unit 12 configured as described above, all the cathodes E2 of the organic EL elements OLED formed in each pixel 20 are electrically connected to the conductive layer ML through the contact holes H. As described above, the conductive layer ML is configured by stacking the first, second, and third conductive layers M1, M2, and M3 having high conductivity. Accordingly, the potential of the cathode E2 of the organic EL element OLED formed in each pixel 20 is all equal to the potential of the conductive layer ML. As a result, the potential of the cathode E2 of the organic EL element OLED does not differ depending on the position formed on the display panel unit 12. That is, for example, when the data signals D1, D2,..., Dm having the same voltage level are supplied to all the pixels 20, there is no difference in the luminance of the organic EL element OLED depending on the position where the pixels 20 are formed. Accordingly, display unevenness can be reduced.

  Therefore, even if the cathode E2 is a top emission type organic EL display composed of a transparent material such as tin-doped indium oxide (ITO) having a relatively low conductivity (relatively high resistivity), the data signal D1, Images corresponding to D2,..., Dm can be displayed with high accuracy.

Further, it is possible to omit the connection area with the cathode E2 that has been formed on the outer edge and outer periphery of the display area in the past, thereby realizing a narrow frame of the display device.
Further, one end of the conductive layer ML protrudes directly from the display panel unit 12 to the outside. The protruding conductive layer ML is used as the connection port Po. Accordingly, by connecting various external devices to the connection port Po, the potential of each cathode E2 of the organic EL element OLED can be directly controlled without providing a connection means such as a special interface.

  Next, the manufacturing method of the organic EL display 10 of this embodiment is demonstrated according to FIGS. 5 to 10 are cross-sectional views of the display panel unit 12 including the pixels 20 shown in FIG.

As shown in FIG. 5A, first, a base protective layer 31 made of silicon dioxide (SiO ₂ ) is formed on a glass substrate 30 using a plasma CVD method. Thereafter, a thin film of titanium (Ti) / copper (Cu) / titanium nitride (TiN) is sequentially formed over substantially the entire surface of the glass substrate 30 except for the left end portion in the drawing by using a sputtering method (FIG. 5B). )reference). In this embodiment, the thickness of the thin film made of titanium (Ti) is 100 nm, the thickness of the thin film made of copper (Cu) is 500 nm, and the thickness of the thin film made of titanium nitride (TiN) is 100 nm. It is. The thin film made of titanium (Ti) corresponds to the first conductive layer M1, the thin film made of copper (Cu) corresponds to the second conductive layer M2, and is made of titanium nitride (TiN). The constituted thin film corresponds to the third conductive layer M3. In addition, by forming the first to third conductive layers M1, M2, and M3 by using the sputtering method in this way, the film formation temperature can be lowered as compared with the case of forming by other methods such as vapor deposition. Can do. As a result, it is possible to prevent the glass substrate 30 and the base protective layer 31 from being defective due to heating.

Subsequently, as shown in FIG. 5C, a base insulating film 32 is formed by laminating silicon dioxide (SiO ₂ ) on the third conductive layer M3 using a CVD method or the like. At this time, the base insulating film 32 is formed to have a thickness of 2ε / 3.5 μm or more. Thereafter, the amorphous silicon layer AS is formed using a plasma CVD method or the like, and then crystal grains are grown by a laser annealing method or a rapid heating method to form polycrystalline silicon. Then, as shown in FIG. 6A, the polycrystalline silicon is patterned by photolithography to form an island-shaped silicon layer 33. Subsequently, a gate insulating film 34 having a film thickness of about 30 nm to 200 nm made of silicon dioxide (SiO ₂ ) is formed on the silicon layer 33 and the base insulating film 32. The gate insulating film 34 is formed by a plasma CVD method, a thermal oxidation method, or the like.

Next, as shown in FIG. 6B, an ion implantation selection mask MS1 is formed on the gate insulating film 34. In this state, phosphorus ions (P) are implanted at a dose of about 1 × 10 ¹⁵ cm ^−2. To do. As a result, a high concentration source region 33HS and a high concentration drain region 33HD are formed in the silicon layer 33, respectively.

Next, after the ion implantation selection mask MS1 is removed by ashing, an aluminum (Al) film having a thickness of about 500 nm is formed on the gate insulating film.
Then, the gate electrode 35 shown in FIG. 6C is formed by patterning the aluminum (Al) film. The gate electrode 35 corresponds to the gate of the driving transistor Qd.

Subsequently, phosphorus ions (P) are ion-implanted into the silicon layer 33 with a dose of about 4 × 10 ¹³ cm ^{−2 using} the gate electrode 35 as a mask. As a result, as shown in FIG. 7A, a lightly doped source region 33LS and a lightly doped drain region 33LD are formed in the silicon layer 33.

Next, a first interlayer insulating film ID1 made of silicon dioxide (SiO ₂ ) is formed over the entire surface on the gate insulating film 34 and the gate electrode 35. Subsequently, by photolithography and etching, as shown in FIG. 7A, the first electrode contact hole C1 is formed at a position corresponding to the source electrode 36 of the driving transistor Qd, and the first electrode contact hole C1 is formed at a position corresponding to the drain electrode 37. A two-electrode contact hole C2 is formed. Then, a conductive layer made of a conductive material such as copper (Cu) or aluminum (Al) is formed and patterned on the first interlayer insulating film ID1, thereby forming the first and second electrodes previously formed. The contact holes C1 and C2 are filled with a conductive material, and a source electrode 36 is formed at a position corresponding to the high concentration source region 33HS, and a drain electrode 37 is formed at a position corresponding to the high concentration drain region 33HD. The source electrode 36 and the drain electrode 37 are formed so as to have a thickness of about 200 nm to 800 nm, respectively. Further, by performing a dry etching process, a contact hole H opened through the first interlayer insulating film ID1, the gate insulating film 34, and the base insulating film 32 is formed. That is, the contact hole H is formed so as to reach the third conductive layer M3 constituting the conductive layer ML.

Further, a second interlayer insulating layer made of silicon dioxide (SiO ₂ ) on the first interlayer insulating film ID1, the source electrode 36, the drain electrode 37, the conductive layer M (right end in the figure) and in the contact hole H, respectively. A film ID2 is formed. The second interlayer insulating film ID2 is desirably formed so as to have a thickness of about 100 nm to 2 μm. Thereafter, a planarizing insulating film 40 is formed on the second interlayer insulating film ID2 by applying photosensitive polyimide, drying, exposing, developing, and baking.

Thereafter, dry etching is performed using the planarization insulating film 40 as a mask so that the planarization insulation film 40 and the first and second interlayer insulation films ID1 and ID2 are opened at positions corresponding to the drain electrode 37, respectively. Hole Ca is formed.
Further, chromium (Cr) is embedded in the anode contact hole Ca by using a sputtering method or the like.

  After that, as shown in FIG. 7B, the first interlayer insulating film ID1 and the chrome (Cr) embedded in the anode contact hole Ca are patterned at predetermined positions on the first interlayer insulating film ID1 and made of chrome (Cr). The first electrode layer 41a is formed. As a result, the first electrode layer 41a is electrically connected to the drain electrode 37 via the anode contact hole Ca. Further, by performing dry etching or the like, the second interlayer insulating film ID2 formed in the contact hole H and on the conductive layer M (right end side in the figure) is deleted.

Next, as shown in FIG. 8, an inorganic film such as SiO ₂ , TiO ₂ , SiN or the like is formed on the planarization insulating film 40 and the first electrode layer 41a by using a CVD method, a sputtering method, a vapor deposition method, or the like. To do. Then, the first bank layer 42a is formed by patterning the opening in the inorganic film so that a part of the first electrode layer 41a is exposed. The first bank layer 42a is formed to have a thickness of about 50 nm.

  Subsequently, a second bank layer 42b is formed on the first bank layer 42a excluding the end portion. The second bank layer 42b is formed by applying a normal photosensitive resin such as an acrylic resin or a polyimide resin to the entire surface of the substrate with a spin coater or a slit coater, drying it with a hot plate or oven, and then passing it through a photomask having a predetermined pattern. It is formed by exposing to light, removing unnecessary resin with a developer, and baking at 200 to 400 ° C. Here, openings are formed in a region where a pixel is formed and a region where a contact hole H reaching the conductive layer ML is formed. The thickness of the second bank layer 42b is preferably in the range of 0.1 to 3.5 [mu] m, particularly about 2 [mu] m. If the thickness of the second bank layer 42b is less than 0.1 μm, the second bank layer 42b may be thinner than the total thickness of the hole injection layer 43 and the light emitting layer 44, and the light emitting layer 44 may overflow from the upper opening. This is not preferable. On the other hand, if the film thickness exceeds 3.5 μm, a step due to the upper opening becomes large, and the transparent conductive layer 47 formed on the second bank layer 42b may be disconnected.

  Further, as shown in FIG. 8, a region is formed in which the conductive layer ML protrudes outward. The portion of the conductive layer ML protruding outward becomes the connection port Po. In this way, the connection port Po is formed.

  Thereafter, a region showing lyophilicity and a region showing liquid repellency are formed on the surfaces of the first and second bank layers 42a and 42b. In this embodiment, each region is formed by a plasma treatment process. Specifically, the plasma treatment step includes a lyophilic step for making the first electrode layer 41a and the first bank layer 42a lyophilic and a lyophobic step for making the second bank layer 42b lyophobic. At least.

Specifically, the glass substrate 30 on which the first and second bank layers 42a and 42b are formed is heated to a predetermined temperature (for example, about 70 to 80 ° C.), and then plasma using oxygen as a reaction gas under atmospheric pressure as a lyophilic process. Processing (O ₂ plasma processing) is performed. Subsequently, as a lyophobic step, plasma treatment using CF ₄ as a reactive gas (CF ₄ plasma treatment) is performed under atmospheric pressure, and the glass substrate 30 heated for the plasma treatment is cooled to room temperature. The surface of the first bank layer 42a is made lyophilic and the surface of the second bank layer 42b is made lyophobic.

  Thereafter, a hole injection layer 43 and a light emitting layer 44 are formed on the first electrode layer 41a by an ink jet method (see FIG. 9A). Specifically, the light emitting layer 44 discharges and dries the composition ink containing the predetermined material for forming the light emitting layer 44 after discharging and drying the composition ink containing the predetermined material for forming the hole injection layer 43. Is formed. The composition ink is reliably applied to the pixels 20 constituted by the first and second bank layers 42a and 42b by the liquid repellency and liquid repellency. In addition, it is preferable to carry out after the formation process of this light emitting layer 44 in inert gas atmosphere, such as nitrogen atmosphere or argon atmosphere, in order to prevent oxidation and moisture absorption of the hole injection layer 43 and the light emitting layer 44. FIG.

  Subsequently, as shown in FIG. 9B, the light emitting layer 44 excluding the connection port Po, the first bank layer 42a and the second bank layer 42b, and the electron injection layer 46 are formed over the entire surface of the contact hole H. To do. The electron injection layer 46 is a transparent material and is formed by a heating vapor deposition method. Thereafter, as shown in FIG. 10A, a transparent conductive layer 47 made of a transparent material is formed on the electron injection layer 46 by a method such as sputtering, vacuum deposition, or CVD. This transparent conductive layer 47 is an electrode layer constituting the cathode E2 of the organic EL element OLED. Therefore, the transparent conductive layer 47 (the cathode E2 of the organic EL element OLED) is electrically connected to the third conductive layer M3 constituting the conductive layer ML via the electron injection layer 48.

The transparent conductive layer 47 is made of tin-doped indium oxide (ITO) in this embodiment.
On the transparent conductive layer 47, a thin film sealing layer 41b made of a transparent material is formed. In the present embodiment, the thin film sealing layer 41b is made of silicon oxynitride (SiO _x N _y ) and is formed by a known appropriate method such as a sputtering method or a CVD method. However, when a thin film sealing layer is formed on the connection port Po, it becomes impossible to conduct. Therefore, when forming the thin film sealing layer 41b, it is preferable to take means such as covering the connection port Po with a metal mask. The thin film sealing layer 41b is also formed on the conductive layer ML on the right end side in the drawing constituting the connection port Po.

  Finally, as shown in FIG. 10B, a transparent adhesive made of an epoxy resin or the like is applied to almost the entire surface of the glass substrate 30 excluding the outer periphery of the substrate, the mounting terminal connection portion (not shown), and the connection port Po. Application is performed and the sealing substrate 50 is bonded. In this way, the display panel unit 12 is manufactured.

  The substrate, the electro-optical device, the connection unit, and the active element described in the claims correspond to the glass substrate 30, the organic EL display 10, the contact hole H, and the driving transistor Qd in the present embodiment, respectively. The element formation layer recited in the claims corresponds to the first interlayer insulating film ID1 or the gate insulating film 34 in the present embodiment. The insulating layer recited in the claims corresponds to the base insulating film 32 in the present embodiment. Further, the protruding portion and the transparent conductive film described in the claims correspond to the connection port Po and the transparent conductive layer 47 in the present embodiment, respectively. Further, the bank layer recited in the claims corresponds to the first bank layer 42a or the second bank layer 42b in the present embodiment. Further, the metal layer described in the claims corresponds to the second conductive layer M2 in the present embodiment.

According to the embodiment, the following features can be obtained.
(1) In the above embodiment, all the cathodes E2 of the organic EL elements OLED formed in each pixel 20 are electrically connected to the conductive layer ML through the contact holes H. As a result, the potential of the cathode E2 of the organic EL element OLED does not differ depending on the position formed on the display panel unit 12. That is, for example, when the data signals D1, D2,..., Dm having the same voltage level are supplied to all the pixels 20, there is no difference in the luminance of the organic EL element OLED depending on the position where the pixels 20 are formed. Accordingly, display unevenness can be reduced.

  Therefore, even if the cathode E2 is a top emission type organic EL display composed of a transparent material such as tin-doped indium oxide (ITO) having a relatively low conductivity (relatively high resistivity), the data signal D1, Images corresponding to D2,..., Dm can be displayed with high accuracy.

  (2) In the embodiment, one end of the conductive layer ML projects directly outward from the display panel unit 12. The protruding conductive layer ML is used as the connection port Po. Accordingly, by connecting various external devices to the connection port Po, the potential of each cathode E2 of the organic EL element OLED can be directly controlled without providing a connection means such as a special interface.

  (3) In the said embodiment, the 1st conductive layer M1 was comprised with titanium (Ti). Therefore, the first conductive layer M1 can be formed with good adhesion to the base protective layer 31. Moreover, the 2nd conductive layer M2 was comprised with copper (Cu). Accordingly, since the conductivity of the conductive layer ML can be increased, it is possible to suppress the occurrence of a potential difference depending on the position where the cathode E2 is formed on the display panel unit 12 accordingly.

Further, the third conductive layer M3 was made of titanium nitride (TiN). Copper (Cu) constituting the second conductive layer M2 reacts with (SiO ₂ ) constituting the base insulating film 32, and as a result, the conductivity of the second conductive layer M2 decreases or the base insulating film 32 It is possible to prevent the insulation from deteriorating.

  (4) In the embodiment, the base protective layer 31, the conductive layer ML, the base insulating film 32, the gate insulating film 34, the first and second interlayer insulating films ID1, ID2, and the planarizing insulating film 40 are formed on the glass substrate 30. Formed. Then, after the planarization insulating film 40 is formed, the first and second bank layers 42a and 42b are formed, and dry etching treatment is performed, so that the previously formed base insulating film 32, gate insulating film 34, first Each of the first and second interlayer insulating films ID1 and ID2 and the first bank layer 42a was removed to form a contact hole H. Thereafter, an electron injection layer 46 and a transparent conductive layer 47 were sequentially formed on the contact hole H.

  By doing in this way, the transparent conductive layer 47 and the conductive layer ML can be electrically connected. As a result, the organic EL display 10 with reduced display unevenness can be manufactured.

  (5) In the said embodiment, the 1st-3rd conductive layers M1, M2, M3 were each formed using the sputtering method. Therefore, the film formation temperature can be lowered as compared with the case of forming by other methods such as vapor deposition. As a result, it is possible to prevent the glass substrate 30 and the base protective layer 31 from being defective.

(6) In the above embodiment, the base insulating film 32 is formed so that the film thickness is 2ε / 3.5 μm or more. Therefore, it is ensured that the material constituting the conductive layer ML diffuses into the silicon layer 33 formed on the base insulating film 32, the data lines X1, X2,..., Xm and the scanning lines Y1, Y2,. Can be prevented. Further, the parasitic capacitance generated between the conductive layer ML, the silicon layer 33, the data lines X1, X2,..., Xm and the scanning lines Y1, Y2,. Quality can be improved.
(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS.
First, the structure of the display panel unit according to the second embodiment of the present invention will be described with reference to FIG. FIG. 11 corresponds to a cross section taken along the line AA in FIG. 3 of the first embodiment.

  The display panel unit 12a according to the present embodiment is the same as the first embodiment except that the structure for electrically connecting the contact hole Hr and the third conductive layer M3 and the manufacturing method thereof are different. . Therefore, the detailed description is omitted except for the structure for electrically connecting the contact hole Hr and the third conductive layer M3 and the manufacturing method thereof.

As shown in FIG. 11, the display panel portion 12 a is formed with a third contact hole C <b> 3 that is opened by communicating the base insulating film 32 and the gate insulating film 34.
The third contact hole C3 is filled with the same material as the conductive material that forms the gate electrode 35 that forms the drive transistor Qd. In addition, the conductive material buried in the third contact hole C3 is formed on a part of the gate insulating film 34. The conductive material formed on part of the gate insulating film 34 becomes the first contact part CON1. A fourth contact hole C4 that opens the first interlayer insulating film ID1 formed on the gate insulating film 34 is formed at a position corresponding to the first contact portion CON1.

  In the fourth contact hole C4, the same material as the conductive material constituting the source electrode 36 or the drain electrode 37 constituting the driving transistor Qd is buried. Further, the conductive material buried in the fourth contact hole C4 is formed so as to run over a part on the first interlayer insulating film ID1. The conductive material formed on a part of the first interlayer insulating film ID1 becomes the second contact part CON2. A contact hole Hr formed through the first and second bank layers 42a and 42b, the planarization insulating film 40, and the second interlayer insulating film ID2 is provided at a position corresponding to the second contact part CON2. ing. In the contact hole Hr, as described in the first embodiment, the electron injection layer 46, the transparent conductive layer 47, and the thin film sealing layer 41b are sequentially formed. Accordingly, the transparent conductive layer 47 is electrically connected to the conductive layer ML through the second contact part CON2 and the first contact part CON1. As a result, the same effect as that of the first embodiment can be obtained.

  Next, the manufacturing method of the organic EL display 10 of this embodiment is demonstrated according to FIGS. Only the manufacturing method of the portion that electrically connects the contact hole H and the conductive layer ML will be described, and the same structure as the other first embodiment is denoted by the reference numeral, and the details of the manufacturing method are omitted.

  First, a base protective layer 31, first, second, and third conductive layers M1, M2, and M3, a base insulating film 32, a silicon layer 33, and a gate insulating film 34 are sequentially formed on the glass substrate 30, and then FIG. As shown in a), a mask Mr1 having an opening Qr1 is provided between the silicon layer 33 and a silicon layer 33a (a silicon layer formed on the left side in the drawing) formed adjacent to the silicon layer 33. Subsequently, by performing a dry etching process, as shown in FIG. 12B, the gate insulating film 34 and the base insulating film 32 corresponding to the opening Qr1 are removed to form a third contact hole C3. . At the same time, the gate insulating film 34 and the base insulating film 32 at a position (right end in the figure) facing a connection port Po described later are also removed.

Thereafter, a mask Mr2 having openings Qr2 and Qr3 is provided in a region corresponding to the channel region 33C and the third contact hole C3 of the silicon layer 33. Subsequently, an aluminum (Al) film is formed by sputtering or the like. Thereafter, the mask Mr2 is removed to form the gate electrode 35 and the first contact part CON1 made of aluminum (Al) and having a thickness of about 500 nm (see FIG. 12C). Accordingly, the first contact part CON1 is formed simultaneously with the gate electrode 35. Subsequently, using the gate electrode 35 as a mask, phosphorus ions (P) are ion-implanted into the silicon layer 33 at a dose of about 4 × 10 ¹³ cm ⁻² to form a low concentration source region 33LS and silicon layer 33. A low concentration drain region 33LD is formed.

  Next, a first interlayer insulating film ID1 is formed on the gate insulating film 34, the gate electrode 35, and the first contact part CON1 (see FIG. 13A), and the formed first interlayer insulating film ID1 is subjected to CMP (chemical reaction). Flattening process using a mechanical polishing). Thereafter, as shown in FIG. 13B, a high-concentration source region in which an opening portion Qr4 is formed on the first interlayer insulating film ID1 at a position facing the first contact portion CON1 and the silicon layer 33 is formed. A mask Mr3 in which openings Qr5a and Qr5b are respectively formed is provided at a position facing 33HS and the high concentration drain region 33HD. Then, by performing an etching process, as shown in FIG. 13C, a fourth contact hole C4 is formed at a position corresponding to the first contact part CON1. A first electrode contact hole C1 is formed at a position corresponding to the source electrode 36 of the drive transistor Qd, and a second electrode contact hole C2 is formed at a position corresponding to the drain electrode 37. At the same time, a first interlayer insulating film ID1 at a position corresponding to a connection port Po described later is also removed.

  Then, a conductive layer made of a conductive material such as copper (Cu) or aluminum (Al) is formed on the first interlayer insulating film ID1, thereby forming the fourth contact hole C4, the first and first layers formed previously. A conductive material is embedded in the two-electrode contact holes C1 and C2. As a result, a second contact portion CON2 is formed which is electrically connected to the first contact portion CON1 and formed at a position over a part of the first interlayer insulating film ID1. A source electrode 36 is formed at a position corresponding to the high concentration source region 33HS, and a drain electrode 37 is formed at a position corresponding to the high concentration drain region 33HD. Accordingly, the second contact part CON2 is formed simultaneously with the source electrode 36 and the drain electrode 37.

Subsequently, as shown in FIG. 14A, a second interlayer insulating film ID2 made of silicon dioxide (SiO ₂ ) is formed on the first interlayer insulating film ID1, the second contact portion CON2, the source electrode 36, and the drain electrode 37. Form. Thereafter, a planarization insulating film 40 made of silicon dioxide (SiO ₂ ) is formed on the second interlayer insulating film ID2. The formed planarization insulating film 40 is planarized using CMP (Chemical Mechanical Polishing) or the like. Thereafter, contact holes are formed at positions facing the drain electrode 37 of the second interlayer insulating film ID2 and the planarizing insulating film 40. At the same time, a contact hole is formed at a position facing the second contact part CON2. At the same time, a second interlayer insulating film ID2 and a planarizing insulating film 40 at a position facing a connection port Po described later are also removed.

  Thereafter, as shown in FIG. 14B, a first electrode layer 41a, a first bank layer 42a, and a second bank layer 42b are sequentially formed on the planarization insulating film 40. After the first bank layer 42a is formed, an opening is formed in the light emitting region. At the same time, a contact hole is formed at a position corresponding to the drain electrode 37. The second bank layer 42b forms an opening of the pixel by applying, drying, and exposing / developing / baking a photosensitive acrylic resin or polyimide resin. At the same time, the second bank layer 42b is also formed at a position corresponding to the drain electrode 37. An opening is formed. Simultaneously with the formation of the respective openings, the first bank layer 42a and the second bank layer 42b at positions corresponding to connection ports Po described later are also removed.

In this state, a contact hole Hr having a position corresponding to the opening Qo as shown in FIG. 14B is formed.
In addition, a region is formed in which the conductive layer ML protrudes outward as shown at the end portion (right end side in the drawing) of the glass substrate 30. The portion of the conductive layer ML protruding outward becomes the connection port Po. In this way, the connection port Po is formed.

  Then, lyophilic and lyophobic regions are formed on the surfaces of the first and second bank layers 42a and 42b by plasma treatment, and the hole injection layer 43 and the light emitting layer 44 are formed on the first electrode layer 41a by an ink jet method. To form.

  Thereafter, the electron injection layer 46 is formed over the entire surface of the light emitting layer 44, the first bank layer 42a and the second bank layer 42b, and the contact hole H. The electron injection layer 46 is made of a transparent material. A transparent conductive layer 47 made of a transparent material is formed on the electron injection layer 46. The transparent conductive layer 47 is an electrode layer constituting the cathode E2 of the organic EL element OLED described above. Therefore, the transparent conductive layer 47 (the cathode E2 of the organic EL element OLED) is electrically connected to the third conductive layer M3 constituting the conductive layer ML via the electron injection layer 46.

On the transparent conductive layer 47, a thin film sealing layer 41b made of a transparent material is formed. In the present embodiment, the thin film sealing layer 41b is made of silicon oxynitride (SiO _x N _y ) and is formed by a known appropriate method such as a sputtering method or a CVD method. However, when a thin film sealing layer is formed on the connection port Po, it becomes impossible to conduct. Therefore, when forming the thin film sealing layer 41b, it is preferable to take means such as covering the connection port Po with a metal mask.

  Finally, a transparent adhesive made of epoxy resin or the like is applied to almost the entire surface of the glass substrate 30 excluding the outer periphery of the substrate, the mounting terminal connection portion (not shown), and the connection port Po, and the sealing substrate 50 is joined. Thus, the display panel unit 12 shown in FIG. 11 is manufactured.

  By manufacturing the organic EL display 10 in this way, the contact hole H does not need to be formed up to the conductive layer ML, and is formed first over the first interlayer insulating film ID1 as described above. Further, it may be formed up to the second contact part CON2. As a result, the contact hole H can be easily formed as compared with the organic EL display of the first embodiment. As a result, the yield can be improved as compared with the organic EL display of the first embodiment.

According to the embodiment, the following features can be obtained.
(1) In the above embodiment, the first contact part CON1 electrically connected to the conductive layer ML is formed on the gate insulating film 34. The first contact part CON1 was formed simultaneously with the gate electrode 35. A second contact part CON2 electrically connected to the first contact part CON1 was formed on the first interlayer insulating film ID1. The second contact part CON2 was formed simultaneously with the source electrode 36 and the drain electrode 37. Then, the second interlayer insulating film ID2, the planarizing insulating film 40, and the first and second bank layers 42a and 42b are formed on the first interlayer insulating film ID1 to form openings (contact holes and the like). At the same time, an opening is formed in a portion corresponding to the contact hole Hr, thereby forming a contact hole Hr reaching the second contact portion CON2. Thereafter, an electron injection layer 46, a transparent conductive layer 47, and a thin film sealing layer 41b were sequentially formed on the contact hole Hr.

Therefore, the transparent conductive layer 47 and the conductive layer ML can be electrically connected without performing the dry etching process up to the conductive layer ML. As a result, since the contact hole H can be easily formed, the yield can be improved.
(Third embodiment)
Next, application of the electronic apparatus of the organic EL display 10 as the electro-optical device described in the first or second embodiment will be described with reference to FIG. The organic EL display 10 can be applied to various electronic devices such as a mobile personal computer, a mobile phone, and a digital camera.

  FIG. 15 is a perspective view showing the configuration of a mobile personal computer. In FIG. 15, the personal computer 70 includes a main body 72 having a keyboard 71 and a display unit 73 using the organic EL display 10. Even in this case, the display unit 73 using the organic EL display 10 exhibits the same effects as those of the first and second embodiments.

In addition, embodiment of invention is not limited to the said embodiment, You may implement as follows.
In the above embodiments, the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 constitute one conductive layer ML. Alternatively, the conductive layer ML may be composed of a single layer composed of one material. In this case, the conductive layer ML may be composed of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), vanadium (V), zirconium (Zr), and alloys or silicides thereof. preferable.

  In the above embodiments, the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 constitute one conductive layer ML. Alternatively, the conductive layer ML may be composed of two layers including only the first conductive layer M1 and the second conductive layer M2. In this case, the first conductive layer M1 is preferably composed of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), and alloys or silicides thereof. The second conductive layer M2 is preferably composed of aluminum (A1), nickel (Ni), and platinum (Pt).

  In each of the above embodiments, the first conductive layer M1 is made of titanium (Ti). The second conductive layer M2 was made of copper (Cu). Furthermore, the third conductive layer M3 was composed of titanium nitride (TiN).

The first conductive layer M1 may be formed of tantalum (Ta), tungsten (W), molybdenum (Mo), and an alloy or silicide thereof. The second conductive layer M2 may be made of aluminum (A1), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), and alloys or silicides thereof. Further, the third conductive layer M3 may be composed of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), and alloys or silicides thereof.
By doing in this way, the same effect as the above-mentioned embodiment can be produced.

  In each of the above embodiments, the electro-optical device is embodied as the organic EL display 10 in which the light emitting layer is composed of organic EL elements, but is not limited to this, and any top emission type electro-optical device may be used. Any electro-optical device may be applied.

  In each of the above embodiments, the cathode E2 of the organic EL element OLED formed in each pixel 20 is all electrically connected to the conductive layer ML via the contact holes H and Hr. Instead of the contact holes H and Hr, the other shape may be used to electrically connect the cathode E2 of the organic EL element OLED and the conductive layer ML.

  In each of the above embodiments, the cathode composed of tin-doped indium oxide (ITO) is used as the cathode E2 of the organic EL element OLED. However, the present invention is not limited to this. You may apply to the organic electroluminescent display comprised with such a transparent conductive thin film. That is, the material constituting the cathode E2 of the organic EL element OLED is not limited.

In each of the above embodiments, the method for forming each layer is not limited to the method described in the above embodiment, and may be formed using other methods.
In each of the above embodiments, the present invention is applied to the organic EL display 10 in which the pixel 20 is configured by the driving transistor Qd in which the silicon layer 33 formed of polysilicon is the channel region 33C. This may be applied to an organic EL display in which the pixel 20 is configured by a driving transistor using a silicon layer formed of a single crystal as a channel region.

  DESCRIPTION OF SYMBOLS 30 ... Glass substrate as a substrate, E1 ... Anode, E2 ... Cathode, Light emitting layer as a luminescent material, 20 ... Pixel, 10 ... Organic EL display as an electro-optical device, ML ... Conductive layer, H, Hr ... Connection part Qd: driving transistor as an active element, ID1, 34: first interlayer insulating film and gate insulating film as an element formation layer, 31: base protective layer, 32: base insulating film as an insulating layer, ML ... conductive layer, M1 ... first conductive layer, M2 ... second conductive layer as metal layer, M3 ... third conductive layer, Po ... connection port as protrusion, 42a, 42b ... first and second as bank layers Bank layer, 41b. Thin film sealing layer as a transparent conductive film, 70 ... Mobile personal computer as an electronic device.

Claims (14)

On a substrate, an anode, a cathode formed at a position facing the anode, and a luminescent material provided between the anode and the cathode, the anode being a pixel provided with the luminescent material In the electro-optical device formed for each,
A conductive layer formed between the substrate and the anode;
An electro-optical device comprising: a connecting portion for electrically connecting the cathode and the conductive layer. The electro-optical device according to claim 1.
The electro-optical device, wherein the connection portion is provided for each pixel. The electro-optical device according to claim 1,
The electro-optical device is characterized in that the connecting portion is formed of a contact hole. The electro-optical device according to any one of claims 1 to 3,
An element forming layer on which an active element for controlling a current supplied to the light emitting material is formed on the substrate;
An electro-optical device, wherein an insulating layer for electrically cutting the element forming layer and the conductive layer is formed between the element forming layer and the conductive layer. The electro-optical device according to claim 4.
2. The electro-optical device according to claim 1, wherein the insulating layer has a film thickness of 2ε / 3.5 μm or more when the dielectric constant is ε. The electro-optical device according to claim 1,
The conductive layer is composed of one of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), vanadium (V), zirconium (Zr), and alloys or silicides thereof. An electro-optical device. The electro-optical device according to claim 1,
The electro-optical device, wherein the conductive layer includes a plurality of conductive layers including at least one metal layer. The electro-optical device according to claim 7.
Provided with a base protective layer for protecting the substrate on the substrate, the base protective layer is composed of silicon dioxide,
The plurality of conductive layers are conductive layers composed of a first conductive layer and a second conductive layer in order from the base protective layer,
The first conductive layer is made of any one of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), and alloys or silicides thereof.
The electro-optical device, wherein the second conductive layer is made of any one of aluminum (A1), nickel (Ni), platinum (Pt), and an alloy or silicide thereof. The electro-optical device according to claim 7.
Provided with a base protective layer for protecting the substrate on the substrate, the protective layer is composed of silicon dioxide,
The plurality of conductive layers are composed of a first conductive layer, a second conductive layer, and a third conductive layer in order from the top protective layer,
The first conductive layer is made of any one of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), and alloys or silicides thereof.
The second conductive layer is composed of any one of copper (Cu), aluminum (A1), nickel (Ni), platinum (Pt), and alloys or silicides thereof.
The third conductive layer is composed of any one of titanium nitride (TiN), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), and alloys or silicides thereof. Electro-optical device characterized. The electro-optical device according to claim 1,
The electro-optical device, wherein the conductive layer includes a protruding portion that protrudes from the substrate. An anode, a cathode formed at a position facing the anode, and a luminescent material provided between the anode and the cathode are provided on the substrate, and the luminescent material is divided into pixels. A bank layer, a conductive layer formed between the substrate and the anode, a connection part for electrically connecting the cathode and the conductive layer, and the luminescent material on the substrate In order to electrically disconnect the element forming layer and the conductive layer between the element forming layer and the conductive layer, and an element forming layer in which an active element for controlling the current supplied to the element is formed In an electro-optical device manufacturing method including the insulating layer,
Forming the conductive layer above the substrate;
Forming the insulating layer, the element forming layer, the anode and the bank layer above the conductive layer;
Forming a connection portion opening pattern for electrically connecting the cathode and the conductive layer simultaneously with forming an opening pattern in the insulating layer;
Forming the luminescent material;
And a step of forming a transparent conductive film on the entire surface of the region where the light emitting material including the connecting portion is formed. The method of manufacturing an electro-optical device according to claim 11.
The conductive layer includes a conductive layer including a first conductive layer, a second conductive layer, and a third conductive layer. The element formation layer includes a first signal line and a second signal line for supplying a signal to the active element. With signal lines,
The first conductive layer is formed simultaneously with forming the first signal line;
The method of manufacturing an electro-optical device, wherein the second conductive layer is formed simultaneously with the formation of the second signal line. The method of manufacturing an electro-optical device according to claim 11 or 12,
An electro-optical device manufacturing method, wherein the conductive layer is formed by sputtering.   An electronic apparatus comprising the electro-optical device according to claim 1.

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