JP2009104320A - Data management device, information processor, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently perform processing to save data before shifting to a power non-supply state, and to restore the saved data when the power non-supply state is released. <P>SOLUTION: Data stored in an RAM are divided into a plurality of processing data, and stored in a flash memory before the operating state of its own device is shifted from an "on-state" for supplying a power to an RAM to a "power non-supply state" for not supplying a power to the RAM, and a data management table showing the corresponding relation of an address as the storage place of each processing data and processing related with the processing data. Then, when the "power non-supply state" is shifted to the "on-state", the address corresponding to each processing is specified based on the data management table, and the processing data stored in each specified address are read from the flash memory, and stored in the RAM. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for moving data between a storage unit that maintains a state in which data is stored by receiving power supply and a storage unit that maintains a state in which data is stored without receiving power supply.

A technique called hibernation is known in which when a computer is turned on, the work contents when the power is turned off are restored. For example, Patent Document 1 describes that when data in a volatile memory is written in a nonvolatile memory before turning off the power, the power is turned off and the power is turned off, and the power is turned on again. A technique for writing back data written in a volatile memory to a volatile memory is disclosed. Patent Document 2 discloses a technique for writing only data stored in a data area and a backup area, out of data in a volatile memory, into a nonvolatile memory before shifting to a sleep mode. According to the technique disclosed in Patent Document 2, since the amount of data to be written to the nonvolatile memory is smaller than when all the data in the volatile memory is written back, the data stored in the nonvolatile memory is reduced. Can be written back to the volatile memory in a short time.
JP 2005-115720 A JP 2007-38580 A

  Incidentally, a computer having a multitask function can execute a plurality of processes in parallel by time sharing or the like. In this case, when the user turns off the power in a state where a plurality of processes are executed and then turns on the power again, first, the user resumes the work for any one of the plurality of processes being executed. Will do. In other words, in an environment where multitasking is possible, like the techniques disclosed in Patent Documents 1 and 2 described above, the work contents of all the processes executed before turning off the power are saved together in a nonvolatile memory. Furthermore, even if all of them are restored to the volatile memory after the power is turned on, the user uses only a part of them. In this case, the time required for the restoration process is increased by the amount of restoration of the work contents that are not used, and the capacity of the volatile memory is wasted.

  The present invention has been made in view of such a background, and an object of the present invention is to save data before shifting to a power non-supply state in which power is not supplied, and the power non-supply state is solved. In this case, the process of restoring the saved data is performed more efficiently than before.

In order to solve the above-described problems, the present invention provides a first storage unit that maintains a state in which data is stored by receiving power supply, and a second storage unit that maintains a state in which data is stored without receiving power supply. A state transition unit that shifts to a power supply state in which power is supplied to the first storage unit, or a power non-supply state in which power is not supplied to the first storage unit, and the state transition unit. First memory for dividing the data stored in the first storage means into a plurality of data and storing the data in the second storage means until the power supply state is shifted to the power non-supply state. Control means; correspondence storage means for storing the correspondence between the storage locations of the respective data stored in the second storage means by the first storage control means and the processing related to the data; in front When the state transition means shifts from the power non-supply state to the power supply state, the specifying means for specifying the storage location corresponding to each of the processes based on the correspondence relation stored by the correspondence relation storage means And second storage control means for reading out data stored in each storage location specified for each processing by the specifying means from the second storage means and storing the data in the first storage means. Provided is a data management device characterized by comprising.
As a result, the process of saving data before shifting to a power non-supply state where power is not supplied and restoring the saved data when the power non-supply state is resolved is more efficient than before. Can be done well.

In a preferred aspect of the present invention, the first storage control unit divides the data stored in the first storage unit into a plurality of data in units of processing using the data. You may memorize | store in a memory | storage means.
As a result, the saved data can be restored for each data divided in units used in the processing.

In a preferred aspect of the present invention, the first storage control unit divides the data stored in the first storage unit into a plurality of data in a predetermined data size unit and stores the data in the second storage unit. It may be memorized.
As a result, the saved data can be restored for each data segmented by a predetermined data size unit.

In a preferred aspect of the present invention, the specifying means includes: process identification information of a certain first process among the plurality of processes; and process identification information of a second process performed after the first process. When the first process is specified as the process performed in the power supply state, the process is associated with the process identification information of the first process as the process performed after the first process. The second process of the stored process identification information is specified, the storage location corresponding to the second process is specified based on the correspondence stored by the correspondence storage means, and the second The storage control means reads out the data stored in the storage location specified by the specifying means as corresponding to the second process from the second storage means, and stores the data in the first storage means. Even .
Thereby, when the first process is performed in the power supply state, the second process performed after the first process can be quickly executed.

In a preferred aspect of the present invention, the specifying unit records a sequence of a plurality of processes performed in accordance with a user instruction in the power supply state, and identifies a process identification of the certain first process from the recorded order. The information and the process identification information of the second process performed after the first process may be specified and stored.
Accordingly, when the first process is performed in the power supply state, the second process specified as the process performed after the first process based on the order of the processes performed according to the user's instruction is performed. It can be executed quickly.

In a preferred aspect of the present invention, the first storage control means includes processing identification information of a certain first process among the plurality of processes and a process of a second process performed after the first process. The identification information is stored in association with each other, and when the first process is performed in the power supply state, the process of the second process stored in association with the process identification information of the first process The identification information is specified, and data other than the data related to the second process is stored in the second storage unit among the plurality of data obtained by dividing the data stored in the first storage unit. Thereafter, data related to the second process may be stored.
As a result, when the execution of the second process is instructed after the first process is performed in the power supply state, the first storage control unit can be quickly executed.

In a preferred aspect of the present invention, the first storage control means records the order of a plurality of processes performed in accordance with a user instruction in the power supply state, and from the recorded order, the first first control unit The process identification information of the process and the process identification information of the second process performed after the first process may be specified and stored.
Thus, when the execution of the second process is instructed after the first process is performed in the power supply state, the process is performed after the first process based on the order of the processes performed according to the user's instruction. The second process specified as the process to be performed can be quickly executed.

In a preferred aspect of the present invention, for each of the data divided by the first storage control means, a frequency storage means for storing a frequency at which a process related to the data is performed is provided, and the second storage The control means may read each of the data from the second storage means in descending order of frequency of processing related to the data, and store the data in the first storage means.
As a result, the saved data can be restored in order from the highest frequency of processing related to the data.

In a preferred aspect of the present invention, for each of the data divided by the first storage control means, there is provided a frequency storage means for storing a frequency at which processing related to the data is performed, and the first storage The control means may store each of the data in the second storage means in descending order of frequency of processing related to the data.
As a result, the data stored in the first storage means can be saved in order from the lowest frequency of processing related to the data.

In a preferred aspect of the present invention, the power supply state includes a first power supply state with high power consumption and a second power supply state with low power consumption. It is a transition condition for shifting from the first power supply state to either the power non-supply state or the second power supply state, and the transition is made again to the first power supply state after the transition. A transition condition that reduces power consumption required until the time is stored, and based on the stored transition condition, the transition from the first power supply state to the non-power supply state is performed, or the first It may be determined whether to shift from the power supply state to the second power supply state, and shift to the determined state.
Thereby, power consumption can be reduced.

According to another aspect of the present invention, there is provided the data management device according to any one of the above, a processing unit that performs processing using the data stored in the first storage unit, and a result processed by the processing unit. An information processing apparatus comprising an output unit is provided.
As a result, the process of saving data before shifting to a power non-supply state where power is not supplied and restoring the saved data when the power non-supply state is resolved is more efficient than before. Can be done well.

The present invention also provides a computer having a first storage means for maintaining a state in which data is stored upon receiving power supply, and a second storage means for maintaining a state in which data is stored without receiving power supply. By state transition means for shifting the power to either the power supply state for supplying power to the first storage means or the power non-supply state for not supplying power to the first storage means, and the state transition means First memory for dividing the data stored in the first storage means into a plurality of data and storing the data in the second storage means until the power supply state is shifted to the power non-supply state. Control means; correspondence storage means for storing the correspondence between the storage locations of the respective data stored in the second storage means by the first storage control means and the processing related to the data; When the state transition means shifts from the non-power supply state to the power supply state, the storage location corresponding to each of the processes is specified based on the correspondence stored by the correspondence storage means And a second storage control means for reading data stored in each storage location specified for each process by the specifying means from the second storage means and storing the data in the first storage means Provide a program to make it function.
As a result, the process of saving data before shifting to a power non-supply state where power is not supplied and restoring the saved data when the power non-supply state is resolved is more efficient than before. Can be done well.

[Constitution]
FIG. 1 is a diagram illustrating a configuration of a display device 1 according to the present embodiment. As shown in the figure, the display device 1 includes a CPU (Central Processing Unit) 10, a ROM (Read Only Memory) 20, a RAM (Random Access Memory) 30, a flash memory 40, an operation unit 50, and a display. Unit 60 and a power supply unit 70. The CPU 10, the ROM 20, the RAM 30, the flash memory 40, the operation unit 50, and the display unit 60 are connected via a bus 80. Each of these units 10 to 60 and the power supply unit 70 are connected via a power supply line (not shown).

  The ROM 20 is a read-only storage medium, and stores a boot program that controls the startup process of the display device 1 and various control programs such as an OS (Operation System). The CPU 10 controls the operation of the display device 1 by executing a control program stored in the ROM 20, and executes various processes by executing various processing programs stored in the flash memory 40. The processing result is output by the display unit 60.

  The RAM 30 is a volatile storage medium that maintains a state in which data is stored by receiving power supply from the power supply unit 70. In other words, the data stored in the RAM 30 continues to be stored for a period in which power is supplied from the power supply unit 70 to the RAM 30, but is erased when the power supply from the power supply unit 70 is lost. The RAM 30 is used as a work area for the CPU 10, and stores data used in processing being executed by the CPU 10, for example. This data includes various programs and functions read from the ROM 20 and the flash memory 40 and loaded into the RAM 30, as well as various values and arguments used in the processing being executed. Hereinafter, these data stored in the RAM 30 are collectively referred to as “process data”.

  The flash memory 40 is a non-volatile storage medium that can maintain a state in which data is stored without receiving power supply from the power supply unit 70. In addition to storing the above-described processing program, the flash memory 40 is provided with a storage area for storing processing data on the RAM 30 being processed by the CPU 10. As described above, the RAM 30 functions as a first storage unit that maintains a state in which processing data is stored by receiving power supply, whereas the flash memory 40 stores a state in which processing data is stored without receiving power supply. It functions as a second storage means for maintaining.

  The operation unit 50 includes, for example, a pen device or a joystick, and supplies an operation signal corresponding to a user operation to the CPU 10. The display unit 60 includes, for example, a storage liquid crystal display using a cholesteric liquid crystal or electrophoresis, and a display control circuit, and displays various images under instructions from the CPU 10. The power supply unit 70 includes, for example, a rechargeable battery and a power supply control circuit, and supplies power to each unit constituting the display device 1.

  Here, the activation state of the display device 1 will be described. The display device 1 has three activation states of “on state”, “sleep state”, and “off state”, and takes one of these activation states. First, the “on state” is a power supply state in which power is supplied to each unit of the display device 1 and is a state in which the display device 1 performs a normal operation. In the “on state”, the CPU 10 performs various processes. Next, the “sleep state” is a state in which power is supplied to only a limited part of the display device 1 and the display device 1 does not operate. In the “sleep state”, power is not supplied to the CPU 10 and the display unit 60, but power is supplied to other components (including the RAM 30). Therefore, it can be said that the “on state” is a first power supply state with high power consumption, and the “sleep state” is a second power supply state with low power consumption. The “off state” is a state when the power supply unit 70 is turned off. In this “off state”, power is not supplied to each part of the display device 1, so the display device 1 does not operate at all. The above-described transition from the “on state” to the “sleep state” is performed, for example, when the standby time during which the CPU 10 does not perform processing in the “on state” becomes a predetermined time or longer. The transition from the “sleep state” to the “on state” is performed, for example, when the operation unit 50 is operated. The “on state” and the “sleep state” are “power supply states” in which power is supplied to at least the RAM 30 among the components of the display device 1, whereas the “off state” does not supply power to the RAM 30. “Power is not supplied”.

[Operation]
Next, the operation of the display device 1 will be described.
(Data backup processing)
Here, first, referring to FIG. 2, data for saving data stored in the RAM 30 when the startup state of the display device 1 shifts from the “power supply state” to the “power non-supply state” described above. The save process will be described. The term “saving data” as used herein means that the data stored in the RAM 30 is stored in the flash memory 40.

  For example, it is assumed that when the display device 1 is in the “on state”, the user operates the operation unit 50 to create, for example, a sentence and an image to be referred to in the document. In response to this operation, the CPU 10 generates processing data used for each processing or reads it from the flash memory 40 and stores it in the RAM 30 (step S11), and creates a sentence using these processing data. Processing A for processing and processing B for creating an image are executed in parallel (step S12).

  The upper part of FIG. 3 is a diagram showing an example of the contents stored in the RAM 30 at this time. The CPU 10 secures one or a plurality of storage areas of the RAM 30 for each processing unit, and stores processing data corresponding to each secured storage area. In the example shown in the upper part of the figure, the processing data A used in the processing A is stored in the storage areas a1 and a4 of the RAM 30, and the processing data B used in the processing B is stored in the storage areas a2 and a3 of the RAM 30. ing. The processing data used for common processing is distributed and stored in different storage areas because of the difference in the nature of the data, for example, the processing data is stored separately in the static area, heap area, stack area, etc. Because. The static area here is a storage area in which static data is stored, the heap area is a storage area that is dynamically allocated, and the stack area is a storage area that functions as a stack.

  The CPU 10 executes process A based on the process data A and executes process B based on the process data B. FIG. 4 is a diagram illustrating an example of the display screen S1 displayed on the display unit 60 as the process A and the process B are executed. On this display screen S1, a process presentation image fa for presenting the process of process A for creating a sentence to the user and a process presentation image for presenting the process of process B for creating an image to the user fb is arranged so as to overlap. For example, when the user performs a task of creating a sentence, the user operates the operation unit 50 while looking at the process presentation image fa to proceed with the process A. The CPU 10 performs steps of the process A while updating the process data A stored in the RAM 30 by appropriately repeating steps S11 and S12 according to this operation. In addition, when performing the work of creating an image, the user operates the operation unit 50 while viewing the process presentation image fb and proceeds with the process B. The CPU 10 repeats step S11 and step S12 as appropriate according to this operation, thereby executing each procedure of process B while updating the process data B stored in the RAM 30.

  When the user interrupts the work, the user performs an operation such as pressing a power button (not shown) of the operation unit 50 to instruct the display device 1 to turn off the power. At this time, the CPU 10 determines whether the user has instructed to turn off the power (step S13 in FIG. 2). For example, if the user has not performed an operation to instruct the power off, the CPU 10 determines that the power off has not been instructed (step S13: NO), and returns to the process of step S11 described above. On the other hand, when an operation for instructing power-off such as pressing the power button is performed by the user, the CPU 10 determines that the power-off is instructed by the user (step S13: YES), and is stored in the RAM 30. The processed data is stored in the flash memory 40 in units of processing in which the processed data is used (step S14). In this example, the processing data stored in the RAM 30 shown in the upper part of FIG. 3 is divided into processing data A used in the process A and processing data B used in the process B, as shown in the lower part of FIG. Are stored in the storage areas A1 and A2 of the flash memory 40, respectively. In this case, the processing data A includes data representing the processing presentation image fa in FIG. Further, the processing data B includes data representing the processing presentation image fb in FIG. At this time, a value stored in a register provided in the CPU 10 is also stored in the flash memory 40.

Subsequently, the CPU 10 creates a data management table indicating the correspondence between the storage locations of the respective processing data stored in the flash memory 40 and the processing using the processing data (step S15).
FIG. 5 is a diagram showing an example of the data management table T1. As shown in the figure, in this data management table T1, an “address” indicating a storage location of each processing data is associated with “processing identification information” of processing using the processing data. This “address” is the head address of the storage area in which data is stored. This “process identification information” is assigned to each process, and is, for example, the program name or process name of a program that realizes the process. For example, in the top record in the figure, “0120” that is an address indicating the storage location of the processing data A and “taskA” that is processing identification information of the processing A are associated with each other. This indicates that the process represented by “taskA”, that is, the process data A used in process A is stored from the address “0120”. Also, in the second record from the top in the figure, “0430” that is an address indicating the storage location of the processing data B and “taskB” that is processing identification information of the processing B are associated with each other. This indicates that the process represented by “taskB”, that is, the process data B used in process B is stored from the address “0430”. The CPU 10 can specify the storage location of the processing data related to the instructed processing by referring to the correspondence relationship described in the data management table T1.

  Subsequently, the CPU 10 stores the created data management table T1 in the flash memory 40. When the data management table T1 is stored, the CPU 10 turns off the power supply unit 70 and shifts the startup state of the display device 1 from the “on state” to the “off state” (step S16 in FIG. 2). As a result, power is not supplied to each part of the display device 1 and data stored in the RAM 30 is erased.

(Data restoration process)
Next, referring to FIG. 6, a data restoration process for restoring the data saved in the flash memory 40 when the activation state of the display device 1 is returned from the “off state” to the “on state”. explain. Here, the term “return” refers to the transition from the “power supply state” to the “power supply state” after the activation state of the display device 1 has been shifted from the “power supply state” to the “power supply state”. It means being done. The data restoration is to store the data saved in the flash memory 40 from the RAM 30 in the RAM 30 again.

  When the power button of the operation unit 50 is turned on by the user (step S21), the CPU 10 executes the control program stored in the ROM 20 to activate the display device 1 (step S22). As a result, the activation state of the display device 1 is shifted from the “off state” to the “on state”. When the display device 1 is in the “on state”, the user operates the operation unit 50 to specify a desired program and instruct to execute it.

  At this time, the CPU 10 determines, based on the data management table T1 of the flash memory 40, whether or not the processing instructed by the user has been executed before the display device 1 shifts to the “off state” ( Step S23). For example, when the process identification information of the process instructed by the user is not described in the data management table T1, the CPU 10 has assumed that the process instructed by the user has not been executed before shifting to the “off state”. Determination is made (step S23: NO). In this case, the CPU 10 considers that there is no process to be resumed, and waits without performing the data restoration process, while executing the process instructed by the user in a normal procedure. The resumption here means that the process is continued from the process before the display device 1 shifts to the “off state”.

  On the other hand, when the process identification information of the process instructed by the user is described in the data management table T1, the CPU 10 determines that the process instructed by the user has been executed before shifting to the “off state”. (Step S23: YES). In this case, the CPU 10 refers to the data management table T1 of the flash memory 40 and specifies an address corresponding to the process instructed by the user (step S24). Subsequently, the CPU 10 reads out the processing data stored from the specified address from the flash memory 40 and stores it in the free area of the RAM 30 (step S25). At this time, the value stored in the register of the CPU 10 before shifting to the “off state” is also read from the flash memory 40 and stored again in the register. And CPU10 performs the process instruct | indicated by the user based on the process data memorize | stored in RAM30 (step S26).

  For example, when resuming the process B for creating an image, the user operates the operation unit 50 to instruct the execution of the process B. In the data management table T1 shown in FIG. 5, “taskB” which is the process identification information of the process B instructed by the user is described. In this case, in step S23, it is determined that the process instructed by the user has been executed before shifting to the “off state” (step S23: YES). In the subsequent step S24, the address stored in association with this “taskB” in the data management table T1 shown in FIG. 5, that is, “0430” is specified. In subsequent step S <b> 25, the processing data B stored from the specified address “0430” is read from the flash memory 40 and stored in the RAM 30. In step S26, the process B is executed based on the process data B stored in the RAM 30.

  FIG. 7 is a diagram illustrating an example of the display screen S2 displayed on the display unit 60 as the process B is executed. As described above, since the processing data B includes data representing the processing presentation image fb in FIG. 4, the processing presentation image fb similar to that shown in FIG. 4 is arranged on the display screen S2. Has been. This indicates that the process B can be executed continuously from the process before the transition to the “off state”. As a result, the user can proceed with the process B from the process before the transition to the “off state”.

  In addition, the user can resume another process by designating a process to be resumed in the same manner as described above. For example, when it is desired to restart the process A for creating a sentence, the user operates the operation unit 50 to instruct the execution of the process A. After executing the process in step S26 described above, the CPU 10 returns to the process in step S23. When the user instructs execution of a new process, the newly instructed process causes the display device 1 to be in the “off state”. It is determined whether or not it has been executed before shifting to "." In the data management table T1 shown in FIG. 5, “taskA” that is the process identification information of the process A instructed by the user is described. In this case, in step S23, it is determined that the process instructed by the user has been executed before shifting to the “off state” (step S23 in FIG. 6: YES). In the subsequent step S24, the address stored in association with this “taskA” in the data management table T1 shown in FIG. 5, that is, “0120” is specified. In subsequent step S <b> 25, the processing data A stored from the identified address “0120” is read from the flash memory 40 and stored in the RAM 30. In step S26, the process A is executed based on the process data A stored in the RAM 30.

  FIG. 8 is a diagram illustrating an example of the display screen S3 displayed on the display unit 60 as the process A is executed. Since the process data A includes data representing the process presentation image fa of FIG. 4 as described above, the display screen S3 includes the data shown in FIG. 4 in addition to the process presentation image fb described above. The same processing presentation image fa is arranged. This indicates that the process A can be executed continuously from the process before the transition to the “off state”. As a result, the user can proceed with the process A from the process before the transition to the “off state”.

  Thus, when the display device 1 shifts from the “on state” to the “off state”, the data saving process is executed, and when the display device 1 returns from the “off state” to the “on state”, the data restoration process is executed. Since the on state and the sleep state are common in that they are power supply states, the data saving process and the data restoration process as described above are not performed between the on state and the sleep state.

  According to the embodiment described above, when shifting from the “power supply state” (“on state” or “sleep state”) to the “power non-supply state” (“off state”), the process is divided into units. The processing data is saved, and only the processing data used for the processing that the user wants to resume is restored when shifting from the “non-power supply state” to the “power supply state”. For this reason, the time required for data restoration is shortened and the memory capacity consumed in the RAM 30 compared to a configuration for restoring the processing data used in all the processes executed before shifting to the “power non-supply state”. Less. That is, it is possible to efficiently perform the process of saving the data before shifting to the “power non-supply state” and restoring the saved data when the “power non-supply state” is solved.

[Modification]
The above is the description of the embodiment, but the contents of this embodiment can be modified as follows. Further, the following modifications may be combined as appropriate.
(Modification 1)
In the embodiment described above, as shown in FIG. 3, in the flash memory 40, the processing data used in one process is handled as a group of data. On the other hand, the processing used in each process Data may be further classified and handled. The upper part of FIG. 9 is a diagram showing an example of the contents stored in the RAM 30 according to this modification. As shown in the upper part of the figure, a static area, a heap area, and a stack area are secured in the RAM 30. As described above, the static area is a storage area in which static data is stored, the heap area is a storage area that is dynamically allocated, and the stack area is a storage area that functions as a stack. In the static area, process data a1 used in process A, process data b1 used in process B, and process data a2 and b2 shared by process A and process B are stored. In the heap area, process data a3 used in process A and process data b3 used in process B are stored. Further, processing data a4 used in the process A and processing data b4 used in the process B are stored in the stack area.

  In this case, the CPU 10 classifies the processing data a1, processing data a2 and b2, processing data a3 and processing data a4 as processing A, and processes data b1, processing data a2 and b2, processing data b3 and processing data b4 into processing B. And stored in the flash memory 40. As shown in the lower part of FIG. 3, the flash memory 40 may store the processing data related to the same process in one storage area having consecutive addresses. As shown in the lower part of FIG. May be divided into a static area, a heap area, and a stack area, and processing data corresponding to each area may be stored. Then, the CPU 10 creates a data management table that represents the correspondence between the address indicating the storage location of each processing data, the processing using the processing data, and the storage area of the RAM 30 in which the processing data is stored. .

In this configuration, for example, when the user is instructed to execute the process A, the CPU 10 refers to the created data management table to determine the address corresponding to the process A instructed by the user and the storage area of the RAM 30. Identify. Subsequently, the CPU 10 reads out the processing data a1, processing data a2 and b2, processing data a3 and processing data a4 stored in the specified address from the flash memory 40. Then, the CPU 10 stores the read processing data in each specified storage area of the RAM 30. In this example, the processing data a1 and the processing data a2 and b2 are stored in the static area of the RAM 30, the processing data a3 is stored in the heap area of the RAM 30, and the processing data a4 is stored in the stack area of the RAM 30. Subsequently, even when the user is instructed to execute the process B, the CPU 10 restores the data in the same manner as described above. However, the CPU 10 does not restore the processing data a2 and b2 whose data has already been restored on the RAM 30.
As described above, if the data stored in the RAM 30 is divided into a plurality of data and stored in the flash memory 40, how the storage area for storing each data in the RAM 30 or the flash memory 40 is configured. May be.

(Modification 2)
In the above-described embodiment, the processing data stored in the RAM 30 is divided and stored in the flash memory 40 by the unit of processing in which the processing data is used. As described above, this processing unit may be a unit corresponding to the processing A or processing B specified by the user, that is, a task unit, or a smaller unit, for example, a processing program for realizing the processing. It may be a process unit or a function unit.

  Further, the processing data stored in the RAM 30 may be stored in the flash memory 40 by being divided into predetermined data size units instead of the various processing units as described above. FIG. 10 is a diagram showing an example of the stored contents of the RAM 30 and the flash memory 40 according to this modification, and FIG. 11 is a diagram showing an example of the data management table T2 according to this modification. The processing data read from the RAM 30 at the time of data saving is divided and stored in the flash memory 40 with a certain data size. This fixed data size is determined in advance according to a mechanism for managing the RAM 30, the flash memory 40, and the like. In the example shown in the drawing, the processing data A and B are divided into data sizes of 100 and stored in the flash memory 40. That is, the data size stored in the storage area between the addresses “0100”, “0200”... Shown in FIG. Further, the processing data stored from the address “0300” stores processing data for processing A and processing data for processing B.

  In this configuration, when restoring the processing data used in the processing A, a part of the processing data A and the processing data B is read from the addresses “0100”, “0200”, “0300” of the flash memory 40 and stored in the RAM 30. Let In this case, a part of the processing data B stored in the RAM 30 is not used. When restoring the processing data used in the processing B, a part of the processing data B and the processing data A is read from the addresses “0300”, “0400”, and “0500” of the flash memory 40 and stored in the RAM 30. In this case, a part of the processing data A stored in the RAM 30 is not used. As described above, when the processing data is not divided into processing units, a part of the processing data returned to the flash memory 40 is not used, and a wasteful storage area is generated in the flash memory 40. It will end up. However, since data reading and writing can be managed in fixed-length data units, data can be saved and restored at high speed by a simple procedure.

(Modification 3)
In the embodiment described above, only the processing data used in the processing instructed by the user is restored, but the present invention is not limited to this. For example, after restoring the process data of the process instructed by the user, a process that is highly likely to be performed after this process is estimated, and the process data may be restored. In this case, the flash memory 40 has a process name (process identification information of the first process) and a process name (process identification information of the second process) performed after the process in advance. It is stored in association. This correspondence is determined by the following method, for example.

(A1) The user operates the operation unit 50 in advance to specify the process name of each process and the process name of the process to be resumed after the process, and stores these in the flash memory 40 in association with each other. Let me. For example, when a certain image is always displayed after a certain sentence is displayed, a process name for displaying a certain sentence and a process name for displaying a certain image are designated. And so on. When executing the process in step S26 of FIG. 6 described above, the CPU 10 refers to this correspondence relationship and identifies the process name associated with the process name of the executed process. Subsequently, the CPU 10 specifies an address corresponding to the process with the specified process name, reads the process data stored at the specified address from the flash memory 40, and stores it in the RAM 30. According to this configuration, when a certain process is executed in the display device 1 returned to the “on state”, the process data of the process designated by the user is automatically restored as the process to be resumed after the process. . Thereby, the process designated as the process to be resumed after each process can be quickly executed.

(A2) Based on the contents of each process, the CPU 10 stores the process name of each process in association with the process name of the process called by the process in the flash memory 40 in advance. For example, when the process C is a process for displaying a menu screen that prompts the user to select one of the processes D, E, and F, the program in which the procedure of the process C is described includes a program called by the process C. Process names of processes D, E, and F, which are processes, are described. Accordingly, the CPU 10 refers to this and stores the process name of the process C in association with the process names of the processes D, E, and F in the RAM 30 or the like. In this configuration, for example, when the process C is executed in step S26 of FIG. 6 described above, the CPU 10 specifies and specifies the processes called by the process C, that is, processes D, E, and F, in the same manner as described above. The processing data of the processing is restored. According to this configuration, when a certain process is executed in the display device 1 returned to the “ON state”, the process data of the process called by the process is automatically restored. Thereby, the process called by each process can be performed quickly.

(A3) Based on the process history of each process, the CPU 10 associates the process name of each process with the process name of the process executed frequently after that process in the flash memory 40 in association with each other. deep. This frequency may be, for example, an absolute value of the number of times the process has been executed, or may be a result of relative evaluation of the number of times the process has been executed (for example, the ratio of the number of processes to a certain period or a certain number). Also good. The CPU 10 accumulates the order of processes instructed by the user as a process history, statistically analyzes the order of processes included in the process history, and which process is frequently executed after which process. And the determination result is stored in the flash memory 40. For example, when it is determined that the frequency at which the process A is executed after the process B is high, the process name of the process B is stored in association with the process name of the process B. In addition, when it is determined that the frequency of execution of the process D is high after another process is executed following the process C, the process name of the process D is stored in association with the process name of the process C. . In this configuration, for example, when the process B is executed in step S26 of FIG. 6 described above, the CPU 10 specifies and specifies the process that is frequently executed after the process B, that is, the process A in the same manner as described above. Restore the processing data of the processed. According to this configuration, when a certain process is executed in the display device 1 that has returned to the “ON state”, the process data of the process that is executed frequently after the process is executed is automatically restored. As a result, it is possible to quickly execute a process that is likely to be executed after each process is executed.
The processing history described above may be accumulated from the time when the display device 1 is used for the first time after factory shipment, or accumulated after being reset at a predetermined timing such as once a week. It may be. When the processing history is accumulated without being reset, the processing data of the processing that is frequently executed after each processing is performed in the long term is automatically restored. On the other hand, when the processing history is reset at a predetermined timing, the processing data of the processing that is frequently executed after each processing is executed in the short term is automatically restored.

(Modification 4)
In the above-described embodiment, the process data used in the process instructed by the user is restored. However, the method for specifying the process data to be restored is not limited to this. For example, the following method can be considered.
(B1) For example, the CPU 10 may actively restore the processing data by itself without waiting for the processing to be instructed by the user. For example, the CPU 10 may obtain the frequency with which each process is executed and restore the process data saved in the flash memory 40 in order from the process data used in the process with the high execution frequency. In this case, the flash memory 40 stores the frequency at which processing using the processing data is performed for each processing data. This frequency may be an absolute value of the number of times the process has been executed, as in the third modification, or may be a result of relative evaluation of the number of times the process has been executed. After starting the display device 1 in step S22 described above, the CPU 10 restores the processing data saved in the flash memory 40 in descending order of execution frequency. In this configuration, processing data used in processing with high execution frequency is restored before processing data used in processing with low execution frequency. Thereby, even if a user does not instruct | indicate a process, the process with high execution frequency can be performed rapidly.

(B2) The CPU 10 may restore the processing data used in the processing performed after the processing based on the processing that was executed before shifting to the “power non-supply state”. In this case, in the flash memory 40, the process name of each process is associated with the process name of the process performed when the process returns to the “on state” via the “power non-supply state” after the process. Is memorized. This correspondence relationship may be determined by the CPU 10 based on the content of the process, or may be determined by the CPU 10 based on the execution order of the process, as described above. In this configuration, the CPU 10 is executed before the display device 1 enters the “power non-supply state” based on the data management table T1 of the flash memory 40 after starting the display device 1 in step S22 described above. Identify the process. Subsequently, the CPU 10 refers to the above-described correspondence relationship, and identifies a process to be performed when the identified process returns to the “on state” via the “power non-supply state”. Then, the CPU 10 reads out processing data used in the specified processing from the flash memory 40 and stores it in the RAM 30. As a result, it is possible to quickly execute a process that is likely to be performed when the display device 1 returns to the “on state”.

(B3) In the above-described embodiment, the process data used in the process instructed by the user is restored, but the present invention is not limited to this. For example, the CPU 10 may restore processing data used in processing that was active before shifting to the “off state”. The active process here is a process in which the user is working among a plurality of processes that are processed by multitasking. In most cases, the process progresses in the foreground of the display screen. This is the process being displayed. In this case, when the processing data of the active process is stored in the flash memory 40, the CPU 10 adds information indicating the active process. In this configuration, after starting the display device 1 in step S22 of FIG. 6 described above, the CPU 10 reads processing data to which information indicating active processing is added from the flash memory 40 and stores it in the RAM 30. Let As a result, it is possible to quickly execute a process that is likely to be performed when the display device 1 returns to the “on state”.

(Modification 5)
In the above-described embodiment, the data saving is performed at the transition timing at which the startup state of the display device 1 shifts from the “power supply state” to the “power non-supply state”. However, the present invention is not limited to this, and the processing data may be saved using a period in which processing and processes by the CPU 10 are not performed. For example, the CPU 10 may save the processing data used in each process when each process ends. Alternatively, the CPU 10 may save the processing data used in each process every time each process constituting each process ends. Further, the CPU 10 may use both of these. According to this configuration, even if the user does not save the processing data one by one, the processing data is automatically stored in the flash memory 40. As a result, for example, it is possible to prevent a situation in which the processing data has disappeared because the processing has been completed without saving the processing data due to power shortage or the like. Furthermore, in this configuration, the CPU 10 may shift the activation state of the display device 1 from the “on state” to the “power non-supply state” each time each process is completed. Thereby, the power consumption of the display apparatus 1 can be reduced.

(Modification 6)
In the above-described embodiment, the order in which a plurality of processing data is saved is not particularly described. However, in the configuration in which the processing data is saved using a period in which no processing or process is performed as in the fifth modification example. The order of saving the processing data may be as follows.
(C1) The CPU 10 may save the processing data using the processing data in ascending order of execution frequency. In this case, the flash memory 40 stores the frequency with which the processing using the processing data is performed for each processing data. This frequency may be an absolute value of the number of times the process has been executed, as in the third modification, or may be a result of relative evaluation of the number of times the process has been executed. When there is a period during which no processing or process is performed, the CPU 10 reads out the processing data stored in the RAM 30 in order from the least frequently executed and stores them in the flash memory 40. In this configuration, processing data used in processing with high execution frequency is saved after processing data used in processing with low execution frequency. In this way, it is possible to preferentially save process data of a process that is unlikely to be executed, that is, process data that is unlikely to be changed, so that the entire save operation can be performed quickly. it can.

(C2) When processing data of a process that is highly likely to be performed after the process being executed is stored in the RAM 30, the CPU 10 stores processing data of a process other than a process that is likely to be performed later. Evacuate first. In this case, in the flash memory 40, the process name of each process and the process name of the process that is likely to be performed after the process are stored in association with each other in the same manner as in the third modification. . That is, this correspondence may be specified by the user in the same manner as described above, may be determined by the CPU 10 based on the contents of the process, or determined by the CPU 10 based on the execution order of the processes. May be. When there is a period during which no process or process is performed, the CPU 10 specifies a process to be executed after the process being executed based on the above-described correspondence. Subsequently, the CPU 10 determines whether or not the process data used in the specified process is stored in the RAM 30. If the process data is stored, the CPU 10 reads the process data other than the process data and stores it in the flash memory 40. Remember me. In this way, it is possible to preferentially save the processing data of a process that is unlikely to be executed to the flash memory 40, so that the entire saving operation can be quickly performed.

(Modification 7)
The above-described embodiment is an example in which the data management device including the CPU 10, the RAM 30, and the flash memory 40 is applied to the display device, but is not limited thereto. In short, this data management device, processing means for performing processing using processing data stored in the storage means for maintaining the state of storing data without receiving power supply, and outputting the result processed by the processing means The present invention can be applied to an information processing apparatus that includes an output unit that performs output.
In the above-described embodiment, the CPU 10 performs a process for saving data from the RAM 30 and a process for restoring data from the flash memory 40. Instead of the CPU 10, a control device dedicated to storage means such as an MMU (Memory Management Unit) may perform these processes. The specific operation is as follows. First, the CPU 10 requests processing data of processing instructed by the user from the MMU. When the requested processing data is stored in the RAM 30, the MMU notifies the CPU 10 that the processing data is stored in the RAM 30. The CPU 10 executes processing instructed by the user based on the processing data stored in the RAM 30. On the other hand, if the requested processing data is not stored in the RAM 30, the MMU notifies the CPU 10 of a fault signal to that effect. In response to this notification, the CPU 10 instructs the MMU to restore the requested processing data from the flash memory 40 to the RAM 30. In response to this instruction, the MMU stores the processing data read from the flash memory 40 in the RAM 30 and notifies the CPU 10 to that effect. The CPU 10 executes processing instructed by the user based on the processing data stored in the RAM 30.

(Modification 8)
In the embodiment described above, when the display device 1 is returned from the “off state” to the “on state”, the user operates the operation unit 50 to specify a desired program and instruct to execute it. However, in addition to this, there are various methods for instructing processing. For example, the CPU 10 may display a list of process names of processes that were being executed when the power was turned off last time on the display unit 60, and allow the user to select a desired process from the list. Further, when the user desires the process A, the user presses the “1” keypad (not shown) of the operation unit 50, and when the user desires the process B, the user presses the “2” keypad (not shown) of the operation unit 50. For example, a method in which the user performs an operation determined for each process may be used.

(Modification 9)
In the above-described embodiment, the transition from the “on state” to the “sleep state” is performed when the standby time of the CPU 10 is equal to or longer than a predetermined time, but this transition condition is not limited to this. For example, the predetermined time may be lengthened or shortened according to the content of the process being executed in the “on state”. For example, in the “ON state”, when the CPU 10 enters a standby state after the menu screen display process for prompting the user to select a menu is performed, the standby time is longer than a normal predetermined time. You may make it shift from "on state" to "sleep state" when it becomes long time or more. This is because the reason that the CPU 10 is in the standby state is not the interruption or cancellation of the work by the user, but the case where the user takes time to make an operation decision.

  In addition, when the standby time of the CPU 10 is equal to or longer than a predetermined time, the viewpoint of which is to reduce the power consumption, whether the display device 1 is shifted to the “off state” or the “sleep state”. You may make it judge from. That is, when the CPU 10 shifts to the “sleep state” to reduce power consumption, the CPU 10 shifts the display device 1 to the “sleep state” without shifting to the “off state”.

  Here, with reference to FIG. 12, the power consumption in each starting state is demonstrated. As shown in the figure, in the “off state”, the power consumption is almost zero, but when returning from the “off state” to the “on state”, a large amount of power is temporarily required to activate each part of the display device 1. Consume power. Therefore, when the “off state” time is short, power consumption is better when returning to the “on state” via the “sleep state” than to returning to the “on state” via the “off state”. Will be reduced. Therefore, the flash memory 40 has a transition condition for shifting from the “on state” to the “off state” or the “sleep state” until the transition to the “on state” again after the transition. The transition conditions that reduce the power consumption required are stored in advance. Then, the CPU 10 determines whether to shift from the “on state” to the “off state” or the “sleep state” based on the transition condition, and shifts to the determined state. In this way, power consumption in the display device 1 can be reduced.

  More specifically, the CPU 10 records a time during which the display device 1 is in the “off state” using a timer that constantly receives power from the power supply unit 70, and based on the recording time, “ It is determined whether to shift to “off state” or “sleep state”. For example, in the case where the time of the previous “off state” is less than the threshold, the display device 1 is shifted to the “sleep state” when the standby time of the CPU 10 is equal to or longer than a predetermined time. On the other hand, when the time when the previous “off state” was equal to or greater than the threshold value, the display device 1 is shifted to the “off state” when the standby time of the CPU 10 is equal to or longer than the predetermined time. In this case, the threshold value to be compared with the previous standby time is based on the power consumption when returning to the “on state” via the “off state” as described in FIG. 12 and the “sleep state”. Thus, the power consumption when returning to the “on state” is equal. Then, the transition condition stored in the flash memory 40 at this time is an algorithm of whether to shift to the “off state” or the “sleep state” based on the threshold value, the previous standby time, and the magnitude relationship between them. It is.

  Further, when the average value of the time when the display device 1 has been in the “off state” in the past is less than the threshold value, the display device 1 shifts to the “sleep state” when the standby time of the CPU 10 exceeds a predetermined time. Let On the other hand, when the average value of the time during which the display device 1 has been in the “off state” in the past is equal to or greater than the threshold value, the display device 1 is shifted to the “off state” when the standby time of the CPU 10 exceeds the predetermined time. Let In this case as well, the power consumption when returning to the “on state” via the “off state” is equal to the power consumption when returning to the “on state” via the “sleep state”. It is time to become. The transition condition stored in the flash memory 40 at this time is based on the threshold value, the average value of the time when the display device 1 has been in the “off state” in the past, and the magnitude relation between these values. ”Or“ sleep state ”.

  If the CPU 10 determines that the process executed in the “on state” is a type of process that immediately returns to the “on state” even if the “off state” is entered, It is also possible to shift to the “sleep state” without shifting to the “off state”. Whether the process is immediately returned to the “on state” or not may be determined in advance according to the contents of each process, or may be obtained by learning from the past processing history by the CPU 10. Good. In this case, the transition condition stored in the flash memory 40 is based on the process name of the process and the process name of the process that are determined in advance to be a type of process that is immediately returned to the “on state”. This is an algorithm for shifting to an off state or a sleep state.

(Modification 10)
In the above-described embodiment, the RAM 30 is exemplified as the first storage unit that maintains the state where the data is stored by receiving the power supply, and the second storage unit maintains the state where the data is stored without receiving the power supply. Although the flash memory 40 has been illustrated, specific examples of these storage means are not limited to the illustration of the embodiment.

(Modification 11)
In the above-described embodiment, the “on state” and the “sleep state” are set as the “power supply state”, and the “off state” is set as the “power supply non-supply state”. Whether it is classified as “supply state” or “non-power supply state” may be determined depending on whether or not power is supplied to the RAM 30. When the “sleep state” is classified as the “non-power supply state”, the CPU 10 determines whether or not its standby time is a predetermined time or more in step S13 of FIG. If so, the process proceeds to step S14. In step S16, the CPU 10 shifts the activation state of the display device 1 from the “on state” to the “sleep state”. Thereby, the data saving process is executed when the activation state of the display device 1 is shifted from the “on state” to the “sleep state”. In steps S21 and S22 described above, when the operation unit 50 is operated by the user, the CPU 10 shifts the activation state of the display device 1 from the “sleep state” to the “on state”. As a result, the data restoration process is executed when the activation state of the display device 1 returns from the “sleep state” to the “on state”.

(Modification 12)
The program executed by the CPU 10 of the display device 1 described above is a recording such as a magnetic tape, a magnetic disk, a flexible disk, an optical recording medium, a magneto-optical recording medium, a CD (Compact Disk), a DVD (Digital Versatile Disk), and a RAM. It can be provided as recorded on the medium. Moreover, it is also possible to make the display device 1 download via a network such as the Internet. That is, the present invention can be realized as a program.

It is a figure which shows the structure of the display apparatus which concerns on this embodiment. It is a flowchart which shows the data saving process by the display apparatus. It is a figure which shows an example of the memory content of RAM and flash memory which concerns on this embodiment. It is a figure which shows an example of the display screen accompanying execution of the process A and B. FIG. It is a figure which shows an example of the data management table which concerns on this embodiment. It is a flowchart which shows the data restoration process by the display device. 12 is a diagram illustrating an example of a display screen that accompanies execution of process B. FIG. It is a figure which shows an example of the display screen accompanying execution of the process A. FIG. It is a figure which shows an example of the memory content of RAM which concerns on a modification, and flash memory. It is a figure which shows an example of the memory content of RAM which concerns on a modification, and flash memory. It is a figure which shows an example of the data management table which concerns on a modification. It is a figure explaining the power consumption in each starting state.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 10 ... CPU, 20 ... ROM, 30 ... RAM, 40 ... Flash memory, 50 ... Operation part, 60 ... Display part, 70 ... Power supply part, 80 ... Bus.

Claims (12)

First storage means for maintaining a state in which data is stored by receiving power supply;
Second storage means for maintaining a state of storing data without receiving power supply;
State transition means for shifting to either a power supply state for supplying power to the first storage means or a power non-supply state for not supplying power to the first storage means;
The data stored in the first storage unit is divided into a plurality of data and stored in the second storage unit until the state shift unit shifts from the power supply state to the power non-supply state. First storage control means for causing
Correspondence storage means for storing the correspondence between the storage locations of the respective data stored in the second storage means by the first storage control means and the processing related to the data;
When the state transition means shifts from the non-power supply state to the power supply state, the storage location corresponding to each of the processes is specified based on the correspondence stored by the correspondence storage means Means,
Second storage control means for reading data stored in each storage location specified for each processing by the specifying means from the second storage means and storing the data in the first storage means A data management device characterized by the above. The first storage control means divides the data stored in the first storage means into a plurality of data in units of processing using the data and stores the data in the second storage means. The data management apparatus according to claim 1, wherein: The first storage control means divides the data stored in the first storage means into a plurality of data in a predetermined data size unit and stores the data in the second storage means. The data management apparatus according to claim 1. The specifying means is:
Process identification information of a certain first process among the plurality of processes and process identification information of a second process performed after the first process are stored in association with each other, and the power supply state When the first process is specified as the process to be performed in the process, the second process of the process identification information stored in association with the process identification information of the first process is performed as the process performed after the first process. Identifying a process, identifying the storage location corresponding to the second process based on the correspondence stored by the correspondence storage means,
The second storage control means
The data stored in the storage location specified by the specifying unit as corresponding to the second process is read from the second storage unit and stored in the first storage unit. Item 2. A data management device according to item 1. The specifying means is:
The order of a plurality of processes performed in accordance with a user instruction in the power supply state is recorded, and the process identification information of the certain first process and the first process are performed from the recorded order. The data management apparatus according to claim 4, wherein the process identification information of the second process is specified and stored. The first storage control means includes
The process identification information of a certain first process among the plurality of processes and the process identification information of a second process performed after the first process are stored in association with each other,
When the first process is performed in the power supply state, the process identification information of the second process stored in association with the process identification information of the first process is specified,
Of the plurality of data obtained by dividing the data stored in the first storage unit, data other than data related to the second process is stored in the second storage unit, and then the second storage unit stores the data. The data management apparatus according to claim 1, wherein data related to the processing of 2 is stored. The first storage control means includes
The order of a plurality of processes performed in accordance with a user instruction in the power supply state is recorded, and the process identification information of the certain first process and the first process are performed from the recorded order. The data management apparatus according to claim 6, wherein the process identification information of the second process is specified and stored. For each data sectioned by the first storage control means, a frequency storage means for storing the frequency at which processing related to the data is performed,
The second storage control unit reads each of the data from the second storage unit in descending order of frequency of processing related to the data, and stores the data in the first storage unit. The data management apparatus according to claim 1. For each data sectioned by the first storage control means, a frequency storage means for storing the frequency at which processing related to the data is performed,
The said 1st memory | storage control means memorize | stores each said data in a said 2nd memory | storage means in an order from the low frequency with which the process relevant to the said data was performed. Data management device. The power supply state includes a first power supply state with high power consumption and a second power supply state with low power consumption,
The state transition means includes
A transition condition for transitioning from the first power supply state to either the power non-supply state or the second power supply state, and transitioning again to the first power supply state after the transition Remember the transition conditions that reduce the power consumption required to
Based on the stored transition condition, it is determined whether to shift from the first power supply state to the power non-supply state or from the first power supply state to the second power supply state. The data management apparatus according to claim 1, wherein the data management apparatus shifts to a determined state. The data management device according to any one of claims 1 to 10,
Processing means for performing processing using data stored in the first storage means;
An information processing apparatus comprising: output means for outputting a result processed by the processing means. A computer comprising first storage means for maintaining a state in which data is stored upon receiving power supply, and second storage means for maintaining a state in which data is stored without receiving power supply,
State transition means for shifting to either a power supply state for supplying power to the first storage means or a power non-supply state for not supplying power to the first storage means;
The data stored in the first storage unit is divided into a plurality of data and stored in the second storage unit until the state shift unit shifts from the power supply state to the power non-supply state. First storage control means for causing
Correspondence storage means for storing the correspondence between the storage locations of the respective data stored in the second storage means by the first storage control means and the processing related to the data;
When the state transition means shifts from the non-power supply state to the power supply state, the storage location corresponding to each of the processes is specified based on the correspondence stored by the correspondence storage means Means,
Functions as second storage control means for reading data stored in each storage location specified for each processing by the specifying means from the second storage means and storing the data in the first storage means Program to let you.

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