JP2009104271A - Audio data reproducing unit and audio data reproducing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an audio data reproducing unit and an audio data reproducing method for reducing power consumption when decoding and reproducing audio data. <P>SOLUTION: The audio data reproducing unit comprises: a DRAM 2 that needs to be refreshed; an SRAM 5 that does not need to be refreshed; an audio decoder 4 for decoding compressed audio data stored in the DRAM 2; and a CPU 9 for controlling the operation state of the DRAM 2. The SRAM 5 stores audio data decoded by the audio decoder 4. The CPU 9 performs control so that the DRAM 2 is placed in accessible normal refresh mode when the audio data stored in the DRAM 2 is decoded by the audio decoder 4, and performs control so that the DRAM 2 is placed in non-accessible self-refresh mode after the audio data decoded by the audio decoder 4 are stored in the SRAM 5. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an audio data reproduction device and an audio data reproduction method.

In a portable audio data reproducing device, the capacity of a battery to be mounted is limited so as not to impair its portability. Therefore, the reproducible time is limited depending on the capacity of the battery once charged or replaced. Therefore, there is a demand for a technique that can reproduce audio data for a longer time using a battery that has been charged or replaced once.
Therefore, conventionally, in a portable audio data reproducing apparatus, a power saving control technique such as stopping the supply of a clock or power to an unused device is used. For example, a CPU (Central Processing Unit) and an audio decoder are in an idle state during a period when no processing is performed, and the operating frequency is lowered. By using these power saving control technologies, the power consumption of the entire apparatus is reduced.

Also, in Patent Document 1, in a mobile phone, centralized refresh processing with high power consumption is performed only before and after standby processing, and only SRAM is used as an access area during standby processing. Thus, a technique for reducing power consumption by performing a self-refresh process with low power consumption is described.
JP 2002-222116 A

  However, when the compressed audio data is reproduced while being decoded, access to a DRAM (Dynamic Random Access Memory) built in the audio data reproducing apparatus frequently occurs. Therefore, the power supply to the DRAM cannot be stopped when the audio data is decoded / reproduced. Specifically, when decoding / reproducing audio data, it is necessary to enable access to a DRAM such as a CPU or an audio decoder. Therefore, when audio data is decoded / reproduced, normal refresh processing that allows access to the DRAM is performed. The power consumption of the normal refresh process is high. Therefore, the power consumption of the entire apparatus becomes high at the time of decoding / reproducing audio data.

  The technique described in Patent Document 1 reduces power consumption by performing self-refresh processing with low power consumption on a DRAM in standby processing in which audio data is not decoded and reproduced. During the self-refresh process, access to the DRAM is impossible. Therefore, the technique described in Patent Document 1 cannot solve the above problem.

  An audio data reproducing device according to a first aspect of the present invention decodes a first RAM that requires refresh, a second RAM that does not require refresh, and compressed audio data stored in the first RAM. A decoding unit; and a control unit that controls a refresh operation state of the first RAM. The second RAM stores the audio data decoded by the decoding means. In addition, the control unit is configured so that when the audio data stored in the first RAM is decoded by the decoding unit, the refresh operation state of the first RAM becomes a normal operation state accessible. At the same time, after the audio data decoded by the decoding means is stored in the second RAM, the refresh operation state of the first RAM is controlled to be an inaccessible power saving state.

  The audio data reproducing method according to the second aspect of the present invention decodes a first RAM that requires refresh, a second RAM that does not require refresh, and compressed audio data stored in the first RAM. An audio data reproducing method of an audio data reproducing apparatus comprising: a decoding means, wherein the audio data reproducing apparatus includes a control unit that controls a refresh operation state of the first RAM, and the second RAM includes: The audio data decoded by the decoding unit is stored, and the control unit is configured to perform a refresh operation state of the first RAM when the audio data stored in the first RAM is decoded by the decoding unit. And the decoding means After more decoded audio data is stored by the second RAM, and controls so that a refresh operation state of the first RAM becomes inaccessible power saving state.

  In the present invention, a first RAM that requires refresh, a second RAM that does not require refresh, a decoding means for decoding compressed audio data stored in the first RAM, and a refresh operation of the first RAM A control unit that controls the state, and the second RAM stores the audio data decoded by the decoding unit, and the control unit decodes the audio data stored in the first RAM by the decoding unit. The first RAM is controlled so that the refresh operation state of the first RAM becomes an accessible normal operation state, and the audio data decoded by the decoding means is stored in the second RAM. The refresh operation state is controlled to be an inaccessible power saving state.

  As a result, the compressed audio data stored in the first RAM is decoded by the decoding means and then stored in the second RAM. For this reason, after the decoded audio data is stored in the second RAM, access to the first RAM is lost. Then, after the decoded audio data is stored in the second RAM, the control unit shifts the refresh operation state of the first RAM to the power saving state, so that while the first RAM is not accessed, The refresh operation state of the first RAM can be set to a power saving state. Therefore, it is possible to further reduce the power consumption of the audio data playback apparatus in decoding and playback of audio data.

  According to the present invention, it is possible to further reduce the power consumption of an audio data reproducing apparatus in decoding and reproducing audio data.

Hereinafter, embodiments to which the present invention can be applied will be described. Note that the present invention is not limited to the following embodiments.
FIG. 1 shows an example of an audio data reproducing apparatus 100 according to an embodiment of the present invention. As shown in FIG. 1, the audio data reproducing device 100 includes a flash memory 1, an external memory 2 (first RAM (Random Access Memory)), and a processor LSI 3.
The processor LSI 3 includes an audio decoder (decoding means) 4, a built-in memory 5 (second RAM), a DMA (Direct Memory Access) controller (transfer means) 6, a PCM (Pulse Code Modulation) controller (output means) 7, It has a clock / power supply controller 8 and a CPU (control unit) 9. Then, the processor LSI 3 controls the entire audio data reproducing apparatus 100.

The flash memory 1 stores compressed audio data.
The external memory 2 includes a DRAM that needs to be refreshed. Hereinafter, the external memory 2 is referred to as DRAM 2. Here, the refresh is an operation for holding the memory of the DRAM 2. Specifically, the memory cell of the DRAM 2 is composed of a capacitor and a transistor. Therefore, it is necessary to repeat charging in order to prevent the stored data from being lost due to a decrease in the charge of the capacitor over time. Such an operation of repeatedly charging is called refresh.
The refresh operation state of the DRAM 2 (hereinafter simply referred to as an operation state) is controlled by the CPU 9. The operation state of the DRAM 2 includes normal refresh (normal operation state) with high power consumption and self-refresh (power saving state) with low power consumption. When the operation state is normal refresh, access to the DRAM 2 is possible. Further, when the operation state is self-refresh, access to the DRAM 2 is impossible.
Also, the audio data stored in the flash memory 1 is expanded in the DRAM 2. Specifically, the compressed audio data stored in the flash memory 1 is temporarily stored in the DRAM 2 and decoded by the audio decoder 4.

The audio decoder 4 decodes the audio data stored in the DRAM 2. Specifically, the audio decoder 4 decodes the audio data stored in the S address of the DRAM 2 and outputs it to the built-in memory 5.
The audio decoder 4 instructs the DMA controller 6 to transfer the audio data stored in the built-in memory 5 to the PCM controller 7 and notifies the CPU 9.
Further, the audio decoder 4 notifies the CPU 9 of the reproduction completion when a completion notification (described later) is notified from the DMA controller 6.

  The built-in memory 5 includes an SRAM that does not require refreshing. Hereinafter, the built-in memory 5 is referred to as SRAM 5. The SRAM 5 stores the audio data decoded by the audio decoder 4 at address D.

The DMA controller 6 transfers the audio data stored in the SRAM 5 to the PCM controller 7.
The DMA controller 6 notifies the audio decoder 4 of completion when transfer of audio data from the SRAM 5 to the PCM controller 7 is completed.

  The PCM controller 7 outputs the audio data stored in the SRAM 5 to the outside as PCM data.

  The clock / power supply controller 8 performs control to reduce the clock and power supplied to the unused device. For example, the clock / power supply controller 8 reduces the clock supplied to the CPU 9 or the power supplied to the CPU 9 when the CPU 9 is in an idle state.

When the audio data stored in the DRAM 2 is decoded by the audio decoder 4, the CPU 9 controls the operation state of the DRAM 2 to be normal refresh, and the audio data decoded by the audio decoder 4 is stored in the SRAM 5. Then, the operation state of the DRAM 2 is controlled to be self-refreshing.
Specifically, when the CPU 9 is notified by the audio decoder 4 that the audio data stored in the SRAM 5 is instructed to be transferred to the PCM controller 7, the operation state of the DRAM 2 becomes self-refreshing. To control.
Further, the CPU 9 controls the operation state of the DRAM 2 to be normal refresh when a reproduction completion notification is given from the audio decoder 4.
The CPU 9 stores the audio data decoded by the audio decoder 4 in the SRAM 5 and controls the operation state of the DRAM 2 to be self-refreshed, and then the audio data from the SRAM 5 to the PCM controller 7 by the DMA controller 6. The transition is made to the idle state until the transfer is completed and the operation state of the DRAM 2 is controlled to be normal refresh.

Next, an audio data reproduction method in the conventional audio data reproduction apparatus will be described with reference to the flowcharts shown in FIGS. Note that the operation state of the DRAM is normally refreshed in the initial stage (step S0).
First, the CPU copies the audio data compressed from the flash memory to the S address of the DRAM (step S1).
Next, the CPU instructs the audio decoder to decode the audio data stored in the DRAM (step S2). Next, the CPU transits to an idle state (step S3).

Next, the audio decoder decodes the audio data stored in the S address of the DRAM and stores it in the D address of the DRAM (step S4).
Next, the audio decoder instructs the DMA controller to transfer the audio data stored in the D address of the DRAM to the PCM controller (step S5). Next, the audio decoder transitions to an idle state (step S6).

Next, the DMA controller transfers the audio data stored at address D of the DRAM to the PCM controller (step S7).
Next, when the transfer of audio data from the D address of the DRAM to the PCM controller is completed, the DMA controller notifies the audio decoder of a completion notification (step S8).

Next, the audio decoder notifies the CPU of a reproduction completion notification of audio data (step S9).
Next, when a playback completion notification is received from the audio decoder, the CPU transitions from the idle state to the normal state (step S10) and returns to step S1.

Next, an audio data reproduction method in the audio data reproduction apparatus 100 according to the embodiment of the present invention will be described with reference to the flowcharts shown in FIGS. The operation state of the DRAM 2 is normally refreshed in the initial stage (step S100).
First, the CPU 9 copies the audio data compressed from the flash memory 1 to the S address of the DRAM 2 (step S101).
Next, the CPU 9 instructs the audio decoder 4 to decode the audio data stored in the DRAM 2 (step S102).

Next, the audio decoder 4 decodes the audio data stored in the S address of the DRAM 2 and stores it in the D address of the SRAM 5 (step S103).
Next, the audio decoder 4 instructs the DMA controller 6 to transfer the audio data stored in the D address of the SRAM 5 to the PCM controller 7 and notifies the CPU 9 of that fact (step S104). Next, the audio decoder 4 transitions to an idle state (step S105).

When notified by the audio decoder 4 in step S104, the CPU 9 controls the operation state of the DRAM 2 to be self-refreshing (step S106). Next, the CPU 9 transitions to an idle state (step S107).
The operation state of the DRAM 2 is self-refreshed under the control of step S106 (step S108).

On the other hand, the DMA controller 6 transfers the audio data stored in the D address of the SRAM 5 to the PCM controller 7 (step S109).
Next, when the transfer of audio data from the D address of the SRAM 5 to the PCM controller 7 is completed, the DMA controller 6 notifies the audio decoder 4 of a completion notification (step S110).

Next, the audio decoder 4 transitions from the idle state to the normal state (step S111), and notifies the CPU 9 of the audio data reproduction completion notification (step S112).
Next, when a playback completion notification is received from the audio decoder 4, the CPU 9 changes from the idle state to the normal state (step S113), and controls the operation state of the DRAM 2 to be normal refresh (step S114).
Next, the operation state of the DRAM 2 becomes normal refresh under the control of step S114 (step S115), and the process returns to step S101.

Next, the relationship between current consumption and playback time in the audio data playback apparatus 100 according to the embodiment of the present invention will be described with reference to the graph shown in FIG.
First, at time t1 shown in FIG. 6, the audio decoder 4 notifies the CPU 9 of completion of reproduction. Thereby, the CPU 9 controls the operation state of the DRAM 2 so as to be normal refresh. Next, at time t2, the audio decoder 4 notifies the CPU 9 that the DMA controller 6 has been instructed to transfer audio data from the SRAM 5 to the PCM controller 7. Thereby, the CPU 9 controls the operation state of the DRAM 2 to be self-refreshing. Next, at time t3, the audio decoder 4 notifies the CPU 9 of completion of reproduction. Thereby, the CPU 9 controls the operation state of the DRAM 2 so as to be normal refresh.
In general, in decoding and reproduction of audio data, the DMA controller 6 transfers the audio data to the PCM controller 7 rather than the time during which the CPU 9 and the audio decoder 4 are operating (corresponding to the time between t1 and t2 in FIG. 6). The longer time (corresponding to the time between t2 and t3 in FIG. 6) is longer. Therefore, in the embodiment of the present invention, the time for the self refresh is longer than the time for the operation state of the DRAM 2 to be the normal refresh. Therefore, as in the embodiment of the present invention, transitioning the operation state of the DRAM 2 to the self-refresh (power saving state) during the operation of the DMA controller 6 has a great effect on power consumption reduction.

  In the audio data reproducing apparatus 100 and the audio data reproducing method according to the embodiment of the present invention described above, the DRAM 2 that needs to be refreshed, the SRAM 5 that does not need to be refreshed, and the audio that decodes the compressed audio data stored in the DRAM 2. A decoder 4 and a CPU 9 for controlling the operation state of the DRAM 2 are provided. The SRAM 5 stores the audio data decoded by the audio decoder 4. In addition, when the audio data stored in the DRAM 2 is decoded by the audio decoder 4, the CPU 9 controls the operation state of the DRAM 2 to be accessible normal refresh, and the audio data decoded by the audio decoder 4 is controlled. After the data is stored in the SRAM 5, the operation state of the DRAM 2 is controlled to be inaccessible self-refresh.

  Thereby, the compressed audio data stored in the DRAM 2 is decoded by the audio decoder 4 and then stored in the SRAM 5. Therefore, after the decoded audio data is stored in the SRAM 5, there is no access to the DRAM 2. After the decoded audio data is stored in the SRAM 5, the operation state of the DRAM 2 is transitioned to the self-refresh by the CPU 9, so that the operation state of the DRAM 2 is changed to the power saving state (self-refresh) while the DRAM 2 is not accessed. Can be. Therefore, it is possible to further reduce the power consumption of the audio data reproducing apparatus 100 in decoding and reproducing the audio data.

The CPU 9 also includes a PCM controller 7 that outputs audio data to the outside, and a DMA controller 6 that transfers audio data stored in the SRAM 5 to the PCM controller 7. The CPU 9 converts the audio data from the SRAM 5 to the PCM controller by the DMA controller 6. When the transfer to 7 is completed, the operation state of the DRAM 2 is controlled to be normal refresh.
As a result, when the transfer of audio data from the SRAM 5 to the PCM controller 7 is completed and the compressed audio data is stored again in the DRAM 2 and decoded, the DRAM 2 can be accessed. Can do.

The CPU 9 stores the audio data decoded by the audio decoder 4 in the SRAM 5 and controls the operation state of the DRAM 2 to be self-refreshed, and then the audio data from the SRAM 5 to the PCM controller 7 by the DMA controller 6. The idle state is maintained until the transfer is completed and the operation state of the DRAM 2 is controlled to be normal refresh.
Thereby, since the CPU 9 is in an idle state while not controlling the operation state of the DRAM 2, power consumption in the CPU 9 can be reduced.

The audio decoder 4 stores the decoded audio data in the SRAM 5, and then instructs the DMA controller 6 to transfer the audio data stored in the SRAM 5 to the PCM controller 7 and notifies the CPU 9.
Thereby, the CPU 9 can detect that the access to the DRAM 2 is lost by the notification and can control the operation state of the DRAM 2 to be self-refreshing.

Further, the DMA controller 6 notifies the audio decoder 4 when the transfer of the audio data from the SRAM 5 to the PCM controller 7 is completed, and the audio decoder 4 plays back to the CPU 9 when the completion notification is notified. Notify completion.
Thereby, the CPU 9 can detect that the transfer of the audio data from the SRAM 5 to the PCM controller 7 is completed by the reproduction completion notification, and can control the operation state of the DRAM 2 to be normal refresh.

It is a block diagram which shows an example of schematic structure of the audio data reproducing | regenerating apparatus concerning embodiment of this invention. It is a flowchart which shows the audio data reproduction method in the conventional audio data reproduction apparatus. It is a flowchart which shows the audio data reproduction method in the conventional audio data reproduction apparatus. It is a flowchart which shows the audio data reproduction method in the audio data reproduction apparatus concerning embodiment of this invention. It is a flowchart which shows the audio data reproduction method in the audio data reproduction apparatus concerning embodiment of this invention. It is a graph which represents typically the relationship between the consumption current and reproduction time in the audio data reproducing | regenerating apparatus concerning embodiment of this invention.

Explanation of symbols

2 DRAM (first RAM)
4 Audio decoder (decoding means)
5 SRAM (second RAM)
6 DMA controller (transfer means)
7 PCM controller (output means)
9 CPU (control unit)
100 Audio data playback device

Claims (10)

A first RAM that needs to be refreshed;
A second RAM that does not require refresh;
Decoding means for decoding the compressed audio data stored in the first RAM;
A control unit for controlling a refresh operation state of the first RAM;
With
The second RAM stores the audio data decoded by the decoding means,
The control unit controls the refresh operation state of the first RAM to be an accessible normal operation state when the audio data stored in the first RAM is decoded by the decoding unit. And an audio data reproducing apparatus for controlling the refresh operation state of the first RAM to an inaccessible power saving state after the audio data decoded by the decoding means is stored in the second RAM. . Output means for outputting audio data to the outside;
Transfer means for transferring audio data stored in the second RAM to the output means;
With
The control unit controls the refresh operation state of the first RAM to be the normal operation state when the transfer of audio data by the transfer unit from the second RAM to the output unit is completed. The audio data reproducing apparatus according to claim 1.   The control section controls the transfer means after the audio data decoded by the decoding means is stored in the second RAM and the refresh operation state of the first RAM is controlled to the power saving state. Until the audio data is transferred from the second RAM to the output means and the refresh operation state of the first RAM is controlled to become the normal operation state. The audio data reproducing apparatus according to claim 2.   The decoding means instructs the transfer means to transfer the audio data stored in the second RAM to the output means after storing the decoded audio data in the second RAM, and The audio data reproducing device according to claim 2 or 3, wherein notification is given to the control unit.   When the transfer of the audio data from the second RAM to the output unit is completed, the transfer unit notifies the decode unit of completion, and the decode unit receives the completion notification, The audio data reproducing apparatus according to claim 2, wherein a reproduction completion notification is sent to the control unit. A first RAM that needs to be refreshed;
A second RAM that does not require refresh;
Decoding means for decoding the compressed audio data stored in the first RAM;
An audio data reproducing method for an audio data reproducing apparatus comprising:
The audio data reproducing device includes a control unit that controls a refresh operation state of the first RAM,
The second RAM stores the audio data decoded by the decoding means,
The control unit controls the refresh operation state of the first RAM to be an accessible normal operation state when the audio data stored in the first RAM is decoded by the decoding unit. And an audio data reproducing method for controlling the refresh operation state of the first RAM to an inaccessible power saving state after the audio data decoded by the decoding means is stored in the second RAM. . The audio data reproduction device includes:
Output means for outputting audio data to the outside;
Transfer means for transferring audio data stored in the second RAM to the output means;
With
The control unit controls the refresh operation state of the first RAM to be the normal operation state when the transfer of audio data by the transfer unit from the second RAM to the output unit is completed. The audio data reproducing method according to claim 6.   The control section controls the transfer means after the audio data decoded by the decoding means is stored in the second RAM and the refresh operation state of the first RAM is controlled to the power saving state. Until the audio data is transferred from the second RAM to the output means and the refresh operation state of the first RAM is controlled to become the normal operation state. The audio data reproducing method according to claim 7.   The decoding means instructs the transfer means to transfer the audio data stored in the second RAM to the output means after storing the decoded audio data in the second RAM, and The audio data reproducing method according to claim 7 or 8, wherein notification is given to the control unit.   When the transfer of the audio data from the second RAM to the output unit is completed, the transfer unit notifies the decode unit of completion, and the decode unit receives the completion notification, The audio data reproduction method according to claim 7, wherein a reproduction completion notification is sent to the control unit.

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