JP2009103810A - Liquid crystal display and repair method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display, capable of avoiding dark spots at all times, due to short circuiting among pixel electrodes. <P>SOLUTION: A TFT 1 is provided with a cutting planned part R for separation from a subpixel electrode Px1 or a source bus line SL1. When a planar shorting S is generated between subpixel electrodes Px1, Px2, the TFT 1, the subpixel electrode Px1 and the source bus line SL1 are separated by the cutting planned part R. All the subpixel electrodes Px1, Px2 are connected to a remaining TFT 2 so that charging current i flows via the shorting S. All the subpixel electrodes Px1, Px2 are applied with a voltage of one polarity so as to avoid resulting in permanent dark spots due to leakage current. The TFT 1 having the cutting planned part R is connected to the subpixel electrode Px1 of a subpixel (A) of a smaller capacity. The TFT 2 has a 90% or higher charging rate, with respect to the total capacity of the subpixels (A), (B). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device particularly suitable for a VA (Vertical Alignment) mode and a repair method thereof.

  In recent years, a new technology called a multi-pixel has been introduced in a VA mode liquid crystal display device used for a liquid crystal television or the like in order to improve viewing angle characteristics in a halftone. As shown in FIG. 9, each pixel is divided into a plurality of sub-pixels A and B. The sub-pixel A first increases the luminance with respect to the input gradation, and the sub-pixel B increases the luminance later. In order to obtain better viewing angle characteristics, it is desirable to make the subpixel A small so that the area ratio of the subpixels A and B is about 1: 2 rather than 1: 1.

  10 (A) and 10 (B) show the configuration of the pixel electrode and common electrode of each of the sub-pixels A and B, respectively, and FIG. 10 (C) shows an equivalent circuit thereof. . There are several methods for applying a potential difference to the sub-pixels A and B. In FIGS. 10A to 10C, for example, the thin-film transistors (Thin Film Transistors) TFT1 and TFT2 dedicated to the sub-pixels A and B are used. Are arranged, and two source bus lines SL1 and SL2 are arranged on the same gate bus line GL to drive TFT1 and TFT2.

  The multi-pixel includes TFT1, TFT2, a liquid crystal element Clc1 constituting the subpixel A, a liquid crystal element Clc2 constituting the subpixel B, and capacitive elements Cst1, Cst2. The gates of TFT1 and TFT2 are connected to the gate bus line GL. The source of the TFT1 is connected to the source bus line SL1, and the drain is connected to one end of the liquid crystal element Clc1 and one end of the capacitive element Cst1. The source of the TFT2 is connected to the source bus line SL2, and the drain is connected to one end of the liquid crystal element Clc2 and one end of the capacitive element Cst2. The other end of the capacitive element Cst1 and the other end of the capacitive element Cst2 are connected to the capacitive element bus line CL.

  The pixel electrode Px1 for the subpixel A is connected to the TFT1, and the pixel electrode Px2 for the subpixel B is connected to the TFT2. As shown in the equivalent circuit diagram of FIG. 10C, the pixel electrode Px1 for the subpixel A and the pixel electrode Px2 for the subpixel B are electrically independent, and the pixel electrodes Px1 and Px2 are connected to the pixel electrodes Px1 and Px2, respectively. The voltage to be written is determined by the control circuit.

  The pixel electrodes Px1 and Px2 are provided with slits 112 for tilting liquid crystal molecules in a 45 degree direction as a configuration unique to the VA mode. Some of these slits 112 are shared with the slits that separate the pixel electrodes Px1 and Px2. On the other hand, the common electrode 121 disposed on the counter substrate also needs a slit 122 for regulating liquid crystal alignment. Note that as the liquid crystal alignment regulating means on the counter substrate side, an insulating protrusion (not shown) may be formed on the common electrode 121. In FIG. 10A, the slit 122 of the common electrode 121 is indicated by a broken line.

  11 and 12 are for explaining the width of the slit 112. The cell thickness d of the liquid crystal display device, that is, the distance between the TFT substrate 110 and the counter substrate 120 is usually about 4 μm. When the width of the slit 112 is sufficiently wide with respect to the cell thickness d, as shown in FIG. 11A, the equipotential surface of the slit 112 goes deep into the glass of the TFT substrate 110, and the slit 112 has a vertical direction. The electric field is weakened. Therefore, as shown in FIG. 11B, the vertical alignment of the liquid crystal molecules 131 in the slit 112 is maintained, while a sufficiently oblique electric field is generated on the pixel electrodes Px1 and Px2 in the vicinity of the slit 112. The orientation direction is stable.

  In the slit 112, the liquid crystal molecules 131 do not fall and do not contribute to the transmittance. Therefore, when the width of the slit 112 is widened, the substantial aperture ratio decreases and the transmittance decreases. On the other hand, when the width of the slit 112 is narrowed, the aperture ratio increases, but as shown in FIG. 12A, the electric field in the vicinity of the slit 112 is not gradually inclined, and as shown in FIG. The alignment stability of the liquid crystal molecules 131 is deteriorated. When the azimuth angle of the liquid crystal molecules 131 deviates from 45 degrees, the effect of the liquid crystal molecules 131 on the polarization changes, so that the transmittance per unit area decreases, and the overall transmittance decreases even if the aperture ratio increases.

  That is, as shown in FIG. 13, there is an optimum value for the width of the slit 112 with respect to the transmittance, and the width of the slit 112 is usually designed to be about 10 μm for a cell thickness d of 4 μm.

  FIG. 14 shows the orientation of the liquid crystal molecules 131 in the slit 112 when a voltage of opposite polarity is applied to the two pixel electrodes Px1 and Px2. In this case, the equipotential surface is greatly different from that in FIGS. 11A and 12A, and the equipotential surface enters the slit 112 perpendicularly between the pixel electrodes Px1 and Px2. In addition, a location having the same potential as the common electrode 121 is necessarily formed in the slit 112. In this place of the same potential, the liquid crystal molecules 131 do not fall down and are extremely stable vertically. On the other hand, the oblique electric field is strong, and as a result, the alignment of the liquid crystal molecules 131 is extremely stable. In addition, this effect increases as the width of the slit 112 becomes narrower.

  In FIG. 15, in consideration of this effect, the slit 112A between the pixel electrodes Px1 and Px2 is narrowed on the premise that voltages having opposite polarities are applied to the two pixel electrodes Px1 and Px2 in the multi-pixel of FIG. It is. Note that the slits 112B at the lower left corner and the upper left corner of the pixel and the slit 122 of the common electrode 121 of the counter substrate 120 do not correspond to the slits between the electrodes Px1 and Px2, and thus are designed as before.

FIG. 16 shows the transmittance when the interval between the slits 112A is narrowed as shown in FIG. When voltages having the same polarity are applied to the two pixel electrodes Px1 and Px2 (same polarity driving), the transmittance is reduced due to the deterioration of liquid crystal alignment when the interval between the slits 112 is 10 μm or less. It can be seen that when a reverse polarity voltage is applied to the electrodes Px1 and Px2 (reverse polarity driving), the transmittance can be improved by narrowing the slit 112A (see, for example, Patent Document 1).
JP 2005-316211 A

  However, as shown in FIG. 15, when the interval between the slits 112A is narrowed, there is a problem that the rate of increase in short-circuit defects between the pixel electrodes Px1 and Px2 increases drastically. Since the length of the slit 112A is very long, a slight dust is present in the screen during the manufacturing process, resulting in a defect.

  In the conventional pixel structure that is not a multi-pixel, the slit exists only for regulating the liquid crystal alignment, and the pixel electrode is all applied with the same polarity voltage. The liquid crystal alignment was not a problem because it was only a microscopic abnormality.

  Further, when the multi-pixel is not driven with the reverse polarity, voltages having the same polarity are applied to the pixel electrodes Px1 and Px2. Therefore, when there is a short circuit, the voltages of the pixel electrodes Px1 and Px2 are not normal, but the deviation from normal is small and the gamma is slightly shifted. For example, in the case of full lighting of 255/255, about 7V is applied to both the pixel electrodes Px1 and Px2 with a positive polarity or a negative polarity, which is indistinguishable from a normal pixel.

  However, in the case of reverse polarity driving, as shown in the equivalent circuit diagram of FIG. 17B, the potential difference between the sub-pixels becomes large, so that the pixel electrodes Px1,1 as shown in FIG. When there is a planar short circuit S between Px2, a large leakage current i flows. For example, in the case of full lighting of 255/255, if the pixel electrode Px1 is + 7V, −7V is applied to the pixel electrode Px2, and if the pixel electrode Px1 is −7V, + 7V is applied to the pixel electrode Px2, and leakage occurs between the pixel electrodes Px1 and Px2. As a result, almost no voltage remained in the pixel, and it was always a dark spot with no voltage applied.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a liquid crystal display device and a repair method thereof that can avoid a dark spot due to a short circuit between pixel electrodes. .

  In the liquid crystal display device according to the present invention, a plurality of pixels are arranged in a matrix and each pixel is divided into a plurality of sub-pixels. Each pixel is divided into a plurality of nonlinear elements and a plurality of nonlinear elements, respectively. A plurality of sub-pixel electrodes connected to each other and applied with voltages of opposite polarities within the same frame; and a bus line connected to the plurality of nonlinear elements. At least one of the nonlinear elements It has a scheduled cutting part that can be cut from the pixel electrode or the bus line.

  A repair method of a liquid crystal display device according to the present invention is a method of repairing a liquid crystal display device in which a plurality of pixels are arranged in a matrix and each pixel is divided into a plurality of sub-pixels. Forming an element, a plurality of subpixel electrodes that are respectively connected to the plurality of nonlinear elements and are applied with voltages of opposite polarities within the same frame, and a bus line connected to the plurality of nonlinear elements; At least one of the non-linear element and the sub-pixel provided with the pre-cut-off portion is provided when the non-linear element can be cut from the sub-pixel electrode or the bus line and a plurality of sub-pixel electrodes are short-circuited. The electrode and the bus line are cut at the planned cutting portion.

  In the liquid crystal display device according to the present invention, when a planar short circuit occurs between the sub-pixel electrodes, the non-linear element having the planned cutting portion, the sub-pixel electrode, and the bus line are all cut by the planned cutting portion. Are connected to the remaining nonlinear elements. Therefore, it is possible to avoid that all the subpixel electrodes are applied with a voltage with a polarity on one side and are always dark spots due to a leak current.

  According to the liquid crystal display device of the present invention, at least one of the non-linear elements is provided with the planned cutting portion that enables the non-linear element to be cut from the sub-pixel electrode or the bus line. According to the method for repairing a display device, when a plurality of sub-pixel electrodes are short-circuited when at least one of the non-linear elements is provided with a cut-off portion, the non-linear element, the sub-pixel electrode and the bus provided with the cut-off portion Since the line is cut at the planned cutting portion, it is possible to avoid a dark spot constantly even when a short circuit occurs between the sub-pixel electrodes.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a configuration of a liquid crystal display device according to an embodiment of the present invention. The repair method of the present embodiment is embodied as the repair method of the liquid crystal display device, and will be described below together.

  This liquid crystal display device is a VA mode liquid crystal display device used for a liquid crystal television or the like. For example, a liquid crystal display panel 1, a backlight unit 2, an image processing unit 3, a storage unit 3A, a frame memory 4, and the like. , A gate driver 5, a data driver 6, a timing control unit 7, and a backlight driving unit 8.

  The liquid crystal display panel 1 performs video display based on the video signal Di transmitted from the data driver 6 by the drive signal supplied from the gate driver 5, and has a plurality of pixels P1 arranged in a matrix. An active matrix liquid crystal display panel is driven for each pixel P1. A specific configuration of the pixel P1 will be described later.

  The backlight unit 2 is a light source that irradiates light to the liquid crystal display panel 1, and includes, for example, a CCFL (Cold Cathode Fluorescent Lamp), an LED (Light Emitting Diode), and the like. ing.

  The image processing unit 3 generates a video signal S2 that is an RGB signal by performing predetermined image processing on the external video signal S1.

  The storage unit 3A stores coordinate information and correction gamma information of a repair pixel P2 when a short circuit occurs in a certain pixel P1 and repair processing is performed by a repair method described later. In addition, the image processing unit 3 performs a process of correcting the gradation on the input signal (video signal S1) to the repair pixel P2 based on the coordinate information and the corrected gamma information stored in the storage unit 3A. The signal S2 is output.

  The frame memory 4 stores the video signal S2 supplied from the image processing unit 3 for each pixel P in units of frames.

  The timing control unit 7 controls the drive timing of the gate driver 5, the data driver 6 and the backlight drive unit 8. The backlight drive unit 8 controls the lighting operation of the backlight unit 2 in accordance with the timing control of the timing control unit 7.

  Hereinafter, a specific configuration of each pixel P1 of the liquid crystal display panel 1 will be described with reference to FIGS. Each pixel P1 has a multi-pixel structure composed of two sub-pixels, and displays, for example, one of the basic colors of red (R; Red), green (G; Green), and blue (B; Blue). It is supposed to be.

  FIG. 2 shows an equivalent circuit of the pixel P1. The pixel P1 includes a TFT 1 and a TFT 2, a liquid crystal element Clc1 constituting one subpixel (hereinafter referred to as subpixel A), and a liquid crystal element Clc2 constituting another subpixel (hereinafter referred to as subpixel B). And capacitive elements Cst1 and Cst2.

  The TFT1 and TFT2 have a function as a switching element for supplying the video signal S3 to the sub-pixels A and B, and are configured by, for example, a MOS-FET (Metal Oxide Semiconductor-Field Effect Transistor). It has three electrodes, gate, source and drain. The gates of TFT1 and TFT2 are connected to a gate bus line GL extending in the left-right direction. Two source bus lines SL1 and SL2 extending in the vertical direction are orthogonal to the gate bus line GL. The source of the TFT1 is connected to the source bus line SL1, and the drain is connected to one end of the liquid crystal element Clc1 and one end of the capacitive element Cst1. The source of the TFT2 is connected to the source bus line SL2, and the drain is connected to one end of the liquid crystal element Clc2 and one end of the capacitive element Cst2.

  The liquid crystal elements Clc1 and Clc2 have a function as display elements that perform an operation for display in accordance with a signal voltage supplied via the TFTs 1 and 2. The other end of the liquid crystal element Clc1 and the other end of the liquid crystal element Clc2 serve as a common electrode formed on the surface of the counter substrate across the liquid crystal.

  The capacitive elements Cst1 and Cst2 generate a potential difference between both ends, and specifically include a dielectric that accumulates charges. The other end of the capacitive element Cst1 and the other end of the capacitive element Cst2 are connected to a capacitive element bus line CL extending in parallel to the gate bus line GL, that is, in the left-right direction.

  FIG. 3 shows a cross-sectional structure of the liquid crystal display panel 1. The liquid crystal display panel 1 includes a VA mode liquid crystal layer 30 between a TFT substrate (drive substrate) 10 and a counter substrate 20. Each of the TFT substrate 10 and the counter substrate 20 is provided with polarizing plates 41 and 42 so that their optical axes (not shown) are orthogonal to each other.

  The TFT substrate 10 is formed on a glass substrate 10A for each pixel P1, TFTs 1 and 2, an interlayer insulating layer 10B made of an organic insulating film or an inorganic insulating film, and a sub-layer made of ITO (Indium Tin Oxide). Pixel electrodes Px1 and Px2 are formed. The sub-pixel electrode Px1 forms a sub-pixel A and is electrically connected to the TFT1. The subpixel electrode Px2 forms a subpixel B and is electrically connected to the TFT2. These subpixel electrodes Px1 and Px2 constitute one pixel electrode 11. The area ratio of the subpixel electrodes Px1 and Px2 may be 1: 1, but the subpixel electrode Px1 is small so as to be, for example, about 1: 2 (see FIG. 4 described later). The capacity is different. A slit 12 for controlling liquid crystal alignment is provided between the sub-pixel electrodes Px1 and Px2. Although not shown, the glass substrate 10A is provided with the capacitive elements Clc1, Clc2, and the like shown in FIG.

  As shown in the equivalent circuit diagram of FIG. 2, the sub-pixel electrode Px1 and the sub-pixel electrode Px2 are electrically independent, and the sub-pixel electrodes Px1 and Px2 are applied with voltages having opposite polarities in the same frame. Yes. Thereby, the width of the slit 12A between the sub-pixel electrodes Px1 and Px2 in the pixel P1 can be narrowed, and the transmittance can be improved.

  The counter substrate 20 is obtained by forming a common electrode (common electrode) 21 made of ITO on a glass substrate 20A. Although not shown, a glass filter, a black matrix, and the like are formed on the glass substrate 20A. In the common electrode 21, a slit 22 for controlling liquid crystal alignment is provided at a position that does not overlap with the slit 12 of the pixel electrode 11.

  FIG. 4A shows a planar configuration of one pixel P1. The TFT 1 has a planned cutting portion R at the boundary with the sub-pixel electrode Px1 or the source bus line SL. The planned cutting portion R is for enabling the TFT 1 to be cut from the sub-pixel electrode Px1 or the source bus line SL1. That is, when a planar short circuit S occurs between the sub-pixel electrodes Px1 and Px2, a repair process is performed at the scheduled cutting portion R, and the TFT 1, the sub-pixel electrode Px1, and the source bus line SL1 are cut. Thereby, in this liquid crystal display device, it is possible to avoid a dark spot due to a short circuit S between the sub-pixel electrodes Px1 and Px2.

  FIG. 4B shows an equivalent circuit of the repair pixel P2 that has been repaired using the planned cutting portion R. In the repair pixel P2, all the subpixel electrodes Px1 and Px2 are connected to the remaining TFT 2, and the charging current i flows through the short circuit S. Therefore, a voltage is applied to all the subpixel electrodes Px1 and Px2 with the polarity on one side (either positive or negative, for example, + in FIG. 4B), and it always becomes a dark spot due to the leakage current. Will be avoided.

  The TFT 1 having the planned cutting portion R is preferably connected to the sub-pixel electrode Px1 of the sub-pixel A having a smaller capacity. This is because the TFT to be left needs to drive both the sub-pixel electrodes Px1 and Px2, and therefore it is desirable to leave the TFT 2 driving the sub-pixel B having a larger capacity.

  The remaining TFT 2 has a charging rate of 90% or more with respect to the total capacity of the plurality of sub-pixels A and B (the voltage that can charge the pixel with respect to the voltage applied to the bus line at one writing). It is preferable to have a ratio). The TFT 2 remaining after the repair process drives both the sub-pixel electrodes Px1 and Px2, and needs to drive a capacitance 1.5 times or more that of the other pixels P1. If the size of the TFT 2 is designed under the most severe conditions, a sufficient voltage cannot be applied to the repair pixel P2, and a dark spot defect may occur even if the repair process is performed. Therefore, it is desirable that the remaining TFT 2 be designed to be large in advance and have sufficient writing ability.

  FIG. 5 illustrates an example of a cross-sectional configuration of the TFT 1 and the planned cutting portion R. For example, the TFT 1 is formed by sequentially laminating a gate electrode 51, a gate insulating film 52, an amorphous silicon layer 53, an n + amorphous silicon layer 54, and a source electrode 55 and a drain electrode 56 on a glass substrate 10A. The subpixel electrode Px1 is connected to the drain electrode 56 of the TFT1 through a connection hole (not shown) provided in the interlayer insulating layer 10B.

  For example, the planned cutting portion R is a portion where the drain electrode 56 of the TFT 1 is not planarly stacked with the other electrode (gate electrode 51 or source electrode 55) of the TFT 1 or the sub-pixel electrodes Px1 and Px2. . When the hole 60 is formed in the scheduled cutting portion R by laser trimming, the drain electrode 56 is melted and attached to the side surface of the hole 60, and the metal layer 61 is formed. Therefore, there is a high possibility that a short circuit will occur through the metal layer 61 unless the interlayer insulating layer 10B is sufficiently thick. However, since the drain electrode 56 is not planarly stacked with the other electrodes or subpixel electrodes Px1 and Px2 of the TFT 1 in the planned cutting portion R, the drain electrode 56 and the other electrodes of the TFT 1 or It is possible to avoid a short circuit between the sub-pixel electrodes Px1 and Px2. Further, the width W of the planned cutting portion R is preferably 3 μm to 5 μm, for example, considering the workability of laser trimming.

  On the other hand, designing in such a way that there is no overlap between the electrodes in the planned cutting portion R may increase a useless region in terms of the aperture ratio. Therefore, when it is assumed in advance that the TFT 1 connected to the sub-pixel electrode Px1 of the sub-pixel A having the smaller capacitance is to be cut, it is desirable to provide the scheduled cutting portion R only on the TFT 1.

  Note that the planned cutting portion R is not limited to the drain electrode 56 but is a portion where the gate electrode 51 or the source electrode 55 of the TFT 1 is not planarly stacked with the other electrodes of the TFT 1 or the sub-pixel electrodes Px1 and Px2. Also good. Further, the planned cutting portion R is a portion where one of the subpixel electrodes Px1 and Px2 is not planarly stacked with the gate electrode 51, the source electrode 55 or the drain electrode 56 of the TFT1, or the other of the subpixel electrodes Px1 and Px2. It may be.

  This liquid crystal display device can be manufactured, for example, by the following manufacturing method.

  First, for example, TFT1 and TFT2 are formed on the glass substrate 10A by a normal manufacturing method. Next, an interlayer insulating layer 10B that covers TFT1 and TFT2 is formed, and connection holes (not shown) are provided by patterning. Subsequently, subpixel electrodes Px1 and Px2 are formed and patterned into a predetermined shape. Thereby, the drive substrate 10 is formed.

  After that, for example, an electrical test is performed on each pixel P1 using an array tester, a pixel P1 having a short circuit S between the sub-pixel electrodes Px1 and Px2 is specified, and the scheduled cutting portion R is provided for the specified pixel P1. A repair process for cutting the TFT 1, the sub-pixel electrode Px1, and the source bus line SL1 at the scheduled cutting portion R is performed. Further, the coordinate information of the repair pixel P2 subjected to the repair process is stored in the storage unit 3A together with the correction gamma information.

  Further, the common electrode 21 having the slits 22 is formed on the glass substrate 20A by a normal manufacturing method, and the counter substrate 20 is formed.

  After the drive substrate 10 and the counter substrate 20 are formed, the liquid crystal layer 30 is formed by arranging the drive substrate 10 and the counter substrate 20 to face each other, forming a sealing layer (not shown) on the outer periphery, and injecting liquid crystal therein. Thereby, the liquid crystal display panel 1 shown in FIGS. 2 to 4 is formed. The liquid crystal display panel 1 is incorporated into a system including a backlight unit 2, an image processing unit 3, a frame memory 4, a gate driver 5, a data driver 6, a timing control unit 7 and a backlight driving unit 8. A liquid crystal display device of the form is completed.

  In the liquid crystal display panel 1, as shown in FIG. 1, the video signal S1 supplied from the outside is subjected to image processing by the image processing unit 3, and a video signal S2 for each pixel P1 is generated. The video signal S2 is stored in the frame memory 4 and supplied to the data driver 6 as the video signal S3. Based on the video signal S3 supplied in this way, a line-sequential display driving operation is performed for each pixel P1 by the driving voltage into each pixel P1 output from the gate driver 5 and the data driver 6. Specifically, on and off of the TFT1 and TFT2 are switched according to a selection signal supplied from the gate driver 5 through the gate bus line GL, and the source bus line SL and the pixel P1 are selectively conducted. ing. Thereby, the illumination light from the backlight unit 2 is modulated by the liquid crystal display panel 1 and output as display light.

  Here, when the TFT1 has the planned cutting portion R and there is a planar short circuit S between the subpixel electrodes Px1 and Px2, the TFT1, the subpixel electrode Px1 and the source bus line SL1 are cut at the planned cutting portion R. And are disconnected. Therefore, in the repair pixel P2 that has been repaired using the planned cutting portion R, all the sub-pixel electrodes Px1 and Px2 are connected to the remaining TFT 2 as shown in FIG. A charging current i flows through. Therefore, a voltage is applied to all the subpixel electrodes Px1 and Px2 with the polarity on one side (either positive or negative, for example, + in FIG. 4B), and it always becomes a dark spot due to the leakage current. can avoid.

  In addition, when the image processing unit 3 generates the video signal S2, the image processing unit 3 performs gradation on the input signal (video signal S1) to the repair pixel P2 based on the coordinate information and the corrected gamma information stored in the storage unit 3A. The process which correct | amends is performed. This is because when TFT1 is cut and subpixel electrodes Px1 and Px2 are driven by TFT2, TFT2 does not perform writing unless it is in a high gradation range of 127/255 or higher as shown in FIG. It becomes a dark spot in the gradation range. Conversely, when the TFT 2 is cut and the sub pixel electrodes Px1 and Px2 are driven by the TFT 1, the total area of the sub pixel electrodes Px1 and Px2 becomes large, so that it may be recognized as a defect of a bright spot in a low gradation region. There is. Therefore, the coordinate information of the repair pixel P2 is stored in the storage unit 3A, and the video signal S1 corresponding to the coordinates is converted based on a preset gradation conversion table (corrected gamma information) to match the luminance. It is desirable to prevent it from being recognized as a defect. As the gradation conversion table, an optimum table can be obtained from the relationship between the area of the subpixels Px1 and Px2 and the gradation-voltage.

  FIG. 6 shows an example (10 bits) of such a gradation conversion table (LUT (Look Up Table)). Specifically, the image processing unit 3 performs gradation for each of the plurality of sub-pixels A and B with respect to an input signal (video signal S1) to the pixel P1 other than the repair pixel P2 among the plurality of pixels P1. The changing process is performed, and the video signal S2A for the sub-pixel A and the video signal S2B for the sub-pixel B are output. On the other hand, the input signal (video signal S1) to the repair pixel P2 is directly output as the video signal S2R without performing the process of changing the gradation for each of the plurality of sub-pixels A and B. As a result, the brightness of the repair pixel P2 is adjusted to match the brightness of the surrounding pixel P1, and the repair pixel P2 is prevented from becoming a dark spot or bright spot defect.

  As described above, in the present embodiment, the TFT 1 is provided with the planned cutting portion R that can cut the TFT 1 from the sub-pixel electrode Px1 or the source bus line SL1, and a short circuit S occurs between the sub-pixel electrodes Px1 and Px2. In this case, since the TFT 1, the sub-pixel electrode Px1, and the source bus line SL1 are cut at the planned cutting portion R, it is always a dark spot even when a short circuit S occurs between the sub-pixel electrodes Px1 and Px2. Can be avoided.

  While the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above-described embodiment, a portion where the drain electrode 56 of the TFT 1 is not planarly stacked with the other electrode (the gate electrode 51 or the source electrode 55) or the sub-pixel electrodes Px1 and Px2 of the TFT 1 is to be cut. However, in the scheduled cutting portion R, one of the plurality of electrodes (the gate electrode 51, the source electrode 55, and the drain electrode 56) of the TFT 1 is connected to another electrode of the TFT 1 with an organic insulating film interposed therebetween. It may be a portion laminated in a plane with the sub-pixel electrodes Px1 and Px2. The planned cutting portion is a portion where one of the sub-pixel electrodes Px1 and Px2 is planarly stacked with the plurality of electrodes of the TFT 1 or the other of the sub-pixel electrodes Px1 and Px2 with an organic insulating film interposed therebetween. May be. This is because even if there is a laminated portion of electrodes in the planned cutting portion R, if there is an organic insulating film having a sufficient thickness between them, the possibility of causing a short circuit that becomes a problem during laser cutting is extremely low.

  Specifically, as shown in FIG. 7, in the planned cutting portion R, the drain electrode 56 of the TFT 1 is planarly stacked with the sub-pixel electrode Px2 with the interlayer insulating layer 10B made of an organic insulating film in between. It can be the part which is. In this case, as shown in FIG. 8, when the hole 60 is formed in the planned cutting portion R by laser trimming, the drain electrode 56 is melted and attached to the side surface of the hole 60, and the metal layer 61 is formed. However, since the interlayer insulating layer 10B is thick, the possibility that the drain electrode 56 and the sub-pixel electrode Px2 are short-circuited via the metal layer 61 is reduced.

  The reason why the organic insulating film is provided between the electrodes having different layers is that the organic insulating film can be easily thickened. Although it is quite disadvantageous to form an inorganic insulating film having a sufficient thickness, it is not impossible to replace the organic insulating film with an inorganic insulating film. In that case, as described in the above embodiment, the planned cutting portion R includes one of the plurality of electrodes (gate electrode 51, source electrode 55, and drain electrode 56) of TFT1 or sub-pixel electrodes Px1 and Px2. It is preferable that the portion is not planarly stacked with the other electrodes of the TFT 1 or the sub-pixel electrodes Px1 and Px2. Incidentally, at present, in order to increase the aperture ratio by taking the pixel electrode 11 as wide as possible, an organic material is often used in combination with the interlayer insulating layer 10B under the pixel electrode 11. In the film below that, the characteristics of TFT1 and TFT2 become unstable, so an organic insulating film is not used.

  Further, for example, in the above embodiment, an example in which each pixel is divided into two sub-pixels has been described. However, the present invention can be applied to a case where each pixel is divided into three or more sub-pixels. Applicable.

  Further, the shape of the sub-pixel is not limited to the above embodiment, and other shapes such as a square or a rectangle may be used as long as the plane area of the pixel is substantially divided.

  In addition, in the above embodiment, the case where TFT1 and TFT2 are used as nonlinear elements has been described as an example. However, the nonlinear element may be a TFD (Thin Film Diode).

It is a figure which shows the whole structure of the liquid crystal display device provided with the liquid crystal display panel which concerns on one embodiment of this invention. FIG. 2 is an equivalent circuit diagram of a pixel of the liquid crystal display panel shown in FIG. 1. FIG. 2 is a cross-sectional view illustrating a partial structure of the liquid crystal display panel illustrated in FIG. 1. FIG. 2 is a plan view and an equivalent circuit diagram illustrating a configuration of a pixel illustrated in FIG. 1. It is sectional drawing showing the structure of the cutting scheduled part shown in FIG. It is a figure showing an example of the gradation conversion table by the image process part shown in FIG. FIG. 5 is a plan view and an equivalent circuit diagram illustrating another configuration of the pixel illustrated in FIG. 4. It is sectional drawing showing the structure of the cutting scheduled part shown in FIG. It is a figure showing an example of the gradation display by the conventional multi pixel. FIG. 10 is a configuration of a pixel electrode and a common electrode of each sub-pixel illustrated in FIG. 9 and an equivalent circuit diagram thereof. It is a figure for demonstrating the width | variety of the slit shown in FIG. It is a figure for demonstrating the width | variety of the slit shown in FIG. It is a figure showing the relationship between the width | variety of a slit, and the transmittance | permeability. It is a figure for demonstrating the orientation of the liquid crystal molecule in a slit at the time of applying a reverse polarity voltage to the two pixel electrodes shown in FIG. It is a top view showing the structure of the pixel of a reverse polarity drive. It is a figure showing the transmittance | permeability at the time of narrowing the width | variety of a slit. It is the top view and equivalent circuit diagram for demonstrating the problem of the conventional slit narrowing.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display panel, 10 ... TFT substrate (driving substrate), 12, 22 ... Slit, 20 ... Opposite substrate, 21 ... Common electrode, 41, 42 ... Polarizing plate, P1 ... Pixel, Px1, Px2 ... Subpixel electrode.

Claims (9)

A liquid crystal display device in which a plurality of pixels are arranged in a matrix and each pixel is divided into a plurality of sub-pixels,
Each pixel includes a plurality of non-linear elements, a plurality of sub-pixel electrodes connected to the plurality of non-linear elements, respectively, to which a voltage is applied in reverse polarity within the same frame, and a bus line connected to the plurality of non-linear elements. Have
At least one of the non-linear elements has a scheduled cutting portion that allows the non-linear element to be cut from the sub-pixel electrode or the bus line. The to-be-cut portion is a portion where one of the plurality of electrodes of the nonlinear element or the subpixel electrode is not planarly stacked with another electrode of the nonlinear element or the subpixel electrode. The liquid crystal display device according to claim 1. An inorganic insulating film or an organic insulating film is provided between one of the plurality of electrodes of the nonlinear element or the sub-pixel electrode and another electrode of the nonlinear element or the sub-pixel electrode. The liquid crystal display device according to claim 2. In the scheduled cutting portion, one of the plurality of electrodes of the nonlinear element or the subpixel electrode is planarly stacked with the other electrode of the nonlinear element or the subpixel electrode with an organic insulating film interposed therebetween. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a portion. The capacitance of the plurality of subpixels is different, and the non-linear element having the to-be-cut portion is connected to a subpixel electrode of a subpixel having a smaller capacitance. 2. A liquid crystal display device according to item 1. 6. The liquid crystal display device according to claim 1, wherein at least one of the nonlinear elements has a charging rate of 90% or more with respect to a total capacity of the plurality of sub-pixels. . At least one of the plurality of pixels is a repair pixel in which the non-linear element, the sub-pixel electrode, and the bus line are cut in the scheduled cutting portion, and stores the coordinate information and the corrected gamma information of the repair pixel And
2. An image processing unit that performs a process of correcting a gradation based on coordinate information and correction gamma information stored in the storage unit with respect to an input signal to the repair pixel. 7. A liquid crystal display device according to any one of items 6 to 6. The image processing unit outputs an input signal to a pixel other than the repair pixel among the plurality of pixels by performing a process of changing a gradation for each of the plurality of sub-pixels, and outputs the signal to the repair pixel. The liquid crystal display device according to claim 7, wherein the input signal is output without performing a process of changing gradation for each of the plurality of sub-pixels. A repair method for a liquid crystal display device in which a plurality of pixels are arranged in a matrix and each pixel is divided into a plurality of sub-pixels,
A plurality of non-linear elements, a plurality of sub-pixel electrodes connected to each of the plurality of non-linear elements and applied with a reverse polarity voltage in the same frame, and a bus line connected to the plurality of non-linear elements, And at least one of the non-linear elements is provided with a scheduled cutting portion that enables the non-linear element to be cut from the sub-pixel electrode or the bus line,
A repair of a liquid crystal display device, wherein when the plurality of subpixel electrodes are short-circuited, the non-linear element provided with the to-be-cut portion, the sub-pixel electrode and the bus line are cut at the to-be-cut portion. Method.

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