JP2009101582A - Data signal feeder, light emitting element array and image formation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit which can form an image at a sufficient speed even when using TFT of low working speed for the driving circuit of a light emitting element. <P>SOLUTION: The data signal feeder concerning this invention has a data signal feeding circuit which is equipped with a sample holding circuit which holds a data signal of the voltage level insufficient for driving a load circuit by sampling the data signal input and an amplification circuit which carries out the voltage amplification of the data signal held in the sample holding circuit in order to feed the data signal to the load circuit. With the amplification circuit, the voltage of the data signal held is boosted up to a voltage sufficient for driving the load circuit by integrating the data signal held in the sample holding circuit with applying an integral time of at least two times or more of the sampling period. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an LED arranged in an array, a data signal supply device for driving light emitting elements such as organic EL and inorganic EL, a light emitting element array using the data signal supply device, and image formation using the light emitting element array The present invention relates to a device and an image display device.

  A light emitting element array in which thousands of light emitting diodes are arranged as an exposure light source of an electrophotographic printer is used. For example, element structures composed of several AlGaAs layers are formed on a compound semiconductor substrate such as GaAs and arrayed (Patent Document 1).

When used for a printer, it is first required to determine the light emitting element size and the light emitting element interval in accordance with a desired printing resolution. Therefore, as the printing resolution becomes higher, the number of light emitting elements increases, thereby reducing the light emitting element size and the light emitting element spacing. Further, in order to use as a light source for a printer, it is required to individually drive the light emitting elements. Actually, by using time-division driving as a driving method, the number of necessary light emitting element electrodes and the number of driving IC chips are reduced to suppress the cost increase. Techniques relating to time-division driving are disclosed in Patent Documents 2 and 3.
Japanese Patent No. 3185049 JP 2001-88345 A JP 2001-246780 A

  When a driving circuit for driving the light emitting element array is manufactured at a large area and at a low cost, it is more advantageous to manufacture a circuit using an organic material or amorphous Si than to manufacture a circuit using crystalline Si.

  However, in the case where the light emitting element is driven by time division driving, the time for writing data to one light emitting element is shorter than in the case where the light emitting elements are individually driven. Therefore, when an organic material or amorphous Si whose operation speed is lower than that of crystalline Si is used for the drive circuit of the light emitting element array, there is a problem that writing in time division with high operation speed cannot be followed.

  An object of the present invention is to solve the above-described problems, and an object of the present invention is to provide a circuit capable of forming an image at a sufficient speed even when a TFT having a low operating speed is used in a light emitting element driving circuit (data signal supply device). That is.

  A data signal supply device according to the present invention includes a sample-and-hold circuit that has a switching transistor, holds a data signal at a voltage level that is insufficient for driving the load circuit by sampling the input data signal, and the load circuit And at least two data signal supply circuits each including an amplifier circuit that amplifies the voltage of the data signal held in the sample and hold circuit in order to supply the amplified data signal.

  Each of the at least two amplifier circuits integrates the data signal held in the sample and hold circuit over an integration time that is at least twice as long as the sampling period, whereby the voltage of the held data signal is obtained. An integration circuit that boosts the voltage to a voltage sufficient for driving the load circuit, and among the plurality of data signal supply circuits, during the integration time in the amplification circuit of one of the data signal supply circuits, the other data The data signal is sampled in the signal supply circuit.

  According to the present invention, a light emitting element can be driven at a sufficient speed even when a TFT having a low operation speed is used in a driving circuit of the light emitting element.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(overall structure)
FIG. 1 is a diagram showing an LSI (100) for time-division driving, a data signal supply device 101 which is a driving circuit for driving light emitting elements arranged in an array, and an LED element 102.

  The LSI (100) for time division driving needs to output pixel signals corresponding to the number of LEDs to emit light. Here, in order to simplify the description, an LSI for time-division driving composed of 4 × 4 wiring is shown, and the number of LEDs to emit light is 16 (LED1 to LED16). In the figure, reference numeral 103 denotes four clock wirings, and 104 denotes four data wirings. Reference numeral 101 denotes a data signal supply device, and this circuit is provided for the number of LEDs.

The clock wiring 103 and the data wiring 104 of the time division driving LSI (100) are connected to the data signal supply device 101, respectively. Specifically, the clock wiring φ ₁ is connected to four data signal supply devices, and the data wiring D ₁ is also connected to the four data signal supply devices. For example, the data signal supply device that drives the LED ₁ is connected to the clock line φ ₁ and the data line D ₁ . By connecting the clock wiring and the data wiring in this way, a pixel signal can be supplied to each data signal supply device.

Referring to FIG. 2, while the clock wiring φ ₁ is ON, the pixel signals of D ₁ −1, D ₂ −1, D ₃ −1, and D ₄ −1 are supplied to the data signal supply device. Is done. By this operation, the LEDs 1 to 4 can emit light. Similarly, while the clock wiring φ ₂ is ON, the pixel signals of D ₁ -2, D ₂ -2, D ₃ -2, and D ₄ -2 are supplied to the data signal supply device. In this case, the LED 8 can emit light from the LED 8. In this way, by operating the clock wiring from φ ₁ to φ ₄ , the LED for one row can be made to emit light. Then, by operating the clock wiring from φ ₁ to φ ₄ again, the LEDs in the next row can be made to emit light.

Since the LSI for time division driving is formed of a material having a relatively fast operation (for example, single crystal Si), data is supplied to the data signal supply device at a high speed. If pixel signals are sent in a time division manner, the number of LSI output terminals can be reduced, but the time allowed for writing image data in one row (d _R ) must be reduced to d _R / n when divided into n. Considering the extreme case where there is no time margin, the clock pulse width for data acquisition must also be reduced to 1 / n.

  However, in the present invention, since the data signal supply device is formed of an organic TFT having a relatively slow operation speed or a TFT having an active layer made of a non-single crystal material, it can follow the operation speed of the time-division drive LSI. Have difficulty. In addition, since the data supply time from the time division drive LSI is short, it is difficult to receive a sufficiently large pixel signal with a TFT having a low operation speed. In the present invention, in order to solve such a problem, the pixel signal from the high-speed time-division driving LSI is accumulated and amplified by the data signal supply device.

(Data signal supply device)
Next, a data signal supply apparatus according to the present invention will be described with reference to FIG.

  The data signal supply apparatus according to the present invention includes at least two data signal supply circuits 113 each including a sample hold circuit 114 and an amplifier circuit 115. The sample and hold circuit 114 has a switching transistor, samples the input data signal, and holds a data signal having a voltage level that is insufficient for driving the load circuit. The amplifier circuit 115 amplifies the voltage of the data signal held in the sample hold circuit 114 in order to supply the amplified data signal to the load circuit.

  Each of the at least two amplification circuits integrates the data signal held in the sample-and-hold circuit over an integration time that is at least twice as long as the sampling period, thereby applying the voltage of the held data signal to the load circuit. The voltage is boosted to a voltage sufficient for driving. Each of the at least two amplification circuits samples the data signal in the other data signal supply circuit during the integration time in the amplification circuit of one data signal supply circuit among the plurality of data signal supply circuits.

  The transistor constituting at least one of the sample hold circuit 114 and the amplifier circuit 115 according to the present invention may be constituted by a thin film transistor or an organic transistor having an active layer made of a non-single crystal semiconductor.

In the data signal supply device shown in FIG. 3, a case where D ₁ −1 data is supplied from the time division circuit is shown as an example. In this case, four signals can be accumulated per pixel. The number of stored data may be determined in consideration of the operation speed of the time division circuit and the data signal supply device. The number of accumulated data can be arbitrarily set.

A configuration in which clocks φ _0A , φ _1A , φ _2A , φ _3A , φ _0p , φ _1p , φ _2p , φ _3p , φ _0B , φ _1B , φ _2B , φ _3B are supplied to the data signal supply device. It has become. Here, φ _0A , φ _1A , φ _2A , and φ _3A are clocks that drive the switching transistors (Tr0A, Tr1A, Tr2A, Tr3A). Further, φ _0p , φ _1p , φ _2p , and φ _3p are clocks that drive the amplifier circuit 115, and φ _0B , φ _1B , φ _2B , and φ _3B are clocks that drive the timing switch 110. Further, FIG. 4 shows a timing chart of each clock, and FIG. 5 shows timings of the pixel signal D ₁ −1 and clocks φ ₁ , φ _0A , φ _0p , φ _0B and voltage changes of V _0A , V _0B .

(Sample hold circuit)
Next, the sample hold circuit 114 will be described.

In FIG. 3, the pixel signals selected by the clock φ _{1 and} transferred by D ₁ −1 are sequentially switched by the switching transistors Tr0A, Tr1A, at the timing shown in FIG. 4 by the clocks φ _0A , φ _1A , φ _2A , φ _3A . Tr2A and Tr3A are switched. The switching transistors Tr0A, Tr1A, Tr2A, Tr3A send the pixel signals of the r-th, (r + 1) -th, (r + 2) -th, and (r + 3) -th to the signal storage capacitors C1 to C4, respectively. Here, the signals accumulated in the capacitors C1 to C4 are data signals having a voltage level that is insufficient for driving the load circuit.

(Amplification circuit)
Next, the amplifier circuit 115 will be described.

In Figure 3, the source of Tr0A has capacitor C1 for signal storage is connected, representing the connection points V _0A. Further, the drain terminal of Tr0p1 and the gate terminal of Tr1 are connected to this connection point. The drain terminal of the Tr1 is connected to Tr0p2, the gate terminals of Tr0p1 and Tr0p2 is connected to the clock phi _0p. The drain terminal of Tr1 is connected to one terminal of the capacitor Cp1, and the source terminal of Tr1 and the other terminal of Cp1 are at ground potential. Here, Cp1 may be provided with a capacitance independently or may be a parasitic capacitance of Tr1. This part becomes an integration circuit.

Tr0p1 resets immediately before, i.e. 4, the potential of _{V 0A} point to discharge C1 and the phi _0p to ON just before the phi _0A shown in FIG. 5 becomes ON to 0V the pixel signal is written into the capacitor C1. Also at the timing of the same clock φ _0p Tr0p2 it is the potential of the ON to the capacitance Cp1 precharge and _{V 0B} to the power supply potential (Vcc).

Tr10 and Tr0A are turned on by the clock φ ₁ and the clock φ _0A , and the pixel signal (0 or 1 digital signal) is accumulated in C1. However, in this case, since Tr10 and Tr0A are made of organic TFTs whose response speed is not sufficiently high, only a part of the signal is accumulated in C1. Therefore, the potential of V _0A shown in FIG. 5 does not increase to a voltage level of 1 even if the signal is 1. At this voltage level, the light emitting element driving transistor TrD1 cannot be quickly turned on.

Therefore, as shown in FIG. _5, (still high channel resistance) insufficient while the Tr1 at a potential of _{V 0A} was turned ON, bring the potential of _{V 0B} to the ground potential (0V) over time (this time Tr0p2 Is OFF). In this case, since it takes a certain amount of time to lower the potential of V _{0B from} the precharge high potential (Vcc) to 0 potential, it is necessary to provide as many data signal supply circuits 113 as can secure this time.

In the figure, the terminal of Cp1 that is not the V _0B potential is at the ground potential (0V). However, in the present invention, the potential difference is not limited to the ground potential, that is, a sufficient potential difference compared with V _0B , that is, TrD1 is switched. As long as the potential difference is sufficient, a potential other than the ground potential may be used.

  With the above operation, the data signal supply circuit outputs the following signals to the timing switch.

When the pixel signal from D ₁ -1 is 1 (ON), the pixel signal is written to C1, and therefore V _0B precharged to Cp1 is lower than the power supply potential (Vcc). Therefore, in this case, a 0 signal is supplied to the timing switch.

Conversely, when the pixel signal from D ₁ −1 is 0 (OFF), the pixel signal is not written to C1, and therefore V _0B precharged to Cp1 is kept at the power supply potential (Vcc). Therefore, in this case, a signal of 1 is supplied to the timing switch.

  Next, the relationship of the threshold voltage of TrD1 in the circuit of FIG. 3 will be described.

_Let I _d (on) be the on-drain current of the amplifying transistor when an on-data signal voltage greater than the threshold voltage is input to the amplifying transistor. The off-drain current of the amplifying transistor when an off-data signal voltage equal to or lower than the threshold voltage is input to the amplifying transistor is defined as I _d (off). Further, it is assumed that the storage capacitor is Cp1, the amplification time is t, and the operation threshold voltage of the load circuit TrD1 is Vth. At this time, the voltage of the amplified data signal is

And the maximum value of the data signal voltage input to the amplifying transistor is V _OAMAX ,

Satisfied. The data signal supply device of the present invention samples and holds the data signal in another data signal supply circuit during the amplification time t of one data signal supply circuit among the plurality of data signal supply circuits.

  In the present invention, the circuit shown in FIG. 3 is shown in order to realize the above function. However, any other circuit may be used as long as it is a circuit that realizes the function of the present invention even if it has other configurations.

(Timing switch)
Next, the timing switch 110 (Tr0B1, Tr0B2, Tr0B3, Tr0B4) will be described.

  The load circuit driven by the data signal supply device according to the present invention includes a switching transistor (timing switch) that is turned on or off in accordance with the data signal output from the amplifier circuit.

  The timing switch 110 controls the timing at which the drive signal output from each data signal supply circuit 113 is supplied to the light emitting element 102. The r-th timing switch in the circuit shown in FIG. 3 will be described.

Cp1 is connected to the drain terminal of Tr0B1, which is a timing switch. Wiring for supplying the clock phi _0B is connected to the gate terminal of the Tr0B1. The source terminal of Tr0B1 is connected to TrD1, which is an inverting input transistor. The inverting input transistor TrD1 is turned on when the input signal is 0, and is turned off when the input signal is 1. The timing switches other than the r-th row are connected in the same manner.

The operation of the timing switch 110 will be described with reference to FIG. When the clock _{φ0A in the} r-th row is turned on, electric charges are accumulated in C1 and the potential of _V0A rises. As a result, the precharged voltage V _0B of Cp1 gradually decreases. Clock phi _0B operating timing switch Tr0B1, the voltage _{V 0B} to ON Tr0B1 after sufficiently reduced. In FIG. 5, as the clock phi ₁ of r + 3 th row of the pixel signal is ON, turns ON the timing switch phi _0B. φ _0B is kept on for a certain period of time, and then turned off just before the timing φ _0p when the charge is precharged to _{Cp 1} .

  FIG. 6 shows a circuit in which the data signal supply device according to the present invention is composed of all n-type transistors. In this circuit, a transistor Tr0C1 and a power supply terminal are provided between the drain terminal of Tr1 (the same applies to a circuit having Tr2 to Tr4) and the drain terminal of Tr0B1. That is, the drain terminal of Tr1 and the gate terminal of Tr0C1 are connected, and the drain terminal of Tr0C1 and the drain terminal of Tr0B1 are connected. Further, the power supply voltage Vcc can be supplied to the drain terminal of Tr0C1.

The operation in this case will be specifically described. Cp1 is connected to the gate terminal of Tr0C1. When the pixel signal from D ₁ -1 is 1 (ON), V _0B precharged to Cp 1 becomes lower than the power supply potential (Vcc). Therefore, at this time, a sufficient voltage is not supplied to the gate terminal of Tr0C1, and Tr0C1 does not operate. Therefore, Vcc is applied to the drain terminal of Tr0B1. At this time, Tr0B1 is turned ON by the signal to the clock phi _0B timing switch is supplied, Vcc (ON signal) is supplied to the gate terminal of TRE1.

Conversely, when the pixel signal from D ₁ −1 is 0 (OFF), V _0B precharged to _{Cp 1} is kept at the power supply potential (Vcc). At this time, since voltage is supplied to the gate terminal of Tr0C1, Tr0C1 operates. In this case, since the drain terminal of Tr0C1 is connected to GND, the potential of the drain terminal of Tr0B1 is GND. Therefore, even if a signal is supplied to the clock _φ0B of the timing switch, no signal is supplied to the gate terminal of TrE1.

(Light emitting element)
In FIG. 3, the LED element (102) which is a light emitting element is connected to the drain terminal of the inverting input transistor TrD1. A power source for driving the LED 1 is connected to the source end of the TrD 1. The source terminal of the timing switch Tr0B1 is connected to the gate terminal of TrD1.

  The LED 1 emits light when a signal at the gate terminal of the TrD1 is 0, and is turned off when the signal at the gate terminal of the TrD1 is 1.

FIG. 6 shows an example in which an inverting input transistor is not used. When the pixel signal from D ₁ −1 is 1 (ON), the LED ₁ is turned on, and the drive current is supplied to emit light. Conversely, when the pixel signal from D ₁ −1 is 0 (OFF), TrE1 is turned OFF and LED1 does not emit light.

  In the above circuit, when n-type TFTs are used except for TrD1, all n-type TFTs are used. However, all of them can also be made using p-type TFTs. A complementary TFT similar to a CMOS can also be used.

  The light emitting element may be an organic EL element.

(Image forming device)
FIG. 7 is a cross-sectional view of an image forming apparatus using the light emitting element according to the present invention. In FIG. 7, a cylindrical (drum) photosensitive member 201 that rotates in the direction of the arrow is installed. Before uniformly charging the photosensitive member, the toner attached to the photosensitive member is removed by the cleaning blade 206, and the photosensitive state by the previous process is cleared by the image erasing unit 207. Next, the photosensitive member is uniformly charged by the charging means 202.

  Thereafter, a part of the photosensitive member charged by the image forming unit 203 is neutralized to form an electrostatic latent image on the photosensitive member 201. Subsequently, the developing unit 204 attaches toner to the electrostatic latent image. Next, the developed image is transferred onto the transfer material 210 by the transfer unit 205. The transfer material 210 onto which the image has been transferred is conveyed by a transfer material conveyance device 209, and the transferred toner image is fixed by an image fixing unit 208.

  In the image forming apparatus according to the present invention, a light emitting element array arranged in the main scanning direction of the photoconductor (direction parallel to the rotation axis of the drum) is used as the image forming unit 203 that forms an electrostatic latent image on the photoconductor 201. be able to. A light emitting element is provided for each pixel in the main scanning direction. The light emitting elements arranged in an array are installed at positions where an electrostatic latent image can be formed on the photoconductor 201, and a part of the photoconductor 201 charged by the light emitting element emitting light can be neutralized. Further, this light emitting element can be driven by the drive circuit described above.

  As another aspect of the image forming apparatus according to the present invention, a stylus (needle) may be used for the image forming unit 203. When a stylus is used, the stylus is arranged in an array in the main scanning direction. Also in this case, a stylus is provided for each pixel in the main scanning direction. The stylus is installed at a position where an electrostatic latent image can be formed on a drum containing a dielectric material, and an electrostatic latent image is formed by discharging a part of the charged drum using the stylus.

The following method is an example of a method for changing the charged state of the drum using a stylus.
For example, the stylus is connected to the position where the LED 1 of FIG. 3 is provided (the drain side of TrD1). Here, it is assumed that the drum is negatively charged. In this case, the stylus is installed in the vicinity of the charged drum. Then, TrD1 is switched to connect the stylus to Vcc2 having a higher potential than the drum. As a result, the portion corresponding to the position where each stylus is installed in the charged drum is neutralized. The drive circuit described above can be used as a circuit for controlling the stylus.

  As described above, by using the driving circuit according to the present invention for the circuit that drives the light emitting element or stylus that is the image forming unit 203, even when a TFT having a low operating speed is used as the driving circuit, image formation can be performed at a sufficient speed. Can do.

(Image display device)
Next, the case where the drive circuit according to the present invention is used in an image display device will be described with reference to FIG.

  FIG. 8A illustrates a case where 16 × 16 LEDs that are light emitting elements are two-dimensionally arranged for the sake of simplicity. When actually used as an image display device, it is necessary to provide light emitting elements corresponding to the resolution of the screen.

  8A, the processing up to the data signal supply device 101 is the same as that in FIG. When the present invention is used as an image display device, a vertical scanning circuit 105 that controls light emission in the vertical scanning direction of light emitting elements (LEDs) 102 arranged in a matrix is provided. The light emitting elements 102 arranged in a matrix are connected to the data signal supply device 101 via the horizontal scanning wiring 116 and also connected to the vertical scanning circuit 105 via the vertical scanning wiring 117.

  FIG. 8B shows a specific circuit example for switching each light emitting element. FIG. 8B shows the case of the light emitting element 1-1, but other light emitting elements have the same circuit. The horizontal scanning wiring 116 is connected to the drain terminal of the switching transistor 1 (TFT1), and the vertical scanning wiring 117 is connected to the gate terminal of the TFT1. The gate terminal of the switching transistor 2 (TFT2) is connected to the source terminal of TFT1, and the source terminal of TFT2 is grounded. Further, the light emitting element 102 has an anode side connected to the power source Vcc, and a cathode side connected to the drain terminal of the TFT 2.

  In the circuit shown in FIG. 8B, when a signal is supplied to the horizontal scanning wiring 116 and the vertical scanning wiring 117, the TFT1 and the TFT2 are turned on and the light emitting element 102 emits light. Note that the circuit shown in FIG. 8B is an example, and any circuit may be used as long as it has a similar function.

  Next, the light emission timing of the light emitting element 102 will be described.

  The data signal supply device 101 controls driving of the light emitting element 102 in the horizontal scanning direction. The vertical scanning circuit 105 controls driving of the light emitting elements in the vertical scanning direction. That is, each data signal supply device 101 supplies pixel signals in the vertical scanning direction over time. The vertical scanning circuit 105 controls the timing of supplying the pixel signals in the vertical scanning direction to the light emitting elements (for example, 1-1, D2-1,... 16-1) arranged in the vertical direction.

This will be specifically described with reference to FIG. In the case of the driving circuit of FIG. 9, four pixel signals from the r-th row to the (r + 3) -th row are supplied to the horizontal scanning wiring 116 by the timing switch 110. Further, in the image display device of FIG. 9, 16 light emitting elements are provided in the vertical scanning direction. In this case, the vertical scanning circuit 105 supplies a drive signal to the light emitting element 102 via the vertical scanning wiring 117 in synchronization with the timings of φ _0B , φ _1B , φ _2B , φ _3B . That is, when the light emitting element 1-1 emits light, the timing φ _0B of the timing switch 110 and the timing φ _0C of the vertical scanning circuit 105 are synchronized. As a result, the drive signal is supplied to the horizontal scanning wiring 116 and the vertical scanning wiring 117 corresponding to the light emitting element 1-1, and the light emitting element 1-1 emits light. Similarly, when the light emitting element 2-1 is caused to emit light, the timing φ _1B of the timing switch 110 and the timing φ _1C of the vertical scanning circuit 105 are synchronized. Similarly, the combinations of the timing of each light emitting element and timing switch and the timing of the vertical circuit 105 are as follows. _{That, (LED3-1, φ 2B, φ} 2C), (LED4-1, φ 3B, φ 3C), (LED5-1, φ 0B, φ 4C), (LED6-1, φ 1B, φ 5C), _{(LED7-1, φ 2B, φ 6C} ), (LED8-1, φ 3B, φ 7C). _{(LED9-1, φ 0B, φ 8C} ), (LED10-1, φ 1B, φ 9C), (LED11-1, φ 2B, φ 10C), (LED12-1, φ 3B, φ 11C). _{(LED13-1, φ 0B, φ 12C} ), (LED14-1, φ 1B, φ 13C), (LED15-1, φ 2B, φ 14C), (LED16-1, φ 3B, φ 15C).

  Although a high-speed LSI may be used as the vertical scanning circuit, the pixel signal from the data signal supply device is sufficiently slower than the time-division driving LSI (100). Even if it is used, it can be driven sufficiently. Examples of such a transistor include an organic transistor and a thin film transistor having an active layer made of a non-single crystal semiconductor.

  With the configuration as described above, the drive circuit according to the present invention can be used as an image display device.

(Element structure)
FIG. 10 shows the structure of an element (TFT) used in the circuit shown in FIG. In FIG. 10A, the semiconductor layer 225 is formed on the source electrode 221 and the drain electrode 222, and such a structure is called a bottom contact type. In FIG. 10B, the source electrode 221 and the drain electrode 222 are formed on the semiconductor layer 225, and this structure is called a top contact type structure. A TFT having any structure may be used in the driving circuit of the present invention.

  In FIG. 10A, the substrate 226 is made of an insulator such as plastic or glass. A gate electrode 223 is formed on the substrate 226 by a coating or vapor deposition technique. A gate insulating film 224 is formed on the gate electrode 223, and a patterned source electrode 221 and drain electrode 222 are formed thereon. Then, a semiconductor layer 225 is formed thereon. Finally, a passivation layer 227 is formed so as to cover this. FIG. 10B can also be manufactured by the same manufacturing method. When an organic semiconductor is used as the semiconductor layer, pentacene, porphyrin, copper porphyrin, rubrene, oligothiophene, polythiophene, phthalocyanine, copper phthalocyanine, merocyanine, C60 can be used. Further, fluorinated pentacene, fluorinated phthalocyanine, PTCDI, fluorinated copper phthalocyanine, and the like can also be used.

As the inorganic semiconductor, amorphous silicon, polycrystalline silicon, an oxide semiconductor (eg, ZnO, InGaZnO ₄ , ZnSnInO, or the like) can be used. As the gate insulating film, polyimide, phenol resin, PMMA and parylene can be used for organic materials, and SiO ₂ can be used for inorganic materials. Parylene, SiO ₂ or the like can be used as the passivation film.

The lower limit of the mobility of the semiconductor layer of the TFT shown in FIG. 10 in which the present invention is preferably used is 1.0 × 10 ⁻² cm ² / Vs, and the upper limit is 1.0 × 10 ² cm ² / Vs.

It is a figure which shows the time division drive circuit and the data signal supply apparatus which concerns on this invention. It is a figure which shows the timing of the data transfer from a time division drive circuit. It is a figure which shows the data signal supply apparatus which concerns on this invention. It is a figure which shows the timing chart of the various clocks of the circuit shown in FIG. FIG. 4 is a timing chart of various clocks of the circuit shown in FIG. 3 and a diagram showing changes in voltages of V _0A and V _0B . It is a figure which shows the data signal supply apparatus which concerns on this invention. 1 is a diagram illustrating an image forming apparatus according to the present invention. It is a figure which shows the circuit of the image display apparatus which concerns on this invention. It is a figure which shows the circuit of the image display apparatus which concerns on this invention. It is sectional drawing of TFT used for the data signal supply apparatus which concerns on this invention.

Explanation of symbols

100 Time division drive LSI
DESCRIPTION OF SYMBOLS 101 Data signal supply apparatus 102 Light emitting element 103 Clock wiring 104 Data wiring 105 Vertical scanning circuit 110 Timing switch 113 Data signal supply circuit 114 Sample hold circuit 115 Amplifier circuit 116 Horizontal scanning wiring 117 Vertical scanning wiring 201 Photoconductor 202 Charging means 203 Image formation Means 204 Developing means 205 Transfer means 206 Cleaning blade 207 Image erasing means 208 Image fixing means 209 Transfer material transport device 210 Transfer material 221 Source electrode 222 Drain electrode 223 Gate electrode 224 Gate insulating film 225 Semiconductor layer 226 Substrate 227 Passivation layer

Claims (8)

A sample-and-hold circuit that has a switching transistor, samples the input data signal, and holds a data signal at a voltage level insufficient for driving the load circuit;
An amplifier circuit that amplifies the voltage of the data signal held in the sample and hold circuit to supply the amplified data signal to the load circuit;
Comprising at least two data signal supply circuits comprising:
Each of the at least two amplifier circuits includes:
By integrating the data signal held in the sample-and-hold circuit over an integration time that is at least twice as long as the sampling period, the voltage of the held data signal is boosted to a voltage sufficient for driving the load circuit. Including an integrating circuit
Among the plurality of data signal supply circuits, the data signal is sampled in another data signal supply circuit during the integration time in the amplifier circuit of one of the data signal supply circuits. Feeding device. 2. The circuit according to claim 1, wherein the amplifier circuit that amplifies the data signal held in the sample hold circuit includes an amplifying transistor having a holding capacitor at an output terminal;
I _d (on) is an on-drain current of the amplifying transistor when an on-data signal voltage greater than the threshold voltage is input to the amplifying transistor.
The off-drain current of the amplifying transistor when an off-data signal voltage equal to or lower than the threshold voltage is input to the amplifying transistor is I _d (off),
The holding capacity is Cp1,
The amplification time is t,
The operation threshold voltage of TrD1 of the load circuit when the V _th, the voltage of the amplified data signal,

And the maximum value of the data signal voltage input to the amplifying transistor is V _OAMAX ,

And the other data signal supply circuit samples and holds the data signal during the amplification time t of one of the plurality of data signal supply circuits.
A data signal supply device.   The data signal supply device according to claim 1, wherein the load circuit includes a switching transistor that is turned on or off in accordance with the data signal output from the amplifier circuit.   4. The transistor constituting at least one of the sample hold circuit and the amplifier circuit is a thin film transistor or an organic transistor having an active layer made of a non-single crystal semiconductor. The data signal supply device described.   5. A light-emitting element array comprising: the data signal supply device according to claim 1; and a light-emitting element that emits light by being supplied with a driving current by the switching transistor. A photoreceptor,
The light-emitting element array according to claim 5 for forming an electrostatic latent image on the photoconductor,
An image forming apparatus comprising: A drum containing a dielectric material;
A plurality of styluses arranged at positions to change the charged state of the drum;
5. An image forming apparatus comprising: the data signal supply device according to claim 1 that changes a potential of the stylus. Two-dimensionally arranged light-emitting element arrays;
The data signal supply device according to any one of claims 1 to 4, wherein a data signal is supplied to a plurality of horizontal scanning lines arranged in a horizontal scanning direction of the light emitting element array;
An image display device comprising: a vertical scanning circuit for scanning the light emitting element array in a vertical scanning direction.

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