JP2009094551A - Counter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a counter device which can enhance time precision of a counter and can facilitate timing verification and layout work of logic IC design. <P>SOLUTION: The counter device performing count operation by dividing the frequency of a clock signal comprises a frequency division circuit having a reset function and generating a frequency division clock signal by dividing the frequency of a clock signal, a counter circuit for counting a frequency division clock signal, and a counter control circuit for generating a reset signal when a load command is received and delivering the reset signal to the frequency division circuit, and then applying a load value and a load signal to the counter circuit during next period of the clock signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a counter device that performs a counting operation by dividing a clock signal, and more particularly to a counter device that can improve the time accuracy of a counter and facilitate logic IC design timing verification and layout work.

  Prior art documents related to a counter device that performs a count operation by dividing a conventional clock signal include the following.

Japanese Patent Laid-Open No. 03-247118 Japanese Patent Laid-Open No. 05-108977 JP 05-129936 A

  FIG. 5 is a block diagram showing an example of a conventional counter device that performs a count operation by dividing a clock signal.

  In FIG. 5, reference numeral 1 denotes a counter control circuit that writes a load value (load) and reads a counter value (read) in response to a command (load command, read command) from a CPU (Central Processing Unit). A frequency dividing circuit that divides by a frequency N (N is an integer of 2 or more) to generate a divided clock signal, 3 is an OR circuit of negative logic input and negative logic output, and 4 is a divided clock signal. It is a counter circuit for counting.

  Further, 100 is a clock signal, 101 is a load value, 102 is a load signal, 103 is a load clock signal, 104 is a divided clock signal, 105 is a counter clock signal, and 106 is a counter value. Furthermore, 1, 2, 3 and 4 constitute a counter device.

  The clock signal 100 is applied to the clock signal input terminals of the counter control circuit 1 and the frequency dividing circuit 2, and the load value 101 and the load signal 102, which are the outputs of the counter control circuit 1, are applied to the input terminals of the counter circuit 4, respectively. .

  The load clock signal 103 that is the output of the counter control circuit 1 is applied to one input terminal of the OR circuit 3, and the divided clock signal 104 that is the output of the frequency dividing circuit 2 is applied to the other input terminal of the OR circuit 3. Applied.

  The counter clock signal 105 that is the output of the OR circuit 3 is applied to the clock signal input terminal of the counter circuit 4, and the counter value 106 that is the output of the counter circuit 4 is applied to the input terminal of the counter control circuit 1.

  Finally, the counter control circuit 1 is connected to a CPU bus indicated by “CB01” in FIG. 5 to which a CPU (not shown) is connected.

  Here, the operation of the conventional example shown in FIG. 5 will be described with reference to FIGS. FIG. 6 is a timing chart for explaining the operation of the conventional example, and FIG. 7 is a truth table for explaining the operation of the OR circuit 3. However, in the description of the operation, the load operation of the counter control circuit 1 will be described, and the description of the counter value read operation will be omitted.

  As shown in FIG. 6, the frequency dividing circuit 2 increments the internal counter in synchronization with the clock signal 100. When the internal counter value is “7”, the frequency dividing circuit 2 sets the internal counter value to “0” in synchronization with the clock signal 100. The frequency-divided clock signal 104 is set to the low level only during the period when the internal counter value is “0”.

  In other words, the frequency dividing circuit 2 repeats the operation of dividing the clock signal 100 by 8 (frequency division number: N = 8) and generating the divided clock signal 104 that outputs the rising clock at that timing. .

  The frequency-divided clock signal 104 is subjected to a logical OR operation with the load clock signal 103 supplied from the counter control circuit 1 and then supplied to the counter circuit 4 as the counter clock signal 105.

  In FIG. 6, the load clock signal 103 is at a low level during the load operation. Therefore, as can be seen from the truth table of FIG. 7, the counter clock signal 105 is obtained by superimposing the low level of the load clock signal 103 on the divided clock signal 104. Become a signal.

  Further, the counter circuit 4 performs a count operation for incrementing the counter value 106 in synchronization with the rising edge of the counter clock signal 105.

  For example, as shown in FIG. 6, the counter value 106 is incremented from “K (K is an arbitrary integer)” to “K + 1” in synchronization with the rising edge of the counter clock signal 105.

  On the other hand, when the counter control circuit 1 receives a load command from the CPU (not shown) via the CPU bus indicated by “CB01” in FIG. 5, the load value 101 designated from the CPU (not shown). The load signal 102 (more precisely, the load signal 102 is set to the high level) is generated in synchronization with the clock signal 100 and output to the counter circuit 4, and the load clock signal 103 is generated and output to the OR circuit 3. .

  Therefore, the low level of the load clock signal 103 is superimposed on the counter clock signal 105 as described above.

  For example, when the load value 101, the load signal 102, and the load clock signal 103 are generated and output in the cycle indicated by “TM11” in FIG. 6, the counter clock signal 105 is output as indicated by “LP11” in FIG. The low level of the load clock signal 103 is superimposed.

  At this time, the load value 101 is supplied to the counter circuit 4 at the same time, and the load signal 102 is at a high level. Therefore, the load value 101 is loaded as the counter value 106 in synchronization with the rise of the counter clock signal 105. .

  For example, since the value of the load value 101 is “L (L is an arbitrary integer)”, the counter circuit 4 changes the counter value 106 from “K + 1” to “L” in synchronization with the rise of the counter clock signal 105. To do.

  As a result, during the load operation, the counter control circuit 1 supplies the counter clock signal 105 obtained by superimposing the low level of the load clock signal 103 on the divided clock signal 104 to the counter circuit 4, and simultaneously supplies the load value 101. The load value can be loaded into the counter circuit 4 by setting the load signal 102 to the high level.

  However, in the conventional example shown in FIG. 5, depending on the timing of the load operation of the counter control circuit 1 (for example, “TM11” in FIG. 6), the counter value 105 immediately after the load operation shown in “PD11” in FIG. There was a problem that the cycle fluctuated (shorter than the subsequent cycle).

  Such a variation in the cycle of the counter value 105 becomes more significant as the value of the frequency division number N of the frequency dividing circuit 2 increases, and the time accuracy of the counter deteriorates due to the influence of the variation in the cycle of the counter value 105. There was a problem that said.

Further, in the logic IC design timing verification, it is necessary to verify two systems of the load clock signal 103 for generating the counter clock signal 105 and the divided clock signal 104, and when the logic IC is laid out, the load clock signal 103 and the divided clock signal are used. There is a problem that the layout work must be performed in consideration of the wiring length of each signal 104.
Therefore, the problem to be solved by the present invention is to realize a counter device capable of improving the timing accuracy of the counter and facilitating the logic IC design timing verification and layout work.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In the counter device that divides the clock signal and performs the counting operation,
A frequency dividing circuit having a reset function to divide a clock signal to generate a divided clock signal; a counter circuit to count the divided clock signal; and a load signal to generate a reset signal to generate the reset signal And a counter control circuit that outputs the load value and the load signal to the counter circuit in the next cycle of the clock signal, and always makes the cycle of the counter value immediately after the load operation constant. It is possible to load the load value to the counter circuit while holding it.

The invention according to claim 2
In the counter device that divides the clock signal and performs the counting operation,
A frequency dividing circuit that has a reset function and generates a divided clock signal by dividing the clock signal, a counter circuit that has a reset function and counts the frequency-divided clock signal, and a reset signal when a reset command is received And a counter control circuit that applies a reset signal to the counter circuit in the next cycle of the clock signal, and always provides a counter value cycle immediately after the reset operation. The counter value of the counter circuit can be reset while keeping it constant.

The invention described in claim 3
In the counter device according to claim 1 or claim 2,
The counter control circuit is
When the read command is received, the counter value from the counter circuit is captured and transmitted, and the load value is loaded into the counter circuit while the cycle of the counter value immediately after the load operation is kept constant, or The counter value of the counter circuit can be reset while the cycle of the counter value immediately after the reset operation is always kept constant.

The present invention has the following effects.
According to the first and third aspects of the invention, when the counter control circuit receives the load command, the counter control circuit generates a reset signal and outputs it to the frequency dividing circuit, and at the next cycle of the clock signal, By supplying and setting the load signal to the high level, it is possible to load the load value to the counter circuit 7 while always keeping the cycle of the counter value immediately after the load operation constant.

  In addition, since the counter value cycle immediately after the loading operation is always constant and the counter value cycle does not fluctuate, the time accuracy of the counter is improved, and the signal for generating the divided clock signal is one system, so verification is easy. Therefore, it is not necessary to consider the wiring length when laying out the logic IC, and the layout work becomes easy.

  According to the invention of claim 2 and claim 3, when the counter control circuit receives the reset command, the counter control circuit generates a reset signal and outputs it to the frequency dividing circuit, and at the next cycle of the clock signal, By setting the circuit reset signal to a high level, the counter value of the counter circuit can be reset while the cycle of the counter value immediately after the reset operation is always kept constant.

  In addition, since the counter value period immediately after the reset operation is always constant and the counter value period does not fluctuate, the time accuracy of the counter is improved, and the signal for generating the divided clock signal is one system so that the verification is easy. Therefore, it is not necessary to consider the wiring length when the logic IC is laid out, and the layout work is facilitated.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a counter device according to the present invention.

  In FIG. 1, 5 is a counter control circuit that writes (loads) a load value and reads (reads) a counter value in response to a command (load command, read command) from the CPU, and 6 has a reset function and separates a clock signal. A frequency divider circuit that generates a divided clock signal by dividing the frequency by N (N is an integer of 2 or more), and 7 is a counter circuit that counts the divided clock signal.

  Further, 110 is a clock signal, 111 is a reset signal for the frequency dividing circuit 6, 112 is a frequency-divided clock signal, 113 is a load value, 114 is a load signal, and 115 is a counter value. Furthermore, 5, 6 and 7 constitute a counter device.

  The clock signal 110 is applied to the clock signal input terminals of the counter control circuit 5 and the frequency dividing circuit 6, and the reset signal 111 that is the output of the counter control circuit 5 is applied to the reset signal input terminal of the frequency dividing circuit 6. The frequency-divided clock signal 112 that is the output of the frequency divider 6 is applied to the reset input terminal of the counter circuit 7.

  Further, the load value 113 and the load signal 114 which are the outputs of the counter control circuit 5 are respectively applied to the input terminals of the counter circuit 7, and the counter value 115 which is the output of the counter circuit 7 is applied to the input terminals of the counter control circuit 5. The

  Finally, the counter control circuit 5 is mutually connected to a CPU bus indicated by “CB21” in FIG. 1 to which a CPU (not shown) is connected.

  Here, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a timing chart for explaining the operation of the embodiment. However, in the description of the operation, the load operation of the counter control circuit 5 will be described, and the description of the counter value read operation will be omitted.

  As shown in FIG. 2, the frequency dividing circuit 6 increments the internal counter in synchronization with the clock signal 110. When the internal counter value is “7”, the frequency dividing circuit 6 sets the internal counter value to “0” in synchronization with the clock signal 110. The frequency-divided clock signal 112 is set to the low level only during the period when the internal counter value is “0”.

  In other words, the frequency dividing circuit 6 repeats the operation of generating the frequency-divided clock signal 112 that divides the clock signal 110 by 8 (frequency division number: N = 8) and outputs the rising clock at that timing. .

  Further, when the reset signal 111 becomes high level, the frequency dividing circuit 6 sets the internal counter value to “0” in the next cycle of the clock signal 110 and the frequency-divided clock signal 112 only during the period when the internal counter value is “0”. Set to low level.

  The counter circuit 7 performs a counting operation for incrementing the counter value in synchronization with the rising edge of the divided clock signal 112.

  For example, as shown in FIG. 2, the counter value 115 is incremented from “K (K is an arbitrary integer)” to “K + 1” in synchronization with the rising edge of the divided clock signal 112.

  On the other hand, the counter control circuit 5 generates a reset signal 111 and outputs the reset signal 111 to the frequency divider 6 when a load command is received from a CPU (not shown) via the CPU bus indicated by “CB21” in FIG. In addition, in the next cycle of the clock signal 110, the load value 113 and the load signal 114 (more precisely, the load signal 114 is set to the high level) designated by the CPU (not shown) are synchronized with the clock signal 110. Generated and output to the counter circuit 7.

  For this reason, the frequency dividing circuit 6 to which the reset signal 111 is applied sets the internal counter value to “0” in the next cycle of the clock signal 110 and outputs the frequency-divided clock signal 112 only during the period when the internal counter value is “0”. Set to low level.

  For example, when the reset signal 111 is applied to the frequency dividing circuit 6 in the cycle indicated by “TM31” in FIG. 2, the internal counter of the frequency dividing circuit 6 in the next cycle of the clock signal 110 indicated by “TM32” in FIG. As the value becomes “0”, the frequency-divided clock signal 112 is set to the low level as indicated by “LP31” in FIG.

  Then, since the load value 113 is supplied in the next cycle of the clock signal 110 and the load signal 114 becomes high level, the counter circuit 7 counts the load value 113 in synchronization with the rising edge of the divided clock signal 112. Load as value 115.

  For example, since the load value 113 is “L (L is an arbitrary integer)” in the cycle indicated by “TM32” in FIG. In synchronization with the rise of the signal 112, the counter value 115 is changed from "K + 1" to "L".

  That is, at the timing of the load operation of the counter control circuit 5 (for example, when the load value 113 and the load signal 114 indicated by “TM32” in FIG. 2 are output), the internal counter value of the frequency divider 6 is set to “0”. Since it has been reset, the cycle of the counter value 115 immediately after the loading operation indicated by “PD31” in FIG. 2 is always constant.

  As a result, when the counter control circuit 5 receives the load command, the counter control circuit 5 generates the reset signal 111 and outputs the reset signal 111 to the frequency dividing circuit 6, and supplies the load value 113 at the next cycle of the clock signal 110. By setting 114 to a high level, it is possible to load the load value to the counter circuit 7 while always keeping the cycle of the counter value 115 immediately after the load operation constant.

  For this reason, the cycle of the counter value 115 immediately after the loading operation is always constant and the cycle of the counter value 115 is not changed. Therefore, the time accuracy of the counter is improved, and the signal for generating the divided clock signal 112 is one system. As a result, verification becomes easy, and it is not necessary to consider the wiring length when the logic IC is laid out, thereby facilitating the layout work.

  Although the embodiment shown in FIG. 1 prevents the fluctuation of the counter value period immediately after the loading operation to the counter circuit, it can also be used to prevent the fluctuation of the counter value period immediately after the reset operation of the counter circuit. It is.

  FIG. 3 is a block diagram showing the configuration of another embodiment of the counter device according to the present invention for preventing fluctuations in the cycle of the counter value immediately after the reset operation of the counter circuit.

  In FIG. 3, 8 is a counter control circuit for writing a load value (loading), reading a counter value (reading), and resetting the counter value by a command (load command, read command, reset command) from the CPU, and 9 is a reset. A frequency dividing circuit that has a function and generates a divided clock signal by dividing the clock signal by a frequency division number N (N is an integer of 2 or more), and 10 is a counter that has a reset function and counts the divided clock signal Circuit.

  Further, 120 is a clock signal, 121 is a reset signal of the frequency dividing circuit 9, 122 is a frequency divided clock signal, 123 is a load value, 124 is a load signal, 125 is a reset signal of the counter circuit 10, and 126 is a counter value. Further, 8, 9 and 10 constitute a counter device.

  The clock signal 120 is applied to the clock signal input terminals of the counter control circuit 8 and the frequency dividing circuit 9, and the reset signal 121 that is the output of the counter control circuit 8 is applied to the reset signal input terminal of the frequency dividing circuit 9. Further, the divided clock signal 122 which is the output of the frequency dividing circuit 9 is applied to the reset input terminal of the counter circuit 10.

  The load value 123, load signal 124, and reset signal 125, which are outputs of the counter control circuit 8, are applied to the input terminals of the counter circuit 10, respectively, and the counter value 126, which is the output of the counter circuit 10, is input to the counter control circuit 8. Applied to the terminal.

  Finally, the counter control circuit 8 is mutually connected to a CPU bus indicated by “CB41” in FIG. 3 to which a CPU (not shown) is connected.

  Here, the operation of another embodiment shown in FIG. 3 will be described with reference to FIG. FIG. 4 is a timing chart for explaining the operation of another embodiment. However, in the description of the operation, the reset operation of the counter control circuit 8 will be described, and the description of the counter value read operation will be omitted.

  As shown in FIG. 4, the frequency dividing circuit 9 increments the internal counter in synchronization with the clock signal 120. When the internal counter value is “7”, the frequency dividing circuit 9 sets the internal counter value to “0” in synchronization with the clock signal 120. The frequency-divided clock signal 122 is set to the low level only during the period when the internal counter value is “0”.

  In other words, the frequency dividing circuit 9 repeats the operation of dividing the clock signal 120 by 8 (frequency division number: N = 8) and generating the divided clock signal 122 that outputs the rising clock at that timing. .

  Further, when the reset signal 121 becomes high level, the frequency dividing circuit 9 sets the value of the internal counter to “0” in the next cycle of the clock signal 120 and the frequency-divided clock signal for the period in which the internal counter value is “0”. 122 is set to the low level.

  The counter circuit 10 performs a count operation for incrementing the counter value in synchronization with the rising edge of the divided clock signal 122.

  For example, as shown in FIG. 4, the counter value 126 is incremented from “K (K is an arbitrary integer)” to “K + 1” in synchronization with the rising edge of the divided clock signal 122.

  On the other hand, when the counter control circuit 8 receives a reset command from a CPU (not shown) via the CPU bus indicated by “CB41” in FIG. At the same time, a reset signal 125 (to be precise, the reset signal 125 is set to a high level) is generated in synchronization with the clock signal 120 and output to the counter circuit 10 in the next cycle of the clock signal 120.

  Therefore, the frequency dividing circuit 9 to which the reset signal 121 is applied sets the internal counter value to “0” in the next cycle of the clock signal 120 and outputs the frequency-divided clock signal 122 only during the period when the internal counter value is “0”. Set to low level.

  For example, when the reset signal 121 is applied to the frequency dividing circuit 9 in the cycle indicated by “TM51” in FIG. 4, the internal counter of the frequency dividing circuit 9 is set in the next cycle of the clock signal 102 indicated by “TM52” in FIG. As the value becomes “0”, the frequency-divided clock signal 122 is set to the low level as indicated by “LP51” in FIG.

  Then, the counter circuit 10 to which the reset signal 125 is applied in the next cycle of the clock signal 120 resets the counter and sets the counter value 126 to “0” in synchronization with the rising edge of the divided clock signal 122.

  For example, since the reset signal 125 is applied in the cycle indicated by “TM52” in FIG. 4 which is the next cycle of the clock signal 120, the counter circuit 10 synchronizes with the rising edge of the divided clock signal 122. Reset to change the counter value 126 from “K + 1” to “0”.

  That is, at the timing of the reset operation of the counter circuit 10 of the counter control circuit 8 (for example, when the reset signal 125 indicated by “TM52” in FIG. 4 is output), the internal counter value of the frequency dividing circuit 9 is set to “0”. Since it has been reset, the cycle of the counter value 126 immediately after the reset operation indicated by “PD51” in FIG. 4 is always constant.

  As a result, when the counter control circuit 8 receives the reset command, the counter control circuit 8 generates the reset signal 121 and outputs the reset signal 121 to the frequency dividing circuit 9, and also sets the reset signal 125 of the counter circuit 10 to the high level in the next cycle of the clock signal 120. By setting the level, the counter value of the counter circuit 10 can be reset while the cycle of the counter value 126 immediately after the reset operation is always kept constant.

  For this reason, the cycle of the counter value 126 immediately after the reset operation is always constant, and the variation of the cycle of the counter value 126 is eliminated. Therefore, the time accuracy of the counter is improved, and the signal for generating the divided clock signal 122 is one system. As a result, verification becomes easy, and it is not necessary to consider the wiring length when the logic IC is laid out, thereby facilitating the layout work.

  Further, in the description of the embodiment shown in FIG. 1, for the sake of simplicity of explanation, explanation of the counter value reading operation is omitted, but the counter control circuit 5 is connected from a CPU (not shown) via a CPU bus. When the read command is received, the counter value 115 input from the counter circuit 7 to the counter control circuit 5 is fetched and transmitted to the CPU (not shown) via the CPU bus.

  Similarly, in the explanation of the embodiment shown in FIG. 3, for the sake of simplicity of explanation, explanation of the counter value read operation is omitted, but the counter control circuit 8 is changed from the CPU (not shown) to the CPU. When a read command is received via the bus, the counter value 126 input from the counter circuit 10 to the counter control circuit 8 is fetched and transmitted to a CPU (not shown) via the CPU bus.

It is a block diagram showing the configuration of an embodiment of a counter device according to the present invention. It is a timing diagram explaining operation | movement of an Example. It is a block diagram which shows the other Example of the counter apparatus based on this invention. It is a timing diagram explaining operation | movement of another Example. It is a block diagram showing an example of a conventional counter device. It is a timing diagram explaining operation | movement of a prior art example. It is a truth table explaining operation | movement of an OR circuit.

Explanation of symbols

1, 5, 8 Counter control circuit 2, 6, 9 Dividing circuit 3 OR circuit 4, 7, 10 Counter circuit 100, 110, 120 Clock signal 101, 113, 123 Load value 102, 114, 124 Load signal 103 Load Clock signal 104, 112, 122 Divided clock signal 105 Counter clock signal 106, 115, 126 Counter value 111, 121, 125 Reset signal

Claims (3)

In the counter device that divides the clock signal and performs the counting operation,
A frequency dividing circuit that has a reset function and generates a divided clock signal by dividing the clock signal;
A counter circuit for counting the divided clock signal;
A counter control circuit that generates a reset signal when the load command is received and outputs the reset signal to the frequency divider circuit, and applies a load value and a load signal to the counter circuit in the next cycle of the clock signal. A counter device. In the counter device that divides the clock signal and performs the counting operation,
A frequency dividing circuit that has a reset function and generates a divided clock signal by dividing the clock signal;
A counter circuit having a reset function and counting the divided clock signal;
And a counter control circuit that generates a reset signal when the reset command is received and outputs the reset signal to the frequency divider circuit, and applies the reset signal to the counter circuit in the next cycle of the clock signal. Counter device. The counter control circuit is
3. The counter device according to claim 1, wherein when a read command is received, the counter value from the counter circuit is fetched and transmitted.

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