JP2009094344A - Storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-reliability storage device highly integrated without causing crosstalk between another storage device and itself, and excelling in mass productivity, and also to provide its manufacturing method. <P>SOLUTION: In this storage device 10, a resistance change element 12 including a resistance change film 11 and a current suppression element 14 including a current suppression layer 13 are connected in series to each other. The resistance change film 11 is arranged in a lower part of a first contact hole 17 formed by penetrating a first interlayer insulation film 16, and the current suppression layer 13 is arranged in an upper part of the first contact hole 17 and in a position facing the resistance change film 11. The resistance change film 11 and the current suppression layer 13 are electrically connected to each other through a plug 18 formed in the first contact hole 17, and a conductive layer 19 in the plug 18 constitutes partial parts of the resistance change element 12 and the current suppression element 14. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a storage device with high mass productivity suitable for miniaturization.

  In recent years, it has been proposed to use a so-called variable resistance element as a memory. Such a resistance change element has a thin film mainly composed of a metal oxide material. When an electric pulse is applied to the thin film, its resistance value changes and the changed resistance value is maintained. When the high resistance state and the low resistance state of the thin film are associated with, for example, “1” and “0” of binary data, binary data can be stored. The magnitude and current density of the electric field due to the applied electric pulse need only be sufficient to change the physical state of the thin film and do not destroy the thin film. Also good.

As a memory device using such a resistance change element, a memory plug is formed at the intersection of upper and lower wirings of a cross-point type memory structure, and a resistance change film having a bipolar characteristic and a diode are combined in the memory plug. A structure of a memory device that is formed in the stacking direction and suppresses high integration and crosstalk is shown (for example, see Patent Document 1).
US Pat. No. 6,753,561

  However, the memory structure disclosed in Patent Document 1 is a structure in which a current suppressing element and a memory device including a resistance change film are stacked in one contact hole, and at least six layers of different materials are stacked. Although it is necessary to form such a multilayer structure, it is not easy to manufacture such a complicated laminated structure, and a very difficult structure is formed by a fine process in which a so-called process rule is less than 100 nm. In addition, since the current suppression element is formed in the contact hole, the current capacity of the current suppression element is determined by the diameter of the contact hole. If the allowable current amount per unit area of the current suppression element is not sufficiently large, the resistance change There also arises a problem that it is difficult to secure a current necessary for stably operating the element.

  The present invention solves the above-described problem, and when configuring a memory device in which a resistance change element including a resistance change film and a current suppression element including a current suppression layer are connected in series, the resistance change film and the current suppression are configured. By forming a structure in which the electrode layer of the resistance change element and the electrode layer of the current suppressing element are connected in a self-aligned manner in the contact hole that connects the layers, high integration can be achieved, and mass production is high and high reliability. It is an object to provide a storage device.

  In order to achieve the above object, a memory device according to the present invention includes a substrate, an interlayer insulating film formed on the substrate, and a first contact hole formed through the interlayer insulating film. A memory device having a resistance change element and a current suppression element formed at least in part, wherein the resistance change element has a resistance change film, and is disposed above or below the first contact hole. The current suppression element includes a current suppression layer, and the current suppression layer is disposed at a position below or above the first contact hole and facing the resistance change film, and the resistance change film and the current suppression layer The layer is electrically connected by a plug formed in the first contact hole, and the conductive layer in the plug constitutes a part of the variable resistance element and the current suppressing element. With such a structure, a highly integrated memory device including a highly reliable memory device with little variation in electrical characteristics can be realized. In addition, a storage device that prevents crosstalk and has a current suppressing element with a large current capacity can be realized.

  The conductive layer in the plug includes a first electrode layer adjacent to the resistance change film and constituting the resistance change element, a second electrode layer adjacent to the current suppression layer and constituting the current suppression element, and the first electrode layer. It is good also as a structure which consists of at least three layers of the 3rd electrode layer which connects 2nd electrode layer. With such a configuration, in the memory device in which the variable resistance element and the current suppressing element are connected in series, a connection structure suitable for higher integration can be realized. And by setting it as such a structure, the electrode material of the electrode of the resistance change element in the 1st contact hole and the electrode of a current suppression element can be selected independently, respectively.

  A plurality of plugs are formed in a matrix in the first interlayer insulating film, and the stripe-shaped first wiring connected to the resistance change layer formed on the upper or lower portion of the plug, and the lower or upper portion of the plug. And a stripe-shaped second wiring connected to the current suppression layer formed on the first wiring and the second wiring. The first wiring and the second wiring are arranged so as to intersect with each other, and plugs formed in a matrix are arranged. The first wiring and the second wiring may be connected via each other. With such a configuration, a cross-point type storage device can be manufactured with high integration by a mass production process having affinity with a fine process in which a so-called process rule is less than 100 nm.

  Further, the first electrode layer or the second electrode layer may cover at least the bottom surface of the first contact hole and may not cover the upper part of the side surface of the first contact hole. By adopting such a configuration, the structure of the conductive layer in the plug can be manufactured more easily, and the electrical connection between the electrode layers constituting the conductive layer, the conductive layer and the resistance change film, or the current suppressing layer can be achieved. The electrical connection with can be further improved.

  Further, the second electrode layer or the first electrode layer may be formed in the first contact hole so as to cover the upper surface of the first contact hole and the upper part of the side surface. By adopting such a configuration, the structure of the conductive layer in the plug can be manufactured more easily, and the electrical connection between the electrode layers constituting the conductive layer, the conductive layer and the resistance change film, or the current suppressing layer can be achieved. The electrical connection with can be further improved.

  The third electrode layer may have a configuration in which the first electrode layer and the second electrode layer are surrounded by the first contact hole. By adopting such a configuration, a material having higher conductivity can be selected and used as the third electrode layer.

  Further, the third electrode layer may be formed in a shape having a convex portion, and the convex portion may be fitted into the concave portion of the first electrode layer or the second electrode layer. With such a configuration, electrical connection between the electrode layers can be further improved.

  The current suppressing element may be a MIM diode, an MSM diode, or a varistor. With this configuration, crosstalk can be easily prevented even in a resistance change element that writes data by applying electric pulses of different polarities, and a sufficient current can be applied to the resistance change element. It can be.

  The memory device of the present invention has a contact for connecting a resistance change film and a current suppression layer when a memory device in which a resistance change element including a resistance change film and a current suppression element including a current suppression layer are connected in series is configured. A structure in which the electrode layer of the resistance change element and the electrode layer of the current suppressing element are connected in a self-aligned manner is formed in the hole. With such a configuration, the variable resistance element and the current suppressing element can be connected in series in a compact manner, so that a highly reliable memory device that can be highly integrated and is mass-productive can be realized. In addition, since the flat variable resistance film and the flat current suppression layer are connected, a memory device with uniform electrical characteristics and less variation can be realized.

  Hereinafter, a storage device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings. In addition, what attached | subjected the same code | symbol in drawing may abbreviate | omit description.

(First embodiment)
1 to 9 are diagrams showing a first embodiment of the present invention. FIG. 1 is a schematic configuration diagram of storage devices 10, 15, and 20 according to the first embodiment of the present invention. FIGS. 1A and 1B are schematic cross-sectional views showing the configuration of the storage devices 10 and 15. FIG. 1C is a schematic cross-sectional view showing the configuration of the storage device 20 in which the conductive layer of FIG.

  1A, in the memory device 10, a resistance change element 12 including a resistance change film 11 and a current suppression element 14 including a current suppression layer 13 are connected in series. The resistance change film 11 is disposed below the first contact hole 17 formed so as to penetrate the first interlayer insulating film 16, and the current suppression layer 13 is disposed above the first contact hole 17. It is arranged at a position facing the resistance change film 11. The resistance change film 11 and the current suppression layer 13 are electrically connected by a plug 18 formed in the first contact hole 17, and the conductive layer 19 in the plug 18 is connected to the resistance change element 12 and the current. A part of the suppression element 14 is configured. As shown in FIG. 1A, the resistance change element 12 has a configuration in which the first wiring 22 and the conductive layer 19 formed on the substrate 21 are arranged below and above the resistance change film 11, The current suppression element 14 has a configuration in which the second wiring 23 formed on the first interlayer insulating film 16 and the current suppression layer 13 and the conductive layer 19 are disposed above and below the current suppression layer 13. .

  1B includes a resistance change element 24 including the resistance change film 11 and a current suppression element 25 including the current suppression layer 13 connected in series. The resistance change film 11 is disposed above the first contact hole 17 formed so as to penetrate the first interlayer insulating film 16, and the current suppression layer 13 is located below the first contact hole 17, and It is arranged at a position facing the resistance change film 11. The resistance change film 24 and the current suppression layer 25 are electrically connected by a plug 18 formed in the first contact hole 17, and the conductive layer 19 in the plug 18 includes the resistance change element 24 and the current. A part of the suppression element 25 is configured. As shown in FIG. 1B, the current suppression element 25 has a configuration in which the first wiring 22 and the conductive layer 19 formed on the substrate 21 are disposed below and above the current suppression layer 13, The resistance change element 24 has a configuration in which the second wiring 23 formed on the first interlayer insulating film 16 and the resistance change film 11 and the conductive layer 19 are arranged above and below the resistance change film 11. . 1A and 1B have a structure in which the positions of the resistance change film 11 and the current suppression layer 13 are interchanged with each other with the plug 18 interposed therebetween, and storage devices having the same characteristics and functions are provided. Realized.

  With such a structure, a highly integrated memory device including a highly reliable memory device with little variation in electrical characteristics can be realized. In addition, it is possible to realize a memory device that prevents crosstalk between the memory devices and has a current suppressing element with a large current capacity. This effect will be described in detail in the description of the embodiment described below. Furthermore, as shown in FIG. 1C, the plug can be realized by a plurality of laminated structures. The conductive layer 19 in the plug 18 is adjacent to the resistance change film 11 and constitutes the first electrode layer 26 constituting the resistance change element 12, and adjacent to the current restraint layer 13 and second electrode layer 27 constituting the current restraint element 14. The first electrode layer 26 and the second electrode layer 27 are connected to each other, and the third electrode layer 28 includes at least three layers. The storage device 20 is configured to be highly integrated in a matrix form as a storage device. That is, the first wiring 22 is surrounded by the second interlayer insulating film 29 up to the same height, and the second wiring 23 is formed on the current suppression layer 13, so Covered with an interlayer insulating film 31.

  With such a configuration, in the memory device in which the variable resistance element and the current suppressing element are connected in series, a connection structure suitable for higher integration can be realized. And by setting it as such a structure, the electrode material of the electrode of the resistance change element in the 1st contact hole and the electrode of a current suppression element can be selected independently, respectively.

  2A and 2B are schematic views showing the configuration of the memory device 20 according to the present embodiment shown in FIG. 1C. FIG. 2A is a plan view seen from the surface 32 of the semiconductor chip, and FIG. 2A is a schematic cross-sectional view of the cross section taken along the line AA in the arrow direction, and FIG. 2C is a schematic cross-sectional view of the cross section taken along the line BB of FIG. 2A in the arrow direction. Show. Note that FIG. 2C shows the same configuration as FIG.

  In FIG. 2A, the memory device 20 is electrically connected with a resistance change element 12, a plug 18, and a current suppression element 14 sandwiched between a first wiring 22 and a second wiring 23 in series in the stacking direction. It is connected to the.

  As shown in FIGS. 2B and 2C, the memory device 20 includes a resistance change element including a resistance change film 11 sandwiched between a first wiring 22 and a first electrode 26 on a semiconductor substrate 21. 12 and the current suppression element 14 including the current suppression element 13 sandwiched between the second electrode 27 and the second wiring 23 are connected in series by the plug 19 of the first contact hole 17.

  Here, the current suppression element 14 is configured to be an MIM (Metal-Insulator-Metal) diode, an MSM (Metal-Semiconductor-Metal) diode, or a varistor. As a result, crosstalk can be easily prevented even in the case where data is written by applying electrical pulses of different polarities to the resistance change element 12, and the resistance change element 12 has sufficient characteristics. It can be set as the structure which can apply an electric current. Since the memory device 20 of the present embodiment has a configuration in which the area of the second wiring 23 corresponding to the upper electrode is larger than the second electrode 27 corresponding to the lower electrode of the current suppression element 14, The element 14 can drive the variable resistance element 12 with a larger driving current.

  FIG. 3 shows a change in resistance value when an electric pulse is applied to the resistance change element 12 of the memory device 20 manufactured with the structure of the schematic cross-sectional view shown in FIGS. 2B and 2C. . When two types of electrical pulses having different polarities are alternately applied between the first wiring 22 of the resistance change element 12 of the storage device 20 and the second wiring 23 of the current suppressing element 14, between the two wirings. Depending on the applied voltage, the resistance value of the resistance change element 12 changes as shown in FIG. That is, as shown in FIG. 3, when a negative voltage pulse (hereinafter referred to as E1) is applied, the resistance value decreases to show a low resistance value Ra, and a positive voltage pulse (hereinafter referred to as E2). ) Is applied, the resistance value increases to show a high resistance value Rb. Here, as a voltage necessary for changing the resistance value, the negative voltage is E1, the positive voltage is E2, and an electric pulse is applied to rewrite the stable resistance value.

  Also, as shown in FIG. 3, when one of the two different resistance values Ra or Rb is set to information “0” and the other is set to information “1”, the resistance value is changed. Different information “0” or information “1” can be read. In FIG. 3, the larger resistance value Rb is assigned to information “0”, and the smaller resistance value Ra is assigned to information “1”. As shown in FIG. 3, when a negative voltage pulse is applied when the resistance value of the resistance change element 12 is Rb, the resistance value Ra is recorded, and the information of the resistance change element 12 is rewritten from “0” to “1”. It is done. Similarly, when a positive voltage pulse is applied when the resistance value of the resistance change element 12 is Ra, the resistance value Rb is recorded, and the information of the resistance change element 12 is rewritten from “1” to “0”.

  When this information is read, the reproduction voltage E3 having a smaller amplitude than the electric pulse applied when changing the resistance value of the resistance change element 12 is applied, and the output current value corresponding to the resistance value shown in FIG. Read. Since the output current value Ia or Ib corresponds to the resistance value Ra or Rb, information “0” or information “1” is read as shown in FIG. In this way, the storage device 20 operates.

  3 and 4 show, as an example, the case of using a resistance change element having a characteristic that the resistance value decreases when a negative voltage pulse is applied and the resistance value increases when a positive voltage pulse is applied. It is. In the following, the embodiment will be described by taking as an example the case of using a variable resistance element having a characteristic that the resistance value decreases when a negative voltage pulse is applied and the resistance value increases when a positive voltage pulse is applied. Even when a device having a characteristic that the resistance value decreases when a positive voltage pulse is applied as a change element and the resistance value increases when a negative voltage pulse is applied is used, the described operation (in the description about the resistance change element, It should be noted that the same holds true (by appropriately modifying the magnitude relationship and / or the positive / negative relationship).

  FIG. 5 schematically shows current-voltage characteristics (IV characteristics) of the current suppression element 14. When the current suppression element 14 is configured by an MIM diode, an MSM diode, or a varistor, the current-voltage characteristics are as follows. As shown in FIG. That is, the current suppressing element 14 has a relatively low resistance when a large voltage is applied in both positive and negative directions, and the current suppressing element 14 has a relatively high resistance when a small voltage not exceeding VH or VL is applied. In particular, since the MSM diode has a structure in which a semiconductor is sandwiched between metals, it is possible to flow a large current (thus, a large range of current that can be passed), and its characteristics are metal. This is due to the potential barrier formed between the metal and the semiconductor adjacent to the metal, but especially when an amorphous semiconductor is used, it is considered that characteristic variations due to the structure of the semiconductor do not occur in principle. This is considered to be more preferable as a current suppressing element.

  In the memory device 20 of the present embodiment, a voltage is applied in a configuration in which the resistance change element 12 and the current suppression element 14 are connected in series. With such a configuration, when the regenerative voltage E3 is applied, the current suppression element 14 has a high resistance, so that the regenerative voltage E3 is applied to the current suppression element 14 with a relatively large voltage division. On the other hand, when a large positive voltage E2 or negative voltage E1 that rewrites the resistance value is applied, the current suppressing element 14 has a low resistance, so that the positive voltage E2 and the negative voltage E1 are relatively divided into the resistance change element 12. Applied with pressure. Therefore, when the resistance value is rewritten, it can be rewritten by applying an appropriate voltage to the memory device. In addition, when the reproduction voltage E3 for reading the resistance value is applied to the storage device 20, a relatively small partial voltage is applied to the resistance change element 12. Therefore, even if noise or the like is superimposed on the reproduction voltage E3, it is erroneous. The resistance value can be safely read without rewriting the resistance value.

  6 and 7 are schematic configuration diagrams of the cross-point type storage device 30 according to the present embodiment. FIG. 6 is a schematic configuration diagram of the configuration of the storage device 30 as viewed from the semiconductor chip surface 33. Here, for example, eight first wirings 34 (34a, 34b, 34c, 34d, 34e, 34f, 34g, 34h) and eight second wirings 35 (35a, 35b, 35c, 35d, 35e, 35f, 35g, 35h). A variable resistance element (not shown) and a current suppressing element (not shown) are connected in series by the plug 18 at the intersection of these and sandwiched between the first wiring 34 and the second wiring 35. Thus, the storage device E is configured. As a whole, a plurality of matrix storage devices E are configured. In addition, the resistance change film 11 and the current suppression layer 13 are sandwiched between the first wiring 34 and the second wiring 35 in a sheet form as shown in FIG.

  7A is a schematic cross-sectional view of the storage device 30 of FIG. 6 as viewed in the direction of the arrow along the line CC, and FIG. 7B is a cross-sectional view of the storage device 30 of FIG. The schematic sectional drawing seen in the arrow direction in the cross section is shown. Note that the storage of the storage device 30 having the same configuration as that of the storage device 20 shown in FIGS. 2B and 2C in the area surrounded by the broken line shown in FIGS. 7A and 7B. Device E is shown.

  As shown in FIGS. 7A and 7B, a plurality of plugs 18 are formed in a matrix in the first interlayer insulating film 16 and are connected to the resistance change film 11 formed below the plug 18. The storage device 30 is further provided with a stripe-shaped first wiring 34 and a stripe-shaped second wiring 35 connected to the current suppression layer 13 formed above the plug 18. The first wiring 34 and the second wiring 35 are arranged in a shape that intersects with the plugs 18 formed in a matrix. At this time, the resistance change film 11 and the current suppression layer 13 are arranged at the upper part and the lower part with the plug 18 interposed therebetween, and the storage device of the present embodiment is configured by changing the positional relationship. May be. Similarly, the storage device of this embodiment may be configured with a configuration in which the positional relationship between the first wiring 34 and the second wiring 35 is also switched.

  With such a structure, a cross-point type storage device can be manufactured with high integration by a mass production process having a so-called process rule that is compatible with a fine process of less than 100 nm.

  In the storage device 30, the resistance change element 12 and the current suppression element 14 are connected in series between the first wiring 34 and the second wiring 35 that apply a voltage for writing and reading information. Thus, it is possible to prevent malfunction due to crosstalk between adjacent storage devices, and to realize a storage device with stable operation.

  The current suppression element 14 is configured as an MIM diode, an MSM diode, or a varistor. Then, even when the variable resistance element 12 has a characteristic of writing data by applying electric pulses of different polarities, in addition to easily preventing crosstalk, the variable resistance element 12 is sufficient. It can be set as the structure which can apply an electric current.

  At this time, even if the noise voltage is added to the applied voltage via the power supply line, it is almost absorbed by the current suppressing element 14, so that malfunctions such as erroneously rewriting the resistance value of the resistance change element 12 occur. Can not be.

  In the memory device 30, the first electrode layer 26 and the second electrode layer 27 are formed in the first contact hole 17 in a self-aligned manner, and as a result, the resistance change element 12 connected in series The current suppressing element 14 is formed in the stacking direction. Thus, the memory device 30 having an element structure suitable for a process for highly integrating memory elements can be realized.

  In addition, the first electrode layer 26 and the second electrode layer 27 are formed in the first contact hole 17, so that the first electrode layer of the resistance change element and the second electrode layer of the current suppressing element are formed. Are shared with the plug of the first contact hole. Therefore, the number of steps of the photomask process and the etching process for forming the electrode layer can be reduced, and the process can be simplified.

  Next, as an example of the method for manufacturing the storage device according to the present embodiment, the process flow of the method for manufacturing the storage device 20 will be described in order with reference to FIGS.

  In the method for manufacturing the memory device 20 according to the present embodiment, a step of forming the first wiring 22 on the substrate 21, and a second interlayer insulating film 29 is formed on the substrate 21 so as to cover the first wiring 22. After that, the second interlayer insulating film 29 is removed until the first wiring 22 is exposed and planarized to the height of the upper surface of the first wiring 22, and the first wiring after the planarization process. 22 and the step of forming the resistance change film 11 on the second interlayer insulating film 29. Then, a step of covering the resistance change film 11 and forming the first interlayer insulating film 16 on the second interlayer insulating film 29 and the first wiring 22, and the first interlayer insulating film 16 penetrating the first interlayer insulating film 16. Plug forming step of forming the plug 18 made of the conductive layer 19 in the first contact hole 17 on the resistance change film 11 on the wiring 22 of the wiring, the current suppressing layer 13 covering the plug 18 and the current suppressing layer 13 Forming a second wiring layer. Then, a step of removing a part of the second wiring layer in a stripe shape and forming a stripe-shaped second wiring 23 orthogonal to the first wiring 22 on the current suppressing layer 13 on the plug 18; In addition, the conductive layer 19 constitutes a part of the variable resistance element 12 and the current suppression element 14, so that the variable resistance element 12 and the current suppression element 14 are connected in series. The process flow will be described in order for the manufacturing method configured as described above.

As shown in FIG. 8A, a conductive material such as an Al material to be the first wiring 22 is formed on the substrate 21 in a stripe shape by vapor deposition and etching. Note that the wiring material is a metal material other than Al, for example, a metal such as Cu, Ti, W, Pt, Ir, Cr, Ni, Nb or a mixture (alloy) thereof, or TiN, TiW, TaN, TaSi ₂ , TaSiN. , TiAlN, NbN, WN, RuO ₂ , In ₂ O ₃ , SnO ₂ , IrO _2, or other conductive compounds, or a laminated structure thereof can be used, but of course, it is limited to these. It is not a thing. A sputtering method or other methods may be used as a method for depositing the wiring material. Then, as shown in FIG. 8B, a second interlayer insulating film 29 is formed so as to cover the substrate 21 and the first wiring 22 by a CVD method or the like.

Then, as shown in FIG. 8C, the second interlayer insulating film is formed by, for example, a CMP (Chemical Mechanical Polishing) technique so that the first wiring 22 is exposed up to the height of the upper surface of the first wiring 22. 29 is removed and planarized, and a second interlayer insulating film 29 is formed so as to fill the space between the first wirings 22. After that, as shown in FIG. 8D, a material for forming the resistance change film 11 is deposited on the first wiring 22 and the second interlayer insulating film 29 by a sputtering method or the like, and only a necessary region is obtained by an etching method. The resistance change film 11 is formed to remain. By forming the resistance change film 11 on the flattened surface as described above, it is possible to form the resistance change film 11 having stable characteristics without variations. Here, as the variable resistance material constituting the variable resistance film 11, a perovskite transition metal oxide, an oxide of a typical metal or a transition metal, or the like can be used. Specifically, Pr _(1-x) Ca _x MnO ₃ (0 <x <1), TiO ₂ , NiO _x (x> 0), Cu _x O (x> 0) and the like, or a substitute thereof, or Although these mixtures and laminated structures are mentioned, of course, it is not limited to these.

Next, as shown in FIG. 9A, the resistance change film 11 is covered and becomes the first interlayer insulating film 16 on the second interlayer insulating film 29 and the first wiring 22, for example, SiO ₂ or the like. An insulating material is deposited by a CVD method or the like. Then, as shown in FIG. 9B, the first contact hole 17 is formed through the first interlayer insulating film 16 on the resistance change film 11 by, for example, a dry etching method.

  Next, as shown in FIG. 9C, a plug 18 made of a conductive layer 19 is formed in the first contact hole 17. At this time, the conductive layer 19 formed in the plug 18 constitutes the first electrode layer 26 constituting the resistance change element 12 adjacent to the resistance change film 11 and the current suppression element 14 adjacent to the current suppression layer 13. The second electrode layer 27 and the third electrode layer 28 connecting the first electrode layer 26 and the second electrode layer 27 are formed to be at least three layers. That is, the conductive material that becomes the first electrode layer 26, the conductive material that becomes the third electrode layer 28 that electrically connects the first electrode layer 26 and the second electrode layer 27, and the second A conductive material for forming the electrode layer 27 is sequentially deposited in the first contact hole 17 in the stacking direction by sputtering. After these three electrode layers are formed, the second electrode layer 27 is removed by CMP technology so that the first interlayer insulating film 16 is exposed up to the upper surface 38 of the first interlayer insulating film 16. A plug 18 having three layers is formed in the contact hole 17.

Then, as shown in FIG. 9D, after depositing a material constituting the current suppression layer 13 on the planarized upper surface 38, a conductive material such as an Al material to be the second wiring 23 is deposited. To do. Then, the current suppressing layer 13 and the second wiring 23 covering the plug 18 are patterned by an etching method to form as shown in FIG. Further, a third interlayer insulating film 31 is formed as a protective film on the first interlayer insulating film 16 by the CVD method or the like so as to cover the current suppressing layer 13 and the second wiring 23. In this way, the storage device 20 is formed. Here, as a material constituting the current suppression layer 13, a compound semiconductor such as GaN, an oxide such as Al ₂ O ₃ , SiO ₂ , Ta ₂ O ₅ , a ZnO-based varistor (ZnO with Bi ₂ O ₃ , Sb ₂ O ₃ , CoO, MnO, Cr ₂ O ₃ , SrO, BaO, Pr ₂ O _3, etc.), nitrides such as SiN _x (x> 0), or a-Si with junctions formed Or organic matter. Of course, the present invention is not limited to this, and exhibits non-linear voltage-current characteristics in which the resistance value decreases as the absolute value of the applied voltage increases at the junction with adjacent electrodes. I just need it.

  In this manner, by configuring the plug to have three layers, it is possible to realize a connection structure suitable for higher integration in the memory device in which the variable resistance element and the current suppressing element are connected in series. And by setting it as such a structure, the electrode material of the electrode of the resistance change element in the 1st contact hole and the electrode of a current suppression element can be selected independently, respectively.

  Further, with such a structure of the manufacturing method, a highly integrated memory device including a highly reliable memory device with little variation in electrical characteristics can be realized. In addition, a storage device that prevents crosstalk and has a current suppressing element with a large current capacity can be realized. In addition, even a fine process whose so-called process rule is less than 100 nm is easy to manufacture and can be manufactured by simplifying the process, and a manufacturing method having a high affinity with semiconductor process rules can be realized.

  In addition, since the first electrode layer 26 and the second electrode layer 27 are formed in the first contact hole 17 in a self-aligning manner, a memory device can be manufactured in a compact manner. The device manufacturing method is suitable for high integration.

  Note that in the manufacturing method of the memory device of the present embodiment, in the above description, the step of forming the resistance change film at the lower portion of the plug and the step of forming the current suppression layer at the upper portion of the plug have been described. Even if the step of forming the current suppression layer and the step of forming the resistance change film on the plug are performed, the memory device can be manufactured by a method similar to the manufacturing method described in this embodiment.

(Second Embodiment)
10A and 10B are schematic views showing the configuration of the storage device 40 according to the second embodiment. FIG. 10A is a plan view seen from the surface 41 of the semiconductor chip, and FIG. 10B is the plan view of FIG. FIG. 10C is a schematic cross-sectional view of the cross section taken along the line G-G in FIG. 10A in the direction of the arrow.

  In FIG. 10A, the storage device 40 is a resistance change element sandwiched between a first wiring 22 and a second wiring 23, similarly to the storage device 20 of FIG. 2 shown in the first embodiment. 12, the plug 42 and the current suppressing element 14 are arranged in series in the stacking direction and electrically connected. Also, as shown in FIGS. 10B and 10C, the memory device 40 has a resistance including the resistance change film 11 sandwiched between the first wiring 22 and the first electrode layer 44 on the semiconductor substrate 21. The change element 12 and the current suppression element 14 including the current suppression element 14 sandwiched between the second electrode layer 48 and the second wiring 23 are connected in series by the plug 42 of the first contact hole 17. ing. Therefore, the storage device 40 is different from the storage device 20 in the structure of the conductive layer 43 of the plug 42.

  10B and 10C, the first electrode layer 44 constituting the conductive layer 43 of the plug 42 covers at least the bottom surface 45 of the first contact hole 17 and the side surface 46 of the first contact hole 17. It is formed in a shape that does not cover the upper portion 47 of the. The second electrode layer 48 is formed in the first contact hole 17 so as to cover the upper surface 49 of the first contact hole 17 and the upper portion 47 of the side surface 46. Further, the third electrode layer 50 is formed in the first contact hole 17 so as to be surrounded by the first electrode layer 44 and the second electrode layer 48.

  By adopting such a configuration, the structure of the conductive layer in the plug can be manufactured more easily, and the electrical connection between the electrode layers constituting the conductive layer, the conductive layer and the resistance change film, or the current suppressing layer can be achieved. The electrical connection with can be further improved. Furthermore, as the third electrode layer, a material having higher conductivity can be selected and used.

  Next, a method for manufacturing the storage device 40 according to the present embodiment will be described. The steps other than the plug step for forming the plug have been described with reference to FIGS. 8 and 9 showing the manufacturing method of the memory device 20 of the first embodiment, and are the same as these steps. Description is omitted.

  11 and 12 are schematic cross-sectional views showing a manufacturing method for the plug forming process for forming the plug of the storage device 40, and the process flow of the plug forming process will be described with reference to FIGS.

  The process up to the plug forming process for forming the plug is the same as in FIGS. 8A to 8D and FIGS. 9A and 9B.

  After that, as shown in FIG. 11A, the bottom surface 45 and the side surface 46 of the first contact hole 17 formed in the first interlayer insulating film 16 and the top surface of the first interlayer insulating film 16 are covered. Then, a conductive film 51 to be the first electrode layer 44 is deposited by sputtering. Then, as shown in FIG. 11 (b), a conductive film 52 that fills the first contact hole 17 and becomes the third electrode layer 50 is deposited on the conductive film 51 by a sputtering method. And a conductive film 52 are formed.

  Next, as shown in FIG. 11C, the conductive film 51 and the conductive film 52 in the first contact hole 17 are embedded as they are, and the conductive film stacked on the first interlayer insulating film 16 is used. The film 51 and the conductive film 52 are removed by the CMP technique. Then, as shown in FIG. 11D, the conductive film 51 embedded in the first contact hole 17 and a part of the upper part of the conductive film 52 are further removed by the CMP technique to thereby form the first contact. A recess 53 is formed in the upper portion of the hole 17. In this way, the first electrode layer 44 and the third electrode layer 50 are formed. At this time, the height of the upper surface 54 of the first electrode layer 44 is formed to be the same as or lower than the height of the upper surface 55 of the third electrode layer 50. By forming in this way, the shape and thickness of the second electrode layer 48 formed in the recess 53 can be determined in advance.

  Then, a conductive film 56 to be the second electrode layer 48 fills the concave portion 53 of the first contact hole 17 and is deposited on the first interlayer insulating film 16 as shown in FIG. Is done. As shown in FIG. 12B, the deposited conductive film 56 is formed on the first interlayer insulating film 16, leaving a portion to be the second electrode layer 48 in the first contact hole 17. The conductive film 56 is removed by a CMP technique. Then, the surface of the first interlayer insulating film 17 and the upper surface 49 of the second electrode layer 48 formed in the first contact hole are flattened, and the plug 42 is thus formed. Further, as shown in FIG. 12B, the current suppressing layer 13 and the second wiring layer 57 are formed on the second electrode layer 48 formed in the upper part of the first contact hole 17. The And the 2nd wiring 23 is formed by etching using a photolithographic technique. In this way, the storage device 40 configured by connecting the variable resistance element 12 and the current suppressing element 14 in series is manufactured.

  As described above with reference to FIGS. 11 and 12, the plug forming step of the memory device 40 includes the step of forming the first electrode layer 44 covering the bottom surface 45 and the side surface 46 of the first contact hole 17; A step of covering the upper portion of the first interlayer insulating film 16 and filling the first contact hole 17 to form the third electrode layer 50 on the first interlayer insulating film 16. Then, after the third electrode layer 50 on the first interlayer insulating film 16 is removed by CMP technique until the surface of the first interlayer insulating film 16 is exposed, it is buried in the upper part of the first contact hole 17. A part of the first electrode layer 44 and the third electrode layer 50 thus formed is removed by a CMP technique to form a recess 53 on the first contact hole 17. Then, in the plug forming step of the memory device 40, the recess 53 is buried, and the second electrode layer 48 is removed on the first interlayer insulating film 16 by CMP until the surface of the first interlayer insulating film 16 is exposed. And flattening step.

  By adopting such a configuration, the structure of the conductive layer in the plug can be manufactured more easily, and the electrical connection between the electrode layers constituting the conductive layer, the conductive layer and the resistance change film, or the current suppressing layer can be achieved. The electrical connection with can be further improved. Further, as the third electrode layer, a material having higher conductivity can be selected and used.

  Note that, compared with the storage device 40 shown in FIG. 12C, the manufacturing method of the storage device shown in the present embodiment even if the positions where the variable resistance element 12 and the current suppressing element 14 are formed are switched between the upper side and the lower side. Can be applied as well. At this time, the positional relationship and shape of the first electrode layer and the second electrode layer constituting the conductive layer of the plug are interchanged, but the present invention can be applied similarly to the manufacturing method of the above-described embodiment. it can.

(Third embodiment)
FIG. 13 is a schematic cross-sectional view showing the configuration of the storage device 60 according to the third embodiment. This embodiment is a variation of the second embodiment described above, and after forming the recess 53 in FIG. 11D, a conductive layer made of the same material as the third electrode layer 50 of the memory device 40 is stacked. As a result, the third electrode layer 61 having the convex portion 62 shown in FIG. 13 can be formed. Therefore, the third electrode layer 50 of the memory device 60 is formed in a shape having the convex portion 62, and the convex portion 62 is fitted into the concave portion of the first electrode layer 44 or the second electrode layer 48. . In FIG. 13, the first electrode layer 44 is fitted in the recess.

  With such a configuration, electrical connection between the electrode layers can be further improved.

  Next, FIG. 14 and FIG. 15 show schematic configuration diagrams of the cross-point type storage device 70 according to the present embodiment. FIG. 14 is a schematic configuration diagram of the configuration of the storage device 70 as viewed from the semiconductor chip surface 71. Here, for example, eight first wirings 72 (72a, 72b, 72c, 72d, 72e, 72f, 72g, 72h) and eight second wirings 73 (73a, 73b, 73c, 73d, 73e, 73f, 73g, 73h). A resistance change element (not shown) and a current suppressing element (not shown) are connected in series by the plug 42 at the intersection of these and sandwiched between the first wiring 72 and the second wiring 73. Thus, the storage device L is arranged. As a whole, a plurality of matrix storage devices L are configured. Note that the resistance change film 11 and the current suppression layer 13 are sandwiched between the first wiring 72 and the second wiring 73 in a sheet form as shown in FIG.

  FIG. 15A shows a schematic cross-sectional view of the storage device 70 of FIG. 14 as seen in the direction of the arrow along the line JJ. FIG. 15B is a schematic cross-sectional view of the storage device 70 of FIG. 14 as seen in the direction of the arrow along the line KK. Note that the storage device of the storage device 70 having the same configuration as the storage device 40 shown in FIGS. 10B and 10C in the area surrounded by the broken line shown in FIGS. 15A and 15B. L is shown.

  As shown in FIGS. 15A and 15B, a plurality of plugs 42 are formed in a matrix in the first interlayer insulating film 16 and are connected to the resistance change film 11 formed below the plugs 42. The storage device 70 is further provided with a stripe-shaped first wiring 72 and a stripe-shaped second wiring 73 connected to the current suppression layer 13 formed above the plug 42. And the 1st wiring 72 and the 2nd wiring 73 are arrange | positioned in the shape which cross | intersects through the plug 42 formed in the matrix form. At this time, the resistance change film 11 and the current suppression layer 13 are arranged at the upper part and the lower part with the plug 42 interposed therebetween, and the storage device of the present embodiment is configured with this positional relationship interchanged. May be. Similarly, the memory device of this embodiment may be configured with a configuration in which the positional relationship between the first wiring 72 and the second wiring 73 is switched.

  With such a structure, a cross-point storage device can be manufactured with high integration by a mass production process having affinity with a fine process whose so-called process rule is less than 100 nm.

  In the storage device 70, the resistance change element 12 and the current suppression element 14 are connected in series between the first wiring 72 and the second wiring 73 to which a voltage for writing and reading information is applied. Thus, it is possible to prevent malfunction due to crosstalk between adjacent storage devices, and to realize a storage device with stable operation.

  The present invention provides a mass-productive storage device suitable for miniaturization and a method for manufacturing the same, and is useful for reducing the size and thickness of electronic devices such as portable information devices and information home appliances.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic block diagram of the memory | storage device based on the 1st Embodiment of this invention, (a) And (b) is a schematic sectional drawing of a memory device, (c) is a memory | storage which (a) has three conductive layers. Schematic cross section of the device BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic diagram which shows the structure of the memory | storage device based on the 1st Embodiment of this invention, (a) is the top view seen from the semiconductor chip surface, (b) is a cross section of the AA line of (a) by the arrow (C) is a schematic cross-sectional view of the cross section taken along line BB in (a) as viewed in the direction of the arrow. Schematic diagram showing a change in resistance value of the memory device according to the first embodiment of the present invention. The figure which shows the relationship between two different resistance values and information "0" and information "1" Schematic diagram of current-voltage characteristics (IV characteristics) of MIM diode 1 is a schematic configuration diagram of a cross-point type storage device according to a first embodiment of the present invention, and is a schematic diagram viewed from the surface of a semiconductor chip BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic block diagram of the cross-point type | mold memory | storage device based on the 1st Embodiment of this invention, (a) is a schematic sectional drawing which looked at the cross section of the CC line of FIG. 6 in the arrow direction, (b) is FIG. 6 is a schematic cross-sectional view of the cross section taken along the line DD in FIG. FIGS. 4A to 4D are process flow diagrams illustrating a method for manufacturing a memory device according to the first embodiment of the invention. FIGS. FIGS. 4A to 4D are process flow diagrams illustrating a method for manufacturing a memory device according to the first embodiment of the invention. FIGS. 4A and 4B are schematic views showing the configuration of a memory device according to a second embodiment of the present invention, where FIG. 5A is a plan view seen from the surface of a semiconductor chip, and FIG. (C) is a schematic cross-sectional view of the cross section taken along line GG in (a) as viewed in the direction of the arrow. (A) to (d) is a process flow diagram showing a method for manufacturing a memory device according to the second embodiment of the present invention. (A) to (c) are process flow diagrams showing a method for manufacturing a memory device according to the second embodiment of the present invention. Schematic sectional view of a storage device according to a third embodiment of the present invention FIG. 6 is a schematic configuration diagram of a cross-point type storage device according to a third embodiment of the present invention, and is a schematic diagram viewed from the surface of a semiconductor chip. FIG. 10 is a schematic configuration diagram of a cross-point type storage device according to a third embodiment of the present invention, in which (a) is a schematic cross-sectional view of a cross section taken along line JJ in FIG. FIG. 14 is a schematic cross-sectional view of the cross section taken along the line KK in FIG.

Explanation of symbols

10, 15, 20, 30, 40, 60, 70 Memory device 11 Resistance change film 12, 24 Resistance change element 13 Current suppression layer 14, 25 Current suppression element 16 First interlayer insulating film 17 First contact hole 18, 42 Plug 19, 43 Conductive layer 21 Board 22, 34, 34a, 34b, 34c, 34d, 34e, 34f, 34g, 34h, 72, 72a, 72b, 72c, 72d, 72e, 72f, 72g, 72h First wiring 23, 35, 35a, 35b, 35c, 35d, 35e, 35f, 35g, 35h, 73, 73a, 73b, 73c, 73d, 73e, 73f, 73g, 73h Second wiring 26, 44 First electrode layer ( Conductive layer)
27, 48 Second electrode layer (conductive layer)
28, 50, 61 Third electrode layer (conductive layer)
29 Second interlayer insulating film 31 Third interlayer insulating film 32, 33, 41, 71 Semiconductor chip surface 36, 38, 49, 54, 55 Upper surface 45 Bottom surface 46 Side surface 51, 52, 56 Conductive film 53 Recessed portion 57 Second Wiring layer 62 convex

Claims (8)

A substrate,
An interlayer insulating film formed on the substrate;
A storage device having a resistance change element and a current suppression element each of which is formed at least in part in a first contact hole formed through the interlayer insulating film;
The variable resistance element has a variable resistance film, and is disposed above or below the first contact hole.
The current suppression element has a current suppression layer, and the current suppression layer is disposed at a position below or above the first contact hole and facing the resistance change film,
The resistance change film and the current suppression layer are electrically connected by a plug formed in the first contact hole, and the conductive layer in the plug is connected to the resistance change element and the current suppression element. A storage device comprising a part. The conductive layer in the plug includes a first electrode layer adjacent to the resistance change film and constituting the resistance change element, a second electrode layer adjacent to the current suppression layer and constituting the current suppression element, the first 2. The memory device according to claim 1, comprising at least three layers of a third electrode layer that connects one electrode layer and the second electrode layer. 3. A plurality of the plugs are formed in a matrix on the first interlayer insulating film,
Striped first wiring connected to the variable resistance layer formed above or below the plug;
A stripe-shaped second wiring connected to the current suppression layer formed below or above the plug;
Further comprising
The first wiring and the second wiring are arranged so as to intersect with each other, and the first wiring and the second wiring are connected via the plugs formed in a matrix. The storage device according to claim 1, wherein the storage device is characterized. The first electrode layer or the second electrode layer covers at least a bottom surface of the first contact hole and does not cover an upper portion of a side surface of the first contact hole. The storage device according to claim 3. The second electrode layer or the first electrode layer is formed in the first contact hole so as to cover an upper surface of the first contact hole and an upper portion of the side surface. Item 5. The storage device according to Item 4. 6. The third electrode layer is surrounded by the first electrode layer and the second electrode layer in the first contact hole. 6. The third electrode layer according to claim 5, wherein the third electrode layer is surrounded by the first electrode layer and the second electrode layer. The storage device described in 1. The third electrode layer is formed in a shape having a convex portion, and the convex portion is fitted into the concave portion of the first electrode layer or the second electrode layer. The storage device according to claim 5. The storage device according to claim 1, wherein the current suppressing element is an MIM diode, an MSM diode, or a varistor.

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