JP2009093791A - Recording device, recording method, reproducing device, reproducing method, recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that generated parity is extended by bit and it is embedded into information bits subjected to run-length-DSV-control, so that a ratio of parity to original information is increased remarkably, and an encoding rate is reduced. <P>SOLUTION: In an information word as an NRZI signal output from a NRZ-NRZI converting circuit 3, parity corresponding to an inner code of a turbo code or an LDPC code or the like is generated by an ECC parity generating circuit 4. After a signal composed of the information word and the parity is made, run-length-limit-DSV control same as that applied to the information word is performed for only parity by a parity part run-length encoding circuit 5. Thereby, the parity subjected to run-length-limit-DSV control is obtained while the information word is kept as it is. Thereby, in the parity in a signal recorded in an optical disk, increase of bits can be suppressed remarkably. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a recording apparatus, a reproducing apparatus, and a recording medium, and in particular, a recording apparatus that performs modulation suitable for recording a run-length limited code on a recording medium such as an optical disc, a recording method, and a recording in which the modulation signal is recorded The present invention relates to a reproducing apparatus, a reproducing method, and a recording medium recorded by a recording apparatus for reproducing an original information word from a run length limited code reproduced from the medium.

  In recent years, application of turbo codes, LDPC (Low Density Parity Check) codes, and the like has been studied at a practical level for the purpose of strengthening error correction as the density of optical disks increases (see, for example, Non-Patent Document 1). When this turbo code or LDPC code is applied to an optical disc, it is necessary to perform run length restriction / DSV (Digital Sum Variation) control in order to cope with the transmission path characteristics of the optical disc. However, it is difficult to directly calculate the parity having such characteristics.

  Therefore, conventionally, a recording apparatus, a reproducing apparatus, and a recording medium as described below have been proposed (for example, see Patent Document 1). The proposed device performs run-length modulation used on an optical disc for user data, generates parity such as turbo code or LDPC code, and expands the generated parity bit by bit. After being embedded in information bits that have already been subjected to run length / DSV control, they are recorded on an optical disc.

  During reproduction, turbo codes and LDPC codes are decoded through a PR (partial response) channel decoder and a MAP (maximum posterior probability) decoder. In the next-stage RLL decoder (demodulation corresponding to run-length modulation), conversion of likelihood information is not required.

Hongwei Song etal, "DC-Free (d, k) Constrained Low Density Parity Check (LDPC) Codes", IEEE 2002 Digest ThA.4, p.377-379 JP 2000-286709 A

  However, in the conventional recording apparatus, reproducing apparatus, and recording medium described in Patent Document 1, the generated parity is bit-extended on a bit-by-bit basis and embedded in information bits that have already undergone run-length / DSV control. The ratio of parity to original information is significantly increased. In Non-Patent Document 1, 1-bit parity is expanded to 7 bits. Therefore, in the conventional recording apparatus, reproducing apparatus, and recording medium, the coding rate is lowered, and the recording capacity for the information that should be recorded is reduced among the recording capacity of the optical disk.

  The present invention has been made in view of the above points. When turbo codes, LDPC codes, and the like are applied to an optical disc, the bits are expanded bit by bit, and information bits already subjected to run length / DSV control are included. It is an object of the present invention to provide a recording apparatus, a reproducing apparatus, and a recording medium that can significantly suppress an increase in parity bits as compared with an embedding method.

  Another object of the present invention is to provide a recording apparatus, a recording method, a reproducing apparatus, a reproducing method, which do not increase the circuit scale by using the same run length demodulation circuit without degrading the performance of run length / DSV. It is to provide a recording medium.

  In order to achieve the above object, a recording apparatus according to a first aspect of the present invention records a run-length limited code obtained by run-length modulation by run-length encoding on an information signal to be recorded on a recording medium. In the apparatus, first run-length encoding means that obtains a first run-length limited code obtained by performing run-length modulation on an information signal to be recorded while performing DSV control and adding a synchronization signal; A conversion means for converting the run-length limited code of NRZI into an NRZI signal, and a parity based on a predetermined error correction method based on an information word that is an NRZI signal output from the conversion means, and an information word and the generated parity A parity generation means for outputting a signal consisting of, and a signal consisting of an information word and a parity output from the parity generation means as inputs. Second run-length encoding means for performing the same run-length modulation and DSV control as those applied to the information word inputted only for the parity, and from the second run-length encoding means The output second run length limit code is recorded on a recording medium.

  In order to achieve the above object, the recording apparatus of the second invention records a run-length limited code obtained by run-length modulation by run-length encoding on an information signal to be recorded on a recording medium. A first run-length encoding unit that obtains a first run-length limited code obtained by performing run-length modulation on an information signal to be recorded while performing DSV control and adding a synchronization signal; Parity generation means for generating a parity based on a predetermined error correction method using the first run length limited code as an information word, and outputting a signal composed of the information word and the generated parity, and output from the parity generation means Receives a signal consisting of an information word and parity as input, and the same run as that applied to the input information word for only the input parity Second run-length encoding means for performing length modulation and DSV control, and conversion means for converting the second run-length limited code output from the second run-length encoding means into an NRZI signal. The NRZI signal output from the means is recorded on a recording medium.

  The recording devices of the first and second inventions generate a parity (turbo code or LDPC code) based on a predetermined error correction method based on an information word, and generate a signal composed of the information word and the generated parity. Among them, the same run length modulation and DSV control as those performed on the information word input only for the parity are performed, and the second run length limited code obtained thereby is recorded on the recording medium. Therefore, compared with the method of extending the bits in bit units and embedding them in the information bits that have already been subjected to run length / DSV control, the increase in the number of parity bits in the second run length limited code to be recorded is suppressed. be able to.

  In the first invention, by generating parity after converting the NRZ signal to the NRZI signal, the occurrence probability of 1 and 0 with respect to the original information signal can be made substantially equal, and the performance of the parity can be sufficiently exhibited. It becomes possible to do.

  In order to achieve the above object, the reproducing apparatus of the third invention reproduces a run length limited code composed of an information word recorded on a recording medium and a parity based on a predetermined error correction method, A reproduction device that decodes the reproduced signal after partial response equalization by an adaptive equalization circuit, and obtains binary data and likelihood information composed of information words and parity by viterbi decoding from the reproduced signal; First run-length decoding means for performing likelihood-length conversion of likelihood information and first run-length decoding means for performing run-length decoding on only the parity of the information word and parity output from the decoding means Error correction means that uses parity to perform error correction on the signal output from, and outputs an information word with the error corrected, and output from the error correction means An NRZI signal, which is an information word in which the error is corrected, is converted into an NRZ signal, and a run-length decoding is performed on the information word, which is an NRZ signal output from the conversion means, to obtain a decoded signal And second run-length decoding means.

  In order to achieve the above object, the reproducing apparatus of the fourth invention reproduces a run-length limited code composed of an information word recorded on a recording medium and a parity based on a predetermined error correction method, A reproduction device that decodes the reproduced signal after partial response equalization by an adaptive equalization circuit, and obtains binary data and likelihood information composed of information words and parity by viterbi decoding from the reproduced signal; The conversion means for converting the information word and parity, which are the NRZI signal output from the decoding means, into the NRZ signal, and the run length decoding is performed only on the parity among the information word and parity which is the NRZ signal output from the conversion means. A first run-length decoding unit that performs likelihood conversion of likelihood information, and a signal output from the first run-length decoding unit, Error correction means that performs error correction using the utility and outputs an information word in which the error is corrected, and a decoded signal that is subjected to run length decoding on the information word in which the error output from the error correction means is corrected And second run-length decoding means for obtaining.

  In the playback devices of the third and fourth inventions, the first run is applied to a run-length limited code that is reproduced from a recording medium and Viterbi-decoded and includes an information word and a parity based on a predetermined error correction method. Run-length decoding is performed on only the parity by the length decoding means, and an information word that has been run-length encoded (run-length modulated) before parity generation is obtained by performing error correction on the information word using the obtained parity. A decoded signal can be obtained by performing run length decoding on the information word by the second run length decoding means. Here, the first and second run-length decoding means can use a common circuit by using a decoding method corresponding to the same run-length modulation for both the information word and the parity.

  Further, in the present invention, run length modulation for an information word and parity is performed on a certain block, and then run length modulation for run length modulation is performed on the information word and parity of the next block. The continuity of state transition can be protected, and DSV control is also ensured.

  In order to achieve the above object, a recording medium according to a fifth aspect of the invention is a recording medium in which a run-length limited code obtained by run-length modulation by run-length encoding is recorded on an information signal to be recorded. The medium is recorded with the second run-length limit code generated by the recording apparatus according to the first aspect of the invention.

  Furthermore, in order to achieve the above object, the recording medium according to the sixth aspect of the invention, a recording medium on which a run-length limited code obtained by run-length modulation of the information signal to be recorded by run-length encoding is recorded The NRZI signal generated by the recording apparatus of the second invention is recorded.

  According to the present invention, an increase in the number of parity bits in a run-length limited code to be recorded is suppressed as compared with a method in which bits are expanded bit by bit and embedded in information bits that have already been subjected to run-length / DSV control. Therefore, it is possible to suppress the coding rate from being lowered to the minimum necessary level, and to achieve the performance of the original run length modulation with respect to the DC code property.

  Also, according to the recording apparatus of the present invention, by generating parity after converting the NRZ signal to the NRZI signal, the occurrence probability of 1 and 0 with respect to the original information signal can be made almost equal, and the performance of the parity is sufficient. It becomes possible to demonstrate to.

  Furthermore, according to the reproducing apparatus of the present invention, since the same run-length demodulation circuit is used for each of the first and second run-length decoding means, the circuit can be shared and the circuit scale can be increased. There is no effect.

  Next, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows a block diagram of a first embodiment of a recording apparatus according to the present invention. In the figure, input data (user data) which is digital information is supplied to a first ECC parity generation circuit 1 where a first ECC parity corresponding to an outer code such as a Reed-Solomon code is generated. The new data word is sent to the run-length encoding circuit 2 together with the original data string. The run-length encoding circuit 2 performs run-length restriction / DSV control in order to match the characteristics of an optical disc that is a recording medium (not shown). The run-length encoding circuit 2 adds a fixed pattern synchronization signal.

  The code string (run length limited code) output from the run-length encoding circuit 2 is, for example, an NRZ (Non Return to Zero) signal that is at a high level when the logic is “1” and at a low level when the logic is “0”. Yes, it is supplied to the NRZ-NRZI conversion circuit 3, where it is converted into an NRZI (Non Return to Zero Inverted) signal. As is well known, the NRZI signal is a signal that is modulated such that the level is inverted in the middle of the bit period of logic “1” and the level is held at the previous level in the bit period of logic “0”.

  The NRZI signal output from the NRZ-NRZI conversion circuit 3 is supplied to a second ECC parity generation circuit 4 where a second parity corresponding to an inner code such as a turbo code or an LDPC code is generated. . The new information word output from the second ECC parity generation circuit 4 and including the second parity and the original data string is supplied to the parity portion run-length encoding circuit 5, where only the second parity is provided. Are subjected to the same run length restriction / DSV control as that applied to the information bits. As a result, it is possible to achieve the performance of the original run-length coding (hereinafter also referred to as run-length modulation) itself, while suppressing the necessary minimum coding rate reduction.

  The signal output from the parity section run length encoding circuit 5 is supplied to the strategy circuit 6 where it is converted into a high frequency pulse for laser light modulation for recording the signal on the optical disk. This high-frequency pulse is supplied to an optical head (not shown) and supplied to a laser diode drive circuit, and the laser beam emitted from the laser diode is modulated to optically record a signal on the optical disk.

  In this embodiment, after run length coding (run length modulation) is performed on an information word and parity of a block, run length coding (run length modulation) is performed on the information word and parity of the next block. Thus, continuity of state transitions in run-length coding (run-length modulation) can be maintained, and DSV control can be ensured.

  Next, a description will be given of a first embodiment of a playback apparatus according to the present invention. FIG. 2 shows a block diagram of a first embodiment of a playback apparatus according to the present invention. An information word and parity reproduced by an optical head (not shown) from an optical disk (not shown) in which information words are recorded with high density by a known optical method by the recording apparatus of FIG. After being converted to a digital signal by being supplied to the A / D converter 11 and sampled by the system clock, the AGC / ATC circuit 12 performs automatic gain control (AGC) and 2 so that the amplitude becomes constant. Automatic threshold control (ATC) is performed for appropriately direct current (DC) control of the value comparison threshold.

  The output signal of the AGC / ATC circuit 12 is supplied to a resampling / DPLL (Digital Phase Locked Loop) 13. Note that the position where the A / D converter 11 is provided may be anywhere before the resampling / DPLL 13. The resampling / DPLL 13 is a digital PLL circuit (phase-locked loop circuit) in which a loop is completed in its own block. The re-sampling / DPLL 13 is for a reproduction signal sampled by the A / D converter 11 with a fixed system clock. Resampled data generated by resampling at a desired bit rate is generated and supplied to the adaptive equalization circuit 14.

  Here, resampling means obtaining the sampling data at the timing of the bit clock by performing decimation interpolation calculation from the data A / D converted at the timing of the system clock. Further, the resampling / DPLL 13 detects a zero cross of the resampling data having a phase of 0 ° and supplies 0 point information obtained thereby to the adaptive equalization circuit 14.

  The 0 point information indicates the point at which bit sampling data crosses the zero level in bit clock units. Further, the resampling / DPLL 13 sets the resampling timing, that is, the frequency and the phase so that it becomes 0 based on the value of the 180 ° phase resampling data corresponding to the zero cross point represented by the 0 point information. Lock it.

  The resampling / DPLL 13 is configured as shown in the block diagram of FIG. 3, for example. In this figure, an interpolator 131 receives an input digital signal from the AGC / ATC circuit 12 of FIG. 2 and a signal from a timing adjuster 134 described later as input signals, and data point phase information input from the timing adjuster 134. The phase point data value is estimated by interpolation from the bit clock and output. The output data value of the interpolator 131 is output to the adaptive equalization circuit 14 as resampling data and also supplied to the phase detector 132. The phase detector 132 detects the zero cross point from the input resampling data, and outputs the phase error using the data value at the zero cross point.

  The output phase error signal of the phase detector 132 is integrated by the loop filter 133 and then supplied to the timing adjuster 134, where the phase of the next data point of the output of the loop filter 133 is estimated, and this data point The phase information and the generated bit clock are supplied to the interpolator 131.

  Referring back to FIG. 2 again, the resampling data output from the resampling / DPLL 13 is supplied to the adaptive equalization circuit 14 composed of a transversal filter together with 0 point information, where PR (partial response) is provided. The characteristic is given and supplied to the Viterbi decoder 15. The Viterbi decoder 15 performs well-known Viterbi decoding (SOVA (Soft Output Viterbi Algorithm) or MAP decoding (maximum posterior probability decoding)) on the equalized reproduction waveform output from the adaptive equalization circuit 14 and binary The data (main) is decoded and output, and likelihood information is generated and supplied to the synchronization signal detection circuit 16.

  The synchronization signal detection circuit 16 detects the synchronization signal from the Viterbi-decoded signal (main signal and likelihood information), and uses the parity signal run-length decoding circuit (likelihood conversion) for the main signal and likelihood information from which the synchronization signal has been removed. ) 17 and run-length decoding is performed only on the second parity. At that time, likelihood conversion is performed on the likelihood information.

  The main signal (binary data) and likelihood information output from the parity part run length decoding circuit 17 is supplied to the ECC circuit 18, where a second parity (turbo code, LDPC code, etc.) corresponding to the inner code is supplied. ) Is subjected to error correction, the main signal is converted into an NRZ signal by the NRZI-NRZ conversion circuit 19. The NRZ signal is supplied to the run-length decoding circuit 20 and subjected to run-length decoding (hereinafter also referred to as run-length demodulation) corresponding to the run-length encoding circuit 2.

  The ECC circuit 21 performs error correction on the signal output from the run-length decoding circuit 20 using a first parity (such as a Reed-Solomon code) corresponding to the outer code in the signal, and the original information data Is output. The ECC circuit 21 receives the result of the parity check obtained by the ECC circuit 18 as erasure information, and also uses this to perform error correction.

  Next, features of the first embodiment will be described with reference to FIGS. 4, 5, 6 and 7. First, features corresponding to the recording apparatus of FIG. 1 will be described with reference to the explanatory diagram of FIG. 4 and the flowchart of FIG. In the ECC parity generation circuit 1, the information word 41 in FIG. 4 is generated as a first ECC parity using a Reed-Solomon code having the information word 41 as a generation element (step RS 0 in FIG. 5), and all of them are run-length codes. The first run-length modulation is performed in the conversion circuit 2, and the information word 42 in FIG. 4 is obtained (step RS1 in FIG. 5).

  Subsequently, after NRZ-NRZI conversion is performed (step RS2 in FIG. 5) and the information word 43 in FIG. 4 which is an NRZI signal is obtained, the ECC parity generation circuit 4 performs inner code such as turbo code or LDPC code. Is generated (step RS3 in FIG. 5). As a result, the ECC parity generation circuit 4 outputs a signal composed of the information word 44 and the parity 45 as shown in FIG.

  After that, in the first embodiment, the same run length restriction / DSV control as that applied to the information word 44 is performed only on the second parity 45 by the parity portion run length encoding circuit 5, that is, 2 run-length modulation is performed (step RS4 in FIG. 5). By this second run length modulation, the information word 44 remains as it is, and the parity 45 becomes the parity 46 subjected to the run length restriction / DSV control.

  As a result, when turbo codes, LDPC codes, and the like are applied to an optical disc, this embodiment is compared with a method in which bit expansion is performed in bit units and embedded in information bits that have already been subjected to run length / DSV control. Then, as shown by 46, the parity can greatly suppress the bit increase.

  Next, features corresponding to the playback apparatus of FIG. 2 will be described together with the explanatory diagram of FIG. 6 and the flowchart of FIG. As shown in FIG. 6, the reproduction signal is composed of an information word 44 and a parity 46, as in FIG. 4, and the second run-length modulation is performed only on the second parity 46 by the parity part run-length decoding circuit 17. Run length decoding (run length demodulation) is performed (step PS1 in FIG. 7). By run-length demodulation corresponding to the second run-length modulation, the parity 46 is demodulated into the parity 51 without changing the information word 44 as shown in FIG. The parity 51 corresponds to the parity 45 in FIG.

  Subsequently, the ECC circuit 18 demodulates the information word 44 corresponding to the turbo code / LDPC code using the parity 51 (step PS2 in FIG. 7), and the information word 52 shown in FIG. 6 is obtained. NRZI-NRZ conversion is performed (step PS3 in FIG. 7). Thereby, the information word 53 shown in FIG. 6 is obtained, and the run length demodulation corresponding to the first run length modulation is performed on the information word 53 (step PS4 in FIG. 7). Thereby, as shown in FIG. 6, the information word 54 is decoded. This information word 54 corresponds to the information word 41 in FIG.

  The feature of this embodiment is the second run-length modulation and the corresponding run-length demodulation. Here, as the second run-length modulation modulation method by the parity portion run-length encoding circuit 5, the known 1T system (T is the period of the channel clock; hereinafter the same) 1-7PP modulation or 2T system 8- There is a modulation method using table conversion such as 16 modulation. The 1-7PP modulation described above uses a table as shown in FIG. 8, and the number of “0” s between “1” and “1” is a minimum of 1 and a maximum of 7 (1,7 ) Modulation is performed in accordance with the RLL run-length restriction rule and while maintaining the same parity as that of the source bit string at the time of encoding.

  On the other hand, in the 8-16 modulation, the input signal shown in FIG. 9A is divided into 8 bits, and these are schematically shown in FIG. As shown, the modulation method obtains a 16-bit output signal. The numerical values in the leftmost column shown in FIG. 9 (C) are decimal values of an 8-bit input word, ranging from 0 to 255, of which 0 to 8 are shown. The column indicated by s (i + 1) indicates the next state after the state indicated by the value of the left column s (i).

  For example, when the initial state is “1” and 8-bit input words are input in the order of “8” and “2”, the first is the case where s (i) = 1 and the leftmost value is “8”. Therefore, a 16-bit value indicated by “8” and s (i) = 1 is output, and the next state is “3” as indicated by d1. Since the next input word is “2”, the leftmost value is “2”, and a 16-bit value indicated by s (i) = 3 indicating the state 3 is output, and s on the right side is output. Since (i + 1) is “1” as indicated by d2, the next state is “1”. Thereafter, similarly, modulation is performed using the table shown in FIG. 9C, whereby a modulated signal having a predetermined run length restriction rule is obtained.

  In the present embodiment, the number of parity bits is expanded by the second run-length modulation, which is 3/2 times in the 1-7PP modulation and 16/8 times in the 8-16 modulation. Therefore, the number of bits can be greatly reduced compared to 7 times the conventional example. As a result, this embodiment contributes to an improvement in recording density.

  Another feature of this embodiment is that parity generation such as turbo code / LDPC code is performed after NRZI conversion. By performing the NRZI conversion, the occurrence probabilities of 0 and 1 are almost equal, so the accuracy is improved in the calculation of likelihood information.

  Furthermore, as shown in the flowchart of FIG. 10, when the processing of step RS1 to step RS4 of FIG. 10 is performed in units of ECC blocks, and the processing of step RS1 to step RS4 of the next block is performed based on the result, The state transition of the run length modulation is optimized, and the DSV characteristics and the like can obtain the maximum effect.

  FIG. 11 shows a block diagram of a modification of the first embodiment of the recording apparatus of the present invention corresponding to this. In the figure, the same components as in FIG. In FIG. 11, the parity part run-length encoding circuit 5 ′ notifies the run-length encoding circuit 2 ′ of the result of the process in step RS3 in FIG. 10 and reflects the result in the processes in steps RS1 to RS4 of the next ECC block. .

  At this time, if the polarity changes in recording / reproduction, there is a problem in LDPC decoding at the time of reproduction, so the direction of the pit / land on the optical disc is determined. That is, the erased land on the optical disk (the state in which the medium is crystallized) totally reflects the laser light from the optical head, whereas the pits formed according to the information signal on the optical disk are generated by the laser light. Since it was cooled rapidly during recording and turned into an amorphous state, and the amount of reflected light was less than when irradiated with laser light during playback, the polarity of the signal from the pits obtained from photoelectric conversion of these reflected light and the land The signal polarity (pit / land direction) is determined in advance.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 12 shows a block diagram of a second embodiment of the recording apparatus according to the present invention. In the figure, the same components as those in FIG. In the first embodiment of FIG. 1, the NRZ-NRZI conversion circuit 3 is provided between the run-length encoding circuit 2 and the ECC parity generation circuit 4. However, in the second embodiment shown in FIG. This is characterized in that an NRZ-NRZI conversion circuit 7 is provided between the partial run length encoding circuit 5 and the strategy circuit 6.

  FIG. 13 shows a block diagram of a second embodiment of a playback apparatus according to the present invention. In the figure, the same components as those in FIG. In the first embodiment shown in FIG. 2, the NRZI-NRZ conversion circuit 19 is provided between the ECC circuit 18 and the run-length decoding circuit 20. However, in the second embodiment shown in FIG. 16 and the parity portion run length decoding circuit 17 is characterized in that an NRZI-NRZ conversion circuit 23 is provided.

  Next, features of the recording apparatus of the second embodiment shown in FIG. 12 will be described with reference to FIGS. In FIG. 14, the same parts as those in FIG. In the recording apparatus of the second embodiment shown in FIG. 12, as shown in FIG. 14, the ECC parity generation circuit 4 applies a turbo code or LDPC code to the information word 42 output from the run-length encoding circuit 2. A second parity corresponding to the inner code is generated (step RS2b in FIG. 15). As a result, the ECC parity generation circuit 4 outputs a signal composed of the information word 61 and the parity 62 as shown in FIG.

  Thereafter, in the second embodiment, the same run length restriction / DSV control as that applied to the information word 61 is performed only on the second parity 62 by the parity portion run length encoding circuit 5, that is, 2 run-length modulation is performed (step RS3b in FIG. 15). For this reason, as shown in FIG. 14, the information word 61 remains as it is, and the parity 62 becomes the parity 63 subjected to the run length restriction / DSV control.

  In the second embodiment, the information word 61 and the parity 63 are converted into the NRZI signal by the NRZ-NRZI conversion circuit 7, and the information word 64 and the parity 65 are output as shown in FIG. (Step RS4b in FIG. 15). As a result, in this embodiment, when turbo code, LDPC code, etc. are applied to an optical disc, the bit is expanded bit by bit, and compared with a method of embedding it in information bits already subjected to run length / DSV control. As shown by 65, the parity can greatly suppress the bit increase.

  Next, features of the second embodiment of the reproducing apparatus according to the present invention shown in FIG. 13 will be described with reference to FIGS. In FIG. 16, the same parts as those in FIG. 14 are denoted by the same reference numerals. In the second embodiment of the playback apparatus according to the present invention shown in FIG. 13, the playback signal output from the synchronizing signal detection circuit 16 in FIG. 13 is the same as in FIG. First, the NRZI-NRZ conversion circuit 23 modulates the NRZ signal (step PS1b in FIG. 17). As a result, the NRZI-NRZ conversion circuit 23 outputs an information word 66 and a parity 67, which are NRZ signals, as shown in FIG.

  Subsequently, the information word 66 and the parity 67 are subjected to run length demodulation corresponding to the second run length modulation, that is, only the second parity 67 by the parity part run length decoding circuit 17 of FIG. Run-length demodulation is performed (step PS2b in FIG. 17). By run-length demodulation corresponding to the second run-length modulation, the parity 67 is demodulated into the parity 68 without changing the information word 66 as shown in FIG. The parity 68 corresponds to the parity 62 in FIG.

  Subsequently, the ECC circuit 18 in FIG. 13 demodulates the information word 66 corresponding to the turbo code / LDPC code using the parity 68 (step PS3b in FIG. 17), and the information word 69 shown in FIG. 16 is obtained. Thereafter, run-length demodulation corresponding to the first run-length modulation is performed by the run-length decoding circuit 20 in FIG. 13 (step PS4b in FIG. 17). Thereby, as shown in FIG. 16, the information word 70 is decoded. This information word 70 corresponds to the information word 41 in FIG.

  Similar to the first embodiment, this embodiment is also characterized by the second run-length modulation / decoding, which increases the number of parity bits. For example, the known 1T system 1-7PP In modulation and the like, it is 3/2 times, and in 2T system 8-16 modulation, it is 16/8 times, and the number of bits can be significantly reduced as compared with 7 times of the conventional example, thereby contributing to improvement in density.

  As shown in the flowchart of FIG. 18, the processes of step RS1b to step RS3b of FIG. 18 are performed in units of ECC blocks, and the process of steps RS1b to RS3b of the next ECC block is performed based on the result. The state transition of the length modulation is optimized, and it is possible to obtain the maximum effect on the DSV characteristics and the like.

  FIG. 19 shows a block diagram of a modified example of the second embodiment of the recording apparatus of the present invention corresponding to this. In the figure, the same components as those in FIG. In FIG. 19, the parity part run-length encoding circuit 5 ′ notifies the run-length encoding circuit 2 ′ of the result of the process in step RS3b in FIG. 18 and reflects the result in the processes in steps RS1b to RS3b of the next block. At this time, if the polarity changes in recording / reproduction, there is a problem in LDPC decoding at the time of reproduction, so the direction of the pit / land on the optical disc is determined.

(Modification of playback device)
Incidentally, in the first and second embodiments of the reproducing apparatus according to the present invention shown in FIGS. 2 and 13, the resampling DPLL 13 is used, but the present invention is not limited to this, and FIG. A playback device having the configuration shown in the block diagram of 20 is also possible. FIG. 20 shows a block diagram of a modification of the main part of the reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 2 or FIG.

  In the modification shown in FIG. 20, a clock is generated from the signal output from the AGC / ATC circuit 12 by the PLL circuit 25 having a known configuration, and the generated clock is supplied to the A / D converter 11 as a sampling clock. The input reproduction RF signal is sampled. That is, the reproduced RF signal sampled and output from the A / D converter 11 is supplied to the AGC / ATC circuit 12, and the level is kept constant and the DC level is controlled. At the same time, it is supplied to the PLL circuit 25.

  The PLL circuit 25 performs edge detection and phase error extraction on the output signal of the AGC / ATC circuit 12 and the output signal of the internal voltage controlled oscillator (VCO) by an internal phase detector, and based on the extracted phase error, The output signal frequency of the VCO is variably controlled, and the output signal of the VCO is supplied to the A / D converter 11 as a clock through a loop filter and is also fed back to the phase detector. Even with such a configuration, the same effect as that of the reproducing apparatus having the configuration shown in FIG. 2 or 13 can be obtained.

1 is a block diagram of a first embodiment of a recording apparatus of the present invention. 1 is a block diagram of a first embodiment of a playback apparatus of the present invention. It is a block diagram of an example of resampling and DPLL in FIG. It is a figure explaining the characteristic of 1st Embodiment of this invention recording device. It is a flowchart explaining 1st Embodiment of this invention recording device. It is a figure explaining the characteristic of 1st Embodiment of this invention reproducing | regenerating apparatus. It is a flowchart explaining 1st Embodiment of this invention reproducing | regenerating apparatus. It is a figure which shows a part of 1-7PP table. It is a figure which shows a part of EFMplus table. It is a flowchart explaining the modification of 1st Embodiment of this invention recording device. It is a block diagram of the modification of 1st Embodiment of this invention recording device. It is a block diagram of 2nd Embodiment of this invention recording device. It is a block diagram of 2nd Embodiment of this invention reproducing | regenerating apparatus. It is a figure explaining the characteristic of 2nd Embodiment of this invention recording device. It is a flowchart explaining 2nd Embodiment of this invention recording device. It is a figure explaining the characteristic of 2nd Embodiment of this invention reproducing | regenerating apparatus. It is a flowchart explaining 2nd Embodiment of this invention reproducing | regenerating apparatus. It is a flowchart explaining the modification of 2nd Embodiment of this invention recording device. It is a block diagram of the modification of 2nd Embodiment of this invention recording device. It is a block diagram of the modification of the principal part of the reproducing | regenerating apparatus which becomes this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ECC parity generation circuit 2, 2 'run length encoding circuit 3, 7 NRZ-NRZI conversion circuit 4 ECC parity generation circuit 5, 5' Parity part run length encoding circuit 6 Strategy circuit 11 A / D converter 12 AGC / ATC circuit 13 Resampling / DPLL
14 Adaptive equalization circuit 15 Viterbi decoder (SOVA, MAP decoding, etc.)
16 Sync signal detection circuit 17 Parity section run length decoding circuit 18, 21 ECC circuit 19, 23 NRZI-NRZ conversion circuit 20 Run length decoding circuit 25 PLL
131 Interpolator 132 Phase Detector 133 Loop Filter 134 Timing Adjuster

Claims (10)

In a recording apparatus for recording a run-length limited code obtained by run-length modulation by run-length encoding on an information signal to be recorded on a recording medium,
First ECC parity generating means for generating a first ECC parity corresponding to an outer code for the information signal to be recorded and outputting the first parity together with the information signal to be recorded;
First run-length encoding means for performing run-length modulation on the information signal to be recorded while performing DSV control in units of ECC blocks, and outputting a first run-length limited code to which a synchronization signal is added;
Conversion means for converting the first run length limited code into an NRZI signal;
Based on the information word that is the NRZI signal output from the conversion means, a second ECC parity is generated based on a predetermined inner code error correction method, and the signal consists of the information word and the second ECC parity. Second ECC parity generation means for outputting
A signal composed of the information word output from the second ECC parity generation means and the second ECC parity is received as an input, and the first run is applied only to the input second ECC parity. The same run length modulation and DSV control as those performed on the information word input by the length encoding means are performed in units of ECC blocks, and a second run length limited code is encoded in the first run length encoding. Second run length encoding means for supplying to the means;
Recording means for recording the second run length limited code output from the second run length encoding means on the recording medium;
Have
The first run length encoding means inputs a result generated in the process of generating the second run length limited code of the previous ECC block from the second run length encoding means, and The information signal to be recorded is run-length modulated while performing DSV control in units of ECC blocks, and a first run-length limit code to which a synchronization signal is added is output.
A recording apparatus. In a recording apparatus for recording a run-length limited code obtained by run-length modulation by run-length encoding on an information signal to be recorded on a recording medium,
First ECC parity generating means for generating a first ECC parity corresponding to an outer code for the information signal to be recorded and outputting the first parity together with the information signal to be recorded;
First run-length encoding means for performing run-length modulation on the information signal to be recorded while performing DSV control in units of ECC blocks, and outputting a first run-length limited code to which a synchronization signal is added;
A second ECC parity is generated based on a predetermined inner code error correction method based on the first run-length limited code, and a signal composed of the information word and the second ECC parity is output. ECC parity generation means of
A signal composed of the information word output from the second ECC parity generation means and the second ECC parity is received as an input, and the first run is applied only to the input second ECC parity. The same run length modulation and DSV control as those performed on the information word input by the length encoding means are performed in units of ECC blocks, and a second run length limited code is encoded in the first run length encoding. Second run length encoding means for supplying to the means;
Conversion means for converting the second run length limited code output from the second run length encoding means into an NRZI signal;
Recording means for recording the NRZI signal output from the conversion means on the recording medium;
Have
The first run-length encoding means inputs a result generated in the process of generating the second run-length limited code of the previous ECC block from the second run-length encoding means, The next information signal to be recorded is run-length modulated while performing DSV control in units of ECC blocks, and outputs a first run-length limit code to which a synchronization signal is added.
A recording apparatus. In a recording medium on which a run-length limited code obtained by run-length modulation by run-length encoding is recorded for an information signal to be recorded,
2. A recording medium on which the second run-length limit code generated by the recording apparatus according to claim 1 is recorded. In a recording medium on which a run-length limited code obtained by run-length modulation by run-length encoding is recorded for an information signal to be recorded,
A recording medium on which the NRZI signal generated by the recording apparatus according to claim 2 is recorded. A first ECC parity generation step of generating a first ECC parity corresponding to an outer code for the information signal to be recorded and outputting the first parity together with the information signal to be recorded;
A first run-length encoding step that performs run-length modulation on the information signal to be recorded while performing DSV control in units of ECC blocks, and outputs a first run-length limited code to which a synchronization signal is added;
An NRZI signal converting step of converting the first run length limited code into an NRZI signal;
A second ECC parity is generated based on a predetermined inner code error correction method based on the information word that is the NRZI signal, and a signal composed of the information word and the second ECC parity is output. ECC parity generation step;
A signal composed of the information word output by the second ECC parity generation step and the second ECC parity is received as an input, and only the first ECC parity is input to the first run. The same run length modulation and DSV control as those applied to the information word input in the length encoding step are performed in units of ECC blocks and output as a second run length limited code. A second run-length encoding step for supplying the result of the run-length modulation and DSV control applied only to ECC parity to the first run-length encoding step;
A recording step of recording the second run-length limited code output from the second run-length encoding step on the recording medium;
Have
In the first run-length encoding step, the run-length modulation and DSV control performed only on the second ECC parity of the previous ECC block output by the second run-length encoding step. The result is input, and the first information to be recorded is run-length modulated while performing DSV control in units of ECC blocks, and a first run-length limit code to which a synchronization signal is added is output.
And a recording method. A first ECC parity generation step of generating a first ECC parity corresponding to an outer code for the information signal to be recorded and outputting the first parity together with the information signal to be recorded;
A first run-length encoding step that performs run-length modulation on the information signal to be recorded while performing DSV control in units of ECC blocks, and outputs a first run-length limited code to which a synchronization signal is added;
A second ECC parity is generated based on a predetermined inner code error correction method based on the first run-length limited code, and a signal composed of the information word and the second ECC parity is output. ECC parity generation step of
A signal composed of the information word output by the second ECC parity generation step and the second ECC parity is received as an input, and only the first ECC parity is input to the first run. The same run length modulation and DSV control as those applied to the information word input in the length encoding step are performed in units of ECC blocks and output as a second run length limited code. A second run-length encoding step for supplying the result of the run-length modulation and DSV control applied only to ECC parity to the first run-length encoding step;
An NRZI conversion step of converting the second run length limited code output by the second run length encoding step into an NRZI signal;
A recording step of recording the NRZI signal output by the NRZI conversion step on the recording medium;
Have
In the first run-length encoding step, the run-length modulation and DSV control performed only on the second ECC parity of the previous ECC block output by the second run-length encoding step. The result is input, and the first information to be recorded is run-length modulated while performing DSV control in units of ECC blocks, and a first run-length limit code to which a synchronization signal is added is output.
And a recording method. Of signals composed of a first information word and a first parity based on a predetermined error correction method, the same as that applied to the first information word for only the first parity A run-length limited code consisting of the second parity obtained by the run-length modulation and the DSV control and the first information word is reproduced from the recording medium, and the playback signal is subjected to Viterbi by SOVA or maximum a posteriori probability decoding. Viterbi decoding means for outputting the first information word, the second parity, and the first likelihood information using decoding;
The first information word from which the synchronization signal is removed by detecting a synchronization signal from the first information word, the second parity, and the first likelihood information output from the Viterbi decoding means; Synchronization detection means for outputting a parity of 2 and first likelihood information;
Run-length decoding is performed only on the second parity to output the first parity and the first information word, and a likelihood conversion of the first likelihood information is performed to perform a second conversion. First run length decoding means for outputting likelihood information;
The first information word, the decoded first parity, and the second likelihood information are received as inputs, error correction is performed using the decoded first parity, and a second information word is output. And first error correction means for outputting erasure information;
Conversion means for converting the second information word output from the first error correction means into an NRZ signal as an NRZI signal and outputting a third information word;
Second run length decoding means for performing run length decoding on the third information word and outputting a fourth information word which is a decoded signal of the first information word;
A second information word that receives the fourth information word and the erasure information as input, performs error correction using the parity included in the fourth information word and the erasure information, and outputs a fifth information word; And an error correction means. Of signals composed of a first information word and a first parity based on a predetermined error correction method, the same as that applied to the first information word for only the first parity The second information word and the second information word obtained by NRZI conversion using a run length limited code consisting of the second parity obtained by performing the run length modulation and the DSV control and the first information word as an NRZ signal. A run-length limited code consisting of three parity bits is reproduced from the recording medium, and the second information word, the third parity, and the first parity code are read from the reproduced signal using SOVA or Viterbi decoding by maximum a posteriori probability decoding. Viterbi decoding means for outputting the likelihood information of
The second information word from which the synchronization signal is removed by detecting a synchronization signal from the second information word, the third parity, and the first likelihood information output from the Viterbi decoding means, Synchronization detection means for outputting parity of 3 and first likelihood information;
NRZ conversion means for converting the second information word and the third parity output from the synchronization detection means into an NRZ signal as an NRZI signal and outputting the third information word and the fourth parity; ,
Run-length decoding is performed only on the fourth parity to output the first parity and the third information word, and likelihood conversion of the first likelihood information is performed. First run-length decoding means for outputting likelihood information of 2;
The third information word, the decoded first parity, and the second likelihood information are received as inputs, error correction is performed using the decoded first parity, and a fourth information word is output. And first error correction means for outputting erasure information;
Second run-length decoding means for performing run-length decoding on the fourth information word and outputting a fifth information word that is a decoded signal of the first information word;
A second information word which receives the fifth information word and the erasure information as input, performs error correction using the parity included in the fifth information word and the erasure information, and outputs a sixth information word; And an error correction means. Of signals composed of a first information word and a first parity based on a predetermined error correction method, the same as that applied to the first information word for only the first parity A run-length limited code consisting of the second parity obtained by the run-length modulation and the DSV control and the first information word is reproduced from the recording medium, and the reproduced signal is subjected to Viterbi by SOVA or maximum a posteriori probability decoding. Viterbi decoding step of outputting the first information word, the second parity, and the first likelihood information using decoding;
The first information word from which the synchronization signal is removed by detecting a synchronization signal from the first information word, the second parity, and the first likelihood information output by the Viterbi decoding step, A synchronization detection step of outputting parity of 2 and first likelihood information;
Run-length decoding is performed only on the second parity to output the first parity and the first information word, and a likelihood conversion of the first likelihood information is performed to perform a second conversion. A first run length decoding step for outputting likelihood information;
The first information word, the decoded first parity, and the second likelihood information are received as inputs, error correction is performed using the decoded first parity, and a second information word is output. And a first error correction step for outputting erasure information;
A conversion step of converting the second information word output by the first error correction step into an NRZ signal as an NRZI signal and outputting a third information word;
A second run-length decoding step that performs run-length decoding on the third information word and outputs a fourth information word that is a decoded signal of the first information word;
A second information word that receives the fourth information word and the erasure information as input, performs error correction using the parity included in the fourth information word and the erasure information, and outputs a fifth information word; And an error correction step. Of signals composed of a first information word and a first parity based on a predetermined error correction method, the same as that applied to the first information word for only the first parity The second information word and the second information word obtained by NRZI conversion using a run length limited code consisting of the second parity obtained by performing the run length modulation and the DSV control and the first information word as an NRZ signal. A run-length limited code consisting of three parity bits is reproduced from the recording medium, and the second information word, the third parity, and the first parity code are read from the reproduced signal using SOVA or Viterbi decoding by maximum a posteriori probability decoding. Viterbi decoding step for outputting likelihood information of
The second information word from which the synchronization signal is removed by detecting a synchronization signal from the second information word, the third parity, and the first likelihood information output from the Viterbi decoding step; A synchronization detection step of outputting 3 parity and first likelihood information;
An NRZ conversion step of converting the second information word and the third parity output by the synchronization detection step into an NRZ signal as an NRZI signal, and outputting the third information word and the fourth parity; ,
Run-length decoding is performed only on the fourth parity to output the first parity and the third information word, and likelihood conversion of the first likelihood information is performed. A first run-length decoding step of outputting likelihood information of 2;
The third information word, the decoded first parity, and the second likelihood information are received as inputs, error correction is performed using the decoded first parity, and a fourth information word is output. And a first error correction step for outputting erasure information;
A second run-length decoding step of performing a run-length decoding on the fourth information word and outputting a fifth information word that is a decoded signal of the first information word;
A second information word which receives the fifth information word and the erasure information as input, performs error correction using the parity included in the fifth information word and the erasure information, and outputs a sixth information word; Error correction steps,
A playback apparatus comprising:

Images