JP2009093014A - Temperature controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a temperature controller equipped with an inexpensive second safety circuit that detects abnormality of a CPU and maintains an off-state of a fixing heater in addition to a safety circuit by hardware in which a CPU is not interposed. <P>SOLUTION: The temperature controller 9 is equipped with: a temperature detection part 23 that detects fixing temperature; the CPU 41 that outputs a heater control signal HC for driving and controlling the fixing heater 21 so that the fixing temperature may be target temperature; the safety circuit 304 that forcibly stops power supply to the fixing heater 21; a pulse generation circuit 45 that generates an edge signal ES from a pulse signal SLCT in a predetermined cycle output by the CPU 41; a timer circuit 49 that outputs a forcible stop signal FS when predetermined time elapses after output voltage from the pulse generation circuit 45 is input; and a gate circuit that turns off the fixing heater 21 according to the output signal from the timer circuit 49 or the heater control signal HC. The one cycle of the pulse signal is set to be shorter than the predetermined time. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a temperature control device incorporated in an image forming apparatus having a thermal fixing device such as a copying machine or a printer, and relates to a temperature detection unit that detects a fixing temperature, and the fixing temperature detected by the temperature detection unit is a target temperature. A temperature that includes a CPU that outputs a heater control signal for driving and controlling the fixing heater, and a safety circuit that forcibly stops power supply to the fixing heater when the fixing temperature reaches an abnormal overheat temperature. The present invention relates to a control device.

  An image forming apparatus adopting an electrophotographic system includes a fixing heater that is driven and controlled by a heater control signal output from a control unit having a CPU, and a fixing heater in order to melt and fix the toner image on a sheet. A fixing device including an internal fixing roller and a pressure roller pressed against the fixing roller is incorporated.

  The fixing roller is controlled to a predetermined target temperature by a fixing heater that is energized and controlled by the control unit. However, if the energization state of the fixing heater is maintained due to an abnormality of the control unit, the fixing roller is overheated to an abnormally high temperature. Since there is a possibility of causing damage to the apparatus, conventionally, a technique for avoiding an abnormal overheating state by a hardware circuit not including a control unit has been proposed.

  For example, there is a safety circuit that connects a thermo switch for monitoring the fixing temperature in series with the energization line to the fixing heater, and forcibly cuts off the power supply to the fixing heater when an abnormal overheat temperature is detected by the thermo switch. Yes.

  However, when a thermal fuse is used as the thermoswitch, if the thermal fuse is blown due to abnormal overheating temperature, the heater is energized unless the thermal fuse is replaced, but the thermal fuse is blown. At a high temperature, there is a risk that the fixing roller, the pressure roller, and the devices and resin members installed around the fixing device may be damaged by high heat.

  Further, when a bimetal type switch is adopted as the thermo switch, the thermo switch is closed and the fixing heater is energized again when the fixing temperature becomes equal to or lower than the abnormal overheating temperature. Therefore, as shown in FIG. However, the fixing roller, the pressure roller, and the devices and resin members installed around the fixing device may be damaged by high heat, or may be distorted or deformed.

  Even when a comparator circuit is provided that turns off the control signal to the fixing heater when the temperature detected by a temperature sensor such as a thermistor provided for controlling the fixing temperature is higher than the abnormal overheating temperature, the fixing temperature is abnormally overheated. It was maintained around the temperature and had the same disadvantages.

  Therefore, in Patent Document 1, the temperature of the fixing heater is monitored, the energization control of the fixing heater and the power on / off control of the power system are performed, and when an abnormality in the fixing heater temperature is detected when the fixing heater is energized, the fixing heater is detected. A single MPU that prohibits energization of the power supply and a power system power supply that is turned off, and an excessive temperature rise that detects an excessive increase in the fixing heater temperature and forcibly turns off the power system power according to the temperature overheating condition Even if the temperature monitoring means of the MPU does not operate normally even if the temperature of the fixing heater rises due to abnormality of the fixing heater control means, etc., the power system is detected by the overtemperature detection / control means. An image forming apparatus characterized by forcibly turning off a power supply has been proposed.

  Specifically, the overtemperature detection / control means includes a watchdog timer circuit that operates when a predetermined time elapses when the temperature of the fixing heater detected by the thermistor is abnormally high, a D-type flip-flop that latches the output signal, and a flip-flop And a relay circuit that cuts off the power supply line to the fixing heater in response to the output signal.

However, in the above-described over-temperature detection / control means, the flip-flop is reset by the reset signal output from the MPU after the abnormality is detected, so that if an abnormality occurs in the MPU and an incorrect reset signal is output, the fixing is performed. There was a possibility that energization to the heater could not be prevented. Further, in order to cope with a malfunction of the flip-flop due to noise or the like, it is necessary to determine whether or not the malfunction occurs and to output a reset signal, so that there is a problem that the control load on the MPU increases.
Japanese Patent Laid-Open No. 10-307514

  In view of the above-described problems, the object of the present invention is to provide an inexpensive second safety circuit that detects an abnormality of the CPU and maintains the fixing heater in an OFF state in addition to a hardware safety circuit that does not involve a CPU. It is in providing a temperature control device.

  In order to achieve the above-mentioned object, a first characteristic configuration of the temperature control device according to the present invention includes a temperature detection unit for detecting a fixing temperature and the temperature detection as described in claim 1 of the document of the claims. A CPU that outputs a heater control signal for driving and controlling the fixing heater so that the fixing temperature detected by the unit reaches a target temperature, and forcibly stops power supply to the fixing heater when the fixing temperature reaches an abnormal overheat temperature A temperature control device configured with a safety circuit configured to generate an edge signal from a pulse signal of a predetermined period output from the CPU, and after an output voltage of the pulse generation circuit is input A timer circuit that outputs a forced stop signal regardless of the heater control signal when a predetermined time elapses, and the fixing heater by the output signal of the timer circuit or the heater control signal A gate circuit for turning off the motor, one cycle of the pulse signal is in a point that is set to be shorter than the predetermined time.

  The pulse generation circuit starts from the rising edge or the falling edge of the pulse signal of a predetermined period (hereinafter referred to as “first period” in the description of “Means for Solving Problems”) output from the CPU. In order to generate a signal, the period of the edge signal (hereinafter referred to as “second period” in the description of “means for solving the problem”) is equal to or less than the first period. The first period is set shorter than a predetermined time from when the power supply voltage is applied until the forced stop signal is output from the timer circuit. Therefore, the second period is shorter than the predetermined time.

  The timer circuit outputs a forced stop signal when a predetermined time elapses after the edge signal as the output voltage of the pulse generation circuit is input as the power supply voltage. However, as described above, the second period is shorter than the predetermined time, Since the output voltage is interrupted every second period before the time elapses, the timer circuit does not output a forced stop signal.

  However, if an abnormality such as CPU runaway or output port latch-up occurs, the pulse signal is fixed at a high level or a low level, and the pulse generation circuit cannot generate an edge signal. Therefore, when a predetermined time elapses after the output voltage of the pulse generation circuit is input, a forced stop signal is output from the timer circuit, and the energization to the fixing heater is forcibly turned off by the gate circuit.

  According to the above-described configuration, the problem that the temperature of the fixing roller is maintained before and after the abnormal overheat temperature detected by the safety circuit in the event of an abnormality such as CPU runaway is eliminated. Such a circuit has a small number of parts and can be constructed very inexpensively.

  In the second characteristic configuration, as described in claim 2, in addition to the first characteristic configuration described above, the timer circuit includes an integration circuit that operates when a power supply voltage is applied; The output circuit is composed of a logic circuit whose output level is inverted when the predetermined time elapses, and the output voltage of the pulse generation circuit is input to the timer circuit as a power supply voltage.

  When the power supply voltage is applied, the output voltage of the integration circuit increases based on a predetermined integration constant, and when a predetermined time determined in relation to the integration constant elapses, the output voltage exceeds a predetermined threshold value. When the output voltage exceeds a predetermined threshold, a signal whose output level is inverted is output from the logic circuit.

  By the way, an edge signal as an output voltage of the pulse generation circuit is applied to the integration circuit as a power supply voltage. When the CPU is operating normally, the power supply voltage applied to the integration circuit is cut off every second period, and the output voltage of the integration circuit decreases every second period shorter than the predetermined time. Therefore, the output level of the logic circuit does not rise to a predetermined threshold value at which it is inverted.

  However, when an abnormal state such as a CPU runaway occurs, the power supply voltage of a constant voltage value is applied to the integration circuit without being cut off. Therefore, when a predetermined time elapses after the power supply voltage is applied, the output voltage of the integration circuit is The output level rises to a predetermined threshold value that is inverted, and a signal whose output level is inverted is output from the logic circuit.

  The integration circuit can be constructed at a low cost by combining a few components such as a resistor and a capacitor, for example, so that an inexpensive temperature control device can be realized.

  In the third feature configuration, as described in claim 3, in addition to the second feature configuration described above, the output level of the timer circuit is reversed when a predetermined time elapses after the power supply voltage is applied. This is because it is composed of a reset IC.

  The reset IC is configured to invert the level and output a signal when a predetermined time elapses after the power supply voltage is applied.

  Since the edge signal as the output voltage of the pulse generation circuit is applied to the reset IC as the power supply voltage, the reset IC is applied every second period when the applied power supply voltage is cut off when the CPU is operating normally. Is reset, and a signal whose level is inverted is not output from the reset IC.

  However, in the event of abnormalities such as CPU runaway, the power supply voltage of a constant voltage value is applied to the reset IC without being interrupted. Therefore, when a predetermined time elapses after the power supply voltage is applied, a signal whose level is inverted is output from the reset IC. Is output.

  According to the above configuration, an inexpensive temperature control device can be realized by using an inexpensive reset IC that is mass-produced.

  In the fourth feature configuration, in addition to the first feature configuration described above, the timer circuit includes a one-shot multi-function in which the output voltage of the pulse generation circuit is input as a trigger voltage. It consists of a vibrator.

  The one-shot multivibrator is configured to output the signal at the original level after inverting the level for a predetermined time when the trigger signal is input, and then outputting the signal at the original level. The edge signal is input as the trigger signal, that is, the output voltage of the pulse generation circuit is input as the trigger voltage.

  When the CPU is operating normally, a level-inverted signal is output from the one-shot multivibrator every second cycle, which is the cycle of the edge signal. Since no signal is generated, the level-inverted signal is not output from the one-shot multivibrator.

  In other words, the timer circuit can be configured using the characteristics of the one-shot multivibrator, and the above-described configuration realizes an inexpensive temperature control device by using an inexpensive one-shot multivibrator that is mass-produced. it can.

  In the fifth feature configuration, in addition to the first feature configuration described above, the timer circuit includes an integration circuit that operates when a power supply voltage is applied; and It is constituted by a logic circuit whose output level is inverted when the predetermined time has passed based on an output signal, and the integrating circuit is discharged by the output voltage of the pulse generation circuit.

  When the power supply voltage is applied, the output voltage of the integration circuit increases based on a predetermined integration constant, and when a predetermined time determined in relation to the integration constant elapses, the output voltage exceeds a predetermined threshold value. When the output voltage exceeds a predetermined threshold, a signal whose output level is inverted is output from the logic circuit.

  The integration circuit is configured to be discharged by the output voltage when the edge signal output from the pulse generation circuit is input as the output voltage of the pulse generation circuit. Therefore, when the CPU is operating normally, the integration circuit is discharged every second period shorter than the predetermined time, so that the output voltage does not rise to the predetermined threshold value, and the output level is inverted from the logic circuit. No signal is output.

  However, when an abnormal state such as a CPU runaway occurs, an edge signal is not generated and the integrating circuit is not discharged. Therefore, when a predetermined time elapses after the power supply voltage is applied, the output voltage of the integrating circuit is a predetermined level at which the output level of the logic circuit is inverted A signal whose output level is inverted is output from the logic circuit.

  The integration circuit can be constructed at a low cost by combining a few components such as a resistor and a capacitor, for example, so that an inexpensive temperature control device can be realized.

  In the sixth feature configuration, as described in claim 6, in addition to any of the first to fifth feature configurations described above, the pulse signal of the predetermined period is polled to a slave CPU subordinate to the CPU. The point is the select signal.

  A CPU configured to communicate with slave CPUs subordinate to each other in a polling system outputs a polling select signal that switches between a high level and a low level at a predetermined cycle in order to identify a slave CPU to be communicated. Each slave CPU determines whether or not it is a communication target based on the signal level of the signal, and the slave CPU that is the communication target communicates with the CPU. If the communication time between the CPU and one slave CPU becomes long, the control of other slave CPUs may be hindered, so the period of the polling select signal is relatively short.

  By the way, one cycle of the pulse signal input to the pulse generation circuit that generates the edge signal is shorter than a predetermined time from when the output voltage of the pulse generation circuit is input until the forced stop signal is output from the timer circuit. There must be.

  Therefore, according to the above-described configuration, the polling select signal is suitable as a pulse signal having a predetermined period to be input to the pulse generation circuit, and is also used as a signal used for edge signal generation. No need to set.

  As described above, according to the present invention, in addition to a hardware safety circuit that does not involve a CPU, a temperature provided with an inexpensive second safety circuit that detects an abnormality of the CPU and maintains an OFF state of the fixing heater. A control device can be provided.

  Hereinafter, a color printer which is an example of an image forming apparatus including the temperature control device of the present invention will be described.

  As shown in FIG. 2, a color printer 100 that employs an electrophotographic method is input from an operation unit 110 on which operation keys for inputting a liquid crystal screen, printing conditions, and the like are arranged, and a personal computer or the like via a network or the like. The toner image formed by the image forming unit 120 on the sheet conveyed from the sheet storage unit 500 including the image forming unit 120 that forms a toner image based on the image data and the sheet feeding control unit 501 that controls sheet conveyance and the like. A transfer unit 130 that transfers the toner image, a functional block such as a fixing unit 200 that melts and fixes the toner image on the paper, a control unit 400 that controls these functional blocks to execute a predetermined image forming process, and a control unit 400 and a power supply unit 300 that supplies necessary power to the paper feed control unit 501 and the like.

  The image forming unit 120 forms an electrostatic latent image by exposing the surface of the photoconductor by scanning a laser beam based on the input image data, and a charging device that uniformly charges the surface of the photoconductor. A photoconductor unit including an exposure device and a developing device that visualizes the formed electrostatic latent image as a toner image is provided for each of the M, C, Y, and K toner colors.

  The transfer unit 130 includes an intermediate transfer belt 132 that superimposes and supports toner images formed by the photosensitive units of the image forming unit 120, a support roller 131 that rotatably supports the intermediate transfer belt 132, and an intermediate transfer belt 132. The image forming apparatus includes a transfer roller 133 that transfers the carried toner image onto a sheet conveyed from the sheet storage unit 500, a blade 134 that removes residual toner on the intermediate transfer belt 132, and the like.

  As shown in FIG. 3, the fixing unit 200 includes a fixing roller 20 in which a fixing heater 21 is housed, and a pressure roller 22 pressed against the fixing roller 20, and serves as a temperature detection unit that detects a fixing temperature on the fixing roller 20. Thermistors 23 are arranged in contact with each other.

  As shown in FIG. 1, the thermistor 23 is connected in series with the resistor R 24, and the divided voltage value of the DC voltage Vdc by the thermistor 23 and the resistor R 24 is input to the control unit 400. In the present embodiment, an NTC thermistor is used as the thermistor 23, and the partial pressure value increases as the temperature increases.

  The power supply unit 300 includes a noise filter 301 provided on the input side of a commercial power supply line, a relay switch 302 as a power switch, and steps down an input AC voltage, and AC / DC converts the stepped-down AC voltage into a DC voltage Vdc. Thus, a power supply circuit 303 that supplies the control unit 400 is provided. A power supply line for supplying power to the fixing heater 21 of the fixing unit 200 is branched immediately after the relay switch 302.

  As shown in FIG. 4, the power supply circuit 303 has a power transformer T30 that receives an AC voltage of AC100V input from a commercial power supply on the primary side and outputs a stepped-down AC voltage AC26V and an AC voltage AC12V from the secondary side, A first DC voltage output unit 31 that AC / DC converts AC voltage AC26V and outputs DC voltage DC24V, and a second DC voltage output unit that AC / DC converts AC voltage AC12V and outputs DC voltage DC3.3V 35 etc. are arranged on the substrate.

  The first DC voltage output unit 31 includes a rectifier 32 configured by a diode bridge, a smoothing capacitor C33, a DC regulator 34, and the like. The AC voltage AC26V is full-wave rectified by the rectifier 32 and smoothed by the smoothing capacitor C33. The DC regulator 34 performs DC / DC conversion and outputs a DC voltage DC24V.

  The second DC voltage output unit 35 includes a rectifier 36 configured by a diode bridge, a smoothing capacitor C37, a DC regulator 38, and the like. The AC voltage AC12V is full-wave rectified by the rectifier 36 and smoothed by the smoothing capacitor C37. The DC regulator 38 performs DC / DC conversion and outputs a DC voltage DC 3.3V.

  In this embodiment, the DC voltage Vdc supplied to the control unit 400 is set to the DC voltage DC3.3V output from the second DC voltage output unit 35, but is limited to such a value. Instead, it can be set as appropriate according to the operating voltage of the controller 400 or the like. For example, the DC voltage Vdc may be set to the DC voltage DC5V.

  As shown in FIG. 2, the sheet storage unit 500 includes a standard cassette 520 and two-stage option cassettes 510a and 510b. The paper feed controller 501 includes a paper feed controller 501a that controls the first-stage option cassette 510a and a paper feed controller 501b that controls the second-stage option cassette 510b. The standard cassette 520 is controlled by the control unit 400.

  As shown in FIGS. 1 and 5, the control unit 400 and the paper feed control unit 501 are configured to include microcomputers 40 and 50 mounted on a substrate, peripheral circuits, and the like, and supply a DC voltage Vdc from a power supply circuit 303. Has been. The microcomputers 40 and 50 incorporate a CPU 41 and 51, a ROM storing a control program, a RAM used as a work area for the CPUs 41 and 51, an input / output circuit, and the like. The control unit 400 and the paper feed control unit 501 are connected by a common communication line via drawer connectors 53 and 54.

  The common communication line includes a select signal line L0 for designating the microcomputer 50 to be communicated with which the microcomputer 40 transmits and receives control data, and the microcomputer 50 designated as the communication object transmits and receives data to and from the microcomputer 40. The ready signal line L1 for informing that the preparation is completed, the clock signal line L2 for transmitting / receiving the clock signal, and the bidirectional serial communication line L3 for transmitting / receiving the control data. In the paper feed controllers 501a and 501b, inverters 52a and 52b for inverting the level of the signal SLCT transmitted through the select signal line L0 are installed.

  The microcomputer 40 controls each functional block based on a control program executed by the CPU 41 and executes a predetermined image forming process. For example, the microcomputer 40 detects the fixing temperature based on the divided voltage value of the DC voltage Vdc generated by the thermistor 23 and the resistor R24.

  The microcomputer 50 controls the option cassette 510 subordinate to the microcomputer 40 based on a control program executed by the CPU 51, that is, receiving a command from the microcomputer 40. For example, when an instruction to start printing is received from the microcomputer 40, the timing is adjusted and the sheet is conveyed from the option cassette 510 to the transfer unit 130.

  The microcomputer 40 and the microcomputer 50 are configured to communicate with each other by a polling method. Specifically, as shown in FIG. 6, the microcomputer 40 transmits a polling select signal SLCT, which is a pulse signal that switches between a high level and a low level in a predetermined cycle, to the select signal line L0 and becomes a communication target. The microcomputers 50a and 50b are selected and communicate in a predetermined order.

  That is, the polling select signal SLCT is a pulse signal having a predetermined cycle T0 output to the microcomputer 50 to which the microcomputer 40 is subordinate, and in this embodiment, the predetermined cycle T0 of the polling select signal SLCT is set to 20 milliseconds. ing.

  When the microcomputer 50 receives the low level polling select signal SLCT and becomes communicable with the microcomputer 40, the microcomputer 50 transmits a low level ready signal RDY to the ready signal line L1 to communicate with the microcomputer 40. When the high-level polling select signal SLCT is received, the connection port of the ready signal line L1 and the bidirectional serial communication line L3 is set to high impedance, and the ready signal line L1 and the bidirectional serial communication line L3 are disconnected. Composed.

  When the low-level polling select signal SLCT is transmitted from the microcomputer 40, the low-level ready signal RDY is transmitted to the ready signal line L1 from the microcomputer 50a that is communicable with the microcomputer 40. The microcomputer 50b that receives the inverted high level polling select signal SLCT sets the connection port of the ready signal line L1 and the bidirectional serial communication line L3 to high impedance. Thereby, communication between the microcomputer 40 and the microcomputer 50a is started.

  When the high-level polling select signal SLCT is transmitted from the microcomputer 40 to the select signal line L0, the connection port of the ready signal line L1 and the bidirectional serial communication line L3 is set to high impedance by the microcomputer 50a, and the inverter 52a The low-level ready signal RDY is transmitted to the ready signal line L1 from the microcomputer 50b that has received the low-level inverted polling select signal SLCT and is in a communicable state with the microcomputer 40. Thereby, communication between the microcomputer 40 and the microcomputer 50b is started.

  When communication is started, a clock signal SCK is transmitted from the microcomputer 40 to the clock signal line L2, and a predetermined amount of control data SIO to the microcomputer 50 is transmitted to the bidirectional serial communication line L3 in synchronization with the clock signal SCK. Sent.

  When a predetermined amount of control data is received, a high-level ready signal RDY is transmitted from the microcomputer 50, and a clock signal SCK is transmitted from the microcomputer 40 ready for data reception to the clock signal line L2. A predetermined amount of data is transmitted to the bidirectional serial communication line L3 in synchronization with the clock signal SCK.

  When a predetermined amount of data is received, the polling select signal SLCT whose level is inverted is transmitted from the microcomputer 40 to the select signal line L0, and thus communication between the microcomputer 40 and the microcomputer 50 is realized.

  As shown in FIG. 1, the temperature control device 9 according to the present invention for controlling the fixing temperature of the fixing unit 200 includes a thermistor 23 for detecting the fixing temperature, and fixing so that the fixing temperature detected by the thermistor 23 becomes a target temperature. A CPU 41 that outputs a heater control signal for controlling the heater 21 and a bimetal thermo switch 304 are provided as a safety circuit for forcibly stopping power supply to the fixing heater 21 when the fixing temperature reaches an abnormal overheating temperature. .

  When the color printer 100 is turned on and the control program is executed by the CPU 41, the microcomputer 40 performs processing such as initialization of the RAM and setting of the input / output port, and then the fixing temperature becomes the target temperature. In addition, the fixing temperature is detected based on the divided voltage value of the DC voltage Vdc by the thermistor 23 and the resistor R24, and a heater control signal HC for driving and controlling the fixing heater 21 is output.

  As shown in FIG. 1, the output port from which the microcomputer 40 outputs the heater control signal HC is connected to the base of the transistor Q42, and the collector of the transistor Q42 and the remote terminal of the triac 305 are connected. Therefore, when the heater control signal HC is input to the base of the transistor Q42, the triac 305 is turned on or off.

  As shown in FIG. 10, when the fixing temperature is lower than the target temperature and the fixing heater 21 is turned on, the microcomputer 40 outputs a low level heater control signal HC to increase the fixing temperature, and the fixing temperature is higher than the target temperature. When the fixing heater 21 is turned off, a high level heater control signal HC is output to lower the fixing temperature.

  In the unlikely event that abnormalities such as CPU runaway or output port latch-up due to abnormal noise occur and the heater control signal HC is latched at a low level, the power supply to the fixing heater 21 is continued and the fixing temperature rises. However, when the fixing temperature reaches the abnormal overheating temperature, the thermo switch 304 is opened, and the power supply to the fixing heater 21 is forcibly stopped to prevent the fixing temperature from rising. However, when the power supply to the fixing heater 21 is stopped and the fixing temperature falls below the abnormal overheating temperature, the thermo switch 304 is closed, the power supply to the fixing heater 21 is resumed, and the fixing temperature rises. Therefore, the fixing temperature is maintained before and after the abnormal overheating temperature.

  If the fixing temperature is maintained around the abnormal overheating temperature, the fixing roller 20 and the pressure roller 22 that constitute the fixing unit 200, and the devices and resin members installed around the fixing unit 200 are damaged by high heat. Or there is a possibility of causing distortion and deformation.

  Therefore, in order to prevent the fixing temperature from being maintained around the abnormal overheat temperature, as shown in FIG. 1, the temperature control device 9 generates an edge signal from the polling select signal SLCT output from the microcomputer 40 with a predetermined period T0. A pulse generation circuit 45 that generates ES, a timer circuit 49 that outputs a forced stop signal FS regardless of the heater control signal HC when a predetermined time elapses after the output voltage of the pulse generation circuit 45 is input, and an output of the timer circuit 49 A gate circuit for turning off the fixing heater 21 by a signal or a heater control signal HC is provided.

  As shown in FIGS. 1 and 7, the pulse generation circuit 45 is delayed by a predetermined time Δt by a polling select signal SLCT, a delay circuit composed of a resistor R46 and a capacitor C47 for delaying the polling select signal SLCT, and a delay circuit. An XNOR circuit 48 to which the delay signal and the heater control signal HC are input is provided. The output terminal of the XNOR circuit 48 is connected to the power supply input terminal of the timer circuit 49.

  The pulse generation circuit 45 generates an edge signal ES from a polling select signal SLCT that is a pulse signal having a predetermined period T0. The edge signal ES generated by the pulse generation circuit 45 is input as the power supply voltage Vin of the timer circuit 49 as the output voltage of the pulse generation circuit 45.

  The edge signal ES of the pulse generation circuit 45 is generated as a pulse signal output at a low level for a predetermined time Δt after the level of the polling select signal SLCT is switched. Since the edge signal ES is a low level signal for each edge of the polling select signal FS, the period T1 is half the predetermined period T0 of the polling select signal FS.

  However, if the polling select signal SLCT is maintained at a high level or a low level when the CPU 41 is out of control due to abnormal noise generation or the output port is latched up, the edge signal ES of the pulse generation circuit 45 is maintained at a high level. Is done.

  As shown in FIGS. 8 and 9, the timer circuit 49 operates when the power supply voltage Vin is applied, and the output level is inverted when a predetermined time T2 elapses based on the output signal of the integration circuit 490. It is composed of a logic circuit 494. One period T0 of the polling select signal SLCT is set shorter than the predetermined time T2.

  The integrating circuit 490 includes a resistor R491 and a capacitor C492 connected in series. When the power supply voltage Vin is applied, the capacitor C492 is charged based on a time constant determined by the resistance value of the resistor R491 and the capacitance of the capacitor C492. When the power supply voltage Vin is cut off, the charge charged in the capacitor C492 is discharged through the diode D493, and the voltage of the capacitor is lowered.

  The logic circuit 494 is configured by a drive circuit having hysteresis characteristics. The input terminal of the drive circuit is connected to the connection node Nod1 of the resistor R491 and capacitor C492 constituting the integrating circuit 490, and the output terminal is connected to the base of the transistor Q44.

  The voltage of the capacitor C492 charged with the power supply voltage Vin is input to the logic circuit 494. When the voltage exceeds the threshold voltage Vth, the logic circuit 494 inverts the level of the output signal and forcibly supplies power to the fixing heater 21. A high level signal is output as the forced stop signal FS to be stopped. The output signal of the logic circuit 494 is the output signal of the timer circuit 49.

  As shown in FIG. 1, the collectors of the transistor Q42 and the transistor Q44 are connected to each other to form a wired OR circuit.

  When a low level signal is input from the timer circuit 49 to the transistor Q44, the triac 305 is turned on or off based on the output signal level of the transistor Q42 driven based on the heater control signal HC.

  When the forced stop signal FS, which is a high level signal, is input from the timer circuit 49 to the transistor Q44, the triac 305 is forcibly turned off and the fixing is performed even if the heater control signal HC output from the CPU 41 is at the low level. Power supply to the heater 21 is stopped. That is, the wired OR circuit composed of the transistor Q42 and the transistor Q44 serves as a gate circuit for turning off the fixing heater 21 by the output signal of the timer circuit 49 or the heater control signal HC.

  As shown in FIG. 9, the polling select signal SLCT output from the microcomputer 40 at a predetermined cycle T0 is input to the pulse generation circuit 45, and the pulse generation circuit 45 generates the edge signal ES of the predetermined cycle T1 from the polling select signal SLCT. Is done. The edge signal ES as the output voltage of the pulse generation circuit 45 is applied as the power supply voltage Vin of the timer circuit 49.

  The power supply voltage Vin changes to a low level every predetermined cycle T1, and the capacitor C492 of the timer circuit 49 is discharged every predetermined cycle T1, so that the forced stop signal FS is output from the logic circuit 494 of the timer circuit 49. Absent.

  However, if an abnormality such as a runaway occurs in the CPU 41 due to the influence of abnormal noise or the like, and the polling select signal SLCT output from the microcomputer 40 is maintained at a high level or a low level, the pulse generation circuit 45 The edge signal ES generated by is maintained at a high level.

  Therefore, the capacitor C492 of the timer circuit 49 is charged without being discharged, and the voltage of the capacitor C492 exceeds the threshold voltage Vth when the predetermined time T2 elapses after the power supply voltage Vin is applied. A stop signal FS is output.

  Therefore, as shown in FIG. 10, when an abnormality occurs due to the runaway of the CPU 41 or the like, the power supply to the fixing heater 21 is forcibly stopped by the forced stop signal FS output from the timer circuit 49. It will not rise to or be maintained around abnormal overheating temperatures.

  As described above, inconvenience that the temperature of the fixing roller 21 is maintained before and after the abnormal overheating temperature detected by the thermo switch 304 when the CPU 41 is out of control or the like. Such a circuit has a small number of parts and can be constructed very inexpensively.

  Another embodiment will be described below.

  In the above-described embodiment, the timer circuit 49 receives the edge signal ES generated by the pulse generation circuit 45 as the output voltage of the pulse generation circuit 45 as the power supply voltage Vin of the timer circuit 49 and applies the power supply voltage Vin. The integration circuit 490 that operates and the logic circuit 494 whose output level is inverted when a predetermined time T2 has passed based on the output signal of the integration circuit 490 are configured. However, the reset is mass-produced and sold at low cost. It may be constituted by an IC.

  For example, as shown in FIG. 11, a comparator 605 whose output signal level changes based on fluctuations in the power supply voltage Vin and a capacitor C609 charged by a signal output from the comparator 605 are connected, and the capacitor C609 is set to a predetermined voltage. In this case, the timer circuit 49 is configured by a reset IC that includes a delay circuit 607 that outputs a high level signal and a transistor Q608 that inverts the signal level output from the delay circuit 607 and outputs a signal. For example, as such a reset IC, a reset IC of S-809xxC series which is a product of Seiko Instruments Inc. can be used.

  The comparator 605 of the reset IC receives the reference voltage Vref generated by the reference voltage generator 601 connected to the DC current power supply 600 at the non-inverting input terminal, and the power supply voltage by the resistors R602, R603, and R604 at the inverting input terminal. The divided voltage value of Vin is input, and the signal level output from the comparator 605 is high when the divided voltage value of the power supply voltage Vin is lower than the reference voltage Vref, and the divided voltage value of the power supply voltage Vin is the reference voltage Vref. When it is higher, it becomes low level.

  In addition, the reset IC includes a transistor Q606 in which the output terminal of the comparator 605 is connected to the gate terminal, and the connection node between the resistor R603 and the resistor R604 is connected to the drain terminal, and the signal level output from the comparator 605 is When the level is high, the transistor R606 is configured to short-circuit the resistor R604. Therefore, even if the voltage drop of the power supply voltage Vin is instantaneous, the reset signal is reliably output from the reset IC. However, it goes without saying that the reset IC is not limited to this product.

  In the above-described embodiment, the pulse generation circuit 45 outputs the edge signal ES from the polling select signal FS to the microcomputer 50 subordinate to the microcomputer 40, that is, the CPU 51 subordinate to the CPU 41, as a pulse signal having a predetermined period T 0 output from the CPU 41. The edge signal ES as the output voltage of the pulse generation circuit 45 is supplied as the power supply voltage Vin of the timer circuit 49. However, the pulse signal is not limited to the polling select signal FS.

  That is, the pulse signal may be a signal that is output in a cycle set shorter than the predetermined time T2 until the forced stop signal FS is output from the timer circuit 49 after the power supply voltage Vin is input. When an image forming apparatus including a pulse motor as a motor that rotationally drives the photosensitive member of the image forming unit 120 includes a temperature control device, the CPU 41 outputs a predetermined cycle to the pulse motor during a printing operation. A pulse signal can be used as the pulse signal.

  Further, when an image forming apparatus including a DC motor driven by a control circuit including a PLL is provided with a temperature control device, a clock signal having a predetermined cycle output by the CPU 41 for driving and controlling the DC motor. Can be used as the pulse signal.

  The pulse signal may be a pulse signal output from the output port of the microcomputer 40 at a cycle set shorter than the predetermined time T2 for the purpose of generating the edge signal ES by the pulse generation circuit 45.

  In the above embodiment, the edge signal ES as the output voltage of the pulse generation circuit 45 has been described as being input to the timer circuit 45 as a power supply voltage. However, as shown in FIG. The reset signal may be input to the timer circuit 49.

  For example, as shown in FIG. 13A, the edge signal ES as the output voltage of the pulse generation circuit 45 is based on the integration circuit 490 that operates when the power supply voltage Vin is applied, and the output signal of the integration circuit 490. It may be input to the integration circuit 490 of the timer circuit 49 constituted by the logic circuit 494 whose output level is inverted when the predetermined time T2 elapses. The edge signal ES is configured to be input to a connection node Nod1 of the resistor R491 and the capacitor C492 that constitute the integrating circuit 490.

  In this case, as shown in FIG. 13B, the integration circuit 490 is discharged by the edge signal ES. More specifically, since the edge signal ES becomes a low level every predetermined cycle T1, the charge charged in the capacitor C492 is discharged every predetermined cycle T1. However, since the edge signal ES is maintained at a high level when the CPU 41 is out of control or the like, the integration circuit 490 is not discharged and the forced stop signal whose output level is high from the timer circuit 49 after a predetermined time T2 has elapsed. FS is output.

  14A, an XOR circuit 70, an integration circuit that integrates the output signal of the XOR circuit 70, an XOR circuit 73 to which the output signal of the integration circuit is input, and an output signal of the XOR circuit 73 The edge signal ES as the output voltage of the pulse generation circuit 45 is supplied to the timer circuit 49 composed of a one-shot multivibrator composed of the XOR circuit 74 to which the signal is It may be input. The integrating circuit is constituted by a resistor R71 and a capacitor C72, and a connection node Nod3 between the resistor R71 and the capacitor C72 is connected to an input terminal of the XOR circuit 73.

  The DC voltage Vdc is input to one input terminal of the XOR circuit 70, the edge signal ES is input to the other terminal, the DC voltage Vdc is input to one input terminal of the XOR circuit 73, and the integration is applied to the other terminal. The voltage of the circuit capacitor C72 is input, the edge signal ES is input to one of the input terminals of the XOR circuit 74, and the output signal of the XOR circuit 73 is input to the other terminal.

  As shown in FIG. 14B, in the one-shot multivibrator, when the edge signal ES is at a high level, a high level signal is output from the transistor Q75, and when the edge signal ES is at a low level, the transistor Q75 Is output at a low level for a predetermined time, and then a high level signal is output.

  Here, the time during which the edge signal ES is output at a low level is much shorter than the predetermined time, and the edge signal ES serves as a trigger pulse for the one-shot multivibrator. Therefore, the one-shot multivibrator is configured to output a high level signal in a stable state, and output a low level signal for a predetermined time and return to a stable state when an edge signal ES serving as a trigger pulse is input. Has been.

  The predetermined time is a time from when the capacitor C72 constituting the differentiating circuit is charged by the XOR circuit 70 until the input signal is charged by the XOR circuit 73 to a threshold voltage determined to be high level.

  As shown in FIG. 14C, the capacitor C72 is charged while the edge signal ES is at a high level. However, since the edge signal ES is at a low level every predetermined cycle T1, the capacitor C72 is changed every predetermined cycle T1. The output voltage of the integrating circuit does not rise to the threshold voltage Vth, and the timer circuit 49 always outputs a low level signal. However, since the edge signal ES is maintained at a high level when the CPU 41 is out of control or the like, the capacitor C72 is charged without being discharged, and when the predetermined time T2 elapses, the output voltage of the integration circuit reaches the threshold voltage Vth. The timer circuit 49 outputs the forced stop signal FS whose output level is high.

  In the above-described embodiment, the temperature control device 9 is composed of a wired OR circuit in which the gate circuit that turns off the fixing heater 21 by the output signal of the timer circuit 49 or the heater control signal HC is composed of the transistor Q42 and the transistor Q44. However, the present invention is not limited to this.

  For example, as shown in FIG. 15A, a gate circuit is configured by a three-state buffer 70 to which a heater control signal is input and a transistor Q42 for inverting the output signal level of the three-state buffer 70. When the above signal is input, the output of the three-state buffer 70 becomes high impedance regardless of the signal level of the heater control signal HC, the transistor Q42 is turned on, and the triac 305 is shut off. As shown in FIG. 15B, a NOR circuit 71 to which the heater control signal HC and the output signal from the timer circuit 49 are input constitutes a gate circuit, and a high level signal is input from the timer circuit 49. Then, the NOR circuit 71 outputs a low level regardless of the heater control signal HC. Signal is outputted or may be configured to triac 305 is cut off.

  In the above-described embodiment, the temperature control device 9 has been described as including the thermo switch 304 as a safety circuit. However, the present invention is not limited to this, and the safety circuit can be used when the fixing temperature reaches an abnormal overheat temperature. What is necessary is just to forcibly stop the power supply to 21. For example, a thermistor 21, a fixing temperature detected by the thermistor 21 and an abnormal overheating temperature are input, and a high level or low level signal is output when the fixing temperature becomes equal to or higher than the abnormal overheating temperature. Based on this, a relay switch that forcibly stops power supply to the fixing heater 21 may be used.

  In the above-described embodiment, the NTC thermistor is used as the temperature detection unit. However, a PTC thermistor may be used. In this case, the logic level of the gate circuit, the reference voltage value input to the comparator, etc. may be appropriately adjusted according to the characteristics of the temperature detection unit.

  In the above embodiment, the case where the temperature control device 9 of the present invention is applied to the color printer 100 has been described. However, the temperature control device 9 according to the present invention is an arbitrary image forming apparatus provided with a fixing heater such as a copying machine. It goes without saying that it is possible to apply to.

  Each of the above-described embodiments is merely an example of the present invention, and the scope of the present invention is not limited by the description. The specific configuration of each part is appropriately selected within the scope of the effects of the present invention. It goes without saying that changes can be designed.

Explanatory drawing of temperature control device Illustration of printer Illustration of fixing unit Power supply circuit illustration Explanatory diagram of control unit and paper feed control unit Illustration of serial communication Illustration of edge signal Illustration of timer circuit Explanatory diagram of output signal of timer circuit Explanatory diagram of fixing temperature controlled by temperature controller Explanatory drawing of the timer circuit in another embodiment Explanatory drawing of the temperature control apparatus in another embodiment (A) is explanatory drawing of the timer circuit in another embodiment, (b) is explanatory drawing of the output signal of the timer circuit in another embodiment. (A) is explanatory drawing of the timer circuit in another embodiment, (b) is explanatory drawing of the output signal of the timer circuit in another embodiment, (c) is explanatory drawing of the output signal of the timer circuit in another embodiment. (A) is explanatory drawing of the gate circuit in another embodiment, (b) is explanatory drawing of the gate circuit in another embodiment. Explanatory diagram of fixing temperature control in the prior art

Explanation of symbols

9: Temperature controller 21: Fixing heater 23: Temperature detector (NTC thermistor)
40: Microcomputer 41: CPU
50: Microcomputer 51: Slave CPU
45: Pulse generation circuit 49: Timer circuit 200: Fixing unit 300: Power supply unit 304: Safety circuit (thermo switch)
305: Triac ES: Edge signal FS: Forced stop signal HC: Heater control signal Q42: Gate circuit (transistor constituting a wired OR circuit)
Q44: Gate circuit (transistor constituting a wired OR circuit)
SLCT: Polling select signal

Claims (6)

A temperature detecting unit for detecting a fixing temperature; a CPU for outputting a heater control signal for driving and controlling the fixing heater so that the fixing temperature detected by the temperature detecting unit becomes a target temperature; and the fixing temperature becomes an abnormal overheating temperature. A temperature control device configured to include a safety circuit that forcibly stops power supply to the fixing heater when the temperature reaches,
A pulse generation circuit that generates an edge signal from a pulse signal having a predetermined period output from the CPU, and a forced stop signal is output regardless of the heater control signal when a predetermined time elapses after the output voltage of the pulse generation circuit is input. And a gate circuit for turning off the fixing heater by an output signal of the timer circuit or the heater control signal, wherein one cycle of the pulse signal is set shorter than the predetermined time.   The timer circuit includes an integration circuit that operates when a power supply voltage is applied, and a logic circuit that inverts an output level when the predetermined time elapses based on an output signal of the integration circuit, and an output of the pulse generation circuit The temperature control apparatus according to claim 1, wherein a voltage is input to the timer circuit as a power supply voltage.   3. The temperature control device according to claim 2, wherein the timer circuit comprises a reset IC whose output level is inverted when a predetermined time elapses after the power supply voltage is applied.   The temperature control device according to claim 1, wherein the timer circuit includes a one-shot multivibrator to which an output voltage of the pulse generation circuit is input as a trigger voltage.   The timer circuit includes an integration circuit that operates when a power supply voltage is applied, and a logic circuit that reverses an output level when the predetermined time elapses based on an output signal of the integration circuit, and outputs the pulse generation circuit The temperature control device according to claim 1, wherein the integration circuit is configured to be discharged by a voltage.   6. The temperature control device according to claim 1, wherein the pulse signal having the predetermined period is a polling select signal for a slave CPU subordinate to the CPU.

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