JP2009088958A - Equalization system in modem and modem - Google Patents

Equalization system in modem and modem Download PDF

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JP2009088958A
JP2009088958A JP2007255544A JP2007255544A JP2009088958A JP 2009088958 A JP2009088958 A JP 2009088958A JP 2007255544 A JP2007255544 A JP 2007255544A JP 2007255544 A JP2007255544 A JP 2007255544A JP 2009088958 A JP2009088958 A JP 2009088958A
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signal
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transmission line
change point
detection circuit
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JP4782754B2 (en
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Sawako Kojima
佐和子 小島
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Mitsubishi Electric Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To perform accurate equalization even when using electric wiring wherein transmission line characteristics are dynamically varied at the same time for communication. <P>SOLUTION: In the equalization system in the modem used for the communication of using the electric wiring at the same time and superimposing communication signals on the electric wiring 101, a transmission line change point detection circuit 6 for detecting the change point of the state of a transmission line from the communication signals which passed through the transmission line of the communication signals and a power supply cycle detection circuit 7 for detecting a power supply cycle are provided, and the equalization is performed in synchronism with the cycle variation of the transmission line by the output of the transmission line change point detection circuit 6 and the output of the power supply cycle detection circuit 7. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

この発明は、電力線及び一般配線などの電気的配線を通信に併用する通信方式におけるモデム装置における等化方式及びモデム装置に関するものである。   The present invention relates to an equalization method and a modem device in a modem device in a communication method in which electrical wiring such as a power line and general wiring is used for communication.

電気的配線を通信に併用する通信方式の代表的な例として、電力線搬送通信装置において、従来では、通信信号(以下、単に「信号」と言う)の伝送特性が電源周期によって変動することから、等化装置を設けて電源周期を検出し一定の等化パタンを切り替える方式としている。(例えば、特許文献1参照)   As a typical example of a communication method that uses electrical wiring for communication, in a power line carrier communication device, conventionally, transmission characteristics of a communication signal (hereinafter simply referred to as “signal”) vary depending on a power cycle. An equalization device is provided to detect a power cycle and switch a constant equalization pattern. (For example, see Patent Document 1)

特開平2−172332号公報(第1図〜第3図及びその説明)JP-A-2-172332 (FIGS. 1 to 3 and explanation thereof)

伝送特性が電源周期によって変動することは周知であり、特許文献1に示されるような電源周期を検出し一定の等化パタンを切り替える等化装置を使用すれば電源周期に依存した伝送特性の変動にそれなりに対処できる。   It is well known that the transmission characteristics vary depending on the power cycle. If an equalizing device that detects the power cycle and switches a certain equalization pattern as shown in Patent Document 1 is used, the variation of the transmission characteristics depending on the power cycle. Can cope with it.

ところが、電力線・一般配線などの電気的配線を通信に併用する通信方式においては、信号の伝送路特性(信号の減衰、ノイズ、通信線路のインピーダンス等)(以下、単に「伝送路特性」と言う)は、通信に併用される電気的配線の線種、線路長、分岐等の条件により周波数特性が厳しく、更に、通信と併用の同一配線に接続される電力機器等の電源回路や前記同一配線に接続されるその他機器の種類やその負荷状態などによる影響により伝送路特性がダイナミックに変動するという特徴があることが分かってきた。   However, in communication systems that use electrical wiring such as power lines and general wiring for communication, signal transmission path characteristics (signal attenuation, noise, communication line impedance, etc.) (hereinafter simply referred to as “transmission path characteristics”) ) Has severe frequency characteristics depending on conditions such as line type, line length, branching, etc. of electrical wiring used for communication, and further, power supply circuits such as power devices connected to the same wiring used for communication and the same wiring It has been found that the characteristics of the transmission path dynamically change due to the influence of the type of other equipment connected to the PC and its load state.

このように、伝送路特性は、通信に併用される電気的配線の線種、線路長、分岐等の条件により周波数特性が厳しく、更に、通信と併用の同一配線に接続される電力機器等の電源回路や前記同一配線に接続されるその他機器の種類やその負荷状態などによる影響により伝送路特性がダイナミックに変動する場合には、変動周期を電源周期のみを検出し、一定の等化パタンを切り替える動作をする従来の等化装置では、前記ダイナミックな変動に対処できない、つまり、復調器などの復調手段への入力信号の信号振幅と位相を通信信号送信源からの送信信号に合わせることすなわち等化(以下、単に「等化」と言う)ができない、という課題があることが分かってきた。   In this way, the transmission line characteristics are severe in frequency characteristics depending on conditions such as the line type, line length, branching, etc. of electric wiring used in communication, and further, such as power equipment connected to the same wiring used in communication When the transmission line characteristics change dynamically due to the influence of the type of power supply circuit and other equipment connected to the same wiring and its load condition, the fluctuation period is detected only for the power supply period and a constant equalization pattern is set. The conventional equalizer that performs the switching operation cannot cope with the dynamic fluctuation, that is, the signal amplitude and phase of the input signal to the demodulator such as a demodulator are matched with the transmission signal from the communication signal transmission source. It has been found that there is a problem that cannot be equalized (hereinafter simply referred to as “equalization”).

この発明は、前述のような実情に鑑みてなされたもので、伝送路特性がダイナミックに変動する電気的配線を通信に併用する場合においても正確な等化が行えるようにすることを目的とするものである。   The present invention has been made in view of the above-described circumstances, and an object thereof is to enable accurate equalization even when electrical wiring whose transmission path characteristics are dynamically changed is used for communication. Is.

この発明に係るモデム装置における等化方式は、電気的配線を併用して当該電気的配線に通信信号を重畳させる通信に使用されるモデム装置における等化方式において、前記通信信号の伝送路を通過した通信信号から前記伝送路の状態の変化点を検出する伝送路変化点検出回路、および電源周期を検出する電源周期検出回路を設け、前記伝送路変化点検出回路の出力と前記電源周期検出回路の出力とにより前記伝送路の状態の周期変動に同期して等化を行うものである。   An equalization method in a modem device according to the present invention is an equalization method in a modem device used for communication in which an electrical wiring is used together and a communication signal is superimposed on the electrical wiring. A transmission line change point detection circuit for detecting a change point of the state of the transmission line from the transmitted communication signal, and a power supply cycle detection circuit for detecting a power supply cycle, and an output of the transmission line change point detection circuit and the power supply cycle detection circuit Is equalized in synchronism with the period fluctuation of the state of the transmission line.

この発明に係るモデム装置は、電気的配線を併用して当該電気的配線に通信信号を重畳
させる通信に使用され送信信号と受信信号との等化を行うモデム装置において、前記送信信号が前記通信信号の伝送路を通過してきた受信信号から前記伝送路の状態の変化点を検出する伝送路変化点検出回路、および電源周期を検出する電源周期検出回路を設け、前記伝送路変化点検出回路の出力と前記電源周期検出回路の出力とにより前記伝送路の状態の周期変動に同期して等化を行うものである。
The modem device according to the present invention is a modem device used for communication in which an electrical wiring is used in combination to superimpose a communication signal on the electrical wiring and performs equalization between a transmission signal and a reception signal. A transmission path change point detection circuit that detects a change point of the state of the transmission path from a received signal that has passed through the transmission path of the signal, and a power supply cycle detection circuit that detects a power supply cycle; Equalization is performed in synchronism with the period fluctuation of the state of the transmission path by the output and the output of the power cycle detection circuit.

この発明は、電気的配線を併用して当該電気的配線に通信信号を重畳させる通信に使用されるモデム装置における等化方式において、前記通信信号の伝送路を通過した通信信号から前記伝送路の状態の変化点を検出する伝送路変化点検出回路、および電源周期を検出する電源周期検出回路を設け、前記伝送路変化点検出回路の出力と前記電源周期検出回路の出力とにより前記伝送路の状態の周期変動に同期して等化を行うので、伝送路特性がダイナミックに変動する電気的配線を通信に併用する場合においても正確な等化が行える効果がある。   The present invention relates to an equalization method in a modem device used for communication in which an electrical wiring is used in combination and a communication signal is superimposed on the electrical wiring, and from the communication signal that has passed through the transmission path of the communication signal, A transmission line change point detection circuit for detecting a state change point and a power supply cycle detection circuit for detecting a power supply period are provided, and an output of the transmission line is determined by an output of the transmission line change point detection circuit and an output of the power supply period detection circuit. Since equalization is performed in synchronization with the periodic fluctuation of the state, there is an effect that accurate equalization can be performed even when electrical wiring whose transmission path characteristics are dynamically changed is used in communication.

この発明は、電気的配線を併用して当該電気的配線に通信信号を重畳させる通信に使用され送信信号と受信信号との等化を行うモデム装置において、前記送信信号が前記通信信号の伝送路を通過してきた受信信号から前記伝送路の状態の変化点を検出する伝送路変化点検出回路、および電源周期を検出する電源周期検出回路を設け、前記伝送路変化点検出回路の出力と前記電源周期検出回路の出力とにより前記伝送路の状態の周期変動に同期して等化を行うので、伝送路特性がダイナミックに変動する電気的配線を通信に併用する場合においても正確な等化が行える効果がある。   The present invention relates to a modem device that is used for communication in which electrical wiring is used in combination to superimpose a communication signal on the electrical wiring and performs equalization between a transmission signal and a reception signal, wherein the transmission signal is a transmission path of the communication signal. A transmission line change point detection circuit that detects a change point of the state of the transmission line from a received signal that has passed through the power supply, and a power supply cycle detection circuit that detects a power supply period, the output of the transmission line change point detection circuit and the power supply Since equalization is performed in synchronization with the period fluctuation of the state of the transmission line based on the output of the period detection circuit, accurate equalization can be performed even when electrical wiring whose transmission line characteristics change dynamically is used in communication. effective.

実施の形態1.
以下この発明の実施の形態1を図1〜図12により説明する。図1は周期変動同期適応等化方式を実行する装置を含むモデム装置の内部構成およびモデム装置の周辺装置・機器との関係の一例を例示するブロック図、図2は図1における周期変動同期適応等化回路5の内部構成および周期変動同期適応等化回路5とその周辺回路との関係の一例を例示するブロック図、図3は図1および図2における電源周期検出回路7におけるゼロクロス検出回路の一例を例示する接続図、図4は図3におけるAC電源の電源波形とフォトカプラの出力波形との関係の一例を示す図、図5は通信信号送信源から送信される信号(図1の信号結合装置12に入力される信号)の信号フレームの構成の一例をリファレンス信号も含めて例示する図、図6は通信システムモデルを示す図、図7は図1および図2における伝送路変化点検出回路6による伝送路推定値と基準点からの誤差値を検出する考え方の一例を示す図、図8は図2における等化タイミング生成回路54の機能の一例を説明する図、図9は図2および図8における等化係数学習回路53の内部構成の一例を示す図、図10は図2および図8における等化係数生成回路52の内部構成の一例を示すブロック図、図11は伝送路特性の変動の一事例である伝送路特性Aを示す図、図12は伝送路特性の変動の他の一事例である伝送路特性Bを示す図である。
Embodiment 1 FIG.
A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram illustrating an example of the internal configuration of a modem device including a device that executes a periodic variation synchronization adaptive equalization method and the relationship between peripheral devices and devices of the modem device, and FIG. 2 is an example of periodic variation synchronization adaptation in FIG. FIG. 3 is a block diagram illustrating an example of the internal configuration of the equalization circuit 5 and the relationship between the period variation synchronization adaptive equalization circuit 5 and its peripheral circuits. FIG. 3 is a diagram of the zero cross detection circuit in the power supply period detection circuit 7 in FIGS. 4 is a connection diagram illustrating an example, FIG. 4 is a diagram illustrating an example of the relationship between the power supply waveform of the AC power source and the output waveform of the photocoupler in FIG. 3, and FIG. 5 is a signal transmitted from the communication signal transmission source (the signal in FIG. 1). FIG. 6 is a diagram illustrating an example of a signal frame configuration including a reference signal, FIG. 6 is a diagram illustrating a communication system model, and FIG. 7 is a diagram illustrating a transmission path change in FIGS. FIG. 8 is a diagram illustrating an example of a concept of detecting an error value from a transmission path estimation value and a reference point by the point detection circuit 6, FIG. 8 is a diagram illustrating an example of a function of the equalization timing generation circuit 54 in FIG. 2 is a diagram showing an example of the internal configuration of the equalization coefficient learning circuit 53 in FIGS. 2 and 8, FIG. 10 is a block diagram showing an example of the internal configuration of the equalization coefficient generation circuit 52 in FIGS. 2 and 8, and FIG. FIG. 12 is a diagram showing a transmission line characteristic A, which is an example of a fluctuation in path characteristics, and FIG.

先ず、この発明の実施の形態1を図1、図2、図3、図4に基づいて説明する。   First, a first embodiment of the present invention will be described with reference to FIGS. 1, 2, 3, and 4. FIG.

周期変動同期適応等化方式を実行する装置を含むモデム装置の内部構成およびモデム装置の周辺装置・機器との関係の一例を例示する図1において、電力線・一般配線などの電気的配線101を通信に併用する通信方式に使用されるモデム装置1は、図示のように、周知の信号結合装置12により電気的配線101に接続されている。周知のとおり通信信号源(図示省略)から電気的配線101を伝送媒体として例えばメガヘルツ(MHz)レベルのキャリヤにより送信された信号は信号結合装置12により取り出されモデム装置1の受信側に入力され、モデム装置1の出力である受信データは、端末装置等(図示省略)に送られる。   Referring to FIG. 1 illustrating an example of the internal configuration of a modem device including a device that executes a period variation synchronous adaptive equalization method and the peripheral device / equipment of the modem device. The modem device 1 used for the communication method used together is connected to the electrical wiring 101 by a known signal coupling device 12 as shown in the figure. As is well known, a signal transmitted from a communication signal source (not shown) using, for example, a megahertz (MHz) level carrier using the electrical wiring 101 as a transmission medium is taken out by the signal coupling device 12 and inputted to the receiving side of the modem device 1. Received data that is the output of the modem device 1 is sent to a terminal device or the like (not shown).

なお、ここで、前記電力線とは、例えば屋外、屋内、高圧、低圧等全ての所謂電力線を意味し、一般配線とは、LANケーブルのような同軸ケーブル、電話線のようなツイストペア線、道路脇の架設通信線等のみならず車両内、その他本モデムが通信可能となる全ての配線を意味する。   Here, the power line means all so-called power lines such as outdoors, indoors, high voltage, low voltage, etc., and general wiring means coaxial cable such as LAN cable, twisted pair line such as telephone line, roadside This means not only the built-in communication line, etc., but also all the wiring that enables communication in the vehicle and other modems.

前記モデム装置1は、電気的配線101からの受信信号が入力される受信側に、受信部の周知のアナログ信号インタフェース部2、周知のA/D(Analog/Digital)変換部3、時間軸の信号を周波数軸へ変換する周知のFFT(First Fourier Transform)部4、新設の周期変動同期適応等化機能回路5、新設の伝送路変化点検出回路6、周知の電源周期検出回路7、および周知の復号化部8を備えている。   The modem device 1 has a well-known analog signal interface unit 2 of a receiving unit, a well-known A / D (Analog / Digital) conversion unit 3, a time axis on the receiving side to which a receiving signal from the electrical wiring 101 is inputted. A well-known FFT (First Fourier Transform) unit 4 for converting a signal to a frequency axis, a newly installed periodic fluctuation synchronization adaptive equalization function circuit 5, a newly installed transmission line change point detecting circuit 6, a well-known power cycle detecting circuit 7, and a well-known The decoding unit 8 is provided.

また、前記モデム装置1は、電気的配線101への信号送信側に、周知の送信データの符号化部11、周波数軸の信号を時間軸へ変換する周知のIFFT(Inverse First Fourier Transform)部10、周知のD/A(Digital/Analog)変換部9、周知のアナログインタフェース部8を備えている。   The modem device 1 includes a known transmission data encoding unit 11 and a known IFFT (Inverse First Fourier Transform) unit 10 for converting a frequency axis signal to a time axis on the signal transmission side to the electrical wiring 101. A well-known D / A (Digital / Analog) conversion unit 9 and a well-known analog interface unit 8 are provided.

次に、図1における周期変動同期適応等化回路5の内部構成および周期変動同期適応等化回路5とその周辺回路との関係の一例を例示する図2において、周期変動同期適応等化回路5は、図示のように、等化器における等化係数を入力信号に乗算する等化係数乗算回路部51、LMS(Least Mean Square)アルゴリズム等で等化係数を計算し更に等化係数学習回路53で学習した等化係数を等化係数乗算回路部51へ選択して設定する等化係数生成回路52、伝送路の変動周期で等化係数を学習する等化係数学習回路53、および等化係数タイミング生成機能部54を備えている。   Next, in FIG. 2 illustrating an example of the internal configuration of the periodic variation synchronization adaptive equalization circuit 5 in FIG. 1 and the relationship between the periodic variation synchronization adaptive equalization circuit 5 and its peripheral circuits, the periodic variation synchronization adaptive equalization circuit 5 is illustrated. As shown in the figure, an equalization coefficient multiplication circuit unit 51 for multiplying an input signal by an equalization coefficient in an equalizer, an equalization coefficient learning circuit 53 by calculating an equalization coefficient by an LMS (Least Mean Square) algorithm or the like. The equalization coefficient generation circuit 52 that selects and sets the equalization coefficient learned in step 5 in the equalization coefficient multiplication circuit unit 51, the equalization coefficient learning circuit 53 that learns the equalization coefficient in the fluctuation period of the transmission path, and the equalization coefficient A timing generation function unit 54 is provided.

図1および図2における電源周期検出回路7におけるゼロクロス検出回路の一例を例示する図3において、そのAC50/60Hzの電源の電源波形は、図4に例示してあるようになるが、図3におけるフォトカプラは、電圧が所定の閾値となる変化点でゼロクロス近傍を検出し、該フォトカプラの出力の波形は図4に例示する通りである。該フォトカプラの出力から、図3に例示のゼロクロス検出回路及びタイミングカウント回路により、ゼロクロス地点からのタイミングを任意に生成することが可能となる。   In FIG. 3 illustrating an example of the zero cross detection circuit in the power cycle detection circuit 7 in FIGS. 1 and 2, the power supply waveform of the AC 50/60 Hz power supply is as illustrated in FIG. The photocoupler detects the vicinity of the zero crossing at the changing point where the voltage becomes a predetermined threshold, and the output waveform of the photocoupler is as illustrated in FIG. From the output of the photocoupler, the timing from the zero cross point can be arbitrarily generated by the zero cross detection circuit and the timing count circuit illustrated in FIG.

次に、図2〜図9を用いて、本実施の形態1の主な特徴となるモデム装置内部機能ブロックである周期変動同期適応等化回路5、伝送路変化点検出回路6、電源周期検出回路7について、それらの機能、内部構成、動作を説明する。   Next, referring to FIG. 2 to FIG. 9, the periodic fluctuation synchronization adaptive equalization circuit 5, the transmission line change point detection circuit 6, and the power supply cycle detection, which are the internal functional blocks of the modem device, which are the main features of the first embodiment. The function, internal configuration, and operation of the circuit 7 will be described.

周期変動同期適応等化機能を有する周期変動同期適応等化回路5、伝送路変化点検出機能を有する伝送路変化点検出回路6、及び電源周期検出機能を有する電源周期検出回路7は、本実施の形態1の目的となる正確な適応等化機能において、伝送路の変動周期を自動的に検出し、そのタイミングにより受信信号の等化係数を学習し、伝送路の変動に合わせて等化係数を切り替える機能を実現する。   The cycle variation synchronization adaptive equalization circuit 5 having the cycle variation synchronization adaptive equalization function, the transmission path change point detection circuit 6 having the transmission path change point detection function, and the power cycle detection circuit 7 having the power cycle detection function are implemented in this embodiment. In the accurate adaptive equalization function that is the object of the first embodiment, the fluctuation period of the transmission line is automatically detected, the equalization coefficient of the received signal is learned at the timing, and the equalization coefficient is matched to the fluctuation of the transmission line Realize the function to switch between.

ここで、一般的な等化機能について補足説明する。
例えば、通信システムモデルを、図6を参照して以下に定義する。
Here, a supplementary explanation will be given of a general equalization function.
For example, a communication system model is defined below with reference to FIG.

送信信号s(t)は、伝送路によって波形歪みを受け、ノイズが加算されて信号y(t)として受信される。この受信信号は、m個の受信系列として等化器に入力される。等化器はこのデータ系列を用い送信信号s(t-d)を推定することによって、波形歪みを補償する。尚、送信信号s(t-d)におけるdは、等化器における遅延である。   The transmission signal s (t) is subjected to waveform distortion by the transmission path, added with noise, and received as a signal y (t). This received signal is input to the equalizer as m received sequences. The equalizer compensates for waveform distortion by estimating the transmission signal s (t-d) using this data series. Note that d in the transmission signal s (t−d) is a delay in the equalizer.

また、線形等化器を例にすると、電気的配線上で発生したフィルタの係数を伝送路の状態に応じて学習する。学習時に既知の信号列を送信し、その受信信号をトレーニングデータとして使用できる場合は、LMS(Least Mean Square)アルゴリズムや、RMS(Recursive Least Square)等の適応アルゴリズムを用いて係数を調整する。   Taking a linear equalizer as an example, the coefficient of the filter generated on the electrical wiring is learned according to the state of the transmission line. When a known signal sequence is transmitted during learning and the received signal can be used as training data, the coefficient is adjusted using an adaptive algorithm such as LMS (Least Mean Square) algorithm or RMS (Recursive Least Square).

入力信号ベクトルは次の(1)式で表される。ただし、ベクトルに付した上付きのTは、転置ベクトルを意味する。

Figure 2009088958
タップ係数ベクトルは次の(2)式で表される。
Figure 2009088958
フィルタ合成ベクトルは次の(3)式で表される。ただし、ベクトルに付した上付きのHは、複素共役転置ベクトルを意味する。
Figure 2009088958
所望信号d(i)との誤差信号c(i)は、以下の(4)式で表される。
Figure 2009088958
The input signal vector is expressed by the following equation (1). However, the superscript T added to the vector means a transposed vector.
Figure 2009088958
The tap coefficient vector is expressed by the following equation (2).
Figure 2009088958
The filter synthesis vector is expressed by the following equation (3). However, the superscript H attached to the vector means a complex conjugate transposed vector.
Figure 2009088958
The error signal c (i) from the desired signal d (i) is expressed by the following equation (4).
Figure 2009088958

等化アルゴリズムで算出された量子化誤差を含む伝送路推定誤差を小さくするために、等化器出力とリファレンス信号との最小二乗誤差LMSを最小にするようにタップ係数誤差を補正する。なお、二乗誤差LMSは、以下の(5)式で表される。

Figure 2009088958
具体的には、以下の(6)式にしたがって、タップ係数を更新する。 In order to reduce the channel estimation error including the quantization error calculated by the equalization algorithm, the tap coefficient error is corrected so as to minimize the least square error LMS between the equalizer output and the reference signal. The square error LMS is expressed by the following equation (5).
Figure 2009088958
Specifically, the tap coefficient is updated according to the following equation (6).

Figure 2009088958
ただし、(6)式におけるμは、ステップサイズである。
タップ係数更新には、入力系列が既知である必要があるが、この既知の入力系列は、通常トレーニングフレームのプリアンブルを使用する。なお、タップとは、特許文献1にも示されているように等化器あるいは等化装置における周知のタップである。
Figure 2009088958
However, μ in the equation (6) is a step size.
In order to update the tap coefficient, the input sequence needs to be known. This known input sequence usually uses the preamble of the training frame. Note that the tap is a well-known tap in an equalizer or an equalization apparatus as disclosed in Patent Document 1.

以下、本実施の形態1の内容に戻る。
本実施の形態1の等化器はトランスバーサルフィルタ構成を例とした。
Hereinafter, the description returns to the contents of the first embodiment.
The equalizer of the first embodiment has a transversal filter configuration as an example.

図1における周期変動同期適応等化回路5の内部構成および周期変動同期適応等化回路5とその周辺回路との関係の一例を例示する図2において、周期変動同期適応等化回路5は、等化係数乗算回路部51、等化係数生成回路52、等化係数学習回路53、および等化係数タイミング生成機能部54を備えている。   In FIG. 2 illustrating an example of the internal configuration of the periodic variation synchronization adaptive equalization circuit 5 in FIG. 1 and an example of the relationship between the periodic variation synchronization adaptive equalization circuit 5 and its peripheral circuits, the periodic variation synchronization adaptive equalization circuit 5 includes: An equalization coefficient multiplication circuit unit 51, an equalization coefficient generation circuit 52, an equalization coefficient learning circuit 53, and an equalization coefficient timing generation function unit 54 are provided.

前記等化係数乗算回路部51は、等化器における等化係数を入力信号に乗算する。前記等化係数生成回路52は、LMS(Least Mean Square)アルゴリズム等で等化係数を計算し、更に等化係数学習回路53で学習した等化係数を前記等化係数乗算回路部51へ選択して設定する。前記等化係数学習回路53は、伝送路の変動周期で等化係数を学習する。等化係数タイミング生成機能部54は、伝送路変化点検出回路6の出力による伝送路変化点検出タイミング及び電源周期検出回路6の出力による電源周期検出タイミングを用いて、真の伝送路の変動周期を検出し、伝送路の状態の周期変動に同期して等化係数を最適に切り替える。   The equalization coefficient multiplication circuit unit 51 multiplies the input signal by the equalization coefficient in the equalizer. The equalization coefficient generation circuit 52 calculates an equalization coefficient by an LMS (Least Mean Square) algorithm or the like, and further selects the equalization coefficient learned by the equalization coefficient learning circuit 53 to the equalization coefficient multiplication circuit unit 51. To set. The equalization coefficient learning circuit 53 learns the equalization coefficient in the fluctuation cycle of the transmission path. The equalization coefficient timing generation function unit 54 uses the transmission line change point detection timing based on the output of the transmission line change point detection circuit 6 and the power supply period detection timing based on the output of the power supply period detection circuit 6, to change the true transmission line fluctuation period. And the equalization coefficient is optimally switched in synchronization with the period fluctuation of the transmission path state.

伝送路の状態の周期変動に同期して等化係数を切り替える場合、電力線・一般配線などの電気的配線を通信に併用する通信方式においては、伝送路の状態の周期変動の検出が課題となる。通信と併用の同一配線に接続される電力機器等の電源回路や前記同一配線に接続されるその他機器の種類やその負荷状態などによる影響によるある一定の周期的に振幅・位相変動が発生する伝送路条件が考えられる。このような伝送路特性の周期変動は、必ずしも電源周期で発生しない。従って、このような伝送路特性の周期変動については、その変動周期は、特許文献1でも提案されているような従来の電源周期に連動した伝送路変動を想定した等化係数切り替え方式では、正確な検出が困難である。   When switching equalization coefficients in synchronization with periodic fluctuations in the state of the transmission line, detection of periodic fluctuations in the state of the transmission line becomes an issue in communication systems that use electrical wiring such as power lines and general wiring for communication. . Transmission in which amplitude and phase fluctuations occur at certain periodic intervals due to the influence of the type of power supply circuit such as power equipment connected to the same wiring used for communication and other equipment connected to the same wiring, and its load state Road conditions are considered. Such periodic fluctuations in transmission path characteristics do not necessarily occur in the power supply period. Therefore, with regard to such periodic fluctuations in transmission line characteristics, the fluctuation period is accurate in the conventional equalization coefficient switching method that assumes transmission line fluctuations linked to the power supply period as proposed in Patent Document 1. Detection is difficult.

従って、前述のように通信と併用の同一配線に接続される電力機器等の電源回路や前記同一配線に接続されるその他機器の種類やその負荷状態などによる影響によるある一定の周期的に振幅・位相変動が発生するといった伝送路特性の周期変動についてはその伝送路変動周期の検出は更に検出精度を向上した最適な方式あるいはメカニズムが必要である。本実施の形態1では、伝送路変化点検出回路6及び電源周期検出回路7の2つの検出信号をさらに計算することでより正確な周期検出を行う。   Therefore, as described above, the amplitude of the power supply circuit such as the power equipment connected to the same wiring used for communication and the other equipment connected to the same wiring, the influence of the load state, and the like on a certain periodic basis. For periodic fluctuations in transmission path characteristics such as phase fluctuations, detection of the transmission path fluctuation period requires an optimum method or mechanism with further improved detection accuracy. In the first embodiment, more accurate cycle detection is performed by further calculating two detection signals of the transmission path change point detection circuit 6 and the power supply cycle detection circuit 7.

ここで、図5、図7を使用して、図2における内部機能ブロックである伝送路変化点検出回路6の動作の説明する。   Here, the operation of the transmission line change point detection circuit 6 which is an internal functional block in FIG. 2 will be described with reference to FIGS.

図5は、通信信号送信源から送信される信号(図1の信号結合装置12に入力される信号)の信号フレームの構成の一例をリファレンス信号も含めて例示する図であり、図5に図示のように、フレームの先頭にリファレンス信号となるプリアンブルが付加される。伝送路変化点検出回路6では、このリファレンス信号のFFT結果(図1におけるFFT部4によるFFT結果)を用いて、実際に伝送路を経て受信した受信信号がどの程度変動したかを測定し、変動量がある閾値を超えた場合、変動が発生したと判断し検出する。図7に例示の変動量の振幅・位相座標上のイメージからも判るように、伝送路変化点検出回路6により伝送路推定値(受信点)と基準点からの誤差値を検出することができる。つまり、伝送路変化点検出回路6では、実際に伝送路を経て受信した受信信号がどの程度変動したかを測定し、変動量がある閾値を超えた場合、変動が発生したと判断し変動量を検出する。   FIG. 5 is a diagram illustrating an example of the configuration of a signal frame of a signal transmitted from a communication signal transmission source (a signal input to the signal combining device 12 in FIG. 1) including a reference signal. As described above, a preamble serving as a reference signal is added to the head of the frame. The transmission line change point detection circuit 6 uses the FFT result of this reference signal (FFT result by the FFT unit 4 in FIG. 1) to measure how much the received signal actually received through the transmission line has changed, If the fluctuation amount exceeds a certain threshold, it is determined that fluctuation has occurred and is detected. As can be seen from the image of the variation amount illustrated in FIG. 7 on the amplitude / phase coordinates, the transmission path change point detection circuit 6 can detect the transmission path estimated value (reception point) and the error value from the reference point. . In other words, the transmission path change point detection circuit 6 measures how much the received signal actually received through the transmission path has fluctuated, and if the fluctuation amount exceeds a certain threshold, it is determined that fluctuation has occurred and the fluctuation amount Is detected.

ここで、電源周期検出回路7の回路構成の一例を例示する図3において、AC50/60Hzの電源の電源波形は、図4に示すようになるが、図3におけるフォトカプラは、電圧が所定の閾値となる変化点でゼロクロス近傍を検出する。該フォトカプラの出力波形は図4に例示する通りである。該フォトカプラの出力信号を図3に示すゼロクロス検出回路及びタイミングカウント回路により、任意にゼロクロス地点からのタイミングを生成することが可能となる。   Here, in FIG. 3 illustrating an example of the circuit configuration of the power cycle detection circuit 7, the power waveform of the AC 50/60 Hz power source is as shown in FIG. 4, but the photocoupler in FIG. The vicinity of the zero cross is detected at the change point serving as the threshold. The output waveform of the photocoupler is as illustrated in FIG. The output signal of the photocoupler can arbitrarily generate timing from the zero cross point by the zero cross detection circuit and the timing count circuit shown in FIG.

前述の図5で説明した伝送路変化点検出回路6による伝送路変化点検出タイミングと、前述の図3、図4で説明した電源周期検出回路7の出力とを入力として、真の伝送路の変動周期を検出し等化係数を最適に切り替えるための等化係数タイミング生成機能を図8に例示してある。   The transmission line change point detection timing by the transmission line change point detection circuit 6 described above with reference to FIG. 5 and the output of the power cycle detection circuit 7 described with reference to FIGS. FIG. 8 illustrates an equalization coefficient timing generation function for detecting the fluctuation period and optimally switching the equalization coefficient.

図2における等化タイミング生成回路54の機能の一例を説明する図8において、等化係数タイミング生成機能54は、タイミング選択回路542、および周期判定回路541を備えており、次の(1)(2)の主機能を有している。(1)伝送路変動の変化点を検出し、伝送路変動に従った等化係数を記憶するための学習タイミングを、等化係数学習回路53に通知する。(2)伝送路変動の変化点を検出し、等化係数学習回路53で記憶した等化係数を、等化器の等化係数乗算回路51に通知する。   In FIG. 8 for explaining an example of the function of the equalization timing generation circuit 54 in FIG. 2, the equalization coefficient timing generation function 54 includes a timing selection circuit 542 and a period determination circuit 541, and the following (1) ( It has the main function of 2). (1) A change point of transmission path fluctuation is detected, and a learning timing for storing an equalization coefficient according to the transmission path fluctuation is notified to the equalization coefficient learning circuit 53. (2) The change point of the transmission path fluctuation is detected, and the equalization coefficient stored in the equalization coefficient learning circuit 53 is notified to the equalization coefficient multiplication circuit 51 of the equalizer.

前記タイミング選択回路542は、伝送路の変化点検出回路6の出力と、さらに電源周期検出回路7の出力とを監視し、(1)電源回路周期と伝送路変化点の検出タイミングが合致した場合と、(2)伝送路変化点検出回路単独で電源周期以外で変化点が検出された場合とを監視し、前記周期判定回路541は、更に長い一定期間、同一周期が発生するかどうかを、一定回数カウントすることで周期変動が確実なものかどうかを判定する。   The timing selection circuit 542 monitors the output of the transmission line change point detection circuit 6 and the output of the power supply cycle detection circuit 7. (1) When the power supply circuit cycle matches the detection timing of the transmission line change point And (2) a case where a transmission point change point detection circuit alone detects a change point other than the power cycle, and the cycle determination circuit 541 determines whether or not the same cycle occurs for a longer fixed period. By counting a certain number of times, it is determined whether or not the periodic fluctuation is certain.

前述のように周期判定回路541が判定して検出した周期信号は、図8に図示のように、等化係数学習回路53、等化係数生成回路52、および等化係数乗算回路51へ通知する。   The period signal detected and detected by the period determination circuit 541 as described above is notified to the equalization coefficient learning circuit 53, the equalization coefficient generation circuit 52, and the equalization coefficient multiplication circuit 51, as shown in FIG. .

図2および図8における等化係数学習回路53の内部構成の一例を示す図9を用いて、等化係数学習回路53について説明する。   The equalization coefficient learning circuit 53 will be described with reference to FIG. 9 showing an example of the internal configuration of the equalization coefficient learning circuit 53 in FIGS.

等化係数学習回路53の内部はメモリ構造であり、周期判定回路541が判定して検出した周期信号のタイミングで、図2における等化係数生成回路52が計算した等化係数を、図9に例示のように、周期タイミングのパタンにあわせて記憶する。   The equalization coefficient learning circuit 53 has a memory structure, and the equalization coefficient calculated by the equalization coefficient generation circuit 52 in FIG. 2 at the timing of the periodic signal determined and detected by the period determination circuit 541 is shown in FIG. As illustrated, it is stored in accordance with the pattern of the cycle timing.

図9の例では、メモリ部Aに、周期タイミングのパタンAに対応の等化係数(乗算するウェイト(図2におけるW,W,・・・W,・・・W))を記憶し、メモリ部Bに、パタンAとは異なる周期タイミングのパタンBに対応の等化係数(乗算するウェイト(図2におけるW,W,・・・W,・・・W))を記憶してある。 In the example of FIG. 9, an equalization coefficient (weights to be multiplied (W 0 , W 1 ,... W m ,... W M in FIG. 2)) corresponding to the period timing pattern A is stored in the memory unit A. stored in the memory unit B, the equalization coefficient corresponding to the pattern B different period timing and pattern a (weight to be multiplied (W 0 in FIG. 2, W 1, ··· W m , ··· W M) ) Is remembered.

次に、図2および図8における等化係数生成回路52の内部構成の一例を示す図10を用いて、等化係数生成回路52を説明する。   Next, the equalization coefficient generation circuit 52 will be described with reference to FIG. 10 showing an example of the internal configuration of the equalization coefficient generation circuit 52 in FIGS.

等化係数生成回路52は、LMSアルゴリズム等による等化係数計算回路522、およびセレクタ521を有し、等化タイミング生成回路54のタイミングに従って、等化係数計算回路522が計算した等化係数(乗算するウェイト)と等化係数学習回路53が記憶する等化係数を選択し、適応等化器における等化係数乗算回路51の等化係数(ウェイト(図2におけるW,W,・・・W,・・・W))を設定する。
尚、等化係数計算回路522では、最小二乗誤差計算にLMSアルゴリズムよりも優れた収束特性を持つRLS(Recursive Least Square)アルゴリズムも用いることもできる。
The equalization coefficient generation circuit 52 includes an equalization coefficient calculation circuit 522 based on an LMS algorithm or the like and a selector 521, and the equalization coefficient (multiplication) calculated by the equalization coefficient calculation circuit 522 according to the timing of the equalization timing generation circuit 54 And the equalization coefficient stored in the equalization coefficient learning circuit 53, and the equalization coefficient (weight (W 0 , W 1 ,... In FIG. 2) of the equalization coefficient multiplication circuit 51 in the adaptive equalizer. W m ,... W M )) are set.
In the equalization coefficient calculation circuit 522, an RLS (Recursive Least Square) algorithm having convergence characteristics superior to the LMS algorithm can also be used for the least square error calculation.

前述の周期変動の変動周期を検出した場合、その周期の先頭で等化器の等化係数(ウェイト)を切り替える必要があるが、変動周期が検出できた後に、1つ前の周期の終了を検出した時点で当化器の等化係数(ウェイト)を切り替えれば、次の周期から適応が可能である。   When the fluctuation period of the above-described period fluctuation is detected, it is necessary to switch the equalizer equalization coefficient (weight) at the head of the period. After the fluctuation period is detected, the end of the previous period is If the equalization coefficient (weight) of the equalizer is switched at the time of detection, adaptation is possible from the next cycle.

従来の装置では、前述のように、電源周期に連動した伝送路変動を想定し変動周期を電源周期のみで検出し、一定の等化パタンを切り替えるため、通信に併用される電気的配線の線種、線路長、分岐等の条件により周波数特性が厳しく、更に、通信と併用の同一配線に接続される電力機器等の電源回路や前記同一配線に接続されるその他機器の種類やその負荷状態などによる影響により伝送路特性がダイナミックに変動するような伝送路条件下では、(1)電源周期以外の周期変動に対する等化ができない、(2)伝送路の特性に対する適応等化と周期変動への等化機能を持たないため、十分な特性改善ができない。   In the conventional apparatus, as described above, the fluctuation of the transmission line linked to the power cycle is assumed, the fluctuation cycle is detected only by the power cycle, and the constant equalization pattern is switched. Frequency characteristics are severe depending on conditions such as type, line length, branching, etc.Furthermore, the type of power supply circuit such as power equipment connected to the same wiring used for communication, the type of other equipment connected to the same wiring, and the load state thereof (1) It is not possible to equalize periodic fluctuations other than the power cycle, under the transmission line conditions where the transmission line characteristics dynamically change due to the influence of (2) Adaptive equalization to the transmission line characteristics and periodic fluctuations Since it does not have an equalization function, sufficient characteristics cannot be improved.

例えば、電力線では、多種多様の家電や電力機器が同一線路上に接続されることが想定されるが、例えば電源周期で図11、図12に示すような、振幅・位相変動が発生するため、モデム装置の受信回路では、振幅・位相点がズレることによる受信エラーが発生する可能性があり、この現象に伴う補完手段を講じる方が好ましい。更に、その他の一般通信線等(通信のみでなく他の用途に使用して、モデムとの共用線路の場合を含める。例えば工場内配線や、列車内配線等を含む。)を併用する場合においても、どのような通信外乱を含む機器が同一線路に接続されるかは想定できず、周期変動は電源周期のみならず、一定周期での切り替え等によるエラーの補完を行う補完手段を講じる方が好ましい。   For example, in a power line, it is assumed that various home appliances and power devices are connected on the same line. However, for example, amplitude and phase fluctuations as shown in FIGS. In the receiving circuit of the modem device, there is a possibility that a reception error occurs due to the deviation of the amplitude / phase point, and it is preferable to take a supplementary means associated with this phenomenon. Furthermore, in the case of using other general communication lines, etc. (including not only communication but also a common line with a modem. For example, wiring in a factory, wiring in a train, etc.) However, it is impossible to assume what kind of communication disturbance will be connected to the same line, and it is better to take supplementary means to compensate for errors by switching not only in the power supply cycle but also in periodic cycles, etc. preferable.

本実施の形態1では、前述の構成、機能、動作から判るように、(1)伝送路変動を電源周期のみならず、伝送路推定結果からの変動量のレベル及び繰り返し周期を推定することで未知の周期変動を検出することが可能であるとともに、(2)等化係数を定常的に学習する適応等化方式と、あらかじめ学習した変動周期の等化係数を周期変動タイミングで呼び出すことで切り替えることにより、迅速にかつ正確な等化が行え、前記補完を行うことが可能である。   In the first embodiment, as can be seen from the above-described configuration, function, and operation, (1) not only the transmission line fluctuation is estimated, but also the fluctuation level and the repetition period are estimated from the transmission line estimation result. It is possible to detect unknown periodic fluctuations and switch between (2) an adaptive equalization method that constantly learns equalization coefficients and an equalization coefficient of a fluctuation period that has been learned in advance by calling it at the period fluctuation timing. Thus, it is possible to perform equalization quickly and accurately, and to perform the complement.

本実施の形態1は、前述の構成、機能、動作から判るように、電力線や一般配線等の電気的配線に通信データを重畳させ、該データを周波数軸上でシングルまたは複数のキャリアにアサインして通信するモデム方式において、伝送路の状態の周期変動に同期して適応等化を行う周期変動同期適応等化機能、送信側の通信信号が伝送路上を通過し受信点における振幅・位相の状態から伝送路を推定し、リファレンス信号からのズレの値により伝送路状態の変化を検出する伝送路変化点検出回路、および電源周期を検出する電源周期検出回路を備えたモデム装置である。   In the first embodiment, as can be seen from the configuration, function, and operation described above, communication data is superimposed on electrical wiring such as power lines and general wiring, and the data is assigned to a single carrier or a plurality of carriers on the frequency axis. In the modem system that communicates with each other, the period fluctuation synchronous adaptive equalization function that performs adaptive equalization in synchronization with the period fluctuation of the transmission path state, the state of the amplitude and phase at the reception point when the transmission side communication signal passes on the transmission path The modem device includes a transmission line change point detection circuit that estimates a transmission line from the reference signal and detects a change in the transmission line state based on a deviation value from a reference signal, and a power supply period detection circuit that detects a power supply period.

本実施の形態1は、換言すれば、電気的配線を併用して当該電気的配線に通信信号を重畳させる通信に使用され送信信号と受信信号との等化を行うモデム装置において、前記送信信号が前記通信信号の伝送路を通過してきた受信信号から前記伝送路の状態の変化点を検出する伝送路変化点検出回路、および電源周期を検出する電源周期検出回路を設け、前記伝送路変化点検出回路の出力と前記電源周期検出回路の出力とにより前記伝送路の状態の周期変動に同期して等化を行うモデム装置である。   In other words, the first embodiment uses the transmission signal in a modem device that is used for communication in which an electrical wiring is used in combination and a communication signal is superimposed on the electrical wiring to equalize a transmission signal and a reception signal. Includes a transmission line change point detection circuit that detects a change point of the state of the transmission line from a received signal that has passed through the transmission line of the communication signal, and a power supply cycle detection circuit that detects a power supply period, and the transmission line change inspection The modem device performs equalization in synchronization with a period fluctuation of the state of the transmission path by an output of the output circuit and an output of the power cycle detection circuit.

本実施の形態1は、換言すれば、受信信号の振幅・位相の状態に基づいて前記伝送路の状態の変化点を検出するモデム装置である。   In other words, the first embodiment is a modem device that detects the change point of the state of the transmission path based on the state of the amplitude and phase of the received signal.

本実施の形態1は、換言すれば、受信信号の振幅・位相のリファレンス信号との誤差に基づいて前記伝送路の状態の変化点を検出するモデム装置である。   In other words, the first embodiment is a modem device that detects a change point of the state of the transmission path based on an error from the reference signal of the amplitude / phase of the received signal.

本実施の形態1は、観点を変えれば、電気的配線を併用して当該電気的配線に通信信号を重畳させる通信に使用されるモデム装置における等化方式において、前記通信信号の伝送路を通過した通信信号から前記伝送路の状態の変化点を検出する伝送路変化点検出回路、および電源周期を検出する電源周期検出回路を設け、前記伝送路変化点検出回路の出力と前記電源周期検出回路の出力とにより前記伝送路の状態の周期変動に同期して等化を行
うモデム装置における等化方式である。
From the viewpoint of the first embodiment, in the equalization method in the modem device used for communication in which the electrical signal is used together and the communication signal is superimposed on the electrical wire, the communication signal passes through the transmission path of the communication signal. A transmission line change point detection circuit for detecting a change point of the state of the transmission line from the transmitted communication signal, and a power supply cycle detection circuit for detecting a power supply cycle, and an output of the transmission line change point detection circuit and the power supply cycle detection circuit Is an equalization method in a modem device that performs equalization in synchronization with the period fluctuation of the state of the transmission path.

実施の形態2.
以下、この発明の実施の形態2を図13〜図15に基づいて説明する。図13は周期変動同期適応等化方式を実行する装置を含むモデム装置の内部構成の他の一例を例示するブロック図、図14は図13における周期変動同期適応等化回路5の内部構成および周期変動同期適応等化回路5とその周辺回路との関係の他の一例を例示するブロック図、図15は図13および図14における検出条件設定機能部20による検出条件の設定についての一例を説明するための説明図である。
Embodiment 2. FIG.
The second embodiment of the present invention will be described below with reference to FIGS. FIG. 13 is a block diagram illustrating another example of the internal configuration of a modem device including a device that executes the periodic variation synchronization adaptive equalization method, and FIG. 14 illustrates the internal configuration and period of the periodic variation synchronization adaptive equalization circuit 5 in FIG. FIG. 15 is a block diagram illustrating another example of the relationship between the fluctuation synchronization adaptive equalization circuit 5 and its peripheral circuits. FIG. 15 illustrates an example of detection condition setting by the detection condition setting function unit 20 in FIGS. It is explanatory drawing for.

本実施の形態2は、前述の実施の形態1における図1に、検出条件設定機能部20を追加したものである。従って、以下の本実施の形態2の説明では、図1と異なる点を主体に説明し、図1と同じ点についての説明は割愛する。   In the second embodiment, a detection condition setting function unit 20 is added to FIG. 1 in the first embodiment. Therefore, in the following description of the second embodiment, the points different from FIG. 1 will be mainly described, and descriptions of the same points as in FIG. 1 will be omitted.

図13において、検出条件設定機能部20は、伝送路変化点検出回路6に対し、伝送路変化点を検出する際の、検出の閾値及び検出時間の幅(Window)を外部から設定できる機能を有しており、ノイズ等で閾値判定の困難であるような場合や、長タイミングでの時間の周期検出が必要な場合等を設定することで、より伝送路状態に適応した正確な検出を可能とするものである。   In FIG. 13, the detection condition setting function unit 20 has a function that allows the transmission line change point detection circuit 6 to set a detection threshold and a detection time width (Window) from the outside when detecting a transmission line change point. It is possible to perform accurate detection that is more adapted to the transmission path condition by setting cases such as when it is difficult to determine the threshold due to noise or when it is necessary to detect the period of time at long timing It is what.

次に、実施形態2の動作について、図13、図14、図15を用いて説明する。   Next, the operation of the second embodiment will be described with reference to FIG. 13, FIG. 14, and FIG.

図13、図14において、検出条件設定機能部20は、例えばCPU等がアクセスできる内部レジスタ等を介し、伝送路変化点検出回路6に対し条件設定を可能とする。伝送路変化点検出回路6が伝送路変化点を検出際の、検出の閾値及び検出時間の幅(Window)を外部から設定できる機能を設けることにより、ノイズ等で閾値判定の困難であるような場合や、長タイミングでの時間の周期検出が必要な場合等を設定することで、より伝送路状態に適応した正確な検出を可能とする。   In FIG. 13 and FIG. 14, the detection condition setting function unit 20 makes it possible to set conditions for the transmission line change point detection circuit 6 via, for example, an internal register that can be accessed by a CPU or the like. When the transmission line change point detection circuit 6 detects the transmission line change point, it is difficult to judge the threshold due to noise or the like by providing a function that can set the detection threshold and the detection time width (window) from the outside. By setting the case or the case where the period detection of the time at the long timing is necessary, it is possible to perform the accurate detection more adapted to the transmission path state.

図15は、検出条件設定機能20による、検出条件設定の例をタイムチャートで示してあり、(e)において、伝送路変化点検出回路6の検出レベル、短期検出幅、周期性を検出する長期検出幅を設定できる様子を示してある。   FIG. 15 is a time chart showing an example of detection condition setting by the detection condition setting function 20, and in FIG. 15E, the detection level, short-term detection width, and periodicity for detecting the transmission line change point detection circuit 6 are detected. It shows how the detection width can be set.

本実施の形態2は、前述の説明から判るように、周期変動に同期して適応等化を行う周期変動同期適応等化機能と伝送路変化点検出回路と電源周期検出回路とを備えた構成において、伝送路変化点を検出する際に、検出の閾値レベル及び検出時間の幅(ウィンドウ)を、外部より設定できる機能を設けたモデム装置である。   As can be seen from the above description, the second embodiment includes a period variation synchronous adaptive equalization function that performs adaptive equalization in synchronization with a period variation, a transmission line change point detection circuit, and a power supply period detection circuit. The modem device is provided with a function capable of externally setting a detection threshold level and a detection time width (window) when detecting a transmission line change point.

本実施の形態2は、換言すれば、伝送路変化点の検出の閾値レベル及び検出時間の幅を設定する機能を設けたモデム装置である。   In other words, the second embodiment is a modem device provided with a function of setting a threshold level for detection of a transmission line change point and a detection time width.

実施の形態3.
以下、この発明の実施の形態3を、図16、図17に基づき説明する。図16は通信信号送信源から送信される信号(図1の信号結合装置12に入力される信号)の信号フレームの構成の他の一例をリファレンス信号も含めて例示する図、図17は周期変動同期適応等化方式を実行する装置を含むモデム装置の内部構成およびモデム装置の周辺装置・機能部との関係の他の一例を例示するブロック図である。
Embodiment 3 FIG.
The third embodiment of the present invention will be described below with reference to FIGS. FIG. 16 is a diagram illustrating another example of the configuration of a signal frame of a signal transmitted from a communication signal transmission source (a signal input to the signal combining device 12 in FIG. 1) including a reference signal, and FIG. It is a block diagram which illustrates another example of the internal structure of the modem apparatus containing the apparatus which performs a synchronous adaptive equalization system, and the relationship with the peripheral device and function part of a modem apparatus.

図16は、前述の実施の形態1における図5のフレーム信号の末尾にリファレンス信号を含むポストアンブルを追加したフレーム構成の事例である。   FIG. 16 shows an example of a frame configuration in which a postamble including a reference signal is added to the end of the frame signal in FIG. 5 in the first embodiment.

図17は、前述の実施の形態1における図1に、電気的配線101への送信側データに対する送信フレームポストアンブル追加機能部312、受信側における受信フレームポストアンブル解析機能部311を追加すると共に、ポストアンブル生成タイミングとして、周期変動同期適応等化機能5からの変動周期タイミング信号を受ける機能を追加した事例である。   FIG. 17 includes a transmission frame postamble addition function unit 312 for transmission side data to the electrical wiring 101 and a reception frame postamble analysis function unit 311 on the reception side in FIG. This is an example in which a function for receiving a fluctuation period timing signal from the period fluctuation synchronization adaptive equalization function 5 is added as a postamble generation timing.

従って、以下の本実施の形態3の説明では、図1および図5と異なる点を主体に説明し、図1および図5と同じ点についての説明は割愛する。   Therefore, in the following description of the third embodiment, the points different from FIGS. 1 and 5 will be mainly described, and the description of the same points as those in FIGS. 1 and 5 will be omitted.

次に、本実施の形態3の動作、機能について、図1、図2、図5、図16、図17を用いて説明する。   Next, operations and functions of the third embodiment will be described with reference to FIGS. 1, 2, 5, 16, and 17.

図17に示すように、図1に、更に、送信側データに対し送信フレームポストアンブル追加機能部312を、受信側に受信フレームポストアンブル解析機能部311を夫々追設し、ポストアンブル生成タイミングとして、周期変動同期適応等化機能(回路)5からの変動周期タイミング信号を受ける機能を追加ことで、送信フレームポストアンブル追加機能部312により、送信フレームに、図5のプリアンブルとともに、フレーム末尾に同様にリファレンス信号を含むポストアンブルを追加する。   As shown in FIG. 17, in FIG. 1, a transmission frame postamble addition function unit 312 is additionally provided for the transmission side data, and a reception frame postamble analysis function unit 311 is additionally provided on the reception side. By adding a function for receiving a fluctuation period timing signal from the period fluctuation synchronization adaptive equalization function (circuit) 5, the transmission frame postamble addition function unit 312 adds the transmission frame to the transmission frame and the preamble of FIG. Add a postamble containing a reference signal to

また、受信フレーム側では、該ポストアンブルのリファレンス信号から、更に伝送路変動分を再度検出し、プリアンブルとポストアンブルとで独立に平行して変動周期を検出することにより、より変動周期検出精度を向上させることが可能である。   On the received frame side, the fluctuation variation is further detected from the reference signal of the postamble, and the fluctuation cycle detection accuracy is further improved by detecting the fluctuation cycle in parallel independently between the preamble and the postamble. It is possible to improve.

尚、ポストアンブルは、フレーム末尾に設けると記したが、フレーム途中でもよい。   Although the postamble is described as being provided at the end of the frame, it may be in the middle of the frame.

前述の実施の形態1では、図2におけるリファレンス信号に関し、図5に示すようにフレームの先頭に、プリアンブルとして基準信号となるリファレンス信号を設けてあるが、本実施の形態3では、図16に示すように、更にフレーム上に、フレームの途中もしくは末尾にポストアンブルを設け、基準信号を増やすことで、より伝送路上の変動の検出回数を増加させ精度を向上することができる。例えば、S/N(Signal to Noise Ratio)比の低い伝送路等では効果的ある。   In the first embodiment, with respect to the reference signal in FIG. 2, a reference signal serving as a reference signal as a preamble is provided at the head of the frame as shown in FIG. 5, but in the third embodiment, in FIG. As shown, a postamble is further provided in the middle or end of the frame on the frame, and the reference signal is increased, so that the number of fluctuations detected on the transmission path can be increased and the accuracy can be improved. For example, it is effective in a transmission line having a low S / N (Signal to Noise Ratio) ratio.

本実施の形態3は、前述の説明から判るように、伝送路変化点検出回路の伝送路推定回路で使用する通信フレーム中のリファレンス信号となるフレームの先頭のプリアンブルに対し、フレーム先頭以外にフレームの途中、もしくはフレーム末尾にリファレンス信号を含むポストアンブルを設けることにより、伝送路変化点検出誤差を少なくするモデム装置である。   In the third embodiment, as can be seen from the above description, a frame other than the frame head is used for the preamble at the head of the frame serving as a reference signal in the communication frame used in the transmission path estimation circuit of the transmission path change point detection circuit. This is a modem device that reduces a transmission path change point detection error by providing a postamble including a reference signal in the middle of the frame or at the end of the frame.

本実施の形態3は、換言すれば、送信信号の信号フレームに、何れもリファレンス信号を有するプリアンブルおよびポストアンブルを設けたモデム装置である。   In other words, Embodiment 3 is a modem device in which a preamble and a postamble each having a reference signal are provided in a signal frame of a transmission signal.

実施の形態4.
以下、この発明の実施の形態4を、図18〜図20に基づいて説明する。図18は信号フレームと伝送路変動による受信エラーの発生との関係の一例を説明する説明図、図19は送信フレームに対する、受信エラーを見越したフレーム中のデータの冗長化の一例を示す図、図20は周期変動同期適応等化方式を実行する装置を含むモデム装置の内部構成およびモデム装置の周辺装置・機能部との関係の更に他の一例を例示するブロック図である。
Embodiment 4 FIG.
A fourth embodiment of the present invention will be described below with reference to FIGS. FIG. 18 is an explanatory diagram for explaining an example of the relationship between signal frames and occurrence of reception errors due to transmission path fluctuations, and FIG. 19 is a diagram showing an example of data redundancy in a frame in anticipation of reception errors with respect to transmission frames; FIG. 20 is a block diagram illustrating still another example of the internal configuration of a modem device including a device that executes the period variation synchronous adaptive equalization method and the relationship between peripheral devices and function units of the modem device.

前述の実施の形態1では、図1に例示の送信信号、受信信号におかる通信フレームの構成は図5となるが、伝送路上の変動周期が検出された場合、予めフレーム上でエラー(通信NG)となる箇所が事前にわかるため、本実施の形態4では、図18、図19に示すように、送信信号において、フレーム上の該箇所を冗長化(無効化)あるいは、受信フレームの解析において、フレーム上の該箇所を冗長化(無効化)することで、通信エラー処理で、再送や無効フレーム処理を行う必要がなくなり、正常なフレームのみを受信することで、モデム装置の同期制御、受信制御の通信異常の状態を回避することを可能とする。   In the first embodiment described above, the configuration of the communication frame in the transmission signal and the reception signal illustrated in FIG. 1 is as shown in FIG. 5. However, if a fluctuation period on the transmission path is detected, an error (communication NG) is previously detected on the frame. In the fourth embodiment, as shown in FIGS. 18 and 19, in the transmission signal, the portion on the frame is made redundant (invalidated) or the received frame is analyzed. By making the part of the frame redundant (invalidated), there is no need to perform retransmission or invalid frame processing in communication error processing. By receiving only normal frames, synchronous control and reception of modem devices It is possible to avoid the state of control communication abnormality.

図20は、図1に対し、送信側データに対する送信フレーム再構築部302を追加し、また受信側に受信フレーム冗長部解析部301を追加し、冗長ビットを設けた再構築フレーム生成タイミング及び該フレームの受信を判断するタイミングとして、周期変動同期適応等化機能5からの変動周期タイミング信号を受ける機能を追加したものである。   20 adds a transmission frame reconstruction unit 302 for the transmission side data to FIG. 1 and adds a reception frame redundancy unit analysis unit 301 to the reception side, As a timing for judging reception of a frame, a function for receiving a fluctuation cycle timing signal from the period fluctuation synchronization adaptive equalization function 5 is added.

次に、本実施の形態4の動作について、図1、図5、図18、図19、図20を用いて説明する。   Next, the operation of the fourth embodiment will be described with reference to FIG. 1, FIG. 5, FIG. 18, FIG.

前述の実施の形態1では、図1に例示の送信信号、受信信号において、通信フレームの構成は図5となる。   In the first embodiment, the configuration of the communication frame in the transmission signal and the reception signal illustrated in FIG. 1 is as shown in FIG.

一方、本実施の形態4における図18は、伝送路上の変動周期が検出された場合、フレーム上でエラー(通信NG)となる箇所を例示してある。受信フレームでこのように、エラーが生じた場合、例えば、ヘッダ部であれば、同期異常による同期はずれや該フレーム全ての受信異常が発生し、データ部であれば、例えば再送動作が発生し、通信帯域を圧迫し、バッファオーバフロー、再送が1回で完了しなかった場合回数オーバーによる受信NG等、各種異常状態が発生する可能性がある。   On the other hand, FIG. 18 in the fourth embodiment exemplifies a location where an error (communication NG) occurs on the frame when a fluctuation period on the transmission path is detected. In this way, when an error occurs in the received frame, for example, if it is a header part, synchronization loss due to synchronization abnormality or reception abnormality of all the frames occurs, and if it is a data part, for example, a retransmission operation occurs, If the communication band is compressed and buffer overflow and retransmission are not completed in one time, various abnormal states such as reception NG due to the number of times exceeding may occur.

図19は、前述の受信NG等の各種異常状態状態を回避するための対策を例示してある。周期動作が検出できた場合、予めフレーム上でエラーとなるタイミングは事前に予測可能である。従って、これに対し、送信フレーム上で、該エラーとなる箇所に対しては、意味のあるデータを送信しない、すなわち、冗長ビットで構成するといった、フレームデータ構築の際に、冗長ビットを付加する機能を前述の実施形態1の機能に追加するものである。   FIG. 19 illustrates measures for avoiding various abnormal state states such as the above-mentioned reception NG. When a periodic motion can be detected, the timing at which an error occurs on a frame can be predicted in advance. Therefore, a redundant bit is added at the time of constructing frame data such that no meaningful data is transmitted to the location where the error occurs in the transmission frame, that is, it is configured with redundant bits. The function is added to the function of the first embodiment.

図20は、図19により説明した機能を実現するため、図1に対し、送信側データに対する送信フレーム再構築部302を追加し、また受信側に受信フレーム冗長部解析部301を追加し、冗長ビットを設けた再構築フレーム生成タイミング及び該フレームの受信を判断するタイミングとして、周期変動同期適応等化機能5からの変動周期タイミング信号を受ける機能を追加したものである。   20 adds a transmission frame reconstruction unit 302 for transmission side data to FIG. 1 and adds a reception frame redundancy unit analysis unit 301 to the reception side in order to realize the function described with reference to FIG. A function for receiving a fluctuation period timing signal from the period fluctuation synchronization adaptive equalization function 5 is added as a timing for generating a reconstructed frame provided with bits and a timing for judging reception of the frame.

本実施の形態4は、前述の説明から判るように、周期変動が検出できた場合、通信フレーム上の周期変動で受信特性が劣化する部分を、通信データ以外の冗長データとするように、、送信フレームを再構築する機能を備えたモデム装置である。   As can be seen from the above description, in the fourth embodiment, when the period variation can be detected, the portion in which the reception characteristics deteriorate due to the period variation on the communication frame is set as redundant data other than the communication data. This is a modem device having a function of reconstructing a transmission frame.

本実施の形態4は、換言すれば、伝送路の状態の周期変動で通信フレーム上の受信特性が劣化する部分を、データ以外の冗長データとするように、、送信フレームを再構築する機能を設けたモデム装置である。   In other words, the fourth embodiment has a function of reconstructing a transmission frame so that a portion where reception characteristics on a communication frame deteriorate due to a period variation of the state of the transmission path is made redundant data other than data. This is a provided modem device.

実施の形態5.
以下、この発明の実施の形態5を、図21〜図23に基づいて説明する。図21は信号フレーム周期と伝送路変動周期とが一致し、受信エラーが周期的に発生する事例を例示す
る図、図22はフレーム長を変え、信号フレーム周期と伝送路変動周期と一致しないよう回避する一例を例示する図、図23は信号フレーム周期と伝送路変動周期とが一致した場合にフレーム長を変え、信号フレーム周期と伝送路変動周期と一致しないようにして受信エラーの周期的発生を回避する手段を例示する図であって、周期変動同期適応等化方式を実行する装置を含むモデム装置の内部構成およびモデム装置の周辺装置・機能部との関係の更に他の一例を例示するブロック図である。
Embodiment 5 FIG.
The fifth embodiment of the present invention will be described below with reference to FIGS. FIG. 21 is a diagram exemplifying a case where the signal frame period and the transmission path fluctuation period coincide with each other and a reception error occurs periodically. FIG. 22 changes the frame length so that the signal frame period does not coincide with the transmission path fluctuation period. FIG. 23 is a diagram illustrating an example of avoidance. FIG. 23 shows a case in which the frame length is changed when the signal frame period and the transmission line fluctuation period coincide with each other, and the reception error is periodically generated so as not to coincide with the signal frame period and the transmission line fluctuation period. FIG. 6 is a diagram illustrating a means for avoiding the problem, and illustrates still another example of the internal configuration of the modem device including the device that executes the period variation synchronous adaptive equalization method and the relationship between the peripheral device and the function unit of the modem device. It is a block diagram.

前述の実施の形態1では、図1に例示の送信信号、受信信号において、通信フレームの構成は図5となる。   In the first embodiment, the configuration of the communication frame in the transmission signal and the reception signal illustrated in FIG. 1 is as shown in FIG.

一方、本実施の形態5における図21、図22に例示するように、伝送路上の変動周期が検出され、しかもフレーム周期と一致する場合、フレーム上において、同一の箇所で通信エラーが毎フレーム発生する可能性がある。   On the other hand, as illustrated in FIGS. 21 and 22 in the fifth embodiment, when a fluctuation period on the transmission path is detected and coincides with the frame period, a communication error occurs at the same location on the frame every frame. there's a possibility that.

受信フレームでこのように、エラーが毎回生じた場合、例えば、ヘッダ部であれば、同期異常による同期はずれが発生し復帰しない状態が連続する、もしくはデータ部であれば、例えば再送動作が毎回発生し、通信帯域を圧迫し、バッファオーバフロー、再送が1回で完了しない場合も高く回数オーバーによる受信NG等、各種異常状態が発生する可能性がある。   Thus, if an error occurs in the received frame every time, for example, if it is a header part, the state of out-of-synchronization due to synchronization abnormality occurs and the state where it does not return continues or if it is a data part, for example, a retransmission operation occurs every time. However, even if the communication band is compressed and the buffer overflow and retransmission are not completed in one time, there is a possibility that various abnormal states such as a reception NG due to the excessive number of times may occur.

そこで、本実施の形態5における図23では、前述の実施の形態1の図1に対し、送信側データに対する送信フレーム長再構築部304を追加し、また、受信側に受信フレーム長解析部303を追加し、更に、冗長ビットを設けた再構築フレーム生成タイミング及び該フレームの受信を判断するタイミングとして、周期変動同期適応等化機能5からの変動周期タイミング信号を受ける機能を追加してあり、本構成、本機能により、変動周期を検出した場合、フレーム長を変動周期と一致させないように変更することにより、毎回フレーム同一箇所で発生させないよう回避する。   Therefore, in FIG. 23 in the fifth embodiment, a transmission frame length reconstruction unit 304 for transmission side data is added to FIG. 1 in the first embodiment, and a reception frame length analysis unit 303 is provided on the reception side. In addition, as a reconstructed frame generation timing provided with redundant bits and a timing for judging reception of the frame, a function of receiving a variation cycle timing signal from the cycle variation synchronization adaptive equalization function 5 has been added, When the fluctuation period is detected by this configuration and this function, the frame length is changed so as not to coincide with the fluctuation period, thereby avoiding the occurrence of occurrence at the same position of the frame every time.

受信フレームでこのように、エラーが毎回生じた場合、例えば、ヘッダ部であれば、同期異常による同期はずれが発生し復帰しない状態が連続する、もしくはデータ部であれば、例えば再送動作が毎回発生し、通信帯域を圧迫し、バッファオーバフロー、再送が1回で完了しない場合も高く回数オーバーによる受信NG等、各種異常状態が発生する可能性があるが、変動周期を検出した場合、本実施の形態5の機能によってフレーム長を変動周期と一致させないように変更することにより、毎回フレーム同一箇所で発生させないよう回避することを可能とする。   Thus, if an error occurs in the received frame every time, for example, if it is a header part, the state of out-of-synchronization due to synchronization abnormality occurs and the state where it does not return continues or if it is a data part, for example, a retransmission operation occurs every time. However, there is a possibility that various abnormal conditions such as reception NG due to excessive number of times may occur even if buffer overflow and retransmission are not completed in one time, but if the fluctuation period is detected, By changing the frame length so as not to coincide with the fluctuation period by the function of the fifth aspect, it is possible to avoid the occurrence of the frame at the same position every time.

本実施の形態5は、前述の説明から判るように、周期変動が検出できた場合、通信フレーム上の特定周期でラーが発生することを回避するため、通信フレーム長を変えてフレーム構成を再構築する機能を備えたモデム装置である。   As can be seen from the above description, in the fifth embodiment, when period fluctuations can be detected, in order to avoid the occurrence of error at a specific period on a communication frame, the frame configuration is re-changed by changing the communication frame length. This is a modem device having a function to be constructed.

本実施の形態5は、換言すれば、送信信号の信号フレーム長を変えて当該フレーム構成を再構築し前記信号フレーム上の特定周期でエラーが発生することを回避する機能を設けたモデム装置である。   In other words, the fifth embodiment is a modem device provided with a function of reconfiguring the frame configuration by changing the signal frame length of the transmission signal and avoiding an error from occurring at a specific period on the signal frame. is there.

なお、図1〜図23において、各図中、同一符合は同一または相当部分を示す。   1 to 23, the same reference numerals denote the same or corresponding parts in each figure.

この発明の実施の形態1を示す図で、周期変動同期適応等化方式を実行する装置を含むモデム装置の内部構成およびモデム装置の周辺装置・機器との関係の一例を例示するブロック図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows Embodiment 1 of this invention, and is a block diagram which illustrates an example of the internal structure of a modem apparatus containing the apparatus which performs a period fluctuation synchronous adaptive equalization system, and the relationship with the peripheral apparatus and apparatus of a modem apparatus. . この発明の実施の形態1を示す図で、図1における周期変動同期適応等化回路5の内部構成および周期変動同期適応等化回路5とその周辺回路との関係の一例を例示するブロック図である。1 is a diagram illustrating a first embodiment of the present invention, and is a block diagram illustrating an example of an internal configuration of a periodic variation synchronization adaptive equalization circuit 5 in FIG. 1 and an example of a relationship between the periodic variation synchronization adaptive equalization circuit 5 and its peripheral circuits. is there. この発明の実施の形態1を示す図で、図1および図2における電源周期検出回路7におけるゼロクロス検出回路の一例を例示する接続図である。FIG. 5 is a diagram illustrating the first embodiment of the present invention, and is a connection diagram illustrating an example of a zero-cross detection circuit in the power cycle detection circuit 7 in FIGS. 1 and 2. この発明の実施の形態1を示す図で、図3におけるAC電源の電源波形とフォトカプラの出力波形との関係の一例を示す図である。FIG. 5 is a diagram illustrating the first embodiment of the present invention, and is a diagram illustrating an example of a relationship between a power supply waveform of an AC power supply and an output waveform of a photocoupler in FIG. 3. この発明の実施の形態1を示す図で、通信信号送信源から送信される信号(図1の信号結合装置12に入力される信号)の信号フレームの構成の一例をリファレンス信号も含めて例示する図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows Embodiment 1 of this invention, and illustrates an example of the structure of the signal frame of the signal (signal input into the signal coupling device 12 of FIG. 1) transmitted from a communication signal transmission source including a reference signal. FIG. この発明の実施の形態1を示す図で、通信システムモデルを示す図である。It is a figure which shows Embodiment 1 of this invention, and is a figure which shows a communication system model. この発明の実施の形態1を示す図で、図1および図2における伝送路変化点検出回路6による伝送路推定値と基準点からの誤差値を検出する考え方の一例を示す図である。It is a figure which shows Embodiment 1 of this invention, and is a figure which shows an example of the idea which detects the error value from the transmission line estimated value and reference point by the transmission line change point detection circuit 6 in FIG.1 and FIG.2. この発明の実施の形態1を示す図で、図2における等化タイミング生成回路54の機能の一例を説明する図である。FIG. 2 is a diagram illustrating the first embodiment of the present invention, and is a diagram illustrating an example of the function of an equalization timing generation circuit 54 in FIG. 2. この発明の実施の形態1を示す図で、図2および図8における等化係数学習回路53の内部構成の一例を示す図である。FIG. 9 is a diagram illustrating the first embodiment of the present invention, and is a diagram illustrating an example of an internal configuration of an equalization coefficient learning circuit 53 in FIGS. 2 and 8. この発明の実施の形態1を示す図で、図2および図8における等化係数生成回路52の内部構成の一例を示すブロック図である。FIG. 9 is a diagram illustrating the first embodiment of the present invention, and is a block diagram illustrating an example of an internal configuration of an equalization coefficient generation circuit 52 in FIGS. 2 and 8. この発明の実施の形態1を示す図で、伝送路特性の変動の一事例である伝送路特性Aを示す図である。It is a figure which shows Embodiment 1 of this invention, and is a figure which shows the transmission line characteristic A which is an example of the fluctuation | variation of a transmission line characteristic. この発明の実施の形態1を示す図で、伝送路特性の変動の他の一事例である伝送路特性Bを示す図である。It is a figure which shows Embodiment 1 of this invention, and is a figure which shows the transmission line characteristic B which is another example of the fluctuation | variation of a transmission line characteristic. この発明の実施の形態2を示す図で、周期変動同期適応等化方式を実行する装置を含むモデム装置の内部構成の他の一例を例示するブロック図である。It is a figure which shows Embodiment 2 of this invention, and is a block diagram which illustrates another example of the internal structure of the modem apparatus containing the apparatus which performs a period fluctuation synchronous adaptive equalization system. この発明の実施の形態2を示す図で、図13における周期変動同期適応等化回路5の内部構成および周期変動同期適応等化回路5とその周辺回路との関係の他の一例を例示するブロック図である。FIG. 14 is a diagram illustrating the second embodiment of the present invention, and is a block illustrating another example of the internal configuration of the periodic fluctuation synchronization adaptive equalization circuit 5 and the relationship between the periodic fluctuation synchronization adaptive equalization circuit 5 and its peripheral circuits in FIG. FIG. この発明の実施の形態2を示す図で、図13および図14における検出条件設定機能部20による検出条件の設定についての一例を説明するための説明図である。It is a figure which shows Embodiment 2 of this invention, and is explanatory drawing for demonstrating an example about the setting of the detection condition by the detection condition setting function part 20 in FIG. 13 and FIG. この発明の実施の形態3を示す図で、通信信号送信源から送信される信号(図1の信号結合装置12に入力される信号)の信号フレームの構成の他の一例をリファレンス信号も含めて例示する図である。FIG. 9 is a diagram illustrating a third embodiment of the present invention, including another example of a signal frame configuration of a signal transmitted from a communication signal transmission source (a signal input to the signal combining device 12 in FIG. 1) including a reference signal. It is a figure illustrated. この発明の実施の形態3を示す図で、周期変動同期適応等化方式を実行する装置を含むモデム装置の内部構成およびモデム装置の周辺装置・機能部との関係の他の一例を例示するブロック図である。The figure which shows Embodiment 3 of this invention, and is a block which illustrates another example of the internal structure of the modem apparatus containing the apparatus which performs a period fluctuation synchronous adaptive equalization system, and the relationship with the peripheral device and a function part of a modem apparatus FIG. この発明の実施の形態4を示す図で、信号フレームと伝送路変動による受信エラーの発生との関係の一例を説明する説明図である。It is a figure which shows Embodiment 4 of this invention, and is explanatory drawing explaining an example of the relationship between a signal frame and generation | occurrence | production of the reception error by a transmission line fluctuation | variation. この発明の実施の形態4を示す図で、送信フレームに対する、受信エラーを見越したフレーム中のデータの冗長化の一例を示す図である。It is a figure which shows Embodiment 4 of this invention, and is a figure which shows an example of the redundancy of the data in the frame which anticipated the reception error with respect to a transmission frame. この発明の実施の形態4を示す図で、周期変動同期適応等化方式を実行する装置を含むモデム装置の内部構成およびモデム装置の周辺装置・機能部との関係の更に他の一例を例示するブロック図である。FIG. 10 is a diagram illustrating a fourth embodiment of the present invention, and illustrates still another example of the internal configuration of a modem device including a device that executes a period variation synchronous adaptive equalization method and the relationship between peripheral devices and function units of the modem device. It is a block diagram. この発明の実施の形態5を示す図で、信号フレーム周期と伝送路変動周期とが一致し、受信エラーが周期的に発生する事例を例示する図である。It is a figure which shows Embodiment 5 of this invention, and is a figure which illustrates the example which a signal frame period and a transmission-line fluctuation | variation period correspond, and a receiving error generate | occur | produces periodically. この発明の実施の形態5を示す図で、フレーム長を変え、信号フレーム周期と伝送路変動周期と一致しないよう回避する一例を例示する図である。It is a figure which shows Embodiment 5 of this invention, and is a figure which illustrates an example which changes a frame length and it avoids so that it may not correspond with a signal frame period and a transmission-line fluctuation period. この発明の実施の形態5を示す図で、信号フレーム周期と伝送路変動周期とが一致した場合にフレーム長を変え、信号フレーム周期と伝送路変動周期と一致しないようにして受信エラーの周期的発生を回避する手段を例示する図であって、周期変動同期適応等化方式を実行する装置を含むモデム装置の内部構成およびモデム装置の周辺装置・機能部との関係の更に他の一例を例示するブロック図である。FIG. 5 is a diagram showing Embodiment 5 of the present invention, in which the frame length is changed when the signal frame period and the transmission path fluctuation period coincide with each other, and the reception error is periodically changed so as not to coincide with the signal frame period and the transmission path fluctuation period. FIG. 5 is a diagram illustrating a means for avoiding occurrence, and illustrates still another example of the internal configuration of a modem device including a device that executes a period variation synchronous adaptive equalization method and the relationship between peripheral devices and function units of the modem device FIG.

符号の説明Explanation of symbols

1 モデム装置、
2 アナログ信号インタフェース部、
3 A/D(Analog/Digital)変換部、
4 FFT(First Fourier Transform)部、
5 周期変動同期適応等化機能回路、
51 等化係数乗算回路部、
52 等化係数生成回路、
521 セレクタ、
522 等化係数計算回路、
53 等化係数学習回路、
54 等化係数タイミング生成機能部、
541 周期判定回路、
542 タイミング選択回路、
6 伝送路変化点検出回路、
7 電源周期検出回路、
8 復号化部、
9 D/A(Digital/Analog)変換部、
10 IFFT(Inverse First Fourier Transform)部、
11 符号化部、
12 信号結合装置、
20 検出条件設定機能部、
101 電気的配線、
301 受信フレーム冗長部解析部、
302 送信フレーム再構築部、
303 受信フレーム長解析部、
304 送信フレーム長再構築部、
311 受信フレームポストアンブル解析機能部、
312 送信フレームポストアンブル追加機能部。
1 modem device,
2 Analog signal interface,
3 A / D (Analog / Digital) converter,
4 FFT (First Fourier Transform) part,
5 Period variation synchronous adaptive equalization function circuit,
51 equalization coefficient multiplication circuit section,
52 Equalization coefficient generation circuit,
521 selector,
522 equalization coefficient calculation circuit,
53 Equalization coefficient learning circuit,
54 Equalization coefficient timing generation function part,
541 period determination circuit,
542 timing selection circuit,
6 Transmission line change point detection circuit,
7 Power cycle detection circuit,
8 Decryption unit,
9 D / A (Digital / Analog) converter,
10 IFFT (Inverse First Fourier Transform) part,
11 Encoding part,
12 signal coupling device,
20 Detection condition setting function section,
101 electrical wiring,
301 Receive frame redundant part analysis part,
302 transmission frame reconstruction unit,
303 Received frame length analysis section,
304 Transmission frame length reconstruction unit,
311 Received frame postamble analysis function part,
312 Transmission frame postamble addition function part.

Claims (8)

電気的配線を併用して当該電気的配線に通信信号を重畳させる通信に使用されるモデム装置における等化方式において、前記通信信号の伝送路を通過した通信信号から前記伝送路の状態の変化点を検出する伝送路変化点検出回路、および電源周期を検出する電源周期検出回路を設け、前記伝送路変化点検出回路の出力と前記電源周期検出回路の出力とにより前記伝送路の状態の周期変動に同期して等化を行うことを特徴とするモデム装置における等化方式。   In an equalization method for a modem device used for communication in which an electrical wiring is used together and a communication signal is superimposed on the electrical wiring, the change point of the state of the transmission path from the communication signal passing through the transmission path of the communication signal A transmission line change point detection circuit for detecting a power supply period and a power supply period detection circuit for detecting a power supply period, and the fluctuation of the state of the transmission line according to the output of the transmission line change point detection circuit and the output of the power supply period detection circuit An equalization method in a modem device characterized by performing equalization in synchronization with 電気的配線を併用して当該電気的配線に通信信号を重畳させる通信に使用され送信信号と受信信号との等化を行うモデム装置において、前記送信信号が前記通信信号の伝送路を通過してきた受信信号から前記伝送路の状態の変化点を検出する伝送路変化点検出回路、および電源周期を検出する電源周期検出回路を設け、前記伝送路変化点検出回路の出力と前記電源周期検出回路の出力とにより前記伝送路の状態の周期変動に同期して等化を行うことを特徴とするモデム装置。   In a modem device that is used for communication in which an electrical wiring is used and a communication signal is superimposed on the electrical wiring and equalizes a transmission signal and a reception signal, the transmission signal has passed through the transmission path of the communication signal A transmission line change point detection circuit for detecting a change point of the state of the transmission line from a received signal, and a power supply cycle detection circuit for detecting a power supply period are provided, and the output of the transmission line change point detection circuit and the power supply cycle detection circuit A modem device characterized in that equalization is performed in synchronism with period fluctuations of the state of the transmission path by output. 請求項2に記載のモデム装置において、受信信号の振幅・位相の状態に基づいて前記伝送路の状態の変化点を検出することを特徴とするモデム装置。   3. The modem device according to claim 2, wherein a change point of the state of the transmission path is detected based on the amplitude / phase state of the received signal. 請求項2に記載のモデム装置において、受信信号の振幅・位相のリファレンス信号との誤差に基づいて前記伝送路の状態の変化点を検出することを特徴とするモデム装置。   3. The modem device according to claim 2, wherein a change point of the state of the transmission path is detected based on an error from the amplitude / phase reference signal of the received signal. 請求項2〜請求項4の何れか一に記載のモデム装置において、前記伝送路変化点の検出の閾値レベル及び検出時間の幅を設定する機能を設けたことを特徴とするモデム装置。   5. The modem device according to claim 2, further comprising a function of setting a threshold level and a detection time width for detecting the transmission line change point. 請求項4に記載のモデム装置において、前記送信信号の信号フレームに、何れもリファレンス信号を有するプリアンブルおよびポストアンブルを設けたことを特徴とするモデム装置。   5. The modem apparatus according to claim 4, wherein a preamble and a postamble each having a reference signal are provided in a signal frame of the transmission signal. 請求項2〜請求項6の何れか一に記載のモデム装置において、前記伝送路の状態の周期変動で通信フレーム上の受信特性が劣化する部分を、データ以外の冗長データとするように、送信フレームを再構築する機能を設けたことを特徴とするモデム装置。   7. The modem device according to claim 2, wherein a transmission data is transmitted so that a portion where reception characteristics on a communication frame deteriorate due to a period variation of a state of the transmission path is redundant data other than data. A modem device provided with a function of reconstructing a frame. 請求項2〜請求項7の何れか一に記載のモデム装置において、前記送信信号の信号フレーム長を変えて当該フレーム構成を再構築し前記信号フレーム上の特定周期でエラーが発生することを回避する機能を設けたことを特徴とするモデム装置。   8. The modem device according to claim 2, wherein a signal frame length of the transmission signal is changed to reconstruct the frame configuration to prevent an error from occurring at a specific period on the signal frame. A modem device provided with a function for
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02172332A (en) * 1988-12-26 1990-07-03 Nec Home Electron Ltd Reception signal equalizer for spread spectrum communication system
WO2006022363A1 (en) * 2004-08-24 2006-03-02 Matsushita Electric Industrial Co., Ltd. Method and apparatus for power line communication
WO2007026413A1 (en) * 2005-08-31 2007-03-08 Mitsubishi Denki Kabushiki Kaisha Power line carrier communication modem

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02172332A (en) * 1988-12-26 1990-07-03 Nec Home Electron Ltd Reception signal equalizer for spread spectrum communication system
WO2006022363A1 (en) * 2004-08-24 2006-03-02 Matsushita Electric Industrial Co., Ltd. Method and apparatus for power line communication
WO2007026413A1 (en) * 2005-08-31 2007-03-08 Mitsubishi Denki Kabushiki Kaisha Power line carrier communication modem

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